Storage Devices

Abstract

A memory device is provided, the memory device comprising a memory cell array and a controller, the memory cell array comprising a plurality of word lines, at least one selection line disposed above the plurality of word lines, and a channel region passing through the plurality of word lines and the at least one selection line, the plurality of word lines and the channel region providing a plurality of memory cells. The controller stores data in a programming memory cell among the plurality of memory cells by sequentially performing a first programming operation and a second programming operation, and determines a programming voltage input to a programming word line connected to the programming memory cell in the first programming operation based on information about the programming memory cell.

Description

[0001] This application is a divisional application of a patent application with an application date of January 7, 2019, application number 201910011507.X, and invention name “Memory Device”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS The entire contents of Korean Patent Application No. 10-2018-0002123 filed on January 8, 2018 in the Korean Intellectual Property Office are incorporated herein by reference. Technical Field

[0003] Embodiments relate to a memory device. Background Art

[0004] As the demand for memory devices with relatively high capacity but small size increases, memory devices with vertically stacked memory cells have been actively studied. As the integration of memory devices increases, the number of vertically stacked memory cells has also increased. Therefore, various methods that can prevent interference between memory cells from increasing have been proposed. Summary of the invention

[0005] According to one aspect, a memory device includes: a memory cell array, the memory cell array including multiple word lines, at least one selection line arranged above the multiple word lines, and a channel region passing through the multiple word lines and the at least one selection line, the multiple word lines and the channel region providing multiple memory cells; and a controller, the controller stores data in a programming memory cell among the multiple memory cells by sequentially performing a first programming operation and a second programming operation, and determines a programming voltage input to a programming word line connected to the programming memory cell in the first programming operation based on information about the programming memory cell.

[0006] According to one aspect, a memory device includes: a first storage area, the first storage area includes a plurality of first storage cells; a second storage area, the second storage area includes a plurality of second storage cells, each of the plurality of second storage cells storing one bit of data; and a controller, the controller storing N bits of data in a first programming storage cell of the first storage area, and dividing the N bits of data into data of each bit to be stored in N second programming storage cells of the second storage area, wherein N is a natural number. Each position of the second programming storage cell in the second storage area corresponds to the position of the first programming storage cell in the first storage area.

[0007] According to one aspect, a memory device includes: a memory cell array, the memory cell array including a plurality of memory cells stacked on a substrate in a direction perpendicular to an upper surface of the substrate; and a controller, the controller storing N-bit data in the plurality of memory cells by sequentially performing a first programming operation and a second programming operation, wherein N is a natural number. The controller inputs different programming voltages to at least a portion of the plurality of memory cells in the first programming operation, so that the at least a portion of the plurality of memory cells have different threshold voltage distributions. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which: Figure 1 shows a schematic block diagram of a memory device according to an example embodiment; Figure 2 shows a view including a memory cell array in a memory device according to example embodiments; Figure 3 A schematic diagram showing a structure of a memory device according to an example embodiment; FIG. 4A to FIG. 5B A diagram illustrating operations in a programming method of a memory device according to example embodiments; Figures 6 to 8 A view showing a memory device according to an example embodiment; Fig.9A , Fig. 9B , Fig. 10A and Fig. 10B A diagram illustrating threshold voltage distribution of memory cells included in a memory device according to example embodiments; Fig.11 A schematic diagram showing a structure of a memory device according to an example embodiment; Fig.12 A view showing a memory device according to an example embodiment; Fig.13 A schematic diagram showing a structure of a memory device according to an example embodiment; Fig.14 A view showing a memory device according to an example embodiment; Fig.15A , Fig. 15B , Fig.16A and Fig. 16B A diagram illustrating threshold voltage distribution of memory cells included in a memory device according to example embodiments; Fig.17 A diagram illustrating an operation of a memory device according to an example embodiment; Figures 18A to 18CA diagram illustrating threshold voltage distributions of memory cells included in a memory device according to example embodiments; and Fig.19 A block diagram of an electronic device including a memory device according to example embodiments is shown. DETAILED DESCRIPTION

[0009] Hereinafter, example embodiments will be described with reference to the accompanying drawings.

[0010] Figure 1 is a schematic block diagram of a memory device according to example embodiments. Figure 2 is a schematic perspective view of a memory cell array included in a memory device according to example embodiments.

[0011] Reference Figure 1 , a memory device 10 according to example embodiments may include a memory controller 20 and a memory cell array 30. The memory controller 20 may include a control logic 21, a row driver 22, a column driver 23, etc. The memory cell array 30 may include a plurality of memory cells MC.

[0012] In an example embodiment, the row driver 22 may be connected to the memory cell MC through the word line WL, the string selection line SSL, the common source line CSL, the ground selection line GSL, etc. The column driver 23 may be connected to the memory cell MC through the bit line BL. In an example embodiment, the row driver 22 may include an address decoder circuit for selecting the memory cell MC to be written or read, and the column driver 23 may include a page buffer to write data to or read data from the memory cell MC. The operations of the row driver 22 and the column driver 23 may be controlled by the control logic 21.

[0013] Reference Figure 2 , the memory cell array 30 according to the example embodiment may include a plurality of memory cells MC. The memory cells MC may be arranged at points where a plurality of word lines WL and a plurality of bit lines BL cross each other, for example, to form a matrix. For example, each memory cell MC may be connected to one word line WL and one bit line BL, respectively.

[0014] A plurality of memory cells MC may be connected in series to each other, thereby providing a memory cell string MCS. In addition to the memory cells MC, the memory cell string MCS may further include a string selection transistor SST and a ground selection transistor GST. In the memory cell string MCS, the string selection transistor SST may be connected to a bit line BL above the memory cell MC. The ground selection transistor GST may be connected to a common source line CSL below the memory cell MC.

[0015] although Figure 2The example embodiment shows that one memory cell string MCS includes one ground selection transistor GST and one string selection transistor SST, but the number of ground selection transistors GST and the number of string selection transistors SST may be changed. In addition, at least one dummy word line may also be located between the ground selection transistor GST and the word line WL and / or between the string selection transistor SST and the word line WL.

[0016] Figure 3 is a schematic diagram of a structure of a memory device according to example embodiments. Figure 3 is a partial perspective view of a memory cell array included in the memory device 100 .

[0017] Reference Figure 3 , a memory device 100 according to example embodiments may include a substrate 101, an upper surface (eg, Figure 3 The substrate 101 includes a plurality of channel structures CH and a dummy channel structure DCH vertically (e.g., along the z-axis direction) to the xy plane in the exemplary embodiment of the present invention, a plurality of gate electrode layers 131 to 138 (gate electrode layers 130) stacked on the substrate 101 (e.g., along the z-axis direction) adjacent to the channel structures CH and extending in the xy plane. The plurality of gate electrode layers 130 may be alternately stacked with a plurality of insulating layers 141 to 149 (insulating layers 140) (e.g., along the z-axis direction). A portion of the plurality of gate electrode layers 130 may be divided into a plurality of portions by an isolation insulating layer 155 (e.g., in the xy plane).

[0018] The plurality of gate electrode layers 130 may provide a ground selection line 131, string selection lines 137 and 138, and a plurality of word lines 132 to 136. The ground selection line 131 may provide a ground selection transistor GST together with the channel structure CH, and the string selection lines 137 and 138 may provide a string selection transistor SST including two string selection transistors SST1 and SST2. Figure 3 , the first string selection transistor SST1 may correspond to the first string selection line 138, and the second string selection transistor SST2 may correspond to the second string selection line 137. A plurality of word lines 132 to 136 located between the ground selection line 131 and the string selection lines 137 and 138 may provide a plurality of memory cells MC1 to MCn together with the channel structure CH.

[0019] The plurality of gate electrode layers 130 may be divided into a plurality of portions by a common source line 151 and a spacer 109 disposed on a sidewall of the common source line 151. The common source line 151 may be formed of a conductive material (e.g., metal, metal compound, polysilicon, etc.) and may be electrically connected to a source region 103 in the substrate 101. The source region 103 may be provided as a source region of a ground selection transistor GST. The common source line 151 may be electrically isolated from the plurality of gate electrode layers 130 by the spacer 109.

[0020] The plurality of channel structures CH and the dummy channel structures DCH may be arranged in a direction perpendicular to the upper surface of the substrate 101 (eg, in Figure 3 The channel structures CH may include a channel region 110, an embedded insulating layer 115 filling an inner space of the channel region 110, a drain region 113 disposed on the channel region 110, a gate insulating layer 160 disposed between the channel region 110 and the gate electrode layer 130, and the like. The gate insulating layer 160 may include a tunnel layer, a charge storage layer, a blocking layer, and the like, and at least a portion of the gate insulating layer 160 may surround the gate electrode layer 130. According to example embodiments, the channel region 110 may be columnar (e.g., cylindrical or prismatic) and may not have the embedded insulating layer 115. In addition, each channel structure CH may have an inclined side surface (e.g., a tapered sidewall) that narrows toward the substrate 101 according to an aspect ratio.

[0021] The plurality of channel structures CH and the dummy channel structures DCH may be separated from each other on the xy plane. According to example embodiments, various changes may be made to the number and arrangement type of the plurality of channel structures CH and the dummy channel structures DCH. For example, the plurality of channel structures CH and the dummy channel structures DCH may be arranged in a zigzag pattern in at least one direction. Figure 3 The example embodiment shows that the plurality of channel structures CH are symmetrical to each other about the isolation insulating layer 155 therebetween (e.g., only through the first string selection line 138), and the plurality of dummy channel structures DCH pass through the isolation insulating layer 155. Alternatively, the isolation insulating layer 155 may extend through the string selection lines 137 and 138, and / or the plurality of channel structures CH may be asymmetrical.

[0022] The channel region 110 may be electrically connected to the substrate 101 via the epitaxial layer 105 disposed thereunder. The channel region 110 may include a semiconductor material (eg, polycrystalline silicon or single crystal silicon), and the semiconductor material may be undoped or may be doped with P-type impurities or N-type impurities. The epitaxial layer 105 may be a layer grown using a selective epitaxial growth (SEG) process. The epitaxial layer 105 may be recessed into the substrate 101 to a predetermined depth, such as Figure 3 shown.

[0023] In order to increase the capacity of the memory device 100, the number of gate electrode layers 130 stacked on the substrate 101 has been increased. As the number of gate electrode layers 130 increases, the aspect ratio of the channel region 110 is also increased. Therefore, in this case, the area deviation in the direction perpendicular to the upper surface of the substrate 101 may increase. The area deviation of the channel region may cause a difference in characteristics of the plurality of memory cells MC1 to MCn.

[0024] In example embodiments, a programming method may be provided that may compensate for characteristic differences of memory cells MC1 to MCn that occur due to various factors including an increase in the number of gate electrode layers 130. In the programming method according to example embodiments, a first programming operation and a second programming operation may be sequentially performed, and the magnitude of a programming voltage used in the first programming operation may be differently determined in consideration of the characteristic differences of memory cells MC1 to MCn.

[0025] FIG. 4A to FIG. 5B is a diagram of operations in a programming method of a memory device according to an example embodiment. FIG. 4A to FIG. 5B The memory cells of the memory device in the example embodiment may be multilevel cells that can store 2-bit data, respectively, but the example embodiment may also be applied to memory cells that can store more than 3-bit data.

[0026] Reference Figure 4A and Figure 4B In the case of a memory device according to example embodiments, data may be stored in a memory cell by sequentially performing a first programming operation and a second programming operation. In example embodiments, the first programming operation and the second programming operation may be performed using a programming method (eg, incremental step pulse program (ISPP) etc.).

[0027] Figure 4A 2 is a diagram showing a first programming operation. Figure 4A By inputting a program voltage to the memory cell to be programmed, the memory cell in the erase state ES may be moved to one of the first pre-state PS1 and the second pre-state PS2. In example embodiments, the first pre-state PS1 may be a state such as the erase state ES, and may indicate a threshold voltage distribution of memory cells that do not store data.

[0028] For example, refer to Figure 4B, when the first programming operation is completed, the memory device may perform a second programming operation to move the memory cell having the first pre-state PS1 to the first state S1 or the second state S2, or to move the memory cell having the second pre-state PS2 to the third state S3 or the fourth state S4. For example, when each memory cell can store 2 bits of data, the first state S1 to the fourth state S4 may correspond to data 00, 01, 10, and 11, respectively.

[0029] Before performing the second programming operation, the memory device may set the intermediate read voltage V IR is input to the memory cell to determine the state of the relevant memory cell as one of the first pre-state PS1 and the second pre-state PS2. In order to accurately determine the state of the relevant memory cell, the intermediate read voltage V IR The value of may be located between the threshold voltage distribution of the first pre-state PS1 and the threshold voltage distribution of the second pre-state PS2.

[0030] Reference Figure 5A and Figure 5B , in the case of a memory device according to example embodiments, data may be stored in a memory cell by sequentially performing a first program operation and a second program operation. Figure 5A is a diagram showing a first programming operation. Figure 5A By inputting a programming voltage to the memory cell to be programmed, the memory cell in the erase state ES can be moved to any one of the first to fourth pre-states PS1 to PS4. For example, the first to fourth pre-states PS1 to PS4 can correspond to data 00, 01, 10, and 11, respectively.

[0031] For example, when the first programming operation is completed, the memory device may adjust the threshold voltage distribution of the memory cells having any one of the first to fourth pre-states PS1 to PS4 to perform the second programming operation so that the threshold voltage distribution of the memory cells may have any one of the first to fourth pre-states S1 to S4. Figure 5B , each of the first to fourth pre-states PS1 to PS4 that the memory cell may have may be changed to the first to fourth states S1 to S4 respectively by the second programming operation. Compared with the distribution of the first to fourth pre-states PS1 to PS4, the first to fourth states S1 to S4 may have a relatively narrow distribution respectively. Therefore, it is possible to ensure that the margin for accurately reading the data of the memory cell is relatively large.

[0032] As described above, as the number of gate electrode layers stacked in a memory device increases and the structure of the memory device becomes complicated, characteristic differences between memory cells may occur. If the same programming voltage is input without considering the characteristic differences between memory cells, the threshold voltage distributions of the memory cells may overlap or the blank area between the threshold voltage distributions may decrease. Therefore, data may not be accurately read.

[0033] In example embodiments, for example, when a first programming operation is performed on a program memory cell to be programmed, the size of a programming voltage input to a programming word line that provides a programming voltage to the program memory cell may be different based on information about the program memory cell. For example, the information about the program memory cell may be a physical location of the program memory cell, and may include the location of the programming word line, the location of a channel region that provides the program memory cell, the location of a string selection line that shares a channel region with the program memory cell, and the like.

[0034] Figures 6 to 8 is a diagram showing a memory device according to an example embodiment. Figures 6 to 8 The described memory device 200 may include a channel region 210 extending in a direction (eg, z-axis direction) perpendicular to an upper surface of a substrate 201. The channel region 210 may be cylindrical with an empty center portion, and an inner space of the channel region 210 may be filled with an embedded insulating layer 205.

[0035] Reference Figures 6 to 8 , a memory device according to example embodiments may include, for example, a plurality of word lines WL1 to WLn stacked one on another in the z-axis direction and adjacent to the channel region 210, string selection lines SSL1 and SSL2 adjacent to the word line WLn, and a ground selection line GSL adjacent to the word line WL1, etc. In example embodiments, the ground selection line GSL may be adjacent to the epitaxial layer 204, but not adjacent to the channel region 210. Therefore, the structure of the ground selection transistor GST may be different from that of the string selection transistors SST1 and SST2 (string selection transistors SST) and the memory cells MC1 to MCn (memory cells MC).

[0036] The memory cells MC may be connected in series with each other between the string selection transistor SST and the ground selection transistor GST. Figures 6 to 8 In the illustrated example embodiment, n memory cells MC are shown to be connected to each other between the string selection transistor SST and the ground selection transistor GST, and the number of memory cells MC may be variously modified.

[0037] The drain region 203 may be formed of a conductive material and may be located adjacent to the string selection transistor SST on the channel region 210, and the source region 202 doped with impurities may be formed in the substrate 201. The drain region 203 and the source region 202 may be connected to the bit line BL and the common source line CSL, respectively. A gate insulating layer 220 including a charge storage layer may be disposed between the channel region 210 and the plurality of word lines WL1 to WLn.

[0038] For example, Figure 6 As shown, the memory cell MC may have a gate insulating layer 220 whose thickness decreases toward the substrate 201. Specifically, as shown in FIG. Figure 6 As shown, the thickness of the embedded insulating layer 205 may be constant along the z-axis direction, and the thickness of the channel region 210 and the gate insulating layer 220 may gradually decrease from the drain region 203 toward the epitaxial layer 204 along the z-axis direction.

[0039] As mentioned above FIG. 4A to FIG. 5B As described, the programming operation according to the example embodiment may include a first programming operation and a second programming operation performed sequentially. For example, when the first programming operation is performed, a first programming voltage may be input to a programming memory cell to be programmed, and when the second programming operation is performed, a second programming voltage may be input to the programming memory cell to be programmed. The first programming voltage and the second programming voltage may have different values.

[0040] In example embodiments, the value of the first programming voltage may be determined differently based on information about the program memory cell. The information about the program memory cell may be information indicating a threshold voltage distribution that varies according to a location of the program memory cell (e.g., a physical location of the program memory cell). In addition, the physical location of the program memory cell may include a location of a program word line providing the program memory cell, a location of a channel region providing the program memory cell together with the program word line, a location of a string selection line sharing the channel region with the program word line, and the like.

[0041] Reference Figure 6 In example embodiments, the first programming voltage may be adjusted according to the position of a programming word line that supplies a programming voltage to a programming memory cell, for example, according to the proximity of the programming word line to the substrate 201. The thickness of the gate insulating layer 220 and the thickness of the charge storage layer included in the programming memory cell may vary according to the distance between the programming word line and the substrate 201, and thus the first programming voltage may be adjusted in consideration of the thickness of the gate insulating layer 220.

[0042] Reference Figure 7, the first programming voltage may be adjusted according to whether the program memory cell is included in the first memory cell string MCS1 or the second memory cell string MCS2. That is, the first programming voltage may be determined in consideration of the positions of the string selection lines SSL1 and SSL2 that share the channel region with the program memory cell. Therefore, the first programming voltage input to the memory cell MC included in the first area unit UA1 may be different from the first programming voltage input to the memory cell MC included in the second area unit UA2. The first area unit UA1 and the second area unit UA2 may be defined by the isolation insulating layer 232.

[0043] Reference Figure 8 , the first memory cell string MCS1 and the second memory cell string MCS2 may also be defined by their distances from the vertical spacer 231 or the common source line 230, wherein the common source line 230 is connected to the source region 202 while dividing the plurality of word lines WL1 to WLn into a plurality of regions. In the memory device, the first programming voltage may be adjusted according to which of the first memory cell string MCS1 and the second memory cell string MCS2 includes a program memory cell.

[0044] Fig.9A , Fig. 9B , Fig. 10A and Fig. 10B is a diagram illustrating threshold voltage distributions of memory cells included in a memory device according to example embodiments.

[0045] First, according to Fig.9A and Fig. 9B In the case of the programming method of the example embodiment shown in , in a multi-level cell (MLC) mode in which two or more data bits are stored in one memory cell, a lower bit may be stored in the memory cell by a first programming operation, and an upper bit may be stored in the memory cell by a second programming operation. Therefore, the programming method may be a shadow programming method. Fig.9A and Fig. 9B is a diagram illustrating a programming method of respective programming memory cells located at different positions in a memory device.

[0046] First, refer to Fig.9A , a first program operation may be performed by inputting a first program voltage to the first program memory cell PMC1 in the erase state 300. The threshold voltage of the first program memory cell PMC1 may be changed to the first pre-state 305 or the second pre-state 306 by the first program operation. For example, the first pre-state 305 may be the same as the erase state 300.

[0047] The memory device can be read by setting the first intermediate read voltage V IR1The first programming memory cell PMC1 is input to the first programming memory cell PMC1 to identify the low bit written to the first programming memory cell PMC1 by the first programming operation. The memory device may perform a second programming operation of inputting a second programming voltage to the first programming memory cell PMC1. Through the second programming operation, the state of the first programming memory cell PMC1 may be changed from the first pre-state 305 to the first state 301 or the second state 302, or the state of the first programming memory cell PMC1 may be changed from the second pre-state 306 to the third state 303 or the fourth state 304.

[0048] For example, when the second programming operation is completed, the memory device may input one of the first to third read voltages R1 to R3 to the first program memory cell PMC1 to verify the success or failure of programming, or read data from the first program memory cell PMC1. The first to fourth states 301 to 304 may correspond to data 00, 01, 10, and 11, respectively.

[0049] On the other hand, the memory device according to the example embodiment may include a flag cell indicating the number of bits of data written to the first program memory cell PMC1. For example, the flag cell may be a memory cell operated in a single-level cell (SLC) mode. The memory device may determine the number of bits of data stored in the first program memory cell PMC1 by inputting a second read voltage R2 among the first read voltage R1 to the third read voltage R3 to the flag cell. For example, when two bits are written in the first program memory cell PMC1, the flag cell may have a state 307.

[0050] Next, refer to Fig. 9B , a first programming operation may be performed by inputting a first programming voltage to the second programming memory cell PMC2 in the erased state 310. The second programming memory cell PMC2 may be located at a position different from that of the first programming memory cell PMC1, and a threshold voltage distribution of the second programming memory cell PMC2 may be different from that of the first programming memory cell PMC1. Therefore, the first programming voltage input to the second programming memory cell PMC2 may be different from the first programming voltage input to the first programming memory cell PMC1.

[0051] In reference Figure 6 In the example described in the exemplary embodiment of the present invention, the first program storage cell PMC1 may be a storage cell located adjacent to the drain region 203, and the second program storage cell PMC2 may be a storage cell located adjacent to the substrate 201. Alternatively, the first program storage cell PMC1 may be a storage cell located adjacent to the substrate 201, and the second program storage cell PMC2 may be a storage cell located adjacent to the drain region 203. Figure 7 and Figure 8Taking the example embodiment shown in FIG. 2 as an example, one of the first program memory cell PMC1 and the second program memory cell PMC2 may be included in the first memory cell string MCS1, and the other may be included in the second memory cell string MCS2.

[0052] The threshold voltage of the second program memory cell PMC2 may be changed to the first pre-state 315 or the second pre-state 316 through the first program operation. For example, the first pre-state 315 may be the same as the erase state 310. The memory device may be configured to store the second intermediate read voltage V IR2 The second programming memory cell PMC2 is input to the second programming memory cell PMC2 to identify the low bit written to the second programming memory cell PMC2. The memory device can perform a second programming operation of inputting a second programming voltage to the second programming memory cell PMC2. Through the second programming operation, the state of the second programming memory cell PMC2 can be changed from the first pre-state 315 to the first state 311 or the second state 312, or the state of the second programming memory cell PMC2 can be changed from the second pre-state 316 to the third state 313 or the fourth state 314.

[0053] Since the first programming voltages input to the first program memory cell PMC1 and the second program memory cell PMC2 are different from each other, the first pre-state 305 and the second pre-state 306 of the first program memory cell PMC1 may be different from the first pre-state 315 and the second pre-state 316 of the second program memory cell PMC2, respectively. IR2 It can also be different from the first intermediate reading voltage V IR1 , and the first to fourth states 311 to 314 of the second program memory cell PMC2 may be different from the first to fourth states 301 to 304 of the first program memory cell PMC1, respectively.

[0054] As a result, the first to third read voltages R1' to R3' of the second program memory cell PMC2 may be different from the first to third read voltages R1 to R3 of the first program memory cell PMC1, respectively. The flag cell may be a memory cell indicating the number of bits of data written to the second program memory cell PMC2. For example, when two bits are written in the second program memory cell PMC2, the flag cell may have a state 317.

[0055] Then, according to Fig. 10A and Fig. 10B In the case of the programming method of the example embodiment shown in , in the MLC mode where two or more data bits are stored in one memory cell, by sequentially performing a first programming operation and a second programming operation, two or more data bits can be stored in one memory cell. Fig.9A and Fig. 9BIn a different manner from the example embodiment of the present invention, the same number of data bits may be stored in the memory cell through the first programming operation and the second programming operation. Therefore, the programming method may be a reprogramming method. Fig. 10A and Fig. 10B is a diagram illustrating a programming method of respective programming memory cells located at different positions in a memory device.

[0056] Reference Fig. 10A , a first program operation may be performed by inputting a first program voltage to the first program memory cell PMC1 set to the erase state 320. The threshold voltage of the first program memory cell PMC1 may be changed to any one of the first to fourth pre-states 325 to 328 by the first program operation. For example, the first pre-state 325 may be the same as the erase state 320.

[0057] After the first programming operation, the memory device may perform a second programming operation of inputting a second programming voltage to the first programming memory cell PMC1. Through the second programming operation, the state of the first programming memory cell PMC1 may be changed to any one of the first state 321 to the fourth state 324. The first state 321 to the fourth state 324 may respectively have a relatively narrow threshold voltage distribution compared to the first pre-state 325 to the fourth pre-state 328. Therefore, a relatively large blank area may be ensured in the threshold voltage distribution of the first programming memory cell PMC1 through the second programming operation.

[0058] For example, when the second programming operation is completed, the memory device may input one of the first to third read voltages R1 to R3 to the first program memory cell PMC1 to verify the success or failure of programming, or read data from the first program memory cell PMC1. The first to fourth states 321 to 324 may correspond to data 00, 01, 10, and 11, respectively.

[0059] Next, refer to Fig. 10B , a first program operation may be performed by inputting a first program voltage to the second program memory cell PMC2 in the erase state 330. The second program memory cell PMC2 may be a memory cell having a threshold voltage distribution different from that of the first program memory cell. In example embodiments, the first program voltage input to the second program memory cell PMC2 may be different from the first program voltage input to the first program memory cell PMC1.

[0060] Describe an example, see Figure 6In the example embodiment shown, the first program memory cell PMC1 or the second program memory cell PMC2 may be a memory cell arranged adjacent to the drain region 203, and the remaining program memory cell may be a memory cell arranged adjacent to the substrate 201. Figure 7 and Figure 8 Taking the illustrated example embodiment as an example, one of the first program memory cell PMC1 and the second program memory cell PMC2 may be included in the first memory cell string MCS1 , and the other may be included in the second memory cell string MCS2 .

[0061] The threshold voltage of the second program memory cell PMC2 may be changed to any one of the first pre-state 335 to the fourth pre-state 338 by the first program operation. For example, the first pre-state 335 may be the same as the erase state 330. The memory device may perform a second program operation of inputting a second program voltage to the second program memory cell PMC2. Through the second program operation, the state of the second program memory cell PMC2 may be changed to any one of the first state 331 to the fourth state 334. Similar to the case of the first program memory cell PMC1, the first state 331 to the fourth state 334 may have a relatively narrow threshold voltage distribution, respectively, compared to the first pre-state 335 to the fourth pre-state 338. Therefore, a relatively large blank area may be ensured in the threshold voltage distribution of the first program memory cell PMC1 by the second program operation.

[0062] Since the first programming voltage input to the first program memory cell PMC1 and the first programming voltage input to the second program memory cell PMC2 may be different from each other, the preliminary states 325 to 328 of the first program memory cell PMC1 and the preliminary states 335 to 338 of the second program memory cell PMC2 may be different from each other, respectively. Therefore, after the second program operation is completed, the first state 331 to the fourth state 334 of the second program memory cell PMC2 may be different from the first state 321 to the fourth state 324 of the first program memory cell PMC1, respectively.

[0063] As a result, the first to third read voltages R1' to R3' for the second program memory cell PMC2 may also be respectively different from the first to third read voltages R1 to R3 for the first program memory cell PMC1. For example, in example embodiments, considering the threshold voltage characteristics of the respective program memory cells PMC1 and PMC2, first program voltages different from each other may be used. Therefore, the read voltages used for program verification or read operations for the respective program memory cells PMC1 and PMC2 may also be determined to be different from each other.

[0064] Fig.11is a schematic diagram of a structure of a memory device according to example embodiments. Fig.11 is a partial perspective view of a memory cell array included in the memory device 400 .

[0065] Reference Fig.11 , a memory device 400 according to example embodiments may include a substrate 401, an upper surface (eg, Fig.11 4. The embodiment of the present invention may include a plurality of channel structures CH and a plurality of dummy channel structures DCH vertically (e.g., along the z-axis direction) to the xy plane of the example embodiment shown in FIG. 4, a plurality of gate electrode layers 431 to 439 (gate electrode layer 430) stacked on the substrate 401 adjacent to the channel structures CH, etc. The plurality of gate electrode layers 430 may be alternately stacked with a plurality of insulating layers 441 to 449 (insulating layer 440), for example, along the z-axis direction, and some of the gate electrode layers (e.g., gate electrode layers 438 and 439) may be divided into a plurality of parts by the isolation insulating layer 455.

[0066] exist Fig.11 In the illustrated example embodiment, the channel region 410 may include a lower channel region 410A and an upper channel region 410B. The lower channel region 410A may be connected to the upper channel region 410B. The gate electrode layer 436 adjacent to the boundary between the lower channel region 410A and the upper channel region 410B may provide a pseudo memory cell DMC. Compared to other memory cells MC1 to MCn, in the pseudo memory cell DMC, a programming operation may not be performed. When the channel region 410 is divided into the lower channel region 410A and the upper channel region 410B, process problems caused by an increase in the number of stages of the memory device 400 may be reduced or prevented.

[0067] The components other than the channel region 410 and the dummy memory cell DMC may be Figure 3 The components of the memory device 100 shown are similar. The gate electrode layer 430 may be divided into a plurality of regions by the common source line 451 and the spacer 409, and the common source line 451 may be connected to the source region 403 formed in the substrate 401. A gate insulating layer 420 may be formed between the channel region 410 and the gate electrode layer 430. The gate insulating layer 420 may include a plurality of layers, and a portion of the gate insulating layer 420 may also be separately formed on the outer side of the channel region 410 and on the corresponding outer side of the gate electrode layer 430.

[0068] Fig.12 is a view illustrating a memory device according to example embodiments. Fig.12 Is from Fig.11 4. A view of a single memory cell string of the memory device 400 is shown in FIG.

[0069] Reference Fig.12, a memory device according to example embodiments may include a plurality of word lines WL1 to WLn stacked on each other (e.g., along the z-axis direction) and adjacent to a channel region 410, string selection lines SSL1 and SSL2 adjacent to the word line WLn, and a ground selection line GSL adjacent to the word line WL1, etc. In example embodiments, the ground selection line GSL may be adjacent to the epitaxial layer 411 instead of the channel region 410. Therefore, the structure of the ground selection transistor GST may be different from that of the string selection transistors SST1 and SST2 (string selection transistors SST) and the memory cells MC1 to MCn (memory cells MC). The dummy word line DWL may be located between at least a portion of the plurality of word lines WL1 to WLn, and the dummy word line DWL may provide a dummy memory cell DMC.

[0070] The memory cells MC may be connected in series with each other between the string selection transistor SST and the ground selection transistor GST. Fig.12 In the illustrated example embodiment, n memory cells MC and one dummy memory cell DMC are shown to be connected to each other between the string selection transistor SST and the ground selection transistor GST, and the numbers of the memory cells MC and the dummy memory cells DMC may be variously modified.

[0071] The drain region 413 may be formed of a conductive material and may be located on the channel region 410, and a source region 403 doped with impurities may be formed in the substrate 401. The drain region 413 and the source region 403 may be connected to the bit line BL and the common source line CSL, respectively. A gate insulating layer 420 including a charge storage layer may be disposed between the channel region 410 and the plurality of word lines WL1 to WLn. In an example, in a memory cell MC adjacent to the substrate 401, due to a process error, the thickness of the gate insulating layer 420 (ie, 420A) may be relatively thin, for example, thinner than the thickness of the gate insulating layer 420 (ie, 420B) close to the drain region 413.

[0072] Fig.13 is a schematic diagram of a structure of a memory device according to example embodiments. Fig.13 is a partial perspective view of a memory cell array included in the memory device 500 .

[0073] In accordance with Fig.13 In the case of the memory device 500 of the example embodiment shown, a source region may not be formed in the substrate 501. The channel region 510 may have a bent U-shape, and a source region of the ground selection transistor and a drain region of the string selection transistor may be provided by conductive layers 512 and 513 formed at both ends of the channel region 510, respectively.

[0074] Reference Fig.13, a plurality of gate electrode layers 531 to 538 (gate electrode layers 530) and a plurality of insulating layers 541 to 549 (insulating layers 540) may be alternately stacked, for example, along the z-axis direction, and the inside of the channel region 510 may be filled with an embedded insulating layer 515. An interlayer insulating layer 570 may also be formed on the plurality of gate electrode layers 530. A gate insulating layer 520 may be formed between the gate electrode layer 530 and the channel region 510. At least one layer of the plurality of layers included in the gate insulating layer 520 may also be formed along the outside of the channel region 510.

[0075] The gate electrode layer 530 may be divided into a plurality of parts by the isolation insulating layer 550. In example embodiments, the isolation insulating layer 550 may be disposed in a U-shape of the channel region 510 bent in a U-shape. Therefore, the memory device 500 may be implemented in such a manner that a single channel region 510 bent in a U-shape is adjacent to the gate electrode layer 530 divided into a plurality of parts.

[0076] Fig.14 is a view illustrating a memory device according to example embodiments. Fig.14 Is from Fig.13 A view of a single memory cell string of memory device 400 is shown.

[0077] Reference Fig.14 , the gate electrode layer may be divided into a plurality of regions by the isolation insulating layer 550 to provide a plurality of word lines UWL and DWL. In example embodiments, upper word lines UWL1-UWLn (UWL) may be provided between the string selection line SSL and the substrate 501, and lower word lines LWL1 to LWLn (LWL) may be provided between the ground selection line GSL and the substrate 510.

[0078] The upper word line UWL and the lower word line LWL are separated from each other by the isolation insulating layer 550, and thus different memory cells may be provided. The upper word line UWL may provide upper memory cells UMC1 to UMCn (UMC), and the lower word line LWL may provide lower memory cells LMC1 to LMCn (LMC). The channel region 510 may be cylindrical and may be bent into a U-shape, and the gate insulating layer 520 may be disposed along the outer side of the channel region 510. For example, the channel region 510 may extend in the substrate 501 along the x-axis direction and the y-axis direction.

[0079] Refer to above Figures 11 to 14The described memory devices 400 and 500 may be configured to select a program memory cell to store data from the memory cells MC, and sequentially perform a first program operation and a second program operation on the program memory cell, thereby storing data. In an example embodiment, the program voltage input to the program memory cell by the memory device 400 may vary based on information about the respective memory cells MC that may affect the threshold voltage distribution of the memory cells MC. In an example embodiment, the information about the respective memory cells MC may include information indicating the physical location of the respective memory cells MC, for example, the location of a word line, the location of a channel region, the distance to a common source line, etc.

[0080] For example, in Fig.11 and Fig.12 In the example embodiment shown, the programming voltage input to the program memory cell may vary depending on whether the program memory cell selected from the memory cells MC is adjacent to the lower channel region 410A or the upper channel region 410B. Fig.13 and Fig.14 In the example embodiment shown, the program voltage input to the program memory cell may vary depending on whether the program memory cell is included in the upper memory cell UMC or the lower memory cell LMC, which will be referred to in detail. Fig.15A , Fig. 15B , Fig.16A and Fig. 16B Describe them together.

[0081] Fig.15A , Fig. 15B , Fig.16A and Fig. 16B is a diagram illustrating threshold voltage distributions of memory cells included in a memory device according to example embodiments.

[0082] In accordance with Fig.15A and Fig. 15B In the case of the programming method of the illustrated example embodiment, in the MLC mode where more than two data bits are stored in a single memory cell, the lower LSB may be stored in the memory cell by a first programming operation and the upper MSB may be stored in the memory cell by a second programming operation. Fig.15A and Fig. 15B is a diagram illustrating a programming method with respect to respective programming memory cells located at different positions in a memory device.

[0083] First, refer to Fig.15A, a first programming operation may be performed by inputting a first programming voltage to the first programming memory cell PMC1 in the erased state 600, and a second programming operation may be performed by inputting a second programming voltage to the first programming memory cell PMC1. The first programming operation and the second programming operation may be performed sequentially and may be performed similarly to the above reference Fig.9A and Fig. 9B Describes the operation.

[0084] The threshold voltage of the first program memory cell PMC1 may be changed to the first pre-state 605 or the second pre-state 606 through the first program operation. IR1 The first programming memory cell PMC1 is input to identify the lower LSB written in the first programming memory cell PMC1, and a second programming operation of inputting a second programming voltage to the first programming memory cell PMC1 may be performed. Through the second programming operation, the state of the first programming memory cell PMC1 may be changed from the first pre-state 605 to the first state 601 or the second state 602, or may be changed from the second pre-state 606 to the third state 603 or the fourth state 604. The flag cell may be a memory cell indicating the number of bits of data written in the first programming memory cell PMC1. For example, when two bits are written in the first programming memory cell PMC1, the flag cell may have a state 607.

[0085] Then, refer to Fig. 15B , the first program operation and the second program operation may be sequentially performed by sequentially inputting the first program voltage and the second program voltage to the second program memory cell PMC2 in the erase state 610. The second program memory cell PMC2 may be located at a position different from that of the first program memory cell PMC1, and the threshold voltage distribution of the second program memory cell PMC2 may be different from that of the first program memory cell PMC1. Therefore, the first program voltage input to the second program memory cell PMC2 may be different from the first program voltage input to the first program memory cell PMC1.

[0086] Describe an example, see Fig.11 In the example embodiment shown, one of the first program memory cell PMC1 and the second program memory cell PMC2 may be a memory cell provided by the lower channel region 410A, and the other may be a memory cell provided by the upper channel region 410B. Fig.13 In the example embodiment shown, one of the first program memory cell PMC1 and the second program memory cell PMC2 may be one of the upper memory cells UMC, and the other may be one of the lower memory cells LMC.

[0087] Since the first programming voltage and the second programming voltage input to the first programming memory cell PMC1 are respectively different from the first programming voltage and the second programming voltage input to the second programming memory cell PMC2, the first state 601 to the fourth state 604 of the first programming memory cell PMC1 may be respectively different from the first state 611 to the fourth state 614 of the second programming memory cell PMC2. Therefore, the first read voltage R1' to the third read voltage R3' used for the program verification or read operation of the second programming memory cell PMC2 may also be respectively different from the first read voltage R1 to the third read voltage R3 of the first programming memory cell PMC1. The flag cell may be a storage cell indicating the number of bits of data written to the second programming memory cell PMC2. For example, when two bits are written in the second programming memory cell PMC2, the flag cell may have a state 617.

[0088] Then, according to Fig.16A and Fig. 16B In the programming method of the example embodiment shown, in an MLC mode where two or more data bits are stored in a single memory cell, by sequentially performing a first programming operation and a second programming operation, two or more data bits can be stored in the memory cell. Fig.15A and Fig. 15B Unlike the example embodiments of the present invention, the same number of data bits may be stored in memory cells through the first program operation and the second program operation. Fig.16A and Fig. 16B is a diagram illustrating a programming method with respect to first and second program memory cells PMC1 and PMC2 located at different positions in a memory device.

[0089] Reference Fig.16A , a first programming operation and a second programming operation may be sequentially performed on the first programming memory cell PMC1 set in the erase state 620. Through the first programming operation, the threshold voltage of the first programming memory cell PMC1 may be changed to one of the first pre-state 625 to the fourth pre-state 628. On the other hand, through the second programming operation, the state of the first programming memory cell PMC1 may be changed to one of the first state 621 to the fourth state 624. The first state 621 to the fourth state 624 may have a relatively narrow threshold voltage distribution, respectively, compared to the first pre-state 625 to the fourth pre-state 628. Therefore, a relatively large blank area may be ensured in the threshold voltage distribution of the first programming memory cell PMC1 through the second programming operation.

[0090] Then, refer to Fig. 16B, the first program operation and the second program operation may be sequentially performed on the second program memory cell PMC2 set in the erase state 630. The second program memory cell PMC2 may be a memory cell having a threshold voltage distribution different from that of the first program memory cell PMC1. In example embodiments, the first program voltage input to the second program memory cell PMC2 may be different from the first program voltage input to the first program memory cell PMC1.

[0091] Describe an example, see Fig.11 In the example embodiment shown, one of the first program memory cell PMC1 and the second program memory cell PMC2 may be a memory cell provided by the lower channel region 410A, and the other may be a memory cell provided by the upper channel region 410B. Fig.13 In the example embodiment shown, one of the first program memory cell PMC1 and the second program memory cell PMC2 may be one of the upper memory cells UMC, and the other may be one of the lower memory cells LMC.

[0092] Since the first programming voltage and the second programming voltage input to the first programming memory cell PMC1 are respectively different from the first programming voltage and the second programming voltage input to the second programming memory cell PMC2, the first state 621 to the fourth state 624 of the first programming memory cell PMC1 may be respectively different from the first state 631 to the fourth state 634 of the second programming memory cell PMC2. Therefore, the first read voltage R1' to the third read voltage R3' used for the program verification or read operation of the second programming memory cell PMC2 may also be respectively different from the first read voltage R1 to the third read voltage R3 of the first programming memory cell PMC1.

[0093] Fig.17 2 is a diagram illustrating an operation of a memory device according to an example embodiment. Fig.17 , a memory device according to an example embodiment may include a first memory region 700A and a second memory region 700B. The first memory region 700A and the second memory region 700B may have the same structure. In one example, a plurality of word lines included in each of the first memory region 700A and the second memory region 700B may be divided into a plurality of regions by a common source line 730 and a spacer 731, and only a string selection line may be divided into two regions by an isolation insulating layer 732 located between the common source lines 730.

[0094] In an example embodiment, the memory cells included in the first memory area 700A may be respectively operated in the MLC mode to store N-bit data, where N is a natural number. The memory cells included in the second memory area 700B may be operated in the SLC mode to store one-bit data. The first memory area 700A may be an area for storing general data, and the second memory area 700B may be an area for providing an operation of on-chip buffered programming (OBP).

[0095] In example embodiments, N-bit data may be stored in each of the first programming storage cells 710 and 720 of the first storage area 700A, and the N-bit data may be divided for each bit to be stored in the N second programming storage cells 711 to 713 and 721 to 723 of the second storage area 700B. In addition, the positions of the N second programming storage cells 711 to 713 and 721 to 723 in the second storage area 700B may correspond to the positions of the first programming storage cells 710 and 720 in the first storage area 700A.

[0096] exist Fig.17 In the illustrated example embodiment, the memory cells of the first storage area 700A may store three bits of data, and the memory cells of the second storage area 700B may store the data stored in the memory cells of the first storage area 700A bit by bit. For example, the 3-bit program data stored in the first program storage cell 710 of the first storage area 700A may be divided for each bit to be stored in the second program storage cells 711 to 713 respectively included in the first block BLK1 to the third block BLK3. For example, the least significant bit of the program data may be stored in the second program storage cell 711 of the first block BLK1, the middle bit of the program data may be stored in the second program storage cell 712 of the second block BLK2, and the most significant bit of the program data may be stored in the second program storage cell 713 of the third block BLK3. Similarly, the 3-bit program data stored in the first program storage cell 720 of the first storage area 700A may be divided for each bit pair to be stored in the second program storage cells 721 to 723 respectively included in the first block BLK1 to the third block BLK3 of the second storage area 700B.

[0097] The positions of the second programming memory cells 711 to 713 and 721 to 723 may be the same as the positions of the first programming memory cells 710 and 720. For example, when the first programming memory cell 710 is provided by the i-th word line from the substrate, the second programming memory cells 711 to 713 may also be selected as memory cells provided by the i-th word line from the substrate. Since the positions of the channel regions are considered together with the positions of the word lines, the second programming memory cells 711 to 713 and 721 to 723 corresponding to the positions of the first programming memory cells 710 and 720, respectively, may be selected.

[0098] Figures 18A to 18C is a diagram illustrating threshold voltage distributions of memory cells included in a memory device according to example embodiments.

[0099] Fig.18A 700B. The memory cells included in the second memory area 700B may be operated in the SLC mode, respectively. Fig.18A , a first programming operation may be performed on the memory cell set in the erase state 800 to change the threshold voltage distribution of the memory cell to the first pre-state 803 and the second pre-state 804. The memory device may change the threshold voltage distribution of the memory cell to the first state 801 and the second state 802 by performing the second programming operation after the first programming operation. Compared with the threshold voltage distribution of the first pre-state 803 and the second pre-state 804, the first state 801 and the second state 802 may have a relatively narrow threshold voltage distribution, and thus may have a relatively large voltage blanking area.

[0100] Fig.18B and 18C is a diagram showing a threshold voltage distribution based on information about a memory cell included in the second memory area 700B. The information of the memory cell may include information indicating the physical location of the memory cell in each of the first to third blocks BLK1 to BLK3 included in the second memory area 700B. The threshold voltage distribution characteristics may vary according to the physical location of the memory cell. In example embodiments, different programming voltages may be applied to the memory cells in consideration of different threshold voltage distribution characteristics of the memory cells.

[0101] Reference Fig.18B , shown above reference Fig.17 The threshold voltage distribution of each second programming memory cell 711 to 713 is described. Fig. 18C , shown above reference Fig.17 The threshold voltage distribution of each second programming memory cell 721 to 723 is described. Fig.18B and Fig. 18CAs shown, the second programming memory cells 711 to 713 and 721 to 723 may have different threshold voltage distribution characteristics according to the positions of the second programming memory cells. In example embodiments, different programming voltages may be applied to the second programming memory cells 711 to 713 and 721 to 723 in consideration of the positions of the second programming memory cells 711 to 713 and 721 to 723 that may affect the threshold voltage distribution characteristics. Fig.18B and Fig. 18C As shown, the threshold voltage distributions of the second program memory cells 711 to 713 and 721 to 723 may be different from each other, and a sufficient voltage blank area may be ensured.

[0102] In particular, as in Fig.18B As can be seen in FIG. 1 , the second programming storage unit 711 can have a first state 811 and a second state 812, the second programming storage unit 712 can have a first state 821 and a second state 822, and the second programming storage unit 713 can have a first state 831 and a second state 833. Fig. 18C As can be seen in FIG. 1 , the second programmed storage cell 721 may have a first state 841 and a second state 842 , the second programmed storage cell 722 may have a first state 851 and a second state 852 , and the second programmed storage cell 723 may have a first state 861 and a second state 862 .

[0103] When data stored in the first memory area 700A is restored or corrected by referring to data stored by respective memory cells in the second memory area 700B, different read voltages V may be applied thereto according to information about the second programmed memory cells 711 to 713 and 721 to 723. RD1 and V RD2 As described above, different programming voltages may be applied according to the positions of the second programming memory cells 711 to 713 and 721 to 723, and thus, the distribution of the second programming memory cells 711 to 713 and 721 to 723 may be different. Therefore, according to the positions of the second programming memory cells 711 to 713 and 721 to 723, the read voltage V for reading the data stored in the second programming memory cells 711 to 713 and 721 to 723 is RD1 and V RD2 They may also be determined differently from each other.

[0104] Fig.19 is a schematic block diagram of an electronic device including a memory device according to an example embodiment. Fig.19, the electronic device 1000 according to an example embodiment may include a display 1010, an input / output unit 1020, a memory 1030, a port 1040, a processor 1050, etc. Examples of the electronic device 1000 may include a television, a desktop computer, etc., and mobile devices such as a smart phone, a tablet computer, a laptop computer, etc. Components such as the display 1010, the input / output unit 1020, the memory 1030, the port 1040, the processor 1050, etc. may communicate with each other via a bus 1060.

[0105] The memory 1030 may include a memory controller 1031 and a memory cell array 1032, and may receive a command sent by the processor 1050 via a bus 1060 to perform operations such as programming, reading, and erasing operations. Examples of the memory 1030 may include a NAND flash memory device, and may include the memory controller 1031 and the memory cell array 1032. Figure 1 to Figure 1 8 any of the memory devices of the various example embodiments described herein.

[0106] The controllers and other processing features of the embodiments described herein may be implemented with logic, for example, the logic may include hardware, software, or both. When implemented at least in part in hardware, the controllers and other processing features may be, for example, any of a variety of integrated circuits, including but not limited to application specific integrated circuits, field programmable gate arrays, combinations of logic gates, systems on chips, microprocessors, or other types of processing or control circuits.

[0107] When implemented at least in part in software, the controller and other processing features may include, for example, a memory or other storage device for storing codes or instructions to be executed by, for example, a computer, a processor, a microprocessor, a controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be those elements described herein or elements other than those described herein. Because the algorithm forming the basis of the method (or the operation of a computer, a processor, a microprocessor, a controller, or other signal processing device) is described in detail, the code or instructions for implementing the operation of the method embodiment can transform the computer, processor, controller, or other signal processing device into a special processor for performing the method described herein.

[0108] As described above, according to example embodiments, the first programming operation and the second programming operation may be sequentially performed to store data in a programming memory cell to store data, and a programming voltage input to the programming memory cell may be adjusted in the first programming operation based on information indicating characteristics of the programming memory cell. Therefore, degradation of the threshold voltage distribution due to interference between memory cells may be prevented, and the operating characteristics and reliability of the memory device may be improved.

[0109] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only, and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art when filing this application, unless otherwise specifically noted, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes may be made in form and detail without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. A storage device, comprising: A memory cell array, the memory cell array comprising a plurality of word lines, at least one selection line disposed above the plurality of word lines, and a channel region passing through the plurality of word lines and the at least one selection line, the plurality of word lines and the channel region forming a plurality of memory cells; as well as a controller that stores data in a program memory cell among the plurality of memory cells by sequentially performing a first program operation and a second program operation, and determines a program voltage input to a program word line connected to the program memory cell in the first program operation based on information about the program memory cell, The controller stores N-bit data in the programming storage unit, where N is a natural number. The first programming operation includes inputting the programming voltage as a first programming voltage to the programming word line to write the lower bit of the N-bit data into the programming storage unit, and the second programming operation includes inputting a second programming voltage to the programming word line to write the upper bit of the N-bit data into the programming storage unit, The controller determines the magnitude of the first programming voltage based on the position of the at least one selection line that shares the channel region with the programmed storage unit.

2. The memory device according to claim 1, wherein: The memory cell array includes a flag cell indicating a number of bits of data stored in the programmed memory cell, and The controller determines a magnitude of a read voltage for reading information of the flag cell based on a magnitude of the first program voltage.

3. The memory device according to claim 2, wherein: The flag cell is programmed as a single level cell.

4. The memory device according to claim 1, wherein: The controller reads a value of the lower bit written to the program memory cell between the first program operation and the second program operation, and determines a magnitude of a read voltage for reading the value of the lower bit based on a magnitude of the first program voltage.

5. The memory device according to any one of claims 1 to 4, wherein: The magnitude of the first programming voltage is different from the magnitude of the second programming voltage.

6. A storage device, comprising: A memory cell array, the memory cell array comprising a plurality of word lines, at least one selection line disposed above the plurality of word lines, and a channel region passing through the plurality of word lines and the at least one selection line, the plurality of word lines and the channel region forming a plurality of memory cells; as well as a controller that stores data in a program memory cell among the plurality of memory cells by sequentially performing a first program operation and a second program operation, and determines a program voltage input to a program word line connected to the program memory cell in the first program operation based on information about the program memory cell, The controller stores N-bit data in the programming storage unit, where N is a natural number. wherein the first programming operation includes inputting a first programming voltage to the programming word line to write the N-bit data into the programming storage unit, and the second programming operation includes inputting a second programming voltage to the programming word line to write the N-bit data into the programming storage unit, and The controller determines the magnitude of the first programming voltage based on the position of the at least one selection line that shares the channel region with the programmed storage unit.

7. The memory device according to claim 6, wherein: The magnitude of the first programming voltage is different from the magnitude of the second programming voltage.

8. A storage device, comprising: a first storage area, the first storage area comprising a plurality of first storage units; a second storage area, the second storage area comprising a plurality of second storage cells, each of the plurality of second storage cells storing one bit of data; as well as A controller storing N-bit data in a first programming storage unit in the first storage area and dividing the N-bit data into data of each bit to be stored in N second programming storage units in the second storage area, wherein N is a natural number, wherein each position of the second programming storage unit in the second storage area corresponds to a position of the first programming storage unit in the first storage area, wherein the controller sequentially performs a first programming operation and a second programming operation on each of the second programming storage cells to divide the N-bit data into data of each bit and store the divided data in the second programming storage cells, wherein the controller determines the magnitude of a programming voltage input to a second programming word line providing the second programming storage cell in the first programming operation based on information about each of the second programming storage cells, and The information about each of the second programmed memory cells includes a location of a string selection line that shares the channel region with the second programmed memory cell.

9. The memory device according to claim 8, wherein: The second storage area includes N storage blocks, and the second programming storage units are located at the same position in the N storage blocks respectively.

10. The memory device according to claim 8, wherein: The controller determines a magnitude of a read voltage for reading data stored in the second program memory cell based on a magnitude of the program voltage input to the second program word line in the first program operation.

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