Memory device, operating method thereof, and memory system

Abstract

The invention provides a memory device and an operating method thereof, and a memory system. The memory device includes a memory array and a peripheral circuit; the storage array comprises a first finger storage area and a second finger storage area; the first finger storage area and the second finger storage area comprise a plurality of storage unit strings; each storage unit string comprises a first bottom selection transistor; the first bottom selection transistor in the first memory region has a first threshold voltage, and the first bottom selection transistor in the second memory region has a second threshold voltage; the first threshold voltage is smaller than the second threshold voltage; the peripheral circuit is configured to apply a first bias voltage to the first bottom selection transistor in a first pre-charging stage of performing programming verification on the first finger memory region; in a first sensing stage after the first pre-charging stage, applying a second bias voltage to the first bottom selection transistor; the first bias voltage is smaller than the second bias voltage; the second bias voltage is less than the second threshold voltage and greater than the first threshold voltage.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a memory device and an operating method thereof, and a memory system. Background Art

[0002] In order to meet the demand for memory integration, a three-dimensional memory including memory cells arranged in three dimensions has been proposed. However, as the memory integration is further improved, the number of memory cells connected to the same word line in the three-dimensional memory also increases, and the efficiency of programming the memory cells decreases, which in turn has a negative impact on the performance of the memory device. Summary of the invention

[0003] In view of this, embodiments of the present disclosure provide a memory device and an operating method thereof, and a memory system to solve at least one problem existing in the prior art.

[0004] To achieve the above objectives, the technical solution of the embodiment of the present disclosure is implemented as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a memory device, comprising a memory array and a peripheral circuit coupled to the memory array; wherein:

[0006] The memory array includes a first finger storage area and a second finger storage area; the first finger storage area and the second finger storage area each include a plurality of memory cell strings; each of the memory cell strings includes a first bottom selection transistor; the first bottom selection transistor in the first finger storage area has a first threshold voltage, and the first bottom selection transistor in the second finger storage area has a second threshold voltage; the first threshold voltage is less than the second threshold voltage; the peripheral circuit is configured as follows:

[0007] In a first precharge phase of performing a program verification operation on a memory cell in the first finger storage area, applying a first bias voltage to the first bottom selection transistor;

[0008] In a first sensing phase after the first precharge phase, a second bias voltage is applied to the first bottom selection transistor; the first bias voltage is less than the second bias voltage; and the second bias voltage is less than the second threshold voltage and greater than the first threshold voltage.

[0009] In an optional implementation, each of the memory cell strings further includes a second bottom selection transistor, the second bottom selection transistor in the first finger storage area has a third threshold voltage, and the second bottom selection transistor in the second finger storage area has a fourth threshold voltage; the third threshold voltage is greater than the fourth threshold voltage;

[0010] The peripheral circuit is further configured to: apply a first turn-on voltage to the second bottom selection transistor in the first precharging stage and the first sensing stage; the first turn-on voltage is greater than the third threshold voltage.

[0011] In an optional implementation, each of the memory cell strings further includes a third bottom selection transistor; the third bottom selection transistor is located between the first bottom selection transistor and the second bottom selection transistor; the third bottom selection transistor has a fifth threshold voltage;

[0012] The peripheral circuit is further configured to: apply a second turn-on voltage to the third bottom selection transistor in the first precharge phase and the first sensing phase; the second turn-on voltage is greater than the fifth threshold voltage.

[0013] In an optional implementation, the first bias voltage is greater than or equal to the negative second turn-on voltage, and the second bias voltage is less than the second turn-on voltage.

[0014] In an optional embodiment, the memory array further includes a common source line connected to each of the memory cell strings, each of the memory cell strings further includes a fourth bottom selection transistor, the fourth bottom selection transistor is closer to the common source line than the first bottom selection transistor and the second bottom selection transistor; the fourth bottom selection transistor has a sixth threshold voltage;

[0015] The peripheral circuit is further configured to: apply a third turn-on voltage to the fourth bottom selection transistor in the first precharge phase and the first sensing phase; the third turn-on voltage is greater than the sixth threshold voltage.

[0016] In an optional implementation, the first bias voltage is greater than or equal to a negative third conduction voltage, and the second bias voltage is less than the third conduction voltage.

[0017] In an optional implementation, the peripheral circuit is further configured as:

[0018] In a second precharge phase of performing a program verification operation on a memory cell in the second finger storage area, a fourth turn-on voltage is applied to the first bottom selection transistor, and a third bias voltage is applied to the second bottom selection transistor; the fourth turn-on voltage is greater than the second threshold voltage;

[0019] In a second sensing phase after the second pre-charging phase, the fourth turn-on voltage is applied to the first bottom selection transistor, and a fourth bias voltage is applied to the second bottom selection transistor; the third bias voltage is less than the fourth bias voltage; and the fourth bias voltage is less than the third threshold voltage and greater than the fourth threshold voltage.

[0020] In an optional implementation, each of the memory cell strings further includes a top selection transistor; and the peripheral circuit is further configured as:

[0021] In the first precharge phase, turning on the top selection transistor in the first finger storage area;

[0022] In the first sensing phase, the unselected top selection transistors in the first finger storage area are turned off, and the selected top selection transistors in the first finger storage area are turned on;

[0023] In the first precharge phase and the first sensing phase, the top selection transistor in the second finger storage area is turned off.

[0024] In a second aspect, an embodiment of the present disclosure provides a memory system, including:

[0025] At least one memory device according to any one of the above embodiments;

[0026] A controller is coupled to the at least one memory device and is configured to control the memory device.

[0027] In a third aspect, an embodiment of the present disclosure provides an operating method of a memory device, including:

[0028] In a first precharge phase of performing a program verification operation on memory cells in a first finger storage area, applying a first bias voltage to a first bottom selection transistor in each memory cell string;

[0029] In a first sensing phase after the first precharging phase, a second bias voltage is applied to the first bottom selection transistor; the first bias voltage is less than the second bias voltage; the second bias voltage is less than a second threshold voltage of the first bottom selection transistor in the second finger storage area and greater than a first threshold voltage of the first bottom selection transistor in the first finger storage area.

[0030] In an optional implementation, the operation method further includes:

[0031] In the first precharge phase and the first sensing phase, a first turn-on voltage is applied to the second bottom selection transistor in each of the memory cell strings; a third threshold voltage of the second bottom selection transistor in the first finger storage area is greater than a fourth threshold voltage of the second bottom selection transistor in the second finger storage area; and the first turn-on voltage is greater than the third threshold voltage.

[0032] In an optional implementation, the operation method further includes:

[0033] In the first precharge phase and the first sensing phase, a second turn-on voltage is applied to a third bottom selection transistor located between the first bottom selection transistor and the second bottom selection transistor; the second turn-on voltage is greater than a fifth threshold voltage of the third bottom selection transistor.

[0034] In an optional implementation, the first bias voltage is greater than or equal to the negative second turn-on voltage, and the second bias voltage is less than the second turn-on voltage.

[0035] In an optional implementation, the operation method further includes:

[0036] In the first precharge phase and the first sensing phase, a third turn-on voltage is applied to a fourth bottom selection transistor closer to a common source line than the first bottom selection transistor and the second bottom selection transistor; the third turn-on voltage is greater than a sixth threshold voltage of the fourth bottom selection transistor.

[0037] In an optional implementation, the first bias voltage is greater than or equal to a negative third conduction voltage, and the second bias voltage is less than the third conduction voltage.

[0038] In an optional implementation, the operation method further includes:

[0039] In a second precharge phase of program verification of the memory cells in the second finger storage area, a fourth turn-on voltage is applied to the first bottom selection transistor, and a third bias voltage is applied to the second bottom selection transistor; the fourth turn-on voltage is greater than the second threshold voltage;

[0040] In a second sensing phase after the second pre-charging phase, the fourth turn-on voltage is applied to the first bottom selection transistor, and a fourth bias voltage is applied to the second bottom selection transistor; the third bias voltage is less than the fourth bias voltage; and the fourth bias voltage is less than the third threshold voltage and greater than the fourth threshold voltage.

[0041] In an optional implementation, the operation method further includes:

[0042] In the first precharge phase, turning on the top selection transistor in the first finger storage area;

[0043] In the first sensing phase, the unselected top selection transistors in the first finger storage area are turned off, and the selected top selection transistors in the first finger storage area are turned on;

[0044] In the first precharge phase and the first sensing phase, the top selection transistor in the second finger storage area is turned off.

[0045] In the technical solution provided in the present disclosure, a storage array in a memory device includes a first finger storage area and a second finger storage area divided based on a threshold voltage of a first bottom selection transistor, and a peripheral circuit is configured to apply a first bias voltage to the first bottom selection transistor in a pre-charging stage of performing a programming verification operation on a storage cell in the first finger storage area, and apply a second bias voltage to the first bottom selection transistor in a sensing stage after the pre-charging stage, wherein the first bias voltage is lower than the second bias voltage, thereby weakening the tendency of the voltage on the first bottom selection transistor to drift upward due to a coupling effect, so that the actual voltage on the first bottom selection transistor can be stabilized near the second bias voltage, and the first bottom selection transistor in the second finger storage area is kept in an off state, thereby reducing the drift of the threshold voltage of the storage cell in the second finger storage area due to a hot carrier injection effect, thereby improving the efficiency of the programming verification operation, and further improving the efficiency and reliability of the programming operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 A schematic diagram of an exemplary system having a memory system provided for an embodiment of the present disclosure;

[0047] Figure 2 A schematic diagram of an exemplary memory card having a memory system provided for an embodiment of the present disclosure;

[0048] Figure 3 A schematic diagram of an exemplary solid state drive having a memory system provided for an embodiment of the present disclosure;

[0049] Figure 4 A schematic diagram of an exemplary memory device including peripheral circuits provided for an embodiment of the present disclosure;

[0050] Figure 5 A cross-sectional schematic diagram of a memory array including a memory cell string provided in an embodiment of the present disclosure;

[0051] Figure 6 A schematic diagram of an exemplary memory device including a memory array and peripheral circuits provided for an embodiment of the present disclosure;

[0052] Figure 7 A schematic diagram of a storage array in a memory device provided by an embodiment of the present disclosure;

[0053] Figure 8 A schematic diagram of distribution of threshold voltages of a first bottom selection transistor and a second bottom selection transistor provided in an embodiment of the present disclosure;

[0054] Fig. 9 A circuit diagram of a storage array provided in an embodiment of the present disclosure Figure 1 ;

[0055] Fig.10 A voltage curve 1 for performing a program verification operation on a memory cell in a first finger storage area provided by an embodiment of the present disclosure;

[0056] Fig.11 A circuit diagram of a storage array provided in an embodiment of the present disclosure Figure 2 ;

[0057] Fig.12 A voltage curve 2 for performing a program verification operation on a memory cell in a first finger storage area provided by an embodiment of the present disclosure;

[0058] Fig.13 A voltage curve for performing a program verification operation on a memory cell in a second finger storage area provided by an embodiment of the present disclosure;

[0059] Fig.14 A flowchart of an operating method of a memory device provided in an embodiment of the present disclosure is provided. DETAILED DESCRIPTION

[0060] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0061] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0062] In the drawings, like reference numerals refer to like elements throughout.

[0063] It should be understood that spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial description terms used herein are interpreted accordingly.

[0064] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0065] Figure 1 Schematic diagram of an exemplary system with a memory device provided in an embodiment of the present disclosure. In an embodiment of the present disclosure, the system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. Figure 1 As shown in , the system 100 may include a host device 101 and a memory system 102, and the memory system 102 may include one or more memory devices 103 and a memory controller 104. The host device 101 may include a processor of an electronic device, such as a central processing unit (CPU), or a system on a chip (SoC), such as an application processor (AP). The host device 101 may be configured to send data to the memory system 102 or receive data from the memory system 102.

[0066] In some embodiments, the memory controller 104 is coupled to the memory device 103 and the host device 101 and is configured to control the memory device 103. The memory controller 104 can manage the data stored in the memory device 103 and communicate with the host device 101. In some embodiments, the memory controller 104 is designed to operate in a low duty cycle environment, such as in a Secure Digital Memory Card (SD card), a Compact Flash Card (CFC), a Universal Serial Bus (USB) flash drive, or in other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In other embodiments, the memory controller 104 is designed to operate in a high duty cycle environment, such as a Solid State Drive (SSD) or an Embedded Multi-Media Card (eMMC).

[0067] The memory controller 104 may be configured to control the operation of the memory device 103, such as read, erase, and program operations. The memory controller 104 may also be configured to manage various functions regarding data stored or to be stored in the memory device 103, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 104 is also configured to process error correction codes regarding data read from or written to the memory device 103. The memory controller 104 may also perform any other suitable functions, such as formatting the memory device 103.

[0068] In some embodiments, the memory controller 104 and the one or more memory devices 103 may be integrated into various types of storage devices, that is, the memory system 102 may be implemented and packaged into different types of terminal electronic products.

[0069] In such Figure 2In one example shown in , the memory controller 104 and the single memory device 103 can be integrated into the memory card 201. The memory card 201 can be a compact flash card, a smart media card (Smart Media Card, SMC), a memory stick (Memory Stick, MS), a multimedia card (Multi-Media Card, MMC), such as RS-MMC, MMCmicro, eMMC, etc., a secure digital card, such as Mini SD card, Micro SD card, SDHC card, etc., a universal flash storage (UFS) card. The memory card 201 can also include a device that connects the memory card 201 to a host device (e.g., Figure 1 The host device 101 in the embodiment of the present invention is coupled to the memory card connector 202. Figure 3 In another example shown in , the memory controller 104 and the plurality of memory devices 103 may be integrated into the SSD 203. The SSD 203 may also include a processor that connects the SSD 203 to a host device (eg, Figure 1 In some embodiments, the storage capacity and / or operating speed of SSD203 is greater than the storage capacity and / or operating speed of memory card 201.

[0070] Figure 4 A circuit diagram of an exemplary memory device 300 including peripheral circuits is provided for some embodiments. The memory device 300 may be Figure 1 300 is an example of a memory device 103 in FIG. The memory device 300 may include a memory array 301 and a peripheral circuit 302 coupled to the memory array 301. The memory array 301 is taken as a three-dimensional NAND type memory array for illustration, wherein the memory cells 305 are NAND memory cells, and the memory cells 305 are provided in the form of an array of memory cell strings 304, each memory cell string 304 extending vertically above a substrate (not shown). In some embodiments, each memory cell string 304 includes a plurality of memory cells 305 coupled in series and stacked vertically. Each memory cell 305 may hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 305. Each memory cell 305 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0071] In some embodiments, each memory cell 305 is a single level cell (SLC) having two possible memory states and thus can store one bit of data. For example, the first memory state "0" can correspond to a first voltage range, and the second memory state "1" can correspond to a second voltage range. In some embodiments, each memory cell 303 is a multi-level cell capable of storing more than a single bit of data in four or more memory states, for example, a multi-level cell (MLC) storing two bits per cell, a triple level cell (TLC) storing three bits per cell, or a quad-level cell (QLC) storing four bits per cell.

[0072] like Figure 4 As shown in , each memory cell string 304 may include a bottom select transistor (Bottom Select Gate, BSG) 307 at its source terminal and a top select transistor (Top Select Gate, TSG) 306 at its drain terminal. The bottom select transistor 307 and the top select transistor 306 may be configured to activate the selected memory cell string 304 during read and program operations. In some embodiments, the sources of the memory cell strings 304 in the same memory block 303 may be coupled through a common source line (Common Source Line, CSL) 310. In other words, all memory cell strings 304 in the same memory block 303 have a common source (Array Common Source, ACS). According to some embodiments, the top select transistor 306 of each memory cell string 304 is coupled to a corresponding bit line (Bit Line, BL) 311, and data can be read or written from the bit line 311 via an output bus (not shown). In some embodiments, each memory cell string 304 is configured to be selected or deselected by applying a selection voltage (e.g., a voltage higher than a threshold voltage of a top select transistor 306) or a deselection voltage (e.g., 0 V) ​​to a corresponding top select transistor 306 via one or more top select lines (TSL) 303 and / or by applying a selection voltage (e.g., a voltage higher than a threshold voltage of a bottom select transistor 307) or a deselection voltage (e.g., 0 V) ​​to a corresponding bottom select transistor 307 via one or more bottom select lines (BSL) 309.

[0073] like Figure 4As shown in , the memory cell string 304 can be organized into a plurality of memory blocks 303, each of which can have a common source line (Common Source Line, CSL) 310. In some embodiments, each memory block 303 is a basic data unit for an erase operation, that is, all memory cells 305 on the same memory block 303 are erased at the same time. In order to erase the memory cells 305 in the selected memory block, the common source line 310 coupled to the selected memory block and the unselected memory blocks in the same plane as the selected memory block can be biased with an erase voltage. It should be understood that in some examples, the erase operation can be performed at a half-memory block level, at a quarter-memory block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 305 of adjacent memory cell strings 304 can be coupled by word lines 312, which select which row of memory cells 305 is affected by a read or program operation.

[0074] Figure 5 A cross-sectional schematic diagram of a memory array including a memory cell string provided in an embodiment of the present disclosure. Figure 5 As shown, the memory array may include a stacked structure 400, which includes a plurality of gate layers 401 and a plurality of insulating layers 402 that are alternately stacked in sequence, and a channel structure 403 that vertically penetrates the gate layers 401 and the insulating layers 402. The gate layers 401 and the insulating layers 402 may be alternately stacked, and two adjacent gate layers 401 are separated by an insulating layer 402. The number of memory cells included in the memory array is mainly related to the number of pairs of gate layers 401 and insulating layers 402 in the stacked structure 400.

[0075] The constituent material of the gate layer 401 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 401 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 401 includes a doped polysilicon layer. Multiple gate layers 401 surround a channel structure 403 to form a memory cell string. The gate layer 401 at the top of the stacked structure 400 can extend laterally as a top selection line, the gate layer 401 at the bottom of the stacked structure 400 can extend laterally as a bottom selection line, and the gate layer 401 extending laterally between the top selection line and the bottom selection line can serve as a word line layer.

[0076] In some embodiments, the stacked structure 400 may be disposed on a substrate 404. The substrate 404 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0077] In some embodiments, the channel structure 403 includes a functional layer, a channel layer, and an insulating filling layer. In some embodiments, the channel layer includes silicon, for example, polycrystalline silicon. In some embodiments, the functional layer is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge capture / storage layer"), and a barrier layer. The channel structure 403 may have a cylindrical shape (e.g., a column shape). According to some embodiments, the channel layer, the tunneling layer, the storage layer, and the barrier layer are radially arranged in this order from the center of the column toward the outer surface of the column. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the functional layer may include a silicon oxide / silicon oxynitride / silicon oxide (ONO) composite layer.

[0078] Return to reference Figure 4 , the peripheral circuit 302 may be coupled to the memory array 301 through the bit line 311, the word line 312, the common source line 310, the bottom selection line 309, and the top selection line 308. The peripheral circuit 302 may include any suitable analog, digital, and mixed signal circuits for applying a voltage signal and / or a current signal to each target memory cell 305 through the bit line 311, the word line 312, the common source line 310, the bottom selection line 309, and the top selection line 308, and sensing a voltage signal and / or a current signal from each target memory cell 305 to implement the operation of the memory array 301. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor technology. For example, Figure 6 Some exemplary peripheral circuits are shown, and the peripheral circuit 302 includes a page buffer / sense amplifier 501, a column decoder / bit line driver 502, a row decoder / word line driver 503, a voltage generator 504, a control logic unit 505, a register 506, a flash memory interface 507, and a data bus 508. It should be understood that in some examples, the peripheral circuit 302 may also include Figure 6 Additional peripheral circuits not shown.

[0079] The page buffer / sense amplifier 501 can be configured to read data from the memory array 301 and program (write) data to the memory array 301 according to a control signal from the control logic unit 505. In one example, the page buffer / sense amplifier 501 can store a page of programming data (write data) to be programmed into the memory array 301. In another example, the page buffer / sense amplifier 501 can perform a programming verification operation to ensure that the data has been correctly programmed into the memory cell coupled to the selected word line. In yet another example, the page buffer / sense amplifier 501 can also sense a low-power signal from a bit line representing a data bit stored in the memory cell, and amplify a small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 502 can be configured to be controlled by the control logic unit 505, and select one or more memory cell strings by applying a bit line voltage generated from the voltage generator 504.

[0080] The row decoder / word line driver 503 may be configured to be controlled by the control logic unit 505 and select / deselect a memory block of the memory array 301 and select / deselect a word line of the memory block. The row decoder / word line driver 508 may also be configured to drive a word line using a word line voltage generated from the voltage generator 504. In some embodiments, the row decoder / word line driver 503 may also select / deselect and drive a bottom selection line and a top selection line. As described in detail below, the row decoder / word line driver 503 is configured to perform a programming operation on a memory cell coupled to (one or more) selected word lines. The voltage generator 504 may be configured to be controlled by the control logic unit 505 and generate a word line voltage (e.g., a read voltage, a programming voltage, a pass voltage, a local voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory array 301.

[0081] The control logic unit 505 may be coupled to each peripheral circuit described above, and is configured to control the operation of each peripheral circuit. The register 506 may be coupled to the control logic unit 505, and includes a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The flash memory interface 507 may be coupled to the control logic unit 505, and act as a control buffer to buffer control commands received from a host-side device (not shown) and relay them to the control logic unit 505, and to buffer status information received from the control logic unit 505 and relay them to the memory controller. The flash memory interface 507 may also be coupled to the column decoder / bit line driver 502 via the data bus 508, and act as a data I / O interface and a data buffer to buffer data and relay them to the storage array 301 or relay or buffer data from the storage array 301.

[0082] As the integration of memory devices continues to improve, the density of memory arrays continues to increase, and the number of memory cells connected to the same word line also increases. When one or more memory cells need to be selected for programming operations, the coupling effect between the memory cell string where the unselected memory cells connected to the selected word line are located and the selected word line will cause the voltage establishment time on the selected word line to become longer, thereby reducing the programming efficiency. The current required to make the selected word line reach the target voltage increases, resulting in an increase in the peak current during the programming operation and an increase in the power consumption of the memory device.

[0083] In this regard, an embodiment of the present disclosure provides a memory device, which includes a memory array and a peripheral circuit coupled to the memory array.

[0084] Figure 7 A schematic diagram of a storage array provided for a specific example of the present disclosure is shown in FIG. Figure 7 As shown, the storage array includes a first finger storage area 10 and a second finger storage area 20 connected to a common source line CSL. The first finger storage area 10 and the second finger storage area 20 each include a plurality of storage cell strings. For example, the first finger storage area 10 includes storage cell strings Str0, Str1, Str2, and Str3, and the second finger storage area 20 includes storage cell strings Str4, Str5, Str6, and Str7.

[0085] It should be noted that Figure 7 The example of a storage array including two finger storage areas, each of which includes four storage cell strings, is taken as an example, but the present disclosure is not limited thereto. In other embodiments, the storage array may include more than two finger storage areas, each of which may include more than four storage cell strings. The present disclosure does not limit the number of finger storage areas in the storage array and the number of storage cell strings in each finger storage area.

[0086] In the embodiments of the present disclosure, continue to refer to Figure 7 Each memory cell string includes a plurality of bottom selection transistors: a first bottom selection transistor BSG1, a second bottom selection transistor BSG2, a third bottom selection transistor BSG3 and a fourth bottom selection transistor BSG4. The gates of the bottom selection transistors in the same row are connected to the same bottom selection line, that is, the peripheral circuit can apply voltage to the bottom selection transistors in the same row through the bottom selection line.

[0087] In some embodiments, each memory cell string further includes a top selection transistor TSG, memory cells connected to word lines WL1 , WL2 , and WL3 , and dummy memory cells connected to a dummy word line DW.

[0088] It should be noted that Figure 7The number of the first bottom selection transistor BSG1, the second bottom selection transistor BSG2, the third bottom selection transistor BSG3 and the fourth bottom selection transistor BSG4, the number of the top selection transistors TSG, the number of word lines and the number of pseudo word lines are only examples, and the present disclosure does not limit the specific number of these structures.

[0089] In some embodiments, the first bottom selection transistor BSG1 in the first finger storage area 10 has a first threshold voltage Vt1, the first bottom selection transistor BSG1 in the second finger storage area 20 has a second threshold voltage Vt2, and the first threshold voltage Vt1 is less than the second threshold voltage Vt2.

[0090] In some embodiments, the second bottom selection transistor BSG2 in the first finger storage area 10 has a third threshold voltage Vt3, the second bottom selection transistor BSG2 in the second finger storage area 20 has a fourth threshold voltage Vt4, and the third threshold voltage Vt3 is greater than the fourth threshold voltage Vt4.

[0091] In a specific example, if Figure 8As shown, the range of the first threshold voltage Vt1 and the fourth threshold voltage Vt4 may be -4V to -2V, and the range of the second threshold voltage Vt2 and the third threshold voltage Vt3 may be 2V to 4V. When only the memory cell string in the first finger storage area 10 needs to be turned on, a bias voltage may be applied to the first bottom selection transistor BSG1, and a turn-on voltage may be applied to other bottom selection transistors. Specifically, the bias voltage may have any voltage value in the range of -2V to 2V, the first threshold voltage Vt1 of the first bottom selection transistor BSG1 in the first finger storage area 10 is lower than the bias voltage, the second threshold voltage Vt2 of the first bottom selection transistor BSG1 in the second finger storage area 20 is higher than the bias voltage, the first bottom selection transistor BSG1 in the first finger storage area 10 is turned on, the first bottom selection transistor BSG1 in the second finger storage area 20 is turned off, and the other bottom selection transistors are all turned on, thereby making the memory cell string in the second finger storage area 20 in a floating state, and realizing the operation of only the memory cells in the first finger storage area 10. Similarly, when only the memory cell string in the second finger storage area 20 needs to be turned on, a bias voltage can be applied to the second bottom selection transistor BSG2, and a turn-on voltage can be applied to other bottom selection transistors, the third threshold voltage Vt3 of the second bottom selection transistor BSG2 located in the first finger storage area 10 is higher than the bias voltage, the fourth threshold voltage Vt4 of the second bottom selection transistor BSG2 located in the second finger storage area 20 is lower than the bias voltage, the second bottom selection transistor BSG2 located in the first finger storage area 10 is turned off, the second bottom selection transistor BSG2 located in the second finger storage area 20 is turned on, and the other bottom selection transistors are all turned on, thereby, the memory cell string in the first finger storage area 10 can be placed in a floating state, and only the memory cells located in the second finger storage area 20 can be operated.

[0092] In the above example, the first bottom selection transistor BSG1 located in the same row has two different threshold voltages, and correspondingly, the second bottom selection transistor BSG2 located in the same row also has two different threshold voltages, so that the storage array can be divided into a first finger storage area 10 and a second finger storage area 20, and a separate operation of the first finger storage area 10 or the second finger storage area 20 can be achieved by applying a bias voltage to the first bottom selection transistor BSG1 or applying a bias voltage to the second bottom selection transistor BSG2, that is, only one finger storage area can be selected, and the storage cell strings in the unselected finger storage areas can be in a floating state, so that the coupling effect of the unselected storage cell strings on the selected word line can be reduced, the establishment time of the word line voltage can be shortened, and the peak current can be reduced, thereby improving the operating efficiency and reducing the power consumption of the memory device.

[0093] In some embodiments, the memory cell strings each include a third bottom selection transistor BSG3 located between the first bottom selection transistor BSG1 and the second bottom selection transistor BSG2, and a fourth bottom selection transistor BSG4 that is closer to the common source line CSL than the first bottom selection transistor BSG1 and the second bottom selection transistor BSG2, the third bottom selection transistor BSG3 located in the first finger storage area 10 and the second finger storage area 20 each have a fifth threshold voltage Vt5, and the fourth bottom selection transistor BSG4 located in the first finger storage area 10 and the second finger storage area 20 each have a sixth threshold voltage Vt6.

[0094] In some specific examples, before performing a programming operation on a memory cell, a programming operation may be performed on the first bottom selection transistor BSG1 and the second bottom selection transistor BSG2, so as to program the first bottom selection transistor BSG1 and the second bottom selection transistor BSG2 in the first finger storage area 10 to the first threshold voltage Vt1 and the third threshold voltage Vt3, respectively, and program the first bottom selection transistor BSG1 and the second bottom selection transistor BSG2 in the second finger storage area 20 to the second threshold voltage Vt2 and the fourth threshold voltage Vt4, respectively. In this process, the third bottom selection transistor BSG3 located between the first bottom selection transistor BSG1 and the second bottom selection transistor BSG2 may play a role of buffering the electric field between the first bottom selection transistor BSG1 and the second bottom selection transistor BSG2 in the programming verification operation, and the fourth bottom selection transistor BSG4 may play a role of bottom shutoff in the programming operation.

[0095] In a specific example, Fig. 9 for Figure 7 The simplified circuit diagram corresponding to the storage array shown is Fig.10 1 is a voltage curve when a program verification operation is performed on the memory cells in the first finger storage area 10 .

[0096] Combined with reference Figure 7 and Fig. 9, the memory cell string 110 and the memory cell string 111 may be any two memory cell strings in the first finger storage area 10, wherein the memory cell string 110 is the memory cell string where the memory cell that needs to perform a programming verification operation is located, that is, the memory cell string 110 is the selected memory cell string in the selected finger storage area, which includes the top selection transistor TSG1, and the memory cell string 111 is the unselected memory cell string in the selected finger storage area, which includes the top selection transistor TSG2. The memory cell string 210 may be any memory cell string in the second finger storage area 20, and the memory cell string 210 is the unselected memory cell string in the unselected finger storage area, which includes the top selection transistor TSG3. Here, the gates of the top selection transistors TSG1, TSG2, and TSG3 are respectively connected to three different top selection lines.

[0097] In the embodiment of the present disclosure, word line WL1 is the selected word line, and word line WL2 and word line WL3 are unselected word lines. In other embodiments, word line WL2 or word line WL3 may also be the selected word line.

[0098] In some embodiments, Fig.10 As shown, the programming verification operation performed on the selected storage cells in the first finger storage area 10 includes two stages: a first precharging stage P1 and a first sensing stage P2. The first sensing stage P2 is a stage in which multiple sensing operations are performed on the selected storage cells in the first finger storage area 10 after the first precharging stage P1.

[0099] In some embodiments, in the first precharge phase P1, the peripheral circuit is configured to: apply a pass voltage Vpass to the top selection transistor in the first finger storage area 10 to turn on the top selection transistor in the first finger storage area 10, that is, the top selection transistor TSG1 in the memory cell string 110 and the top selection transistor TSG2 in the memory cell string 111 are both turned on, and apply a ground voltage Vss to the top selection transistor in the second finger storage area 20 to turn off the top selection transistor in the second finger storage area 20, that is, the top selection transistor in the memory cell string 210 is turned on. TSG3 is turned off; a turn-on voltage Vpass is applied to the unselected word lines WL2 / WL3 and the pseudo word line DW; a first turn-on voltage Vpass1 is applied to the second bottom selection transistor BSG2, and the first turn-on voltage Vpass1 is greater than the third threshold voltage Vt3; a second turn-on voltage Vpass2 is applied to the third bottom selection transistor BSG3, and the second turn-on voltage Vpass2 is greater than the fifth threshold voltage Vt5; a third turn-on voltage Vpass3 is applied to the fourth bottom selection transistor BSG4, and the third turn-on voltage Vpass3 is greater than the sixth threshold voltage Vt6.

[0100] It should be noted that in Fig.12In the example shown, the starting voltages of the word lines WL1, WL2, and WL3 and the pseudo word line DW are all the power supply voltage Vdd, thereby shortening the time for the voltage to be established on the word lines, but the present disclosure is not limited thereto. In other embodiments, the starting voltages of the word lines WL1, WL2, and WL3 and the pseudo word line DW may all be the ground voltage Vss. In this case, it is necessary to apply a turn-on voltage to the selected word line WL1 in the first precharge phase P1, so as to turn on the unselected memory cell strings in the first finger storage area 10.

[0101] In the embodiments of the present disclosure, except for the first on-voltage Vpass1, the second on-voltage Vpass2, the third on-voltage Vpass3 and the fourth on-voltage Vpass4 whose relative sizes are specifically limited, other on-voltages Vpass refer to voltages that can turn on the corresponding storage cells or transistors, and the present disclosure does not limit their specific sizes.

[0102] In some embodiments, in the first precharge phase P1, the peripheral circuit is configured to apply a higher voltage to the bottom selection transistors except the first bottom selection transistor BSG1 so that the other bottom selection transistors are all in the on state. At this time, the voltage that needs to be applied to the first bottom selection transistor BSG1 can turn on the first bottom selection transistor BSG1 in the first finger storage area 10 and turn off the first bottom selection transistor BSG1 in the second finger storage area 20. As a result, the memory cell strings in the first finger storage area 10 are all in the on state, and the channels are coupled to the common source line CSL, and the common source line CSL is coupled to the ground voltage Vss, so that the channel voltage in the first finger storage area 10 can be set to the ground voltage Vss, while the channels of the memory cell strings in the second finger storage area 20 are in a floating state, and the channel voltage is coupled to a higher voltage by the gate voltage.

[0103] In the embodiment of the present disclosure, the peripheral circuit is configured to perform a precharge operation only on the memory cell strings in the first finger storage area 10 in the first precharge phase P1. On the one hand, the precharge operation is performed on all the memory cell strings in the first finger storage area 10, and the channel voltage of the unselected memory cell strings in the first finger storage area 10 can be set to the ground voltage Vss. Therefore, in the subsequent first sensing phase P2, taking the unselected memory cell string 111 as an example, when the memory cell connected to the selected word line WL1 in the memory cell string 111 is in the off state, the voltage of the channel between the top selection transistor TSG2 and the memory cell, and the voltage of the channel between the memory cell and the first bottom selection transistor BSG1 are both maintained at the ground voltage Vss, and a large voltage difference will not be generated near the channel of the memory cell, so that the hot carrier injection effect (Hot Carrier Injection, HCI) caused by the large voltage difference can be effectively weakened, and the threshold voltage drift generated by the unselected memory cell in the programming operation of the selected memory cell can be reduced. On the other hand, in the first precharge stage P1, the memory cell strings in the finger storage area 20 are all in a floating state, which can weaken the coupling effect between the memory cell strings in the finger storage area 20 and the selected word line WL1, thereby shortening the voltage establishment time on the word line WL1 and improving the efficiency of the programming verification operation.

[0104] In some embodiments, Fig.10 As shown, in the first precharge phase P1, in order to turn on the first bottom selection transistor BSG1 located in the first finger storage area 10 and turn off the first bottom selection transistor BSG1 located in the second finger storage area 20, the peripheral circuit can be configured to apply a second bias voltage Vbias2 to the first bottom selection transistor BSG1, and the second bias voltage Vbias2 is less than the second threshold voltage Vt2 and greater than the first threshold voltage Vt1. However, in this case, as Fig.10 As shown in the dotted part of the voltage curve corresponding to the first bottom selection transistor BSG1, in the first pre-charging stage P1, when the peripheral circuit applies a higher voltage to the bottom selection transistors other than the first bottom selection transistor BSG1, during the voltage rising period, due to the coupling effect between the bottom selection lines, the voltage on the first bottom selection transistor BSG1 may be coupled to a higher voltage and may exceed the second threshold voltage Vt2, resulting in the first bottom selection transistor BSG1 in the second finger storage area 20 cannot be completely turned off.

[0105] like Fig.11As shown, in the above embodiment, taking the memory cell string 210 in the second finger storage area 20 as an example, since the voltage on the first bottom selection transistor BSG1 is coupled to a higher voltage, the first bottom selection transistor BSG1 in the memory cell string 210 cannot be completely turned off, and the memory cell connected to the selected word line WL1 in the memory cell string 210 is still in the off state, resulting in the channel between the memory cell and the first bottom selection transistor BSG1 being coupled to the common source line CSL, and the channel voltage being set to the ground voltage Vss, while the channel between the memory cell and the top selection transistor TSG3 is still in a floating state, and the channel voltage will still be coupled to a higher voltage by the gate voltage. In this case, a larger voltage difference will be generated in the channel near the memory cell, and the threshold voltage of the memory cell may drift due to the hot carrier injection effect.

[0106] In some embodiments, the peripheral circuit is configured as follows: in a first precharge phase P1 of a programming verification operation on a memory cell in the first finger storage area 10, a first bias voltage Vbias1 is applied to the first bottom selection transistor BSG1; in a first sensing phase P2 after the first precharge phase P1, a second bias voltage Vbias2 is applied to the first bottom selection transistor BSG2, and the first bias voltage Vbias1 is less than the second bias voltage Vbias2.

[0107] In some specific examples, the first bias voltage Vbias1 is greater than or equal to the negative second pass voltage Vpass2 , and the second bias voltage Vbias2 is less than the second pass voltage Vpass2 .

[0108] In some specific examples, the first bias voltage Vbias1 is greater than or equal to the negative third pass voltage Vpass3 , and the second bias voltage Vbias2 is less than the third pass voltage Vpass3 .

[0109] In a specific example, if Fig.12As shown, in the voltage curve corresponding to the first bottom selection transistor BSG1, the solid line represents the voltage applied to the first bottom selection transistor BSG1 by the peripheral circuit, and the dotted line represents the actual voltage on the first bottom selection transistor BSG1. In the first pre-charging stage P1, a lower first bias voltage Vbias1 is applied to the first bottom selection transistor BSG1, which can weaken the tendency of the voltage on the first bottom selection transistor BSG1 to drift upward due to the coupling effect between the bottom selection lines, so that the actual voltage on the first bottom selection transistor BSG1 can be stabilized near the second bias voltage Vbias2, and the first bottom selection transistor BSG1 in the second finger storage area 20 remains in the off state, reducing the drift of the threshold voltage of the storage cell in the second finger storage area 20 due to the hot carrier injection effect, so that the reliability of the programming operation of the memory device can be further improved while improving the efficiency of the programming verification operation.

[0110] In the above example, the peripheral circuit applies the first bias voltage Vbias1 with a fixed voltage value to the first bottom selection transistor BSG1 and continues until the first pre-charging phase P1 ends, but the present disclosure is not limited thereto.

[0111] In some embodiments, the peripheral circuit may stop applying the first bias voltage Vbias1 to the first bottom selection transistor BSG1 before the first pre-charging stage P1 ends, and the voltage applied by the peripheral circuit to the first bottom selection transistor BSG1 begins to gradually increase from the first bias voltage Vbias1 to the second bias voltage Vbias2.

[0112] In some embodiments, the voltage value of the first bias voltage Vbias1 can also be continuously changed. It can be gradually reduced from the ground voltage Vss to a minimum value in the initial stage of the first pre-charging stage P1, and then gradually increased from the minimum value to a maximum value, or other suitable changing methods can be used to dynamically adjust the actual voltage on the first bottom selection transistor BSG1.

[0113] It can be understood that the influence of the coupling effect on the voltage on the first bottom selection transistor BSG1 is mainly concentrated in the initial stage of the first pre-charging stage P1, that is, the stage in which the voltage on the bottom selection line and the word line connected to other bottom selection transistors is established. In this stage, the voltage on the bottom selection line and the word line gradually rises from the starting voltage to a higher turn-on voltage, and the voltage change rate is large, which will enhance the coupling effect and cause the voltage on the first bottom selection transistor BSG1 to have an upward drift trend. Therefore, the first bias voltage Vbias1 can be applied to the first bottom selection transistor BSG1 only in the first pre-charging stage P1 or the initial stage of the first pre-charging stage P1.

[0114] In some embodiments, continue to refer to Fig.12 , in the first sensing stage P2 after the first pre-charging stage P1, the peripheral circuit is configured as follows: applying the second bias voltage Vbias2 to the first bottom selection transistor BSG1; continuing to apply the first turn-on voltage Vpass1 to the second bottom selection transistor BSG2, applying the second turn-on voltage Vpass2 to the third bottom selection transistor BSG3, and applying the third turn-on voltage Vpass3 to the fourth bottom selection transistor BSG4; turning off the unselected top selection transistor TSG2 in the first finger storage area 10; turning off the top selection transistor TSG3 in the second finger storage area 20; keeping the selected top selection transistor TSG1 in the first finger storage area 10 turned on; continuing to apply the turn-on voltage Vpass to the unselected word lines WL2 / WL3 and the pseudo word lines; applying the first verification voltage Vpv1, the second verification voltage Vpv2, and the third verification voltage Vpv3 ​​to the selected word line WL1 in sequence to perform a sensing operation on the selected storage cell.

[0115] Here, the first sensing stage P2 includes three sensing operations as an example, but the present disclosure is not limited thereto. In other embodiments, the sensing stage may include only two sensing operations or more than three sensing operations.

[0116] In some embodiments, Fig.12 As shown, the peripheral circuit is also configured as follows: in a first preparation stage P3 after the first sensing stage P2, a turn-on voltage Vpass is applied to the selected word line WL1 to turn on the selected memory cell, and the accumulated electrons in the channel of the selected memory cell string can be discharged; in a second preparation stage P4 after the first preparation stage P3, a power supply voltage Vdd is applied to the word line WL1, so that the voltage on the word line WL1 gradually decreases from the turn-on voltage Vpass to the power supply voltage Vdd, and the remaining electrons in the channel are discharged from the bit line direction; in a third preparation stage P5 after the second preparation stage P4, a power supply voltage Vdd is applied to the word line WL2, the word line WL3 and the pseudo word line DW, and a ground voltage Vss is applied to other selection lines, so that the voltages on the word line and each selection line are restored to the voltage before the programming verification operation is performed.

[0117] In another specific example, Fig.13 is a voltage curve when performing a program verification operation on the memory cells in the second finger storage area 20, such as Fig.13As shown, the peripheral circuit is also configured as follows: in the second pre-charging stage P6 of performing programming verification operation on the memory cells in the second finger storage area 20, the fourth turn-on voltage Vpass4 is applied to the first bottom selection transistor BSG1, and the third bias voltage Vbias3 is applied to the second bottom selection transistor BSG2; the fourth turn-on voltage Vpass4 is greater than the second threshold voltage Vt2; in the second sensing stage P7 after the second pre-charging stage P6, the fourth turn-on voltage Vpass4 is applied to the first bottom selection transistor BSG1, and the fourth bias voltage Vbias4 is applied to the second bottom selection transistor BSG2; the third bias voltage Vbias3 is less than the fourth bias voltage Vbias4; the fourth bias voltage Vbias4 is less than the third threshold voltage Vt3 and greater than the fourth threshold voltage Vt4.

[0118] In the embodiment of the present disclosure, similar to the case where a programming verification operation is performed on the memory cells in the first finger storage area 10, when a programming verification operation is performed on the memory cells in the second finger storage area 20, the peripheral circuit first applies a lower third bias voltage Vbias3 to the second bottom selection transistor BSG2, which can weaken the tendency of the voltage on the second bottom selection transistor BSG2 to drift upward due to the coupling effect between the bottom selection lines or the coupling effect between the pseudo word line and the bottom selection line, so that the actual voltage on the second bottom selection transistor BSG2 can be stabilized near the fourth bias voltage Vbias4, and the second bottom selection transistor BSG2 in the first finger storage area 10 remains in the off state, reducing the drift of the threshold voltage of the memory cells in the first finger storage area 10 due to the hot carrier injection effect, thereby improving the efficiency of the programming verification operation to improve the programming efficiency while further improving the reliability of the programming operation of the memory device.

[0119] It should be noted that in the embodiment of the present disclosure, the peripheral circuit is configured to perform a programming operation including multiple programming loops on the storage cells in the first finger storage area 10 or the second finger storage area 20, each programming loop may include a programming pulse application operation and a programming verification operation, and for multiple programming loops, the programming pulse applied to the selected word line may be incremental, and the verification voltage applied to the selected word line may also be different. Fig.12 and Fig.13 This is a voltage curve when performing a program verification operation on a memory cell. That is, the above example only takes the program verification operation in one programming loop as an example. Before the program verification operation, the peripheral circuit is also configured to perform a program pulse applying operation.

[0120] In the embodiment of the present disclosure, the specific composition and function implementation of the peripheral circuit can refer to the above description of Figure 6As described above, in the peripheral circuit, the control logic unit can control the row decoder / word line driver to apply the voltage generated by the voltage generator to the top selection transistor, the bottom selection transistor, the word line and the pseudo word line in the above embodiments via the row decoder / word line driver.

[0121] Based on the concept similar to the above-mentioned memory device, the present disclosure also provides a memory system, which includes: at least one memory device in any of the above-mentioned embodiments; a controller coupled to the at least one memory device and configured to control the memory device. For the specific composition and function implementation of the memory system, please refer to the above description of Figures 1 to 7 For the sake of brevity, the description is not repeated here.

[0122] Based on the same concept as the above memory device, the present disclosure also provides an operation method of the memory device. Fig.14 1 is a flow chart of an operation method of the memory device, wherein the memory device comprises the following steps:

[0123] Step S1000: in a first precharge phase of performing a program verification operation on memory cells in a first finger storage area, applying a first bias voltage to a first bottom selection transistor in each memory cell string;

[0124] Step S2000: In a first sensing phase after a first pre-charging phase, a second bias voltage is applied to a first bottom selection transistor; the first bias voltage is less than the second bias voltage; the second bias voltage is less than a second threshold voltage of the first bottom selection transistor in the second finger storage area and greater than a first threshold voltage of the first bottom selection transistor in the first finger storage area.

[0125] Combined with reference Figure 7 , Fig.12 and Fig.14 , executing step S1000 includes: applying a first bias voltage Vbias1 to the first bottom selection transistor BSG1 in a first precharge phase P1 of a program verification operation on a memory cell in the first finger storage area 10. Executing step S2000 includes: applying a second bias voltage Vbias2 to the first bottom selection transistor BSG1 in a first sensing phase P2 after the first precharge phase P1, the first bias voltage Vbias1 being less than the second bias voltage Vbias2, the second bias voltage Vbias2 being less than a second threshold voltage Vt2 of the first bottom selection transistor BSG1 in the second finger storage area 20 and being greater than a first threshold voltage Vt1 of the first bottom selection transistor in the first finger storage area 10.

[0126] In some embodiments, the operating method of the memory device also includes: in the first precharging stage P1 and the first sensing stage P2, applying a first turn-on voltage Vpass1 to the second bottom selection transistor BSG2 in each memory cell string; the third threshold voltage Vt3 of the second bottom selection transistor BSG2 in the first finger storage area 10 is greater than the fourth threshold voltage Vt4 of the second bottom selection transistor BSG2 in the second finger storage area 20; the first turn-on voltage Vpass1 is greater than the third threshold voltage Vt3.

[0127] In some embodiments, the operating method of the memory device further includes: in the first pre-charging stage P1 and the first sensing stage P2, applying a second turn-on voltage Vpass2 to a third bottom selection transistor BSG3 located between the first bottom selection transistor BSG1 and the second bottom selection transistor BSG2; the second turn-on voltage Vpass2 is greater than the fifth threshold voltage of the third bottom selection transistor BSG3.

[0128] In some specific examples, the first bias voltage Vbias1 is greater than or equal to the negative second pass voltage Vpass2 , and the second bias voltage Vbias2 is less than the second pass voltage Vpass2 .

[0129] In some embodiments, the operating method of the memory device also includes: in the first pre-charging stage P1 and the first sensing stage P2, applying a third turn-on voltage Vpass3 to the fourth bottom selection transistor BSG4 which is closer to the common source line CSL than the first bottom selection transistor BSG1 and the second bottom selection transistor BSG2; the third turn-on voltage Vpass3 is greater than the sixth threshold voltage Vt6 of the fourth bottom selection transistor BSG4.

[0130] In some specific examples, the first bias voltage Vbias1 is greater than or equal to the negative third pass voltage Vpass3 , and the second bias voltage Vbias2 is less than the third pass voltage Vpass3 .

[0131] In some embodiments, the operating method of the memory device also includes: in the first precharge phase P1, turning on the top selection transistors TSG1 and TSG2 in the first finger storage area 10; in the first sensing phase P2, turning off the unselected top selection transistor TSG2 in the first finger storage area 10 and turning on the selected top selection transistor TSG1 in the first finger storage area 10; in the first precharge phase P1 and the first sensing phase P2, turning off the top selection transistor TSG3 in the second finger storage area 20.

[0132] In some embodiments, in conjunction with reference Figure 7 and Fig.13The operation method of the memory device also includes: in a second pre-charging stage P6 for programming and verifying the memory cells in the second finger storage 20, applying a fourth pass voltage Vpass4 to the first bottom selection transistor BSG1, and applying a third bias voltage Vbias3 to the second bottom selection transistor BSG2; the fourth pass voltage Vpass4 is greater than the second threshold voltage Vt2; in a second sensing stage P7 after the second pre-charging stage P6, applying a fourth pass voltage Vpass4 to the first bottom selection transistor BSG1, and applying a fourth bias voltage Vbias4 to the second bottom selection transistor BSG2; the third bias voltage Vbias3 is less than the fourth bias voltage Vbias4; the fourth bias voltage Vbias4 is less than the third threshold voltage Vt3 and greater than the fourth threshold voltage Vt4.

[0133] In the embodiment of the present disclosure, only one finger storage area may be selected to perform a programming operation including a programming verification operation to improve programming efficiency. Taking the programming verification operation performed on the memory cells in the first finger storage area 10 as an example, in the first precharge phase P1 of the programming verification operation, a lower first bias voltage Vbias1 may be applied to the first bottom selection transistor BSG1 to weaken the tendency of the voltage on the first bottom selection transistor BSG1 to drift upward due to the coupling effect between the bottom selection lines, so that the actual voltage on the first bottom selection transistor BSG1 is stabilized near the second bias voltage Vbias2, and the first bottom selection transistor BSG1 in the second finger storage area 20 is kept in the off state, reducing the drift of the threshold voltage of the memory cells in the second finger storage area 20 due to the hot carrier injection effect, thereby further improving the reliability of the programming operation of the memory device while improving the efficiency of the programming verification operation.

[0134] The features disclosed in several device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new device embodiments.

[0135] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0136] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A memory device, characterized in that: The memory device includes a memory array and a peripheral circuit coupled to the memory array; wherein, The memory array includes a first finger storage area and a second finger storage area; the first finger storage area and the second finger storage area each include a plurality of memory cell strings; each of the memory cell strings includes a first bottom selection transistor; the first bottom selection transistor in the first finger storage area has a first threshold voltage, and the first bottom selection transistor in the second finger storage area has a second threshold voltage; the first threshold voltage is less than the second threshold voltage; the peripheral circuit is configured as follows: In a first precharge phase of performing a program verification operation on a memory cell in the first finger storage area, applying a first bias voltage to the first bottom selection transistor; In a first sensing phase after the first precharge phase, a second bias voltage is applied to the first bottom selection transistor; the first bias voltage is less than the second bias voltage; and the second bias voltage is less than the second threshold voltage and greater than the first threshold voltage.

2. The memory device according to claim 1, wherein: Each of the memory cell strings further includes a second bottom selection transistor, the second bottom selection transistor in the first finger storage area has a third threshold voltage, the second bottom selection transistor in the second finger storage area has a fourth threshold voltage; the third threshold voltage is greater than the fourth threshold voltage; The peripheral circuit is further configured to: apply a first turn-on voltage to the second bottom selection transistor in the first precharging stage and the first sensing stage; the first turn-on voltage is greater than the third threshold voltage.

3. The memory device according to claim 2, wherein: Each of the memory cell strings further includes a third bottom selection transistor; the third bottom selection transistor is located between the first bottom selection transistor and the second bottom selection transistor; the third bottom selection transistor has a fifth threshold voltage; The peripheral circuit is further configured to: apply a second turn-on voltage to the third bottom selection transistor in the first precharge phase and the first sensing phase; the second turn-on voltage is greater than the fifth threshold voltage.

4. The memory device according to claim 3, wherein: The first bias voltage is greater than or equal to a negative second conduction voltage, and the second bias voltage is less than the second conduction voltage.

5. The memory device according to claim 2, wherein: The memory array further includes a common source line connected to each of the memory cell strings, each of the memory cell strings further includes a fourth bottom selection transistor, the fourth bottom selection transistor is closer to the common source line than the first bottom selection transistor and the second bottom selection transistor; the fourth bottom selection transistor has a sixth threshold voltage; The peripheral circuit is further configured to: apply a third turn-on voltage to the fourth bottom selection transistor in the first precharge phase and the first sensing phase; the third turn-on voltage is greater than the sixth threshold voltage.

6. The memory device according to claim 5, characterized in that The first bias voltage is greater than or equal to a negative third conduction voltage, and the second bias voltage is less than the third conduction voltage.

7. The memory device according to claim 2, wherein: The peripheral circuit is further configured as: In a second precharge phase of performing a program verification operation on a memory cell in the second finger storage area, a fourth turn-on voltage is applied to the first bottom selection transistor, and a third bias voltage is applied to the second bottom selection transistor; the fourth turn-on voltage is greater than the second threshold voltage; In a second sensing phase after the second pre-charging phase, applying the fourth turn-on voltage to the first bottom selection transistor and applying a fourth bias voltage to the second bottom selection transistor; The third bias voltage is lower than the fourth bias voltage; the fourth bias voltage is lower than the third threshold voltage and higher than the fourth threshold voltage.

8. The memory device according to claim 1, wherein: Each of the memory cell strings further includes a top selection transistor; and the peripheral circuit is further configured to: In the first precharge phase, turning on the top selection transistor in the first finger storage area; In the first sensing phase, the unselected top selection transistors in the first finger storage area are turned off, and the selected top selection transistors in the first finger storage area are turned on; In the first precharge phase and the first sensing phase, the top selection transistor in the second finger storage area is turned off.

9. A memory system, characterized in that: include: At least one memory device as claimed in any one of claims 1 to 8; A controller is coupled to the at least one memory device and is configured to control the memory device.

10. A method for operating a memory device, characterized in that: include: In a first precharge phase of performing a program verification operation on memory cells in a first finger storage area, applying a first bias voltage to a first bottom selection transistor in each memory cell string; In a first sensing phase after the first pre-charging phase, applying a second bias voltage to the first bottom selection transistor; The first bias voltage is less than the second bias voltage; The second bias voltage is less than a second threshold voltage of the first bottom selection transistor in the second finger storage area and greater than a first threshold voltage of the first bottom selection transistor in the first finger storage area.

11. The method for operating a memory device according to claim 10, wherein: The operation method also includes: In the first precharge phase and the first sensing phase, a first turn-on voltage is applied to the second bottom selection transistor in each of the memory cell strings; a third threshold voltage of the second bottom selection transistor in the first finger storage area is greater than a fourth threshold voltage of the second bottom selection transistor in the second finger storage area; and the first turn-on voltage is greater than the third threshold voltage.

12. The method for operating a memory device according to claim 11, characterized in that: The operation method also includes: In the first precharge phase and the first sensing phase, a second turn-on voltage is applied to a third bottom selection transistor located between the first bottom selection transistor and the second bottom selection transistor; the second turn-on voltage is greater than a fifth threshold voltage of the third bottom selection transistor.

13. The method for operating a memory device according to claim 12, wherein: The first bias voltage is greater than or equal to a negative second conduction voltage, and the second bias voltage is less than the second conduction voltage.

14. The method for operating a memory device according to claim 11, characterized in that: The operation method also includes: In the first precharge phase and the first sensing phase, a third turn-on voltage is applied to a fourth bottom selection transistor closer to a common source line than the first bottom selection transistor and the second bottom selection transistor; the third turn-on voltage is greater than a sixth threshold voltage of the fourth bottom selection transistor.

15. The method for operating a memory device according to claim 14, characterized in that: The first bias voltage is greater than or equal to a negative third conduction voltage, and the second bias voltage is less than the third conduction voltage.

16. The method for operating a memory device according to claim 11, wherein: The operation method also includes: In a second precharge phase of program verification of the memory cells in the second finger storage area, a fourth conduction voltage is applied to the first bottom selection transistor, and a third bias voltage is applied to the second bottom selection transistor; the fourth conduction voltage is greater than the second threshold voltage; In a second sensing phase after the second pre-charging phase, the fourth turn-on voltage is applied to the first bottom selection transistor, and a fourth bias voltage is applied to the second bottom selection transistor; the third bias voltage is less than the fourth bias voltage; and the fourth bias voltage is less than the third threshold voltage and greater than the fourth threshold voltage.

17. The method for operating a memory device according to claim 10, wherein: The operation method also includes: In the first precharge phase, turning on the top selection transistor in the first finger storage area; In the first sensing phase, the unselected top selection transistors in the first finger storage area are turned off, and the selected top selection transistors in the first finger storage area are turned on; In the first precharge phase and the first sensing phase, the top selection transistor in the second finger storage area is turned off.

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