Test method and device for nonvolatile memory and test equipment

Abstract

The invention relates to the technical field of integrated circuit testing, and discloses a testing method for nonvolatile memories, the testing method is applied to testing equipment, the testing equipment is in communication connection with to-be-tested groups based on an I2C bus, and each to-be-tested group comprises a plurality of nonvolatile memories; the test method comprises the following steps: sending a test start instruction to a to-be-tested group to indicate the to-be-tested group to execute an engineering mode; in the engineering mode, allocating different test resources to each to-be-tested group; and performing pipeline testing on all the nonvolatile memories of the to-be-tested group corresponding to the test resources in a polling manner to realize parallel testing of all the nonvolatile memories. According to the method, the test duration of the nonvolatile memory can be shortened, and the test efficiency of the nonvolatile memory in the to-be-tested group is improved. The invention further discloses a testing device and testing equipment for the nonvolatile memory.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit testing, for example, to a testing method and device, and testing equipment for non-volatile memory. Background Art

[0002] At present, as the proportion of integrated circuit testing costs in the overall cost continues to increase, there is an urgent need to improve testing efficiency and reduce testing costs.

[0003] In order to improve test efficiency and reduce test costs, the relevant technology provides a test method for non-volatile memory, including the following steps: configuring the same device address for all chips to be tested; after the configuration is completed, allocating independent test resources to each chip to be tested; and testing the chips to be tested in a parallel testing manner.

[0004] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related art:

[0005] The testing method provided by the related art needs to allocate independent testing resources to each chip to be tested, which consumes a large amount of testing resources during the testing process.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0007] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0008] The embodiments of the present disclosure provide a test method, an apparatus and a test device for a non-volatile memory, so as to shorten the test time of the non-volatile memory and improve the test efficiency of the non-volatile memory in a test group.

[0009] In some embodiments, the test device is applied, the test device is connected to the group to be tested based on the I2C bus, and each group to be tested includes multiple non-volatile memories; the testing method includes: sending a test start instruction to the group to be tested to instruct the group to be tested to execute the engineering mode; in the engineering mode, different test resources are allocated to each group to be tested; all non-volatile memories of the group to be tested corresponding to the test resources are pipeline tested in a polling manner to achieve parallel testing of all non-volatile memories.

[0010] In some embodiments, a pipeline test is performed on all non-volatile memories of a test group corresponding to a test resource in a polling manner, including: selecting a first non-volatile memory to be tested from the same test group; performing an erase and write test on the first non-volatile memory to be tested; after completing the erase and write test on the first non-volatile memory to be tested, selecting a second non-volatile memory to be tested from other non-volatile memories; performing an erase and write test on the second non-volatile memory to be tested, and completing the erase and write test of all non-volatile memories in the same test group in sequence in a polling manner.

[0011] In some embodiments, a pipeline test is performed on all non-volatile memories of a test group corresponding to a test resource in a polling manner, and further includes: after selecting a first non-volatile memory to be tested from the same test group, other non-volatile memories are selected from the same test group; while performing an erase and write test on the first non-volatile memory to be tested, erase and write instructions are sent to other non-volatile memories or read and verify operations are performed on other non-volatile memories.

[0012] In some embodiments, each non-volatile memory in the same group to be tested is configured with a different test address; a first non-volatile memory to be tested and other non-volatile memories are selected from the same group to be tested, including: selecting a non-volatile memory corresponding to a target test address from the same group to be tested as the first non-volatile memory to be tested; selecting a non-volatile memory different from the non-volatile memory corresponding to the target test address from the same group to be tested as other non-volatile memories.

[0013] In some embodiments, it also includes: before sending a test start instruction to the group to be tested to instruct the group to be tested to execute the engineering mode, grouping the non-volatile memories on the same wafer to obtain different groups of groups to be tested, and configuring different test addresses for the non-volatile memories in the same group to be tested.

[0014] In some embodiments, performing a read verification operation on other non-volatile memories includes: sending a read instruction to other non-volatile memories to perform a data read operation, and reading data from other non-volatile memories.

[0015] In some embodiments, different test resources are allocated to each group to be tested, including: connecting the serial data lines of all non-volatile memories of the same group to be tested, and respectively allocating first test resources to all non-volatile memories of the same group to be tested through the serial data lines; and connecting the serial data lines of all other non-volatile memories of the same group to be tested, and respectively allocating second test resources to all non-volatile memories of each other group to be tested through the serial data lines; wherein the second test resources are independent of the first test resources.

[0016] In some embodiments, it also includes: after the parallel testing of all non-volatile memories is completed, a user start instruction is sent to the group to be tested to instruct the group to be tested to execute user mode; in user mode, the address of each non-volatile memory in the same group to be tested is configured according to the mode requirements in user mode to reset the test address of the non-volatile memory in engineering mode to the device address.

[0017] In some embodiments, the testing device includes a processor and a memory storing program instructions, and the processor is configured to execute the aforementioned testing method for non-volatile memory when running the program instructions.

[0018] In some embodiments, the test equipment includes: a test equipment body; and the aforementioned test device for non-volatile memory installed in the test equipment body.

[0019] The test method, apparatus and test device for non-volatile memory provided by the embodiments of the present disclosure can achieve the following technical effects:

[0020] The disclosed embodiment sends a test start instruction to the group to be tested to start the engineering mode. After the group to be tested starts the engineering mode, the test equipment allocates different test resources to each group to be tested, and performs pipeline testing on all non-volatile memories of the same group to be tested corresponding to the test resources in a polling manner. In this way, all non-volatile memories of the same group to be tested share the test resources to achieve time-sharing multiplexing of the I2C bus during testing, thereby improving the utilization rate of test resources during non-volatile memory testing. At the same time, non-volatile memories of different groups to be tested can be tested in parallel, which helps to shorten the test time of the non-volatile memories and improve the test efficiency of the non-volatile memories in the group to be tested.

[0021] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0023] Figure 1 is an environmental schematic diagram of a test system for a non-volatile memory provided by an embodiment of the present disclosure;

[0024] Figure 2 is a schematic diagram of a testing method for a non-volatile memory provided by an embodiment of the present disclosure;

[0025] Figure 3is a schematic diagram of another testing method for a non-volatile memory provided by an embodiment of the present disclosure;

[0026] Figure 4 is a schematic diagram of another testing method for a non-volatile memory provided by an embodiment of the present disclosure;

[0027] Figure 5 is a schematic diagram of another testing method for a non-volatile memory provided by an embodiment of the present disclosure;

[0028] Figure 6-1 It is a connection diagram of multiple non-volatile memories in the same test group provided by an embodiment of the present disclosure;

[0029] Figure 6-2 It is a test timing flow chart of a non-volatile memory in the same test group provided by an embodiment of the present disclosure;

[0030] Figure 7-1 It is a connection diagram of a non-volatile memory provided by the related art;

[0031] Figure 7-2 It is a test timing flow chart of a non-volatile memory provided by the related technology;

[0032] Figure 8 Schematic diagram of a testing device for a non-volatile memory provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0034] The terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0035] Unless otherwise stated, the term "plurality" means two or more.

[0036] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0037] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0038] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0039] Combination Figure 1 As shown, an embodiment of the present disclosure provides a test system for a non-volatile memory, including a test device 100 and a test group 200. The test device 100 is connected to the test group 200 for communication based on an I2C bus 300, and each test group 200 includes a plurality of non-volatile memories. The I2C bus 300 represents a bidirectional two-wire synchronous serial bus developed by Philips. It only requires two wires to transmit information between devices connected to the bus. As an example, the test group 200 includes chip 1, chip 2, and chip n. Wherein, n is an integer greater than or equal to 3.

[0040] Based on the above test system for non-volatile memory, combined with Figure 2 As shown, the embodiment of the present disclosure provides a testing method for a non-volatile memory, comprising:

[0041] S01, the testing device sends a test start instruction to the group to be tested to instruct the group to be tested to execute an engineering mode.

[0042] S02: In the engineering mode, the test device allocates different test resources to each group to be tested.

[0043] S03, the testing device performs pipeline testing on all non-volatile memories of the test group corresponding to the test resource in a polling manner to achieve parallel testing of all non-volatile memories.

[0044] Using the test method for non-volatile memory provided by the embodiment of the present disclosure, the embodiment of the present disclosure sends a test start instruction to the group to be tested to start the engineering mode. After the group to be tested starts the engineering mode, the test equipment allocates different test resources to each group to be tested, and performs pipeline testing on all non-volatile memories of the same group to be tested corresponding to the test resources in a polling manner. In this way, all non-volatile memories of the same group to be tested share the test resources to achieve time-sharing multiplexing of the I2C bus during testing, thereby improving the utilization rate of test resources during non-volatile memory testing. At the same time, non-volatile memories of different groups to be tested can be tested in parallel, which helps to shorten the test time of the non-volatile memories and improve the test efficiency of the non-volatile memories in the group to be tested.

[0045] Optionally, combined Figure 3 As shown, the test equipment performs pipeline testing on all non-volatile memories of the group to be tested corresponding to the test resource in a polling manner, including:

[0046] S11, the testing device selects a first non-volatile memory to be tested from the same group to be tested.

[0047] S12, the testing device performs an erase and write test on the first non-volatile memory to be tested.

[0048] S13, after the erase and write test on the first non-volatile memory to be tested is completed, the testing device selects a second non-volatile memory to be tested from other non-volatile memories.

[0049] S14, the testing device performs an erase and write test on the second non-volatile memory to be tested, and completes the erase and write test of all non-volatile memories in the same test group in turn in a polling manner.

[0050] In this way, after the embodiment of the present disclosure selects the first non-volatile memory to be tested from the same group to be tested, the first non-volatile memory to be tested is subjected to an erase and write test. After the erase and write test of the first non-volatile memory to be tested is completed, the embodiment of the present disclosure selects the second non-volatile memory to be tested from other non-volatile memories and performs an erase and write test on it, until the erase and write test of all non-volatile memories in the same group to be tested is completed in sequence by polling. In this way, the embodiment of the present disclosure can implement the erase and write test of all non-volatile memories in each group to be tested by polling pipeline mode, which helps to shorten the test time of the non-volatile memory and improve the test efficiency of the non-volatile memory in the group to be tested.

[0051] Optionally, combined Figure 4 As shown, the test equipment performs pipeline testing on all non-volatile memories of the group to be tested corresponding to the test resource in a polling manner, including:

[0052] S21, the testing device selects a first non-volatile memory to be tested from the same group to be tested.

[0053] S22, the testing device selects other non-volatile memories from the same group to be tested.

[0054] S23, while the test device performs an erase and write test on the first non-volatile memory to be tested, it sends an erase and write instruction to other non-volatile memories or performs a read and verify operation on other non-volatile memories, wherein other non-volatile memories refer to non-volatile memories other than the first non-volatile memory to be tested in the same test group.

[0055] S24, after the erase and write test on the first non-volatile memory to be tested is completed, the testing device selects a second non-volatile memory to be tested from other non-volatile memories.

[0056] S25, the testing device performs an erase and write test on the second non-volatile memory to be tested, and completes the erase and write test of all non-volatile memories in the same test group in turn in a polling manner.

[0057] In this way, the embodiment of the present disclosure selects the first non-volatile memory to be tested from the same group to be tested, and also selects other non-volatile memories from the same group to be tested. While performing the erase and write test on the first non-volatile memory to be tested, erase and write instructions are also sent to other non-volatile memories or read and verify operations are performed on other non-volatile memories. The embodiment of the present disclosure utilizes the characteristics of the I2C bus and the erase and write characteristics of the non-volatile memory to increase the number of parallel tests of the non-volatile memories in the same group to be tested, which helps to improve the test efficiency of the non-volatile memories in the group to be tested.

[0058] Optionally, before the test device sends the test start instruction to the group to be tested, the test device further includes: grouping the non-volatile memories on the same wafer to obtain different groups to be tested, and configuring different test addresses for the non-volatile memories in the same group to be tested.

[0059] Optionally, each non-volatile memory in the same group to be tested is configured with a different test address. The test device selects a first non-volatile memory to be tested and other non-volatile memories from the same group to be tested, including:

[0060] The testing device selects a non-volatile memory corresponding to a target test address from the same group to be tested as a first non-volatile memory to be tested.

[0061] The test equipment selects a non-volatile memory corresponding to a different target test address from the same test group as the other non-volatile memory.

[0062] In this way, after the embodiment of the present disclosure selects the non-volatile memory corresponding to the target test address from the same group to be tested as the first non-volatile memory to be tested, the non-volatile memory different from the non-volatile memory corresponding to the target test address is selected from the same group to be tested as the other non-volatile memory. The embodiment of the present disclosure can perform erase and write tests on the first non-volatile memory to be tested and send erase and write instructions or read verification to other non-volatile memories in a polling manner according to different test addresses in the group to be tested, thereby increasing the number of parallel tests of non-volatile memories in the same group to be tested and improving the test efficiency of non-volatile memories in the group to be tested.

[0063] Optionally, before the test device sends a test start instruction to the group to be tested to instruct the group to be tested to execute the engineering mode, the test device further includes: configuring a different test address for each non-volatile memory of the same group to be tested, and storing the test addresses of all non-volatile memories of each group to be tested.

[0064] The test device selects a non-volatile memory corresponding to a target test address from the same group to be tested as a first non-volatile memory to be tested, including: the test device randomly selects a test address from the test addresses storing the same group to be tested as the target test address of the same group to be tested; the test device selects a non-volatile memory corresponding to the target test address from the same group to be tested as the first non-volatile memory to be tested.

[0065] It should be noted that the specific implementation of the test device selecting the second non-volatile memory to be tested from other non-volatile memories can refer to the specific steps of the test device selecting the target test address from the same group to be tested. The embodiments of the present disclosure will not be repeated here.

[0066] Optionally, the test device performs a read verification operation on other non-volatile memories, including: sending a read instruction to the other non-volatile memories to execute a data read operation, and reading data from the other non-volatile memories.

[0067] In this way, the embodiment of the present disclosure can perform read and verify operations on other non-volatile memories while performing erase and write tests on the first non-volatile memory to be tested, which is beneficial to increase the number of parallel tests of non-volatile memories in the same group to be tested, thereby improving the test efficiency of the non-volatile memories in the group to be tested.

[0068] Optionally, the test device allocates different test resources to each group to be tested, including:

[0069] The test device connects the serial data lines of all non-volatile memories in the same test group, and allocates the first test resource to all non-volatile memories in the same test group through the serial data lines.

[0070] The test equipment connects the serial data lines of all non-volatile memories in the same test group, and allocates second test resources to all non-volatile memories in each of the same test group through the serial data lines; wherein the second test resources are independent of the first test resources.

[0071] In this way, the disclosed embodiment connects the serial data lines of all non-volatile memories in the same group to be tested and allocates the first test resource to all non-volatile memories in the same group to be tested through the serial data lines. At the same time, the disclosed embodiment connects the serial data lines of all non-volatile memories in other groups to be tested and allocates the second test resource, which is independent of the first test resource, to all non-volatile memories in other groups to be tested through the serial data lines. In this way, only one set of input and output ports need to be led out for the same group to be tested, which is conducive to reducing the number of line connections when testing non-volatile memories and further improving the test efficiency of non-volatile memories in the group to be tested.

[0072] Optionally, the serial data lines of all non-volatile memories in the same test group are connected via a probe card, and the serial clock lines of all non-volatile memories in the same test group are connected via a probe card.

[0073] In this way, by connecting the serial data lines of all non-volatile memories in the same group to be tested through probe cards and connecting the serial clock lines of all non-volatile memories in the same group to be tested through probe cards, the same group to be tested only needs to lead out one group of input and output ports to implement the test of the group to be tested, while reducing the number of non-volatile memory test line connections and reducing the needle card cost, thereby reducing the test cost of the non-volatile memories in the group to be tested.

[0074] Combination Figure 5 As shown, the embodiment of the present disclosure also provides another testing method for a non-volatile memory, including:

[0075] S31, the testing device sends a test start instruction to the group to be tested to instruct the group to be tested to execute the engineering mode.

[0076] S32: In the engineering mode, the test device allocates different test resources to each group to be tested.

[0077] S33, the testing device performs pipeline testing on all non-volatile memories of the test group corresponding to the test resource in a polling manner to achieve parallel testing of all non-volatile memories.

[0078] S34, after the parallel test of all non-volatile memories of the test equipment is completed, a user start instruction is sent to the group to be tested to instruct the group to be tested to execute the user mode.

[0079] S35 , the test device performs address configuration on each non-volatile memory of the same test group according to the mode requirement in the user mode in the user mode, so as to reset the test address of the non-volatile memory in the engineering mode to the device address.

[0080] Using the test method for non-volatile memory provided by the embodiment of the present disclosure, the embodiment of the present disclosure sends a test start instruction to the group to be tested to enable it to start the engineering mode. After the group to be tested starts the engineering mode, the test equipment allocates different test resources to each group to be tested, and performs pipeline testing on all non-volatile memories of the same group to be tested corresponding to the test resources in a polling manner. After completing the parallel testing of all non-volatile memories, the embodiment of the present disclosure also sends a user start instruction to the group to be tested to instruct it to execute the user mode. In the user mode, the test equipment performs address configuration on each non-volatile memory of the same group to be tested according to the mode requirements in the user mode to reset the test address of the non-volatile memory in the engineering mode to the device address, thereby ensuring that the device address of the group to be tested is the address required in the user mode after the test is completed, and is not restricted by the test scheme.

[0081] In a specific embodiment, the test addresses of all non-volatile memories of each group to be tested in the engineering mode are independent of the device addresses of all non-volatile memories of each group to be tested in the user mode. Before instructing the group to be tested to execute the engineering mode, the test device configures different test addresses to each non-volatile memory of the same group to be tested. And after instructing the group to be tested to execute the user mode, the test address is configured for each non-volatile memory of the same group to be tested according to the mode requirements in the user mode to reset the test address of the non-volatile memory in the engineering mode to the device address to achieve the corresponding configuration of the device address in each group to be tested.

[0082] In practical applications, Figure 6-1 This is a schematic diagram of connecting multiple non-volatile memories in the same test group provided by an embodiment of the present disclosure. Figure 6-2 This is a test timing flow chart of a non-volatile memory in the same test group provided by an embodiment of the present disclosure.

[0083] like Figure 6-1 and Figure 6-2 As shown, the same test group includes 8 non-volatile memories, and the test addresses of the 8 non-volatile memories in the engineering mode are configured as 0, 1, 2, 3, 4, 5, 6, and 7 respectively.

[0084] The serial data lines SDA of the eight non-volatile memories are connected through the probe card, and the test equipment allocates the first test resources to the eight non-volatile memories of the group to be tested through the serial data lines SDA. At the same time, the serial clock lines SCL of the eight non-volatile memories are connected through the probe card, and the test equipment allocates the second test resources to the eight non-volatile memories of the group to be tested through the serial clock lines SCL.

[0085] After the test equipment selects the non-volatile memory at the test address 0 as the first non-volatile memory to be tested, it performs an erase and write test on the first non-volatile memory to be tested. During the erase and write test, it sends an erase and write instruction to other non-volatile memories or performs a read and verify operation on other non-volatile memories, so as to complete the erase and write test of all non-volatile memories in the same test group in turn through polling.

[0086] Figure 7-1 It is a connection diagram of a non-volatile memory provided by the related technology. Figure 7-2 The test timing flow chart of a non-volatile memory provided by the related technology is shown in FIG. The test group includes 8 non-volatile memories, and the device addresses of the 8 non-volatile memories are all configured as 0.

[0087] like Figure 7-1 and Figure 7-2As shown, in the related art, the test equipment configures the same device address for 8 non-volatile memories; after the test equipment configuration is completed, independent test resources are allocated to the 8 non-volatile memories respectively; the test equipment tests the non-volatile memories corresponding to each test resource in a parallel test mode.

[0088] By comparison, it can be seen that, by adopting the test method for non-volatile memory provided by the embodiment of the present disclosure, only one group of I2C buses needs to be allocated to the non-volatile memory of the same group to be tested. At the same time, the characteristics of the I2C bus and the erasing characteristics of the non-volatile memory are fully utilized to realize time-sharing testing of the non-volatile memory, thereby saving the total test time of the group to be tested.

[0089] Combination Figure 8 As shown, the embodiment of the present disclosure provides a test device 70 for non-volatile memory, including a processor (processor) 700 and a memory (memory) 701. Optionally, the device 70 may also include a communication interface (Communication Interface) 702 and a bus 703. Among them, the processor 700, the communication interface 702, and the memory 701 can communicate with each other through the bus 703. The communication interface 702 can be used for information transmission. The processor 700 can call the logic instructions in the memory 701 to execute the test method for non-volatile memory of the above embodiment.

[0090] In addition, the logic instructions in the memory 701 described above may be implemented in the form of software functional units and when sold or used as independent products, may be stored in a computer-readable storage medium.

[0091] The memory 701 is a computer-readable storage medium that can be used to store software programs and computer executable programs, such as program instructions / modules corresponding to the method in the embodiment of the present disclosure. The processor 700 executes the functional application and data processing by running the program instructions / modules stored in the memory 701, that is, the test method for non-volatile memory in the above embodiment is implemented.

[0092] The memory 701 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory 701 may include a high-speed random access memory and may also include a non-volatile memory.

[0093] Combination Figure 1As shown, an embodiment of the present disclosure provides a test device 100, including: a test device body, and the above-mentioned test device 70 for non-volatile memory. The test device 70 for non-volatile memory is installed on the test device body. The installation relationship described here is not limited to placement inside the product body, but also includes installation connections with other components of the test device 100, including but not limited to physical connections, electrical connections or signal transmission connections. It can be understood by those skilled in the art that the test device 70 for non-volatile memory can be adapted to a feasible test device body, thereby realizing other feasible embodiments.

[0094] An embodiment of the present disclosure provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are configured to execute the above-mentioned test method for a non-volatile memory.

[0095] The technical solution of the embodiment of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiment of the present disclosure. The aforementioned storage medium may be a non-transient storage medium, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, and other media that can store program codes.

[0096] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible changes. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and the claims, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

[0097] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods for each specific application to implement the described functions, but such implementations should not be considered to exceed the scope of the embodiments of the present disclosure. The technicians may clearly understand that, for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above may refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

[0098] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units can be only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiment of the present disclosure may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit.

[0099] The flowchart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to the embodiment of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. In the description corresponding to the flowchart and the block diagram in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in a different order from the order disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified functions or actions, or may be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. A testing method for a non-volatile memory, characterized in that: Applied to test equipment, the test equipment is connected to the test group based on the I2C bus, and each test group includes multiple non-volatile memories; Test methods include: Sending a test start instruction to the group to be tested to instruct the group to be tested to execute the engineering mode; In engineering mode, different test resources are allocated to each group to be tested; All non-volatile memories of the test group corresponding to the test resource are pipeline tested in a polling manner to achieve parallel testing of all non-volatile memories.

2. The testing method according to claim 1, characterized in that: Perform pipeline testing on all non-volatile memories of the group to be tested corresponding to the test resource in a polling manner, including: Selecting a first non-volatile memory to be tested from the same group to be tested; Performing an erase and write test on the first non-volatile memory to be tested; After the erase and write test of the first non-volatile memory to be tested is completed, selecting a second non-volatile memory to be tested from other non-volatile memories; The second non-volatile memory to be tested is subjected to an erasure test, and the erasure test of all non-volatile memories in the same group to be tested is completed in turn in a polling manner.

3. The testing method according to claim 2, characterized in that: Performing pipeline testing on all non-volatile memories of the group to be tested corresponding to the test resource in a polling manner, further comprising: After selecting the first non-volatile memory to be tested from the same group to be tested, selecting other non-volatile memories from the same group to be tested; While performing an erase and write test on the first non-volatile memory to be tested, an erase and write instruction is sent to other non-volatile memories or a read and verify operation is performed on other non-volatile memories.

4. The testing method according to claim 3, characterized in that: Each non-volatile memory of the same test group is configured with a different test address; Selecting a first non-volatile memory to be tested and other non-volatile memories from the same group to be tested, including: Selecting a non-volatile memory corresponding to a target test address from the same test group as a first non-volatile memory to be tested; A non-volatile memory different from the one corresponding to the target test address is selected from the same test group as the other non-volatile memory.

5. The testing method according to claim 4, characterized in that: Also includes: Before sending a test start instruction to the group to be tested to instruct the group to be tested to execute the engineering mode, the non-volatile memories on the same wafer are grouped to obtain different groups of groups to be tested, and different test addresses are configured for the non-volatile memories in the same group to be tested.

6. The testing method according to claim 3, characterized in that: Perform read verification operations on other non-volatile memories, including: A read command is sent to the other nonvolatile memory to perform a data read operation, and data is read from the other nonvolatile memory.

7. The testing method according to any one of claims 1 to 6, characterized in that: Different test resources are allocated to each test group, including: Connecting serial data lines of all non-volatile memories in the same test group, and respectively allocating first test resources to all non-volatile memories in the same test group through the serial data lines; and, The serial data lines of all non-volatile memories in the same test group are connected, and second test resources are respectively allocated to all non-volatile memories in each of the same test group through the serial data lines; wherein the second test resources are independent of the first test resources.

8. The testing method according to any one of claims 1 to 6, characterized in that: Also includes: After the parallel test of all non-volatile memories is completed, a user start instruction is sent to the group to be tested to instruct the group to be tested to execute the user mode; In the user mode, address configuration is performed on each non-volatile memory of the same test group according to the mode requirement in the user mode, so as to reset the test address of the non-volatile memory in the engineering mode to the device address.

9. A testing device for a non-volatile memory, comprising a processor and a memory storing program instructions, characterized in that: The processor is configured to execute the testing method for a non-volatile memory according to any one of claims 1 to 8 when running the program instructions.

10. A testing device, characterized in that: include: Test equipment body; The test device for non-volatile memory as claimed in claim 9 is installed in the test equipment body.

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