Preparation method of gate oxide layer, MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and electronic equipment

Abstract

The invention relates to the technical field of semiconductors, and provides a gate oxide layer preparation method, an MOSFET and electronic equipment, and the gate oxide layer preparation method comprises the steps: providing a silicon carbide substrate, cleaning the silicon carbide substrate, and carrying out the wet oxygen pretreatment, so as to form a first oxide layer on the surface of the silicon carbide substrate; performing high-temperature thermal oxidation on the silicon carbide substrate on which the first oxide layer is formed so as to grow a second oxide layer on the first oxide layer; depositing an oxide film on the second oxide layer through ALD, wherein the oxide film comprises silicon oxide and a plurality of hydroxyl groups; and carrying out nitriding annealing on the first oxide layer, the second oxide layer and the oxide film to form a gate oxide layer on the silicon carbide substrate. By adopting the method, the interface state density of the gate oxide layer can be reduced to 1e10 <-1 > e11cm <-2 > eV <-1 > level, and the prepared gate oxide layer has a more stable interface.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a gate oxide layer preparation method, MOSFET and electronic equipment. Background Art

[0002] MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a field effect transistor that controls the switching of a semiconductor conductive channel by applying voltage to the gate of a metal layer and the source through an oxide layer, thereby generating an electric field effect.

[0003] Silicon carbide has the characteristics of large bandgap, high critical breakdown electric field, high thermal conductivity and high electron saturation drift velocity. Silicon carbide MOSFET performs better than silicon-based MOSFET in the fields of high voltage, high temperature and high power. Therefore, silicon carbide-based MOSFET is now gradually replacing silicon-based MOSFET. Both can prepare the oxide dielectric layer by high-temperature thermal oxidation method.

[0004] However, in the process of high-temperature oxidation of silicon carbide to form a gate oxide layer, due to the different properties of carbon and silicon in silicon carbide, a large number of defects with different structures and properties will appear at the interface between silicon carbide and silicon oxide. These defects can easily become carrier capture traps, and the interface state density is high, resulting in lower channel mobility and higher on-resistance of silicon carbide MOSFET. The existing technology only uses high-temperature thermal oxidation and oxynitride passivation to improve the interface state density, which is limited. Summary of the invention

[0005] In view of the shortcomings of the prior art, the purpose of the present invention is to provide a gate oxide layer preparation method, MOSFET and electronic equipment. The present invention solves the technical problems of high interface state density and unstable interface in traditional silicon carbide MOSFET by wet oxygen pretreatment and high-temperature thermal oxidation combined with ALD deposition of an oxide dielectric layer.

[0006] In order to achieve the above object, the present invention is implemented by the following technical solutions: A method for preparing a gate oxide layer comprises the following steps: Providing a silicon carbide substrate, cleaning the silicon carbide substrate, and performing a wet oxygen pretreatment to form a first oxide layer on the surface of the silicon carbide substrate; Performing high-temperature thermal oxidation on the silicon carbide substrate on which the first oxide layer is formed, so as to grow a second oxide layer on the first oxide layer; ALD deposits an oxide film on the second oxide layer, wherein the oxide film includes silicon oxide and a plurality of hydroxide groups; The first oxide layer, the second oxide layer and the oxide film are subjected to nitridation annealing to form a gate oxide layer on the silicon carbide substrate.

[0007] Compared with the prior art, the beneficial effects of the present invention are as follows: a composite silicon oxide dielectric layer including the first oxide layer and the second oxide layer is formed by wet oxygen pretreatment and high-temperature thermal oxidation, and then the high-quality oxide film with hydroxyl groups can be effectively deposited by ALD (Atomic Layer Deposited) deposition technology to form a stacked structure, and the stacked structure can capture positive charges and generate positive fixed charges. Compared with the traditional structure formed only by high-temperature thermal oxidation or passivation treatment, the stacked structure can generate a flat band voltage that is more left, and then the gate oxide layer is formed after nitridation annealing, and the gate oxide layer is further stabilized, and the interface state density of the gate oxide layer can be reduced to 1e10~1e11cm -2 eV -1 The prepared gate oxide layer has a more stable interface.

[0008] Furthermore, the thickness of the first oxide layer ranges from 10Å to 100Å.

[0009] Furthermore, the thickness of the second oxide layer is less than 20 nm.

[0010] Furthermore, the temperature range of the wet oxygen pretreatment is 650° C. to 1150° C., and the time of the wet oxygen pretreatment is 10 min to 200 min.

[0011] Furthermore, the temperature range of the high-temperature thermal oxidation is 650° C. to 1500° C., and the time of the high-temperature thermal oxidation is 1 min to 120 min.

[0012] Furthermore, the temperature range of the ALD deposition is 260°C to 360°C.

[0013] Furthermore, the temperature of the nitridation annealing is less than or equal to the temperature of the high-temperature thermal oxidation, and the time of the nitridation annealing is 30 min to 180 min.

[0014] A MOSFET comprises a gate oxide layer, wherein the gate oxide layer is prepared by the gate oxide layer preparation method as described in the above technical solution.

[0015] An electronic device comprises the MOSFET as described in the above technical solution. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a flowchart of a method for preparing a gate oxide layer in Example 1 of the present invention; The following specific implementation manner will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0017] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0018] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0020] See also Figure 1 The method for preparing a gate oxide layer in Embodiment 1 of the present invention comprises the following steps: Step S10: providing a silicon carbide substrate, cleaning the silicon carbide substrate, and performing a wet oxygen pretreatment to form a first oxide layer on the surface of the silicon carbide substrate; Preferably, a wafer made of silicon carbide is provided for pre-gate cleaning, and the pre-gate cleaning adopts SC1 solution. Furthermore, the wafer may be subjected to a sacrificial oxidation process, and then the natural oxide layer on the surface is removed to improve the surface morphology of silicon carbide.

[0021] Specifically, in the step S10, the thickness of the first oxide layer ranges from 10Å to 100Å, the temperature range of the wet oxygen pretreatment is from 650°C to 1150°C, and the time of the wet oxygen pretreatment is from 10min to 200min.

[0022] The first oxide layer is silicon oxide, the thickness of the first oxide layer is 50Å, and the first oxide layer covers the silicon carbide substrate.

[0023] Step S20: performing high-temperature thermal oxidation on the silicon carbide substrate on which the first oxide layer is formed, so as to grow a second oxide layer on the first oxide layer; Preferably, the high temperature thermal oxidation adopts dry oxygen oxidation.

[0024] Specifically, in step S20, the thickness of the second oxide layer is less than 20 nm, the temperature range of the high-temperature thermal oxidation is 650° C. to 1500° C., and the time of the high-temperature thermal oxidation is 1 min to 120 min.

[0025] Preferably, the thickness of the second oxide layer is 12 nm, and the total thickness of the first oxide layer and the second oxide layer is measured by using an ellipsometer to obtain a 5-point average thickness.

[0026] Step S30: depositing an oxide film on the second oxide layer by ALD, wherein the oxide film includes silicon oxide and a plurality of hydroxyl groups; Specifically, in step S30, the temperature range of the ALD deposition is 260°C to 360°C.

[0027] Preferably, an ALD process precursor that can generate silicon oxide and hydroxyl groups is used. The oxide film layer has oxygen vacancies. The oxygen vacancies are similar to donor traps and bind positive charges. The traditional oxide layer prepared only by high-temperature thermal oxidation method captures electrons and generates negative fixed charges. The structure prepared by the method in this embodiment can produce a flat band voltage that is more left than the traditional structure.

[0028] Step S40: performing nitridation annealing on the first oxide layer, the second oxide layer and the oxide film to form a gate oxide layer on the wafer.

[0029] Preferably, the nitridation annealing is performed in a nitrogen monoxide atmosphere, the temperature of the nitridation annealing is 1200° C., and the duration is 100 min.

[0030] Specifically, in the step S40, the temperature of the nitridation annealing is less than or equal to the temperature of the high-temperature thermal oxidation, and the time of the nitridation annealing is 30 min to 180 min.

[0031] Preferably, in Example 1, the wet oxygen pretreatment temperature is 1000°C, the wet oxygen pretreatment time is 120 min, the high temperature thermal oxidation temperature is 1400°C, the high temperature thermal oxidation time is 2 min, and the ALD deposition temperature is 300°C.

[0032] Embodiment 2 of the present invention also provides a method for preparing a gate oxide layer. The difference between the method for preparing a gate oxide layer in this embodiment and the method for preparing a gate oxide layer in Embodiment 1 is that: The wet oxygen pretreatment temperature is 650°C.

[0033] Embodiment 3 of the present invention also provides a method for preparing a gate oxide layer. The difference between the method for preparing a gate oxide layer in this embodiment and the method for preparing a gate oxide layer in Embodiment 1 is that: The wet oxygen pretreatment temperature is 1150°C.

[0034] Embodiment 4 of the present invention also provides a method for preparing a gate oxide layer. The difference between the method for preparing a gate oxide layer in this embodiment and the method for preparing a gate oxide layer in Embodiment 1 is that: The wet oxygen pretreatment time is 10 minutes.

[0035] Embodiment 5 of the present invention also provides a method for preparing a gate oxide layer. The difference between the method for preparing a gate oxide layer in this embodiment and the method for preparing a gate oxide layer in Embodiment 1 is that: The wet oxygen pretreatment time is 200 minutes.

[0036] Embodiment 6 of the present invention also provides a method for preparing a gate oxide layer. The difference between the method for preparing a gate oxide layer in this embodiment and the method for preparing a gate oxide layer in Embodiment 1 is that: The ALD deposition temperature is 260°C.

[0037] Embodiment 7 of the present invention also provides a method for preparing a gate oxide layer. The difference between the method for preparing a gate oxide layer in this embodiment and the method for preparing a gate oxide layer in Embodiment 1 is that: The ALD deposition temperature is 360°C.

[0038] Comparative Example 1 A method for preparing a gate oxide layer, which is different from the method for preparing a gate oxide layer in Example 1 in that: The wet oxygen pretreatment temperature is 400°C.

[0039] Comparative Example 2 A method for preparing a gate oxide layer, which is different from the method for preparing a gate oxide layer in Example 1 in that: The wet oxygen pretreatment time is 240 minutes.

[0040] Comparative Example 3 A method for preparing a gate oxide layer, which is different from the method for preparing a gate oxide layer in Example 1 in that: The ALD deposition temperature is 250°C.

[0041] Comparative Example 4 A method for preparing a gate oxide layer, which is different from the method for preparing a gate oxide layer in Example 1 in that: A wafer with an exposed silicon carbide substrate is provided, the wafer is cleaned, and the wafer is subjected to only high-temperature thermal oxidation, the high-temperature thermal oxidation temperature is 1400° C., and the high-temperature thermal oxidation time is 13 minutes. It can be understood that the gate oxide layer preparation method in this comparative example is a traditional full thermal oxidation method.

[0042] The experiment used a silicon carbide substrate with a 4° deviation from the (11-20) crystal plane and doped with nitrogen at a concentration of 8e15cm -3 , and the natural oxide layer on the surface of the wafer is removed by cleaning and sacrificial oxidation process, and gate oxide layers are prepared on multiple wafers according to the gate oxide layer preparation methods in the above embodiments 1 to 7 and comparative examples 1 to 4, wherein annealing treatment is performed in a nitrogen monoxide atmosphere, and after the gate oxide layer is prepared, a BOE etching solution is used to remove the oxide layer on the back of the wafer, and an aluminum electrode is formed on the front of the wafer by a sputtering process, and a test pattern is formed by a photolithography process and an aluminum etching solution, and aluminum metal is sputtered on the back of the wafer to form a back electrode for testing, and finally the interface state density is measured by a high-frequency-quasi-static method, and the corresponding preparation parameters and test results are shown in the following table:

[0043] It should be noted that, in order to ensure the reliability of the verification results, when the gate oxide layers of the above embodiments 1 to 7 and comparative examples 1 to 4 of the present invention are prepared, except for the above parameters, other processes and parameters should remain consistent.

[0044] It can be concluded from the above table that the gate oxide layer prepared by the gate oxide layer preparation method provided in Example 1 of the present invention has a greatly reduced interface state density compared to Comparative Example 4, that is, compared to the traditional full thermal oxidation gate oxide layer. The traps of the gate oxide layer prepared in Example 1 capture positive charges and generate positive fixed charges, which generate a flat band voltage that is more left than the traditional full thermal oxidation gate oxide layer. By controlling each parameter within a preset range, the stability of the overall structure can be effectively ensured, and the interface quality of the gate oxide layer can be greatly improved.

[0045] In some embodiments, the present invention further provides a MOSFET, wherein the MOSFET includes a gate oxide layer, and the gate oxide layer is prepared by the gate oxide layer preparation method described in the above embodiment 1.

[0046] In some embodiments, the present invention further provides an electronic device, wherein the electronic device comprises the MOSFET as described in the above embodiments.

[0047] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0048] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for preparing a gate oxide layer, characterized in that: The steps include: Providing a silicon carbide substrate, cleaning the silicon carbide substrate, and performing a wet oxygen pretreatment to form a first oxide layer on the surface of the silicon carbide substrate; Performing high-temperature thermal oxidation on the silicon carbide substrate on which the first oxide layer is formed, so as to grow a second oxide layer on the first oxide layer; ALD deposits an oxide film on the second oxide layer, wherein the oxide film includes silicon oxide and a plurality of hydroxide groups; The first oxide layer, the second oxide layer and the oxide film are subjected to nitridation annealing to form a gate oxide layer on the silicon carbide substrate.

2. The method for preparing a gate oxide layer according to claim 1, characterized in that: The thickness of the first oxide layer ranges from 10Å to 100Å.

3. The method for preparing a gate oxide layer according to claim 1, characterized in that: The thickness of the second oxide layer is less than 20 nm.

4. The method for preparing a gate oxide layer according to claim 1, characterized in that: The temperature range of the wet oxygen pretreatment is 650° C. to 1150° C., and the time of the wet oxygen pretreatment is 10 min to 200 min.

5. The method for preparing a gate oxide layer according to claim 1, characterized in that: The temperature range of the high temperature thermal oxidation is 650° C. to 1500° C., and the time of the high temperature thermal oxidation is 1 min to 120 min.

6. The method for preparing a gate oxide layer according to claim 1, characterized in that: The temperature range of the ALD deposition is 260°C to 360°C.

7. The method for preparing a gate oxide layer according to claim 5, characterized in that: The temperature of the nitridation annealing is less than or equal to the temperature of the high-temperature thermal oxidation, and the time of the nitridation annealing is 30 min to 180 min.

8. A MOSFET comprising a gate oxide layer, characterized in that: The gate oxide layer is prepared by the gate oxide layer preparation method according to any one of claims 1 to 7.

9. An electronic device, characterized in that: Comprising a MOSFET as claimed in claim 8.

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