Board-level packaging method and packaging structure

Abstract

The embodiment of the invention provides a board-level packaging method and a packaging structure, and the method comprises the steps: providing a square panel, and enabling a first surface of the square panel to be provided with a plurality of grooves; fixing the non-functional surfaces of the plurality of bridging chips in the corresponding grooves; forming a first rewiring layer on the first surface of the square panel and the functional surface of the bridging chip; forming a plurality of conductive columns penetrating through the thickness of the square panel on the square panel; forming a second rewiring layer electrically connected with the conductive columns on the second surface of the square panel; and forming a power management module on the second rewiring layer, and forming a chip operation module on the first rewiring layer. A large-area square panel is adopted as a carrier plate, so that high computing power integration of the board-level packaging structure is realized; the square panel is provided with a groove, and the plurality of bridging chips are arranged in the groove, so that the packaging height of the whole packaging structure is reduced; the chip operation module realizes high-density interconnection by means of a plurality of bridging chips; and a plurality of conductive columns penetrating through the thickness of the square panel are formed on the square panel, so that the transmission path is effectively shortened.

Description

Technical Field

[0001] The disclosed embodiments belong to the field of semiconductor packaging technology, and specifically relate to a board-level packaging method and packaging structure. Background Art

[0002] SoW (System on wafer) integrates a certain number of computing chips onto a whole wafer as a whole to form an ultra-high performance (HPC) chip system.

[0003] SoW uses FO technology to reconstruct the computing chip into a wafer with a glass carrier as the carrier, completes the interconnection between chips through plastic packaging and rewiring, peels off the carrier, and interconnects the power device with the computing chip through flip-chip on the reconstructed wafer to form the entire on-wafer system.

[0004] Due to the limitation of wafer size, the overall performance of a single SoW system is limited.

[0005] In view of the above problems, it is necessary to propose a board-level packaging method and packaging structure that are reasonably designed and effectively solve the above problems. Summary of the invention

[0006] The embodiments of the present disclosure aim to solve at least one of the technical problems existing in the prior art and provide a board-level packaging method and packaging structure.

[0007] The present disclosure provides a board-level packaging method, the method comprising:

[0008] Providing a square panel, wherein a first surface of the square panel is provided with a plurality of grooves;

[0009] Fixing the non-functional surfaces of the plurality of bridge chips to the corresponding grooves;

[0010] forming a first redistribution layer on the first surface of the square panel and the functional surface of the bridge chip;

[0011] forming a plurality of conductive pillars on the square panel extending through the thickness of the square panel;

[0012] forming a second redistribution layer electrically connected to the conductive pillars on the second surface of the square panel;

[0013] A power management module is formed on the second redistribution layer, and a chip operation module is formed on the first redistribution layer.

[0014] Optionally, forming a plurality of conductive pillars on the square panel and penetrating the thickness of the square panel includes:

[0015] Drilling along the second surface of the square panel to form a plurality of through holes penetrating the thickness of the square panel;

[0016] A conductive material is electroplated in the through hole to form the conductive pillar.

[0017] Optionally, the forming of a plurality of conductive pillars penetrating the thickness of the square panel further comprises:

[0018] When providing the square panel, a first surface of the square panel is provided with a plurality of blind holes extending toward a second surface thereof, and a conductive material is provided in the blind holes;

[0019] After forming the first redistribution layer, the second surface of the square panel is thinned to expose the blind hole, thereby forming the conductive column that penetrates the thickness of the square panel.

[0020] Optionally, forming a power management module on the second redistribution layer includes:

[0021] A plurality of power management chips and a plurality of first connectors are formed on the second redistribution layer.

[0022] Optionally, forming a chip computing module on the first redistribution layer includes:

[0023] A chip operation layer and a plurality of second connectors are formed on the first redistribution layer, wherein the chip operation layer includes at least a plurality of computing chips.

[0024] Optionally, forming a chip computing module on the first redistribution layer further includes:

[0025] A chip operation layer and a plurality of photoelectric conversion chips are formed on the first redistribution layer, wherein the chip operation layer at least includes a plurality of computing chips.

[0026] Optionally, fixing the plurality of non-functional surfaces of the bridge chips to the corresponding grooves includes:

[0027] Mounting the non-functional surfaces of the plurality of bridge chips on the bottom wall of the corresponding groove, with a gap between the bridge chip and the side wall of the groove;

[0028] The first redistribution layer is formed on the first surface of the square panel and the functional surface of the bridge chip, comprising:

[0029] forming a first dielectric layer in the gap, the first surface of the square panel, and the functional surface of the bridge chip;

[0030] Patterning the first dielectric layer located on the first surface of the square panel and the functional surface of the bridge chip to form a plurality of first openings on the first dielectric layer;

[0031] A first metal layer electrically connected to the bridge chip is formed in the first opening.

[0032] Optionally, forming a second redistribution layer electrically connected to the conductive pillar on the second surface of the square panel includes:

[0033] forming a second dielectric layer on a second surface of the square panel;

[0034] patterning the second dielectric layer to form a plurality of second openings on the second dielectric layer;

[0035] A second metal layer electrically connected to the conductive pillar is formed in the second opening.

[0036] Optionally, the square panel is a glass panel.

[0037] Another aspect of the embodiments of the present disclosure provides a board-level packaging structure, which is formed by packaging using the board-level packaging method described above.

[0038] The board-level packaging method and packaging structure of the embodiments of the present disclosure provide a square panel, form a board-level packaging structure on the square panel, and use a large-area square panel as a carrier board, which significantly improves the chip capacity, area utilization and I / O density, and significantly improves system performance, thereby solving the problem of limited performance of a single SoW system and realizing high computing power integration of the board-level packaging structure; the square panel is provided with a plurality of grooves, and a plurality of bridge chips are arranged in the grooves of the corresponding square panels, thereby reducing the packaging height of the entire packaging structure; the chip computing module realizes high-density interconnection with the help of a plurality of bridge chips, and no longer needs to rely on building a fine line structure in the RDL; a plurality of conductive columns are formed on the square panel to penetrate its thickness, thereby realizing vertical interconnection of the packaging structure, and realizing vertical power supply on the back of the square panel, thereby effectively shortening the transmission path. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A schematic diagram of a process of a board-level packaging method according to an embodiment of the present disclosure;

[0040] Figures 2 to 15 A schematic diagram of a process flow of a board-level packaging method according to an embodiment of the present disclosure;

[0041] Figures 16 to 29 A schematic diagram of a process flow of a board-level packaging method according to another embodiment of the present disclosure;

[0042] Fig.30 It is a structural schematic diagram of a board-level packaging system of another embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the embodiments of the present disclosure are further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0044] like Figure 1 As shown, one aspect of an embodiment of the present disclosure provides a board-level packaging method S100, the method 100 comprising:

[0045] S110, providing a square panel, wherein a first surface of the square panel is provided with a plurality of grooves.

[0046] S120, fixing the non-functional surfaces of the plurality of bridge chips to the corresponding grooves.

[0047] S130 , forming a first redistribution layer on the first surface of the square panel and the functional surface of the bridge chip.

[0048] S140, forming a plurality of conductive pillars penetrating the thickness of the square panel.

[0049] S150, forming a second redistribution layer electrically connected to the conductive pillars on the second surface of the square panel.

[0050] S160, forming a power management module on the second redistribution layer, and forming a chip operation module on the first redistribution layer.

[0051] The board-level packaging method and packaging structure of the embodiments of the present disclosure provide a square panel, form a board-level packaging structure on the square panel, and use a large-area square panel as a carrier board, which significantly improves the chip capacity, area utilization and I / O density, and significantly improves system performance, thereby solving the problem of limited performance of a single SoW system and realizing high computing power integration of the board-level packaging structure; the square panel is provided with a plurality of grooves, and a plurality of bridge chips are arranged in the grooves of the corresponding square panels, thereby reducing the packaging height of the entire packaging structure; the chip computing module realizes high-density interconnection with the help of a plurality of bridge chips, and no longer needs to rely on building a fine line structure in the RDL; a plurality of conductive columns are formed on the square panel to penetrate its thickness, thereby realizing vertical interconnection of the packaging structure, and realizing vertical power supply on the back of the square panel, thereby effectively shortening the transmission path.

[0052] The specific process of a board-level packaging method S100 according to an embodiment of the present disclosure is described below in conjunction with several embodiments.

[0053] Example 1

[0054] In step S110, Figure 2As shown, a square panel 22 is provided, and a first surface of the square panel 22 is provided with a plurality of grooves 44. Wherein, when the square panel 22 is provided, a first surface of the square panel 22 is provided with a plurality of blind holes 46' extending toward a second surface thereof, and a conductive material is provided in the blind holes 46'.

[0055] In this embodiment, a large-area square panel is used as a carrier board, which significantly improves the chip capacity, area utilization and I / O density, and significantly improves system performance, thereby solving the problem of limited performance of a single SoW system and realizing high computing power integration of a board-level packaging structure.

[0056] In step S120, Figure 3 As shown, the non-functional surfaces of the plurality of bridge chips 24 are fixed to the corresponding grooves 44 .

[0057] Specifically, Figure 3 As shown, the non-functional surfaces of the plurality of bridge chips 24 are mounted and fixed to the bottom wall of the corresponding groove 44. There is a gap between the bridge chip 24 and the side wall of the groove 44. It should be noted that the number of the bridge chips 24 is not specifically limited and can be limited according to actual needs.

[0058] In step S130, Figure 4 and Figure 5 As shown, a first redistribution layer is formed on the first surface of the square panel 22 and the functional surface of the bridge chip 24 .

[0059] The process of forming the first redistribution layer may be as follows:

[0060] Specifically, Figure 4 As shown, a first dielectric layer 28 is formed in the gap, the first surface of the square panel 22 and the functional surface of the bridge chip 24. In this embodiment, the first dielectric layer 28 can be a PI layer.

[0061] The first dielectric layer 28 located on the first surface of the square panel 22 and the functional surface of the bridge chip 24 is patterned to form a plurality of first openings on the first dielectric layer 28 .

[0062] like Figure 5 As shown, a first metal layer 30 electrically connected to the bridge chip 24 is formed in the first opening. In the embodiment of the present disclosure, the first metal layer 30 may be a metal copper layer.

[0063] like Figure 6 As shown, the first redistribution layer is fixed to the carrier 50 by temporary bonding adhesive. Figure 7 As shown, the flipping makes the carrier plate 50 located at the bottom for support.

[0064] In step S140 , a plurality of conductive pillars are formed on the square panel to penetrate the thickness of the square panel.

[0065] Specifically, Figure 7 As shown, the second surface of the square panel 22 is thinned by grinding or the like to expose the blind holes, thereby forming a plurality of conductive pillars 46 that penetrate the thickness of the square panel 22. In other words, the conductive pillars 46 are TGVs.

[0066] In this embodiment, by forming a plurality of conductive pillars on the square panel and penetrating the thickness of the square panel, vertical interconnection between the two sides of the square panel can be achieved, thereby effectively shortening the transmission path.

[0067] In step S150, Figure 8 As shown, a second redistribution layer electrically connected to the conductive pillars 46 is formed on the second surface of the square panel 22 .

[0068] The process of forming the second redistribution layer may be as follows:

[0069] like Figure 8 As shown, a coating process or the like is used to form a second dielectric layer 52 on the second surface of the square panel 22. In this embodiment, the second dielectric layer 52 may be a PI layer.

[0070] The second dielectric layer 52 is patterned by photolithography, etching and other processes to form a plurality of second openings on the second dielectric layer 52 .

[0071] like Figure 8 As shown, a second metal layer 54 electrically connected to the conductive pillar 46 is formed in the second opening by electroplating or other processes. The second metal layer 54 may be a metal copper layer.

[0072] In step S160, if Figures 9 to 15 As shown, a power management module is formed on the second redistribution layer, and a chip operation module is formed on the first redistribution layer.

[0073] Wherein, forming a power management module on the second redistribution layer specifically includes:

[0074] like Fig. 9 As shown, a plurality of power management chips 56 and a plurality of first connectors 34 are formed on the second redistribution layer. Specifically, a plurality of power management chips 56 and a plurality of first connectors 34 are formed on the second metal layer 54. Among them, a first cable 36 is arranged on the first connector 34. The power management chip 56 is used to supply power to the board-level packaging structure, and the first connector 34 can realize electrical connection between multiple board-level packaging structures.

[0075] It should be noted that the first connector 34 and the power management chip 56 can be arranged at intervals. Of course, the first connector 34 can also be arranged on the second redistribution layer in the edge area of ​​the square panel 22 to facilitate electrical connection between multiple board-level packaging structures. There is no specific limitation on the number and distribution position of the first connector 34 and the power management chip 56, and they can be selected according to actual needs.

[0076] Wherein, forming a chip operation module on the first redistribution layer may specifically include:

[0077] like Fig.10 As shown, Fig. 9 The intermediate package is clamped on the fixture 58 to achieve structural suspension. Fig.11 As shown, Fig.10 The intermediate package shown is turned over and the carrier 50 is removed. Fig.12 As shown, a chip operation layer 32 and a plurality of second connectors 34' are formed on the first redistribution layer, wherein a second cable 36' is arranged on the second connector 34'. The chip operation layer 32 includes at least a plurality of computing chips. The chip operation layer 32 may also include a memory chip or other types of computing chips. The second connector 34' is used for electrical connection between a plurality of board-level packaging structures.

[0078] In this embodiment, the chip computing layer 32 is located on the second redistribution layer in the central area of ​​the square panel 22, and the second connector 34' is located on the second redistribution layer in the edge area of ​​the square panel to facilitate electrical connection with adjacent packaging structures.

[0079] Wherein, forming a chip operation module on the first redistribution layer may further include:

[0080] like Fig.13 As shown, a chip operation layer 32 and a plurality of photoelectric conversion chips 38 are formed on the first redistribution layer, wherein an optical fiber 40 is arranged on the photoelectric conversion chip 38. The optical fiber 40 on the photoelectric conversion chip 38 is used for electrical connection between a plurality of board-level packaging structures. The chip operation layer 32 includes at least a plurality of computing chips. The chip operation layer 32 may also include a storage chip or other types of computing chips.

[0081] In this embodiment, the chip computing layer 32 is located on the second redistribution layer in the central area of ​​the square panel 22, and the photoelectric conversion chip 38 is located on the second redistribution layer in the edge area of ​​the square panel, which facilitates electrical connection with adjacent packaging structures.

[0082] It should be noted that the present embodiment does not specifically limit the type of connector in the chip computing module, and the connector can be selected according to needs.

[0083] like Fig.14 and Fig.15 As shown, the jig 58 is removed to obtain a board-level packaging structure.

[0084] Illustratively, in this embodiment, the square panel 22 may be a glass panel.

[0085] In the prior art, the carrier is peeled off during the packaging process, and the final packaging structure does not contain the carrier. However, the board-level packaging structure of the embodiment of the present disclosure retains the square glass panel, and effectively controls the warping of the board-level packaging structure by using the rigidity of the glass panel, solves the problem of large-area EMC and chip CTE mismatch in the prior art, and improves the reliability of the board-level packaging structure. In addition, a plurality of conductive columns are arranged on the retained square panel to realize vertical interconnection of the packaging structure, effectively shortening the transmission path.

[0086] Example 2

[0087] In step S110, Fig.16 As shown, a square carrier plate 22 is provided, and a first surface of the square carrier plate 22 is provided with a plurality of grooves 44 .

[0088] In this embodiment, a large-area square panel is used as a carrier board, which significantly improves the chip capacity, area utilization and I / O density, and significantly improves system performance, thereby solving the problem of limited performance of a single SoW system and realizing high computing power integration of a board-level packaging structure.

[0089] In step S120, Fig.17 As shown, the non-functional surfaces of the plurality of bridge chips 24 are mounted and fixed to the bottom wall of the corresponding groove 44. There is a gap between the bridge chip 24 and the side wall of the groove 44. It should be noted that the number of the bridge chips 24 is not specifically limited and can be limited according to actual needs.

[0090] In step S130, Fig.18 and Fig.19 As shown, a first redistribution layer is formed on the first surface of the square panel 22 and the functional surface of the bridge chip 24 .

[0091] The process of forming the first redistribution layer may be as follows:

[0092] Specifically, Figure 4 As shown, a first dielectric layer 28 is formed in the gap, the first surface of the square panel 22 and the functional surface of the bridge chip 24. In this embodiment, the first dielectric layer 28 can be a PI layer.

[0093] The first dielectric layer 28 located on the first surface of the square panel 22 and the functional surface of the bridge chip 24 is patterned to form a plurality of first openings on the first dielectric layer 28 .

[0094] like Fig. 20 As shown, the first redistribution layer is fixed to the carrier 50 by temporary bonding adhesive. Fig.21 As shown, the flipping makes the carrier plate 50 located at the bottom for support.

[0095] In step S140 , a plurality of conductive pillars are formed on the square panel to penetrate the thickness of the square panel.

[0096] like Fig.21 As shown, the specific process of forming the conductive pillar 46 can be as follows: drilling along the second surface of the square panel 22 to form a plurality of through holes penetrating the thickness of the square panel; and electroplating conductive material in the through holes to form the conductive pillar 46.

[0097] In this embodiment, by forming a plurality of conductive pillars on the square panel and penetrating the thickness of the square panel, vertical interconnection between the two sides of the square panel can be achieved, thereby effectively shortening the transmission path.

[0098] In step S150, if Fig. 22 As shown, a second redistribution layer connected to the conductive pillars 46 is formed on the second surface of the square panel 22 .

[0099] The specific process of forming the second redistribution layer is as follows: Fig. 22 As shown, a second dielectric layer 52 is formed on the second surface of the square panel 22, the second dielectric layer 52 is patterned to form a plurality of second openings, and a second metal layer 54 is formed in the second openings, wherein the second metal layer 54 is electrically connected to the conductive pillars 46. In this embodiment, the second dielectric layer 52 may be a PI layer, and the second metal layer 54 may be a metal copper layer.

[0100] In step S160, if Figure 23 to Figure 29 As shown, a power management module is formed on the second redistribution layer, and a chip operation module is formed on the first redistribution layer.

[0101] Wherein, forming a power management module on the second redistribution layer specifically includes:

[0102] like Fig.23As shown, a plurality of power management chips 56 and a plurality of first connectors 34 are formed on the second redistribution layer. Specifically, a plurality of power management chips 56 and a plurality of first connectors 34 are formed on the second metal layer 54. Among them, a first cable 36 is arranged on the first connector 34. The power management chip 56 is used to supply power to the board-level packaging structure, and the first connector 34 can realize electrical connection between multiple board-level packaging structures.

[0103] It should be noted that the first connector 34 and the power management chip 56 can be arranged at intervals. Of course, the first connector 34 can also be arranged on the second redistribution layer in the edge area of ​​the square panel 22 to facilitate electrical connection between multiple board-level packaging structures. There is no specific limitation on the number and distribution position of the first connector 34 and the power management chip 56, and they can be selected according to actual needs.

[0104] Wherein, forming a chip operation module on the first redistribution layer may specifically include:

[0105] like Fig.24 As shown, Fig.23 The intermediate package is clamped on the fixture 58 to achieve structural suspension. Fig.25 As shown, Fig.24 The intermediate package shown is turned over and the carrier 50 is removed. Fig.28 As shown, a chip operation layer 32 and a plurality of second connectors 34' are formed on the first redistribution layer, wherein a second cable 36' is arranged on the second connector 34'. The chip operation layer 32 includes at least a plurality of computing chips. The chip operation layer 32 may also include a memory chip or other types of computing chips. The second connector 34' is used for electrical connection between a plurality of board-level packaging structures.

[0106] In this embodiment, the chip computing layer 32 is located on the second redistribution layer in the central area of ​​the square panel 22, and the second connector 34' is located on the second redistribution layer in the edge area of ​​the square panel to facilitate electrical connection with adjacent packaging structures.

[0107] Wherein, forming a chip operation module on the first redistribution layer may further include:

[0108] like Fig. 27 As shown, a chip operation layer 32 and a plurality of photoelectric conversion chips 38 are formed on the first redistribution layer, wherein an optical fiber 40 is arranged on the photoelectric conversion chip 38. The optical fiber 40 on the photoelectric conversion chip 38 is used for electrical connection between a plurality of board-level packaging structures. The chip operation layer 32 includes at least a plurality of computing chips. The chip operation layer 32 may also include a storage chip or other types of computing chips.

[0109] In this embodiment, the chip computing layer 32 is located on the second redistribution layer in the central area of ​​the square panel 22, and the photoelectric conversion chip 38 is located on the second redistribution layer in the edge area of ​​the square panel, which facilitates electrical connection with adjacent packaging structures.

[0110] It should be noted that the present embodiment does not specifically limit the type of connector in the chip computing module, and the connector can be selected according to needs.

[0111] like Fig.28 and Fig.29 As shown, the jig 58 is removed to obtain a board-level packaging structure.

[0112] Illustratively, in this embodiment, the square panel 22 may be a glass panel.

[0113] In the prior art, the carrier is peeled off during the packaging process, and the final packaging structure does not contain the carrier. However, the board-level packaging structure of the embodiment of the present disclosure retains the square glass panel, and effectively controls the warping of the board-level packaging structure by using the rigidity of the glass panel, solves the problem of large-area EMC and chip CTE mismatch in the prior art, and improves the reliability of the board-level packaging structure. In addition, a plurality of second conductive pillars are arranged on the retained square panel to realize vertical interconnection of the packaging structure, effectively shortening the transmission path.

[0114] Another aspect of the present disclosure provides a board-level packaging structure, which is formed by packaging using the board-level packaging method S100 described above. The specific steps of the board-level packaging method S100 have been described in detail above and will not be repeated here.

[0115] The board-level packaging structure of the disclosed embodiment adopts a large-area square panel as a carrier board, which significantly improves the chip capacity, area utilization and I / O density, and significantly improves system performance, thereby solving the problem of limited performance of a single SoW system and realizing high computing power integration of the board-level packaging structure; the square panel is provided with a plurality of grooves, and a plurality of bridge chips are arranged in the grooves of the corresponding square panels, thereby reducing the packaging height of the entire packaging structure; the chip computing module realizes high-density interconnection with the help of a plurality of bridge chips, and no longer needs to rely on building a fine line structure in the RDL; a plurality of conductive columns are formed on the square panel through its thickness, thereby realizing vertical interconnection of the packaging structure and realizing vertical power supply on the back of the square panel, thereby effectively shortening the transmission path.

[0116] like Fig.30 As shown, another aspect of the embodiment of the present disclosure provides a board-level packaging system A, comprising at least one board-level packaging structure 100 as described above. The specific structural features of the board-level packaging structure 100 have been described in detail above and will not be repeated here.

[0117] When the board-level packaging system A includes a plurality of board-level packaging structures 100 , the plurality of board-level packaging structures 100 are electrically connected to each other through the first connector 34 and the second connector 34 ′ / the photoelectric conversion chip 38 .

[0118] In one embodiment, the first surfaces of the plurality of board-level packaging structures 100 can be electrically connected via the first cable 36 of the first connector 34, and the second surfaces of the plurality of board-level packaging structures 100 can be electrically connected via the second cable 36′ of the second connector 34′, forming Fig.30 Board-level packaging system A is shown.

[0119] In another embodiment, the first surfaces of the plurality of board-level packaging structures A can be electrically connected by the first cable 36 of the first connector 34, and the second surfaces of the plurality of board-level packaging structures 100 can be electrically connected by the optical cable 40 of the photoelectric conversion chip 38, forming Fig.30 Board-level packaging system A is shown.

[0120] It should be noted that, in this embodiment, there is no specific limitation on the electrical connection method between the multiple board-level packaging structures 100, and it can be selected according to actual needs.

[0121] It should be further explained that there is no specific requirement for the number of board-level packaging structures 100 in the board-level packaging system A, and the number can be selected according to the size of the board-level packaging structure.

[0122] The board-level packaging system of the disclosed embodiment includes at least one board-level packaging structure as described above. The board-level packaging structure adopts a large-area square panel as a carrier board, which significantly improves the chip capacity, area utilization and I / O density, and significantly improves the system performance, thereby solving the problem of limited performance of a single SoW system and realizing high computing power integration of the board-level packaging structure; the square panel is provided with a plurality of grooves, and a plurality of bridge chips are arranged in the grooves of the corresponding square panels, thereby reducing the packaging height of the entire packaging structure; the chip operation module realizes high-density interconnection with the help of a plurality of bridge chips, and no longer needs to rely on building a fine line structure in the RDL; a plurality of conductive columns are formed on the square panel through its thickness to realize vertical interconnection of the packaging structure, and realize vertical power supply on the back of the square panel, thereby effectively shortening the transmission path.

[0123] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the embodiments of the present disclosure, but the embodiments of the present disclosure are not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the embodiments of the present disclosure, and these modifications and improvements are also considered to be within the protection scope of the embodiments of the present disclosure.

Claims

1. A board-level packaging method, characterized in that: The method comprises: Providing a square panel, wherein a first surface of the square panel is provided with a plurality of grooves; Fixing the non-functional surfaces of the plurality of bridge chips to the corresponding grooves; forming a first redistribution layer on the first surface of the square panel and the functional surface of the bridge chip; forming a plurality of conductive pillars on the square panel extending through the thickness of the square panel; forming a second redistribution layer electrically connected to the conductive pillars on the second surface of the square panel; A power management module is formed on the second redistribution layer, and a chip operation module is formed on the first redistribution layer.

2. The board-level packaging method according to claim 1, characterized in that: The method of forming a plurality of conductive pillars penetrating the thickness of the square panel comprises: Drilling along the second surface of the square panel to form a plurality of through holes penetrating the thickness of the square panel; A conductive material is electroplated in the through hole to form the conductive pillar.

3. The board-level packaging method according to claim 1, characterized in that: The method further comprises forming a plurality of conductive pillars on the square panel through the thickness of the square panel, and further comprising: When providing the square panel, a first surface of the square panel is provided with a plurality of blind holes extending toward a second surface thereof, and a conductive material is provided in the blind holes; After forming the first redistribution layer, the second surface of the square panel is thinned to expose the blind hole, thereby forming the conductive column that penetrates the thickness of the square panel.

4. The board-level packaging method according to any one of claims 1 to 3, characterized in that: The forming of a power management module on the second redistribution layer comprises: A plurality of power management chips and a plurality of first connectors are formed on the second redistribution layer.

5. The board-level packaging method according to any one of claims 1 to 3, characterized in that: The forming of a chip computing module on the first redistribution layer includes: A chip operation layer and a plurality of second connectors are formed on the first redistribution layer, wherein the chip operation layer includes at least a plurality of computing chips.

6. The board-level packaging method according to any one of claims 1 to 3, characterized in that: The forming of a chip operation module on the first redistribution layer further includes: A chip operation layer and a plurality of photoelectric conversion chips are formed on the first redistribution layer, wherein the chip operation layer at least includes a plurality of computing chips.

7. The board-level packaging method according to any one of claims 1 to 3, characterized in that: Fixing the plurality of non-functional surfaces of the bridge chips to the corresponding grooves comprises: Mounting the non-functional surfaces of the plurality of bridge chips on the bottom wall of the corresponding groove, with a gap between the bridge chip and the side wall of the groove; The first redistribution layer is formed on the first surface of the square panel and the functional surface of the bridge chip, comprising: forming a first dielectric layer in the gap, the first surface of the square panel, and the functional surface of the bridge chip; Patterning the first dielectric layer located on the first surface of the square panel and the functional surface of the bridge chip to form a plurality of first openings on the first dielectric layer; A first metal layer electrically connected to the bridge chip is formed in the first opening.

8. The board-level packaging method according to any one of claims 1 to 3, characterized in that: The second redistribution layer electrically connected to the conductive pillar is formed on the second surface of the square panel, comprising: forming a second dielectric layer on a second surface of the square panel; patterning the second dielectric layer to form a plurality of second openings on the second dielectric layer; A second metal layer electrically connected to the conductive pillar is formed in the second opening.

9. The board-level packaging method according to any one of claims 1 to 3, characterized in that: The square panel is a glass panel.

10. A board-level packaging structure, characterized in that: The board-level packaging method according to any one of claims 1 to 9 is used for packaging.

Images