A scheduling method and related apparatus

Abstract

The embodiment of the present specification provides a scheduling method, which takes a plurality of to-be-scheduled wafers in a target material set as an object, determines a wafer priority order, and based on the priority order of the to-be-scheduled wafers, adds a next to-be-scheduled wafer to scheduling and out of the piece, so as to guarantee the continuity of the out of the piece, reduce the probability of the occurrence of idle equipment modules in the semiconductor process equipment, and improve the scheduling efficiency of the semiconductor process equipment.

Description

Technical Field

[0001] This specification relates to the field of semiconductor technology, specifically to automatic control technology within the semiconductor technology field, and more specifically to a scheduling method and related apparatus. Background Technology

[0002] Semiconductor process equipment is a type of equipment used for semiconductor wafer manufacturing. It may include modules such as an alignment module, robotic arms, load locks, load ports, and multiple process chambers. Semiconductor process equipment enables automated wafer processing and transfer.

[0003] To improve the efficiency of semiconductor process equipment, multiple wafers can be processed in parallel. However, current wafer scheduling technologies in semiconductor process equipment suffer from low equipment utilization. Summary of the Invention

[0004] This specification provides a scheduling method and related apparatus to improve equipment utilization.

[0005] To achieve the above technical objectives, the embodiments of this specification provide the following technical solutions:

[0006] In a first aspect, one embodiment of this specification provides a scheduling method applied to a controller of a semiconductor process equipment, the semiconductor process equipment further including a wafer loading / unloading station, the scheduling method comprising:

[0007] Obtain a target material set, which includes multiple wafers to be scheduled;

[0008] Based on the priority parameters of the wafers to be scheduled, the priority order of the multiple wafers to be scheduled is determined;

[0009] Based on the priority order of the wafers to be scheduled, the wafers to be scheduled are sequentially scheduled from the corresponding wafer loading and unloading positions, and the wafers to be scheduled with higher priority are dispatched earlier than the wafers with lower priority.

[0010] Secondly, one embodiment of this specification provides a semiconductor process scheduling device, including: a processor and a memory; the memory stores a computer program, and when the processor executes the computer program, it implements the scheduling method described in any of the above claims.

[0011] Thirdly, one embodiment of this specification provides a semiconductor process apparatus, including a semiconductor process scheduling device and multiple device modules;

[0012] The semiconductor process scheduling equipment is configured to schedule the wafer to be scheduled for output according to any of the scheduling methods described above.

[0013] Fourthly, one embodiment of this specification also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the scheduling method described above.

[0014] As can be seen from the above technical solutions, the scheduling method provided in the embodiments of this specification takes multiple wafers to be scheduled in the target material set as objects, determines the priority order of the wafers, and adds the next wafer to be scheduled to the scheduling and outputs it based on the priority order of the wafers to be scheduled, so as to ensure continuous output. Because the wafers are no longer bound to the semiconductor process equipment during the scheduling process, the probability of idle equipment modules appearing in the semiconductor process equipment is reduced, and the scheduling efficiency of the semiconductor process equipment is improved. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments or prior art of this specification, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this specification. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0016] Figure 1 A schematic diagram of a semiconductor process apparatus provided for one embodiment of this specification;

[0017] Figure 2 A schematic diagram of another semiconductor process apparatus provided for one embodiment of this specification;

[0018] Figure 3 A flowchart illustrating a scheduling method provided for one embodiment of this specification;

[0019] Figure 4 A schematic diagram of a process for determining wafer priority is provided for one embodiment of this specification;

[0020] Figure 5 A schematic diagram of a process for determining the priority of process tasks is provided for one embodiment of this specification;

[0021] Figure 6 A schematic diagram illustrating a process for determining the priority of a control task, provided as one embodiment of this specification;

[0022] Figure 7This is a schematic diagram of a computing device provided for one embodiment of this specification. Detailed Implementation

[0023] Unless otherwise defined, the technical or scientific terms used in the embodiments of this specification shall have the ordinary meaning understood by one of ordinary skill in the art to which this specification pertains. The terms "first," "second," and similar terms used in the embodiments of this specification do not indicate any order, quantity, or importance, but are merely used to avoid confusion of constituent elements.

[0024] Unless the context otherwise requires, throughout this specification, "a plurality of" means "at least two," and "including" is interpreted as open-ended or encompassing, that is, "including, but not limited to." In the description of this specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this specification. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example.

[0025] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this specification.

[0026] Overview

[0027] refer to Figure 1 , Figure 1 A schematic diagram of a semiconductor process equipment is shown. The equipment may include a first robotic arm 10, a second robotic arm 20, a wafer loading / unloading station 21, a calibration module 22, a cooling module 23, a buffer module 24, a vacuum lock 25, and multiple process chambers 11; wherein,

[0028] Each wafer loading / unloading position 21 can hold one wafer box, and each wafer box can hold multiple wafers.

[0029] The calibration module 22 may include a slot, and the calibration module 22 can calibrate the wafer placed in the slot.

[0030] Processing Module 11: Each processing module 11 may have one slot for placing a wafer for processing.

[0031] Cooling module 23 (Cooler) is used to cool the wafer after processing.

[0032] The first robotic arm 10 (or vacuum transfer robot, abbreviated as VTR) can be a dual-arm robotic arm. The two arms of the dual-arm robotic arm can be at 180° and remain fixed. Each arm has a slot, and each slot can hold a wafer. Under normal circumstances, the two arms cannot perform wafer picking and placing operations at the same time. The first robotic arm 10 is responsible for transporting wafers between the vacuum lock 25 and multiple process chambers 11.

[0033] The vacuum lock (LoadLock) 25 can have two slots, each slot can hold one wafer. The vacuum lock 25 can switch between atmospheric and vacuum states. When the vacuum lock state is switched to atmospheric state, the wafer located on the side of the second robot arm 20 can be sent into the vacuum lock 25. When the vacuum lock 25 is switched to vacuum state, the wafer located on the side of the first robot arm 10 can be sent into the vacuum lock 25.

[0034] The second robotic arm 20 (or air transfer robot, abbreviated as ATR) can be a single-arm robotic arm. The second robotic arm 20 can have a slot to place a wafer. The second robotic arm 20 can be responsible for moving the wafer between the wafer loading / unloading position 21, the calibration module 22 and the vacuum lock 25.

[0035] The buffer module 24, also known as the material buffer, can hold multiple wafers to prevent the wafer loading / unloading position 21 from simultaneously storing wafers that have undergone processing and wafers that have not undergone processing.

[0036] Understandable, Figure 1 This description is for illustrative purposes only and may not be intended to demonstrate a feasible structure for a semiconductor process apparatus. In other embodiments, the semiconductor process apparatus may include more or fewer types of equipment modules. For example, some semiconductor process apparatuses may include at least some of the equipment modules in a first robotic arm 10, a second robotic arm 20, a wafer loading / unloading station 21, a calibration module 22, a cooling module 23, a buffer module 24, a vacuum lock 25, and multiple process chambers 11. The number of equipment modules of the same type included in the semiconductor process apparatus may also vary, for example, in... Figure 1In the semiconductor process equipment shown, there are 3 wafer loading / unloading positions 21, 4 buffer modules 24, 2 vacuum locks 25, and 4 process chambers 11. However, in other embodiments, the number of wafer loading / unloading positions 21 can be 2 or 4, etc., the number of buffer modules 24 can be 6 or 8, etc., the number of vacuum locks 25 can be 3 or 4, etc., and the number of process chambers 11 can be 6 or 8, etc., for example in... Figure 2 The semiconductor process equipment shown has four wafer loading / unloading positions (LP1-LP4), four process chambers (PM1-PM4), and two vacuum locks (LLA and LLB). Figure 2 The semiconductor process equipment shown does not include a buffer module. This specification does not limit the feasible topology of the semiconductor process equipment, and the specific topology depends on the actual situation.

[0037] In semiconductor process equipment, the first and second robotic arms can be referred to as the transfer module, and all other modules besides the first and second robotic arms can be referred to as equipment modules. During the scheduling process of semiconductor process equipment, [the following is used]: Figure 2 Taking the semiconductor process equipment shown as an example, the wafer process path can be represented as: LoadPort->Aligner->LoadLock->PM->LoadLock->Cooler->LoadPort. The PM modules can be freely combined in parallel from PM1 to PM4. For example, path 1: LoadPort->Aligner->LoadLock->PM1 / PM2->LoadLock->Cooler->LoadPort; path 2: LoadPort->Aligner->LoadLock->PM3 / PM4->LoadLock->Cooler->LoadPort. The controller of the semiconductor process equipment typically schedules wafers in units of a wafer pod (Foup). Before a wafer in a wafer pod participates in scheduling, the wafer pod is loaded onto a wafer loading / unloading position. During scheduling, scheduling can be performed on a unit of a wafer pod, that is, a control task is established for all wafers in a wafer pod. This control task can be called a Cjob (Control job), and wafers in different control tasks can be triggered from different wafer loading / unloading positions.

[0038] A control task may include at least one process task, which can be called a Pjob (Process job). Different process tasks have different wafer process paths, while wafers in the same process task have the same process path. Each process task contains at least one wafer.

[0039] When creating a control task, you can set its type. Control task types can include ManuJobs, HighestJobs, HigherJobs, and NormalJobs.

[0040] A manual task is a separate control task that is manually inserted. A manual task includes at least one process task, which contains at least one wafer. The manual task can be used to implement the process of moving the wafer from one location to another in a semiconductor process device.

[0041] The highest priority task is an emergency order that has the authority to interrupt all other control tasks that are being executed except for manual tasks. It can stop control tasks that have already started wafer output from outputting wafers, but wafers that have already been output from the wafer loading / unloading position can continue to complete the remaining process path.

[0042] Higher-level tasks are also a type of urgent order. Their priority is lower than the highest-level task but higher than ordinary tasks. They cannot interrupt a control task of type ordinary that is currently being executed, but they can jump the queue to execute before other control tasks of type ordinary that are not yet being executed. For example, suppose there are two control tasks of type ordinary, Task 1 and Task 2, which are being executed in a queue. While Task 1 is being executed, the host computer issues a control task of type higher-level task. This newly issued control task can jump the queue to execute before Task 2, but it cannot interrupt the currently executing Task 1.

[0043] Normal tasks are the types of tasks performed during the normal operation of semiconductor process equipment, and they have the lowest priority among all control tasks.

[0044] When a control task is created, configuration priorities are also assigned to the process tasks within the control task to define the scheduling order of different process tasks within the same control task. Within the same process task, different wafers have different priorities, and the scheduling order of wafers can be determined according to their identification (e.g., wafer ID).

[0045] To strictly control the scheduling scale, some scheduling methods allocate idle process chambers to wafers based on information such as the occupancy of process chambers in semiconductor process equipment and task priorities. This involves binding wafers to idle process chambers; when the remaining process time for a wafer in a process chamber reaches a predetermined duration, the chamber is released, and the scheduling algorithm allocates it to the next wafer, thus ensuring that all scheduled wafers are processed strictly according to priority within the process chambers.

[0046] However, the inventors discovered that this scheduling method may cause the scheduling results to deviate from the globally optimal choice. In some cases, some equipment modules of the semiconductor process equipment may become idle, thereby reducing the overall scheduling and production efficiency.

[0047] For example, suppose a control task Cjob contains a process task Pjob. This Pjob includes scheduling tasks for 25 wafers, with wafers identified as 1 to 25, and their priorities decreasing sequentially from 1 to 25. Assume the process path for the wafers in this Pjob is: LoadPort->Aligner->LoadLock->PM1 / PM2->LoadLock->Cooler->LoadPort; the processing time for each wafer in the process chamber is 100 seconds. Following the scheduling method described above, during scheduling, process chamber PM1 is bound to the wafer with priority 1, and process chamber PM2 is bound to the wafer with priority 2. When the wafer with priority 1 enters PM1 to begin processing, and there is a predetermined time remaining before the end of the process (e.g., 50 seconds), PM1 is released, and the scheduling algorithm binds PM1 to the next wafer with priority 3. Similarly, when the wafer with priority 2 enters PM2 to begin processing, and there are 50 seconds remaining before the end of the process, PM2 is released, and the scheduling algorithm binds PM2 to the next wafer with priority 4. At this point, if the release timing of PM1 (or the timing when the scheduling algorithm binds the next wafer to the process chamber) is set to 50 seconds before the end of the wafer process, then for any process path and process time configuration, PM1 will be released at this time. This release timing is not determined by the scheduling algorithm, nor is it an attribute that changes with the process path; rather, it is an empirical value manually configured during the scheduling process. This release timing may be suitable for some process paths and process times, but when the process path and process time change, it may lead to some equipment modules being idle.

[0048] Assuming that PM1 is released 50 seconds before the end of the wafer process, for Pjobs of process path A and process time A, this ensures that no equipment module in the semiconductor process equipment is idle, guaranteeing high efficiency. However, for Pjobs of process path B and process time B, PM1 may need to be released 70 seconds before the end of the process to ensure that no equipment module in the semiconductor process equipment is idle. But since the scheduling algorithm does not detect all wafers that need to be scheduled, it only detects the next wafer and schedules it 50 seconds before the end of the wafer process in PM1. This will cause a 20-second delay in the timing of the next wafer's output. In this case, even if the Aligner and LoadLock equipment modules before PM1 are idle due to no wafers being occupied, the scheduling algorithm will not schedule the next wafer from the wafer loading / unloading position, resulting in a decrease in the scheduling and production efficiency of the entire equipment.

[0049] To address this issue, the inventors discovered that multiple wafers to be scheduled within the target material set can be prioritized. Based on this priority, the next wafer to be scheduled can be added to the schedule and rolled out, ensuring continuous wafer rollout. This reduces the probability of idle equipment modules in the semiconductor process equipment and improves the scheduling efficiency of the semiconductor process equipment. Furthermore, the timing for adding the next wafer to be scheduled to the schedule and rolling out can be when the target module (e.g., the first equipment module that the wafer arrives at after being rolled out from the wafer loading / unloading position) is idle.

[0050] Based on the above concept, the embodiments of this specification provide a scheduling method, which will be described exemplarily below with reference to the accompanying drawings.

[0051] Exemplary methods

[0052] To be applied Figure 3 Taking the controller of the semiconductor process equipment shown in the figure as an example, this specification provides a scheduling method. The semiconductor process equipment further includes a wafer loading / unloading station. In some embodiments, the semiconductor process equipment may also include a target module, which is the first equipment module that the wafer arrives at after being ejected from the wafer loading / unloading station. The scheduling method includes:

[0053] S301: Obtain a target material set, wherein the target material set includes multiple wafers to be scheduled;

[0054] S302: Determine the priority order of the multiple wafers to be scheduled based on the priority parameters of the wafers to be scheduled;

[0055] S303: The wafers to be scheduled are sequentially dispatched from the corresponding wafer loading / unloading positions, and the dispatch time of the wafers with higher priority is earlier than that of the wafers with lower priority.

[0056] The controller of the semiconductor process equipment includes, but is not limited to, the host computer of the semiconductor process equipment. During the scheduling process, the controller can receive scheduling information, which may include relevant information about the wafer to be scheduled, relevant information about the control tasks to be generated, and relevant information about the process tasks. After receiving the scheduling information, the controller uses the scheduling information as input to the scheduling algorithm, so that the scheduling algorithm can schedule the wafer to be scheduled based on this scheduling information. The scheduling method provided in the embodiments of this specification can be part of the scheduling algorithm in the controller, used to determine the priority order of the wafers to be scheduled and to schedule the wafers to be unloaded based on the priority order. The complete scheduling algorithm can also be used to plan the wafer scheduling sequence based on the process path and the current state of the equipment module. This scheduling sequence records the scheduling actions of the wafer to be scheduled to return to the wafer loading / unloading position according to the process path, the start time and end time of each scheduling action, and other information.

[0057] The target material set can refer to the collection of all wafers currently located at the wafer loading / unloading position that are awaiting scheduling. This target material set may include wafers waiting to execute control and process tasks. In this embodiment, instead of scheduling wafers by binding them to idle process chambers and then scheduling them, the priority order of the multiple wafers awaiting scheduling is determined, and then the wafers are scheduled for wafer unloading based on this priority order. This reduces the probability of long-term idle periods for equipment modules in semiconductor process equipment, improving scheduling and production efficiency.

[0058] The priority parameters of the wafers to be scheduled may include parameters that affect the wafer unloading order. These parameters include, but are not limited to, any one or any combination of the following: the configuration priority (e.g., identification) of the wafer to be scheduled, the configuration priority of the process task to which the wafer to be scheduled belongs, the configuration priority of the control task to which the wafer to be scheduled belongs, the creation time of the process task to which the wafer to be scheduled belongs, the creation time of the control task to which the wafer to be scheduled belongs, the wafer unloading time of the control task to which the wafer to be scheduled belongs, and the wafer unloading time of the process task to which the wafer to be scheduled belongs. This specification does not impose any limitations on this, and the specifics depend on the actual situation. The wafer unloading time of a certain control task or process task refers to the time when the first wafer in that task leaves the wafer loading / unloading position, as planned by the scheduling algorithm. When the scheduling algorithm first receives information about a control task or process task, the wafer turnout time is assumed to be infinite. The scheduling algorithm can make preliminary plans based on the identity of the wafer to be scheduled, the configuration priority of the process task to which the wafer belongs, and the configuration priority of the control task to which the wafer belongs. This allows the algorithm to obtain the wafer turnout time for each control task or process task. The wafer turnout time, to a certain extent, represents the scheduling priority of different tasks (control tasks / process tasks) and can be used as a reference parameter to determine the priority of the wafer to be scheduled.

[0059] In one feasible implementation, the target module may refer to the first device module that the wafer arrives at after being ejected from the wafer loading / unloading position, for example, in Figure 1 In this context, the target module may include a buffer module or a calibration module. Figure 2 In this specification, the target module may include a calibration module (Aligner). The target module may vary depending on the structure of the semiconductor process equipment. This specification does not limit it and the specific choice depends on the actual situation.

[0060] The step of scheduling the wafers to be scheduled from their corresponding loading / unloading positions according to their priority order specifically includes:

[0061] When the target module is idle, the wafers to be scheduled are sequentially dispatched from the corresponding wafer loading / unloading positions based on the priority order of the wafers to be scheduled.

[0062] In this embodiment, a timing method is provided for scheduling a wafer to be dispatched from the wafer loading / unloading position. This timing can be when the target module is idle. The target module refers to the first device module that the wafer arrives at after being dispatched from the wafer loading / unloading position. In this way, the idle time of the target module can be minimized, thereby improving the processing efficiency of the semiconductor process equipment for the wafer.

[0063] In one feasible implementation, a feasible method for determining the priority of a wafer to be scheduled is provided. Specifically, the priority parameter includes: the configuration priority of the wafer to be scheduled; the control task includes at least one process task, the process task includes at least one scheduling task for the wafer to be scheduled, and the process paths of the wafers to be scheduled in the same process task are the same.

[0064] Determining the priority order of multiple wafers to be scheduled based on their priority parameters includes:

[0065] For the multiple wafers to be scheduled belonging to the same process task, the priority of the wafers to be scheduled is determined according to their configuration priority, with the priority of the wafers to be scheduled having a higher configuration priority than that of the wafers to be scheduled having a lower configuration priority.

[0066] In one implementation, the configuration priority of a wafer to be scheduled can be determined based on its identity identifier. In this implementation, for multiple scheduled wafers belonging to the same process task, determining their respective priorities based on configuration priorities can ensure the orderly scheduling of each scheduled wafer within the same process task.

[0067] In an optional implementation, the priority parameter further includes: the wafer unloading time of the wafer to be scheduled and the creation time of the control task to which the wafer to be scheduled belongs;

[0068] Determining the priority order of multiple wafers to be scheduled based on their priority parameters includes:

[0069] For each wafer to be scheduled belonging to different process tasks, compare the wafer exit time of the wafer to be scheduled with the creation time of the control task to which the wafer belongs to other wafers to be scheduled, and determine that the priority of the wafer to be scheduled with an earlier wafer exit time is higher than the priority of the wafer to be scheduled with a later creation time of the control task to which it belongs.

[0070] In an optional implementation, the priority parameter further includes: the priority of the process task to which the wafer to be scheduled belongs; determining the priority order of the plurality of wafers to be scheduled based on the priority parameter of the wafer to be scheduled includes:

[0071] For multiple wafers to be scheduled belonging to different process tasks, and the wafer rollout time of each wafer to be scheduled is no earlier than the creation time of the control task to which the other wafers to be scheduled belong, the priority of the multiple wafers to be scheduled is determined according to the priority of the process task to which each wafer to be scheduled belongs. The priority of the wafer to be scheduled with a higher priority of the process task to which it belongs is higher than the priority of the wafer to be scheduled with a lower priority of the process task to which it belongs.

[0072] Specifically, in one embodiment, if two wafers to be scheduled belong to the same process task, the priority of the wafers to be scheduled is determined according to their configuration priority.

[0073] If the two wafers to be scheduled belong to different process tasks, the priority of the first wafer is set to be higher than that of the second wafer, wherein the wafer exit time of the first wafer is earlier than the creation time of the control task to which the second wafer belongs.

[0074] If the two wafers to be scheduled belong to different process tasks, and the wafer rollout time of either wafer is not earlier than the creation time of the control task to which the other wafer belongs, then the priority of the two wafers to be scheduled is determined according to the priority of the process tasks to which each wafer belongs.

[0075] refer to Figure 4 , Figure 4 A feasible process for comparing the priorities of two wafers to be scheduled (i.e., wafer 1 and wafer 2) is shown. When the priority parameters of wafer 1 and wafer 2 are input, it is first determined whether wafer 1 and wafer 2 belong to the same process job (Pjob). If so, the priority can be determined directly based on the configuration priority of wafer 1 and wafer 2. In the wafer cassette, in order to distinguish different wafers, wafers are usually assigned corresponding identification tags. In one embodiment, the configuration priority of the wafers decreases sequentially according to the order of the identification tags from smallest to largest.

[0076] If wafer 1 and wafer 2 do not belong to the same process task, then determine whether there is a wafer whose wafer rollout time is less than the creation time of the control task to which the other wafer belongs. If so, it means that in the initial planning of the scheduling algorithm, the wafer with the earlier rollout time has a higher priority for scheduling. The wafer with the earlier rollout time can be designated as the first wafer, and the other wafer as the second wafer. The priority of the first wafer is determined to be higher than that of the second wafer.

[0077] If the wafer rollout time of one wafer is less than the creation time of the control task to which the other wafer belongs, then the priority of the process task to which each of the two wafers belongs is determined as the priority of the corresponding wafer.

[0078] In this embodiment, a feasible method for determining wafer priority using several priority parameters is presented. This method is simple and easy to implement, and does not require complex calculations.

[0079] In one feasible implementation, a feasible process for determining the priority of process tasks is provided, with reference to... Figure 5 The process includes:

[0080] For process tasks belonging to the same type of control task, the wafer output time, the priority of the control task to which each process task belongs, and the configuration priority are compared in turn. Based on the comparison results, the priority of each process task is determined. Among them, the earlier the wafer output time, the higher the priority of the process task; the higher the priority of the control task to which the process task belongs, the higher the priority of the process task; and the higher the configuration priority of the process task, the higher the priority of the process task.

[0081] In an optional implementation, the process of determining the priority of the process tasks includes:

[0082] For process tasks belonging to different control tasks, the priority of the corresponding process task is determined according to the priority of the control task to which it belongs. The higher the priority of the control task to which it belongs, the higher the priority of the process task.

[0083] Specifically, if two process tasks belong to the same type of control task, the wafer output time of the two process tasks, the priority of the control task to which the two process tasks belong, and the configuration priority of the two process tasks are compared in turn. Based on the comparison results, the priority of the two process tasks is determined. The configuration priority of the process tasks is assigned when the process tasks are created, and the configuration priority of the process tasks is used to characterize the scheduling order of process tasks of the same type.

[0084] If the two process tasks belong to different types of first control tasks and second control tasks respectively, the priority of the process tasks is determined according to the respective types of the first control task and the second control task.

[0085] Figure 5 A feasible process for comparing the priorities of two process tasks (i.e., Pjob1 and Pjob2) is shown. When Pjob1 and Pjob2 are used as input, it is first determined whether Pjob1 and Pjob2 belong to the same type of control task (Cjob). If so, the wafer output time of the two process tasks, the priority of the control task to which the two process tasks belong, and the configuration priority of the two process tasks are compared in sequence. Based on the comparison results, the priority of the two process tasks is determined. If not, the priority is determined according to the type of control task to which Pjob1 and Pjob2 belong.

[0086] In one feasible implementation, a feasible process is provided to determine the priority of two process tasks by sequentially comparing their wafer turnout times, the priority of the control tasks to which the two process tasks belong, and the configuration priority of the two process tasks, based on the comparison results. This process includes:

[0087] If the two process tasks have different output times, the process task with the earlier output time has a higher priority.

[0088] If the output time of two process tasks is the same, compare the priority of the control task to which the two process tasks belong. The process task with the higher priority of the control task to which it belongs has a higher priority.

[0089] If the control tasks to which the two process tasks belong have the same priority, compare the configuration priorities of the two process tasks, and the process task with the higher configuration priority has a higher priority.

[0090] In this embodiment, when determining the priority of process tasks, the importance of the wafer turnout time, the priority of the control task to which the process task belongs, and the configuration priority of the process task are decreased in that order. This is because the scheduling algorithm has already made preliminary planning based on numerous parameters when initially planning and determining the wafer turnout time of the process tasks. This wafer turnout time can accurately represent the scheduling priority of the process tasks. Therefore, comparing the wafer turnout times of the process tasks first can more accurately determine the priority between them. In addition, in this embodiment, the method of determining the priority of process tasks is simple and easy to implement, requiring no complex calculations.

[0091] In an alternative implementation, a feasible process for determining the priority of control tasks is provided, such as... Figure 6 As shown, the process may include:

[0092] For control tasks of the same type, the output time, creation time, and configuration priority of each control task are compared in turn. Based on the comparison results, the priority of each control task is determined. Among them, the control task with the earlier output time has a higher priority; the control task with the earlier creation time has a higher priority; and the process task with the higher configuration priority has a higher priority.

[0093] Optionally, the process of determining the priority of the control task includes:

[0094] For control tasks of different types, the priority of the control task is determined according to the type of the control task.

[0095] Specifically, if the two control tasks are of the same type, the output time, creation time and configuration priority of the two control tasks are compared in turn, and the priority of the control task is determined according to the comparison result; the configuration priority of the control task is assigned when the control task is created, and the configuration priority of the control task is used to characterize the scheduling order of control tasks of the same type.

[0096] If the two control tasks are of different types, the priority of the control tasks is determined according to their types.

[0097] Similarly, in this embodiment, when determining the priority of control tasks, the importance of the output time, creation time, and configuration priority of control tasks is reduced in that order. This is because the scheduling algorithm has already planned with reference to many parameters when initially planning and determining the output time of control tasks. The output time can accurately represent the scheduling priority of control tasks. Therefore, comparing the output times of control tasks first can more accurately determine the priority between control tasks.

[0098] Optionally, in one implementation, as described above, the type of control task may include: manual task and highest task;

[0099] Thus, determining the priority of the control task based on its type specifically includes:

[0100] Control tasks of the manual type have a higher priority than other types of control tasks;

[0101] Control tasks of type "highest priority" have higher priority than control tasks that are not classified as manual tasks or "highest priority".

[0102] For each control task that is not a manual task or a top-level task, compare the output time of that control task with the creation time of other control tasks, and determine that the control task with the earlier output time has a higher priority than the control task with the later creation time.

[0103] Optionally, in one embodiment, the control task type further includes: higher-level tasks and normal tasks;

[0104] The step of determining the priority of the control task based on the type of the control task further includes:

[0105] For each control task that is neither a manual task nor a top-level task, if the output time of each control task is no earlier than the creation time of other control tasks, then the control task of the higher-level task has a higher priority than the control task of the normal task.

[0106] Specifically, in one embodiment, the above-described process for determining the priority of the control task can be further described as follows: The step of sequentially comparing the output time, creation time, and configuration priority of two control tasks, and determining the priority of the control task based on the comparison result, specifically includes:

[0107] If the output times of the two control tasks are different, the process task with the earlier output time has a higher priority.

[0108] If the output times of two control tasks are the same, the creation times of the control tasks are compared, and the control task with the earlier creation time has a higher priority.

[0109] If two control tasks are created at the same time, their configuration priorities are compared, and the control task with the higher configuration priority has a higher priority.

[0110] To accurately determine the priority of control tasks, we still refer to Figure 6 In one implementation, if the two control tasks are of different types, the priority of the control tasks is determined according to their types, specifically including:

[0111] If there is a manual task among the two control task types, the control task of the manual task type is determined to have a higher priority than the other control task.

[0112] If the manual task is not present in either of the two control task types, then if a highest-level task exists, the control task of the highest-level task is determined to have a higher priority than the other control task.

[0113] If neither the manual task nor the highest task exists in the two control tasks, then if the output time of the first control task is earlier than the creation time of the second control task, the priority of the first control task is determined to be higher than the priority of the second control task.

[0114] If the output time of the first control task is earlier than the creation time of the second control task, then the control task of the higher type has a higher priority than the control task of the normal type.

[0115] The manual task includes user-inserted control tasks, the highest task includes control tasks of other types besides the manual task, and the higher task includes control tasks that are inserted before executing a regular task that has not yet been executed.

[0116] Assuming the control tasks to be compared are Cjob1 and Cjob2, the first step is to determine whether the types of the two control tasks are the same. If they are the same, the output time, creation time, and configuration priority of the control tasks of Cjob1 and Cjob2 are compared in turn. Based on the comparison results, the priority of Cjob1 and Cjob2 is determined. If they are not the same, if there are manual tasks, the control task of type manual task in Cjob1 and Cjob2 is determined to have a higher priority.

[0117] If there are no manual tasks, then if there are top-level tasks, the control task of type top-level task in Cjob1 and Cjob2 will be given higher priority.

[0118] If there are no manual tasks and a highest priority task, unlike the traditional priority determination method, it is determined whether the output time of the first control task is earlier than the creation time of the second control task. If so, the priority of the first control task is determined to be higher than the priority of the second control task. If not, the priority of the control task of the higher type is determined to be higher than the priority of the control task of the normal type.

[0119] In this embodiment, if the two control tasks are of the higher-level task and the normal task, respectively, and the normal task has already been executed, the higher-level task cannot interrupt the normally task that is already being executed. That is, the priority of a normally task that has already produced a film should be higher than the priority of a newly created higher-level task. Therefore, by comparing the film production time and creation time of the two control tasks, if the film production time of one control task is earlier than the creation time of the other, the control task with the earlier film production time is given priority, thus ensuring the normal execution of the normally task that has already produced a film. In this embodiment, the correct determination of the priorities of the higher-level task and the normally task currently being executed is ensured through the above comparison method.

[0120] Exemplary device

[0121] In one exemplary embodiment of this specification, a semiconductor process scheduling apparatus is also provided, comprising: a processor and a memory; the memory stores a computer program, and when the processor executes the computer program, it implements the scheduling method described in any of the above embodiments.

[0122] Accordingly, this specification also provides a semiconductor process apparatus, including: a semiconductor process scheduling device and multiple device modules;

[0123] The semiconductor process scheduling equipment is configured to schedule the wafer to be scheduled for output according to the scheduling method described in any of the above embodiments.

[0124] Another embodiment of this application also proposes a computing device, see [link to relevant documentation] Figure 7 As shown, an exemplary embodiment of this specification also provides a computing device, including: a memory and a processor, the memory storing a computer program, the processor executing the computer program and performing steps in the scheduling methods according to various embodiments of this specification described in the foregoing embodiments.

[0125] The internal structure of the computing device can be as follows: Figure 7As shown, the computing device includes a processor, memory, network interface, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The network interface is used to communicate with external terminals via a network connection. When the computer program is executed by the processor, it follows the steps of the scheduling methods according to various embodiments of this specification described in the above embodiments.

[0126] The processor may include the main processor, as well as baseband chips, modems, etc.

[0127] The memory stores a program that executes the technical solution of this invention, and may also store an operating system and other critical business functions. Specifically, the program may include program code, which includes computer operation instructions. More specifically, the memory may include read-only memory (ROM), other types of static storage devices capable of storing static information and instructions, random access memory (RAM), other types of dynamic storage devices capable of storing information and instructions, disk storage, flash memory, etc.

[0128] The processor can be a general-purpose processor, such as a general-purpose central processing unit (CPU), a microprocessor, etc., or an application-specific integrated circuit (ASIC), or one or more integrated circuits used to control the execution of the program of the present invention. It can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0129] Input devices may include devices that receive data and information input by the user, such as keyboards, mice, cameras, scanners, light pens, voice input devices, touch screens, pedometers, or gravity sensors.

[0130] Output devices may include devices that allow information to be output to the user, such as displays, printers, speakers, etc.

[0131] The communication interface may include any transceiver-like device for communicating with other devices or communication networks, such as Ethernet, Radio Access Network (RAN), Wireless Local Area Network (WLAN), etc.

[0132] The processor executes programs stored in memory and calls other devices, which can be used to implement various steps of any of the scheduling methods provided in the above embodiments of this application.

[0133] The computing device may also include a display component and a voice component. The display component may be a liquid crystal display screen or an e-ink display screen. The input device of the computing device may be a touch layer covering the display component, or a button, trackball or touchpad set on the casing of the computing device, or an external keyboard, touchpad or mouse, etc.

[0134] Those skilled in the art will understand that Figure 7 The structures shown are merely block diagrams of some structures related to the solutions in this specification and do not constitute a limitation on the computing devices on which the solutions in this specification are applied. Specific computing devices may include more or fewer components than those shown in the figures, or combine certain components, or have different component arrangements.

[0135] Exemplary computer program products and storage media

[0136] In addition to the methods and devices described above, the scheduling methods provided in the embodiments of this specification can also be computer program products, which include computer program instructions that, when executed by a processor, cause the processor to perform the steps in the scheduling methods according to various embodiments of this specification as described in the "Exemplary Methods" section above.

[0137] The computer program product described herein can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments described herein. These programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0138] Furthermore, embodiments of this specification also provide a computer-readable storage medium having a computer program stored thereon, the computer program being executed by a processor of the steps in the scheduling methods according to various embodiments of this specification as described in the "Exemplary Methods" section above.

[0139] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. Any references to memory, storage, databases, or other media used in the embodiments provided in this specification can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.

[0140] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0141] The embodiments described above are merely illustrative of several implementation methods outlined in this specification. While the descriptions are specific and detailed, they should not be construed as limiting the scope of the solutions provided in this specification. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this specification, and these all fall within the scope of protection of this specification. Therefore, the scope of protection for this patent should be determined by the appended claims.

Claims

1. A scheduling method, characterized in that, A controller for semiconductor process equipment, the semiconductor process equipment further including a wafer loading / unloading station and a target module, the target module being the first device module to which the wafer to be scheduled arrives after being ejected from the wafer loading / unloading station, the scheduling method including: Obtain a target material set, which includes multiple wafers to be scheduled; the target material set contains all wafers currently located at the wafer loading / unloading position to be scheduled; Based on the priority parameters of the wafers to be scheduled, a priority order of multiple wafers to be scheduled is determined; the priority order is used to characterize the priority of the wafers to be scheduled being unloaded from the wafer loading / unloading position; Based on the priority order of the wafers to be scheduled, the wafers to be scheduled are sequentially scheduled from the corresponding wafer loading and unloading positions, and the wafers to be scheduled with higher priority are dispatched earlier than the wafers with lower priority. The step of scheduling the wafers to be scheduled from their corresponding loading / unloading positions sequentially based on their priority order includes: When the target module is idle, the wafers to be scheduled are sequentially dispatched from the corresponding wafer loading / unloading positions based on the priority order of the wafers to be scheduled.

2. The method according to claim 1, characterized in that, The priority parameter includes: the configuration priority of the wafer to be scheduled; Determining the priority order of multiple wafers to be scheduled based on their priority parameters includes: For the multiple wafers to be scheduled belonging to the same process task, the priority of the wafers to be scheduled is determined according to their configuration priority, with the priority of the wafers to be scheduled having a higher configuration priority than that of the wafers to be scheduled having a lower configuration priority.

3. The method according to claim 2, characterized in that, The priority parameters also include: the wafer unloading time of the wafer to be scheduled and the creation time of the control task to which the wafer to be scheduled belongs; Determining the priority order of multiple wafers to be scheduled based on their priority parameters includes: For each wafer to be scheduled belonging to different process tasks, compare the wafer exit time of the wafer to be scheduled with the creation time of the control task to which the wafer belongs to other wafers to be scheduled, and determine that the priority of the wafer to be scheduled with an earlier wafer exit time is higher than the priority of the wafer to be scheduled with a later creation time of the control task to which it belongs.

4. The method according to claim 3, characterized in that, The priority parameter further includes: the priority of the process task to which the wafer to be scheduled belongs; determining the priority order of multiple wafers to be scheduled based on the priority parameter of the wafer to be scheduled includes: For multiple wafers to be scheduled belonging to different process tasks, and the wafer rollout time of each wafer to be scheduled is no earlier than the creation time of the control task to which the other wafers to be scheduled belong, the priority of the multiple wafers to be scheduled is determined according to the priority of the process task to which each wafer to be scheduled belongs. The priority of the wafer to be scheduled with a higher priority of the process task to which it belongs is higher than the priority of the wafer to be scheduled with a lower priority of the process task to which it belongs.

5. The method according to claim 4, characterized in that, The process of determining the priority of the process tasks includes: For process tasks belonging to the same type of control task, the wafer turnout time, the priority of the control task to which each process task belongs, and the configuration priority are compared in turn. Based on the comparison results, the priority of each process task is determined. Among them, the earlier the wafer turnout time, the higher the priority of the process task; the higher the priority of the control task to which the process task belongs, the higher the priority of the process task; and the higher the configuration priority of the process task, the higher the priority of the process task.

6. The method according to claim 4 or 5, characterized in that, The process of determining the priority of the process tasks includes: For process tasks belonging to different control tasks, the priority of the corresponding process task is determined according to the priority of the control task to which it belongs. The higher the priority of the control task to which it belongs, the higher the priority of the process task.

7. The method according to claim 6, characterized in that, The process of determining the priority of the control task includes: For control tasks of the same type, the output time, creation time, and configuration priority of each control task are compared in turn. Based on the comparison results, the priority of each control task is determined. Among them, the control task with the earlier output time has a higher priority; the control task with the earlier creation time has a higher priority; and the process task with the higher configuration priority has a higher priority.

8. The method according to claim 7, characterized in that, The process of determining the priority of the control task includes: For control tasks of different types, the priority of the control task is determined according to the type of the control task.

9. The method according to claim 8, characterized in that, The types of control tasks include: manual tasks and top-level tasks; Determining the priority of the control task based on its type specifically includes: Control tasks of the manual type have a higher priority than other types of control tasks; Control tasks of type "highest priority" have higher priority than control tasks that are not classified as manual tasks or "highest priority". For each control task that is not a manual task or a top-level task, compare the output time of that control task with the creation time of other control tasks, and determine that the control task with the earlier output time has a higher priority than the control task with the later creation time.

10. The method according to claim 9, characterized in that, The types of control tasks also include: higher-level tasks and ordinary tasks; The step of determining the priority of the control task based on the type of the control task further includes: For each control task that is neither a manual task nor a top-level task, if the output time of each control task is no earlier than the creation time of other control tasks, then the control task of the higher-level task has a higher priority than the control task of the normal task.

11. A semiconductor process scheduling device, characterized in that, include: Processor and memory; The memory stores a computer program, and when the processor executes the computer program, it implements the scheduling method according to any one of claims 1 to 10.

12. A semiconductor process apparatus, characterized in that, Includes semiconductor process scheduling equipment and multiple equipment modules; The semiconductor process scheduling device is configured to schedule the wafer to be scheduled for output according to the scheduling method according to any one of claims 1 to 10.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the scheduling method according to any one of claims 1 to 10.

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