Shallow groove isolation forming method, semiconductor device and chip

Abstract

The invention provides a shallow trench isolation forming method, a semiconductor device and a chip, and relates to the technical field of semiconductors. The shallow trench isolation forming method comprises the following steps: providing a substrate, and sequentially forming a buffer layer and a stop layer with an etching window on the upper surface of the substrate; performing first etching processing on the buffer layer through the etching window so as to form a buffer groove in the buffer layer; wherein the groove wall of the buffer groove is of a concave arc-shaped structure; performing second etching processing on the groove bottom of the buffer groove so as to form an initial isolation groove on the substrate at the bottom of the buffer groove; a notch, connected with the buffer groove, of the initial isolation groove is of a smooth chamfer structure; performing third etching processing on the groove bottom of the initial isolation groove to deepen the depth of the initial isolation groove to form an isolation groove; and filling the isolation trench to form shallow trench isolation. According to the invention, the smooth chamfer can be formed at the opening of the shallow trench isolation, the performance stability of the semiconductor structure is improved, and the reliability of the semiconductor is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a shallow trench isolation forming method, a semiconductor device and a chip. Background Art

[0002] Shallow Trench Isolation (STI) is a structure used to isolate transistors and other semiconductor devices in semiconductor manufacturing. Its main function is to create an electrically isolated area on a silicon wafer to prevent electrical interference between different devices while maintaining a compact layout between devices.

[0003] In the prior art, a buffer layer 101 and a stop layer are usually formed on a substrate in sequence, and then a shallow trench isolation etching window is formed on the buffer layer, and the substrate is etched through the shallow trench isolation etching window to form a rectangular trench, and then a dielectric is filled in the rectangular trench to form a shallow trench isolation. The shallow trench isolation formed in this way has an opening close to the substrate that is not smooth enough, resulting in poor performance and low reliability of the semiconductor structure. Summary of the invention

[0004] In view of the technical problems of poor performance and low reliability of semiconductor structures in the prior art, the present invention provides a shallow trench isolation forming method, a semiconductor device and a chip. The shallow trench isolation forming method can form a smooth chamfer at the opening of the shallow trench isolation, effectively avoiding the loss of the gate oxide layer subsequently formed on the shallow trench isolation, thereby improving the performance stability of the semiconductor structure and improving the reliability of the semiconductor.

[0005] To achieve the above-mentioned purpose, the first aspect of the present invention provides a method for forming shallow trench isolation, which comprises: providing a substrate, and sequentially forming a buffer layer and a stop layer having an etching window on the upper surface of the substrate; wherein the etching window can expose the buffer layer; performing a first etching process on the buffer layer through the etching window to form a buffer groove in the buffer layer; wherein the groove wall of the buffer groove is a concave arc configuration; the buffer groove can expose the substrate; performing a second etching process on the bottom of the buffer groove to form an initial isolation groove in the substrate; wherein the groove where the initial isolation groove connects with the buffer groove is a smooth chamfer configuration; performing a third etching process on the bottom of the initial isolation groove to deepen the depth of the initial isolation groove and form an isolation groove in the substrate; filling the isolation groove to form shallow trench isolation.

[0006] Furthermore, the etching gas used in the first etching process includes: isotropic etching gas and anisotropic etching gas.

[0007] Furthermore, the etching gas used in the second etching process includes: isotropic etching gas and anisotropic etching gas.

[0008] Furthermore, the isotropic etching gas includes, but is not limited to, one or more of SF6, CH2F2 and C4F8.

[0009] Furthermore, the etching gas used in the third etching process includes anisotropic etching gas.

[0010] Furthermore, the anisotropic etching gas includes but is not limited to: one or two of Cl 2 and HBr.

[0011] Furthermore, the gases used in the first etching treatment include: CH2F2, SF6 and HBr; the etching conditions of the first etching treatment include: the flow rate of CH2F2 is between 0 and 60 sccm; the flow rate of SF6 is between 0 and 60 sccm; the flow rate of HBr is between 0 and 40 sccm; the etching time is between 20s and 40s; the reaction pressure is between 5mtorr and 20mtorr; and the bias power of the reaction chamber is between 100W and 400W.

[0012] Furthermore, the gases used in the second etching treatment include: Cl2, CH2F2, O2 and HBr; the etching conditions of the second etching treatment include: the flow rate of Cl2 is between 50sccm and 100sccm; the flow rate of CH2F2 is between 0sccm and 60sccm; the flow rate of O2 is between 0 and 10sccm; the flow rate of HBr is between 0 and 40sccm; the etching time is between 10s and 30s; the electric field parameters of the second etching treatment include: the reaction pressure is between 20mtorr and 50mtorr; the bias power of the reaction chamber is between 200W and 400W.

[0013] Furthermore, the gases used in the third etching treatment include: Cl2, O2 and HBr; the etching conditions of the third etching treatment include: the flow rate of O2 is between 0 and 10 sccm; the flow rate of Cl2 is between 50 sccm and 200 sccm; the flow rate of HBr is between 20 sccm and 100 sccm; the etching time is between 40s and 60s; the reaction pressure is between 5mtorr and 20mtorr; and the bias power of the reaction chamber is between 100W and 400W.

[0014] Furthermore, the thickness of the buffer layer is between

[0015] A second aspect of the present invention provides a semiconductor device, wherein the semiconductor device comprises a shallow trench isolation formed by the shallow trench isolation forming method described above.

[0016] A third aspect of the present invention provides a chip, which includes the semiconductor device described above.

[0017] Through the technical solution provided by the present invention, the present invention has at least the following technical effects:

[0018] The shallow trench isolation formation method of the present invention forms a buffer layer and a stop layer on the upper surface of the substrate in sequence, forms an etching window capable of exposing the buffer layer in the stop layer, performs a first etching process on the buffer layer through the etching window, forms a buffer groove in the buffer layer, and the groove wall of the buffer groove is a concave arc-shaped configuration. Then, the groove bottom of the buffer groove is subjected to a second etching process to form an initial isolation groove on the substrate at the bottom of the buffer groove. Since the groove wall of the buffer groove is a concave arc-shaped configuration, the angle between the groove wall and the substrate is greater than 90 degrees. When forming the initial isolation groove, it is convenient to form a notch with a smooth chamfered configuration at the junction with the buffer groove, which can effectively avoid the loss of the gate oxide layer subsequently formed on the shallow trench isolation, and improve the performance stability of the semiconductor structure. Then, the groove bottom of the initial isolation groove is subjected to a third etching process to deepen the depth of the initial isolation groove to form an isolation groove, and a dielectric is filled in the isolation groove to form a shallow trench isolation. The present invention can form a smooth chamfer at the opening of the shallow trench isolation, effectively avoiding the loss of a gate oxide layer subsequently formed on the shallow trench isolation, improving the performance stability of the semiconductor structure, and improving the reliability of the semiconductor structure.

[0019] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific implementations, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:

[0021] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific implementations, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:

[0022] Figure 1 A flow chart of a shallow trench isolation forming method provided by an embodiment of the present invention;

[0023] Figure 2 A schematic diagram of the structure of a shallow trench isolation formed in a shallow trench isolation forming method in the prior art;

[0024] Figure 3 A schematic structural diagram of a substrate formed in an embodiment of a shallow trench isolation forming method provided in an embodiment of the present invention;

[0025] Figure 4A schematic diagram of the structure of a buffer layer and a stop layer formed in an embodiment of a shallow trench isolation forming method provided in an embodiment of the present invention;

[0026] Figure 5 A schematic diagram of the structure of an etching window formed in an embodiment of a shallow trench isolation forming method provided in an embodiment of the present invention;

[0027] Figure 6 A schematic structural diagram of a buffer trench formed in an embodiment of a shallow trench isolation forming method provided in an embodiment of the present invention;

[0028] Figure 7 A schematic diagram of the structure of an initial isolation trench formed in an embodiment of a shallow trench isolation forming method provided in an embodiment of the present invention;

[0029] Figure 8 A schematic diagram of the structure of an isolation trench formed in an embodiment of a shallow trench isolation forming method provided in an embodiment of the present invention;

[0030] Fig. 9 A schematic structural diagram of a shallow trench isolation formed in an embodiment of a shallow trench isolation forming method provided in an embodiment of the present invention.

[0031] Description of Reference Numerals

[0032] 100 - substrate; 101 - buffer layer; 102 - stop layer; 103 - initial opening; 104 - shallow trench isolation; 200 - substrate; 201 - buffer layer; 202 - stop layer; 203 - buffer trench; 204 - initial isolation trench; 205 - isolation trench; 206 - shallow trench isolation. DETAILED DESCRIPTION

[0033] The specific implementation of the embodiment of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the embodiment of the present invention, and is not used to limit the embodiment of the present invention.

[0034] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0035] In the present invention, unless otherwise specified, directional words such as "up, down, top, bottom" are usually used with reference to the directions shown in the drawings or are used to describe the relative positional relationships of components in the vertical, perpendicular or gravity direction.

[0036] As the background technology, the performance of existing semiconductor devices is relatively poor.

[0037] Please refer to Figure 2In the prior art, a substrate 100 is first provided, and then a buffer layer 101 and a stop layer 102 are sequentially formed on the substrate 100, and then an etching window is formed in the stop layer 102, and the buffer layer 101 is etched through the etching window, and an initial opening 103 is formed in the buffer layer 101 to expose the substrate 100 below, and then the substrate 100 is etched downward through the initial opening 103 to form an isolation trench, and a dielectric is filled in the isolation trench to form a shallow trench isolation 104. The gas used in the etching process is chlorine gas, and the etching process is vertically downward, so that the opening corners of the shallow trench isolation 104 formed are not smooth enough, resulting in reduced performance reliability of the semiconductor structure.

[0038] On this basis, the present invention provides a method for forming shallow trench isolation, wherein a buffer layer and a stop layer are sequentially formed on the upper surface of a substrate, an etching window capable of exposing the buffer layer is formed in the stop layer, a first etching process is performed on the buffer layer through the etching window, and a buffer groove is formed in the buffer layer, wherein the groove wall of the buffer groove is a concave arc-shaped configuration. Then, a second etching process is performed on the groove bottom of the buffer groove to form an initial isolation groove on the substrate at the bottom of the buffer groove. Since the groove wall of the buffer groove is a concave arc-shaped configuration, the angle between the groove wall and the substrate is greater than 90 degrees. When forming the initial isolation groove, it is convenient to form a notch with a smooth chamfered configuration near the buffer groove, which can effectively avoid the loss of the gate oxide layer subsequently formed on the shallow trench isolation, and improve the performance stability of the semiconductor structure. Then, a third etching process is performed on the groove bottom of the initial isolation groove to deepen the depth of the initial isolation groove to form an isolation groove, and a dielectric is filled in the isolation groove to form a shallow trench isolation. The present invention can form a smooth chamfer at the opening of the shallow trench isolation, effectively avoiding the loss of a gate oxide layer subsequently formed on the shallow trench isolation, improving the performance stability of the semiconductor structure, and improving the reliability of the semiconductor structure.

[0039] The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0040] Please refer to Figure 1In a first aspect, an embodiment of the present invention provides a shallow trench isolation forming method, the method comprising: S101: providing a substrate 200 and sequentially forming a buffer layer 201 and a stop layer 202 having an etching window on the upper surface of the substrate 200; wherein the etching window can expose the buffer layer 201; S102: performing a first etching process on the buffer layer 201 through the etching window to form a buffer groove 203 in the buffer layer 201; wherein the groove wall of the buffer groove 203 is a concave arc configuration; the buffer groove 203 can Exposing the substrate 200; S103: performing a second etching process on the bottom of the buffer trench 203 to form an initial isolation trench 204 on the substrate 200; wherein, the groove where the initial isolation trench 204 connects with the buffer trench 203 is a smooth chamfered configuration; S104: performing a third etching process on the bottom of the initial isolation trench 204 to deepen the depth of the initial isolation trench 204 and form an isolation trench 205 on the substrate 200; S105: filling the isolation trench 205 to form a shallow trench isolation 206.

[0041] Specifically, step S101 is first performed: providing a substrate 200 and sequentially forming a buffer layer 201 and a stop layer 202 having an etching window on the upper surface of the substrate 200 ; wherein the etching window can expose the buffer layer 201 .

[0042] Specifically, in the embodiment of the present invention, first provide Figure 3 The substrate 200 shown in the figure is one of a silicon substrate, a silicon germanium substrate, a silicon-on-insulator substrate, and a germanium-on-insulator substrate. Then, a substrate 200 is formed on the substrate 200. Figure 4 The buffer layer 201 and the stop layer 202 shown, the material of the buffer layer 201 includes silicon oxide, and the formation method includes: deposition or secondary oxidation. The material of the stop layer 202 includes silicon nitride, and the formation method includes deposition. When the isolation structure 206 is subsequently formed, the stop layer 202 can be used as a stop layer for planarizing the isolation structure 206. Since the material of the stop layer 202 is silicon nitride, the stress is very large, and direct deposition on the silicon substrate 200 will cause dislocations on the silicon surface. Depositing a layer of silicon oxide as the buffer layer 201 can prevent the silicon nitride material of the stop layer 202 from being deposited on the silicon surface to cause dislocations.

[0043] like Figure 5As shown, an anti-reflection layer (not shown in the figure) is then formed on the stop layer 202, and then a mask layer (not shown in the figure) with an etching window is formed thereon, the etching window of the mask layer exposes part of the stop layer 202, the stop layer 202 is etched through the etching window, and the etching window is transferred to the stop layer 202 until the buffer layer 201 is exposed. The anti-reflection layer can reduce or eliminate the reflection of light on the semiconductor surface, thereby improving the accuracy and efficiency of the photolithography process. The material of the mask layer includes organic matter, and the mask layer is used to define the positions of the buffer trench 203, the initial isolation trench 204 and the isolation trench 205 to be formed subsequently.

[0044] Then, step S102 is performed: performing a first etching process on the buffer layer 201 through an etching window to form a buffer groove 203 in the buffer layer 201 ; wherein the groove wall of the buffer groove 203 is a concave arc-shaped configuration; and the buffer groove 203 can expose the substrate 200 .

[0045] Furthermore, the etching gas used in the first etching process includes: isotropic etching gas and anisotropic etching gas.

[0046] Furthermore, the isotropic etching gas includes, but is not limited to, one or more of SF6, CH2F2 and C4F8.

[0047] Furthermore, the anisotropic etching gas includes but is not limited to: one or two of Cl 2 and HBr.

[0048] Furthermore, the gases used in the first etching treatment include: CH2F2, SF6 and HBr; the etching conditions of the first etching treatment include: the flow rate of CH2F2 is between 0 and 60 sccm; the flow rate of SF6 is between 0 and 60 sccm; the flow rate of HBr is between 0 and 40 sccm; the etching time is between 20s and 40s; the reaction pressure is between 5mtorr and 20mtorr; and the bias power of the reaction chamber is between 100W and 400W.

[0049] Furthermore, the thickness of the buffer layer 201 is between

[0050] Specifically, in the embodiment of the present invention, the buffer layer 201 is subjected to a first etching process through an etching window, and a Figure 6The buffer groove 203 is shown. The etching gas used in the first etching process includes: isotropic etching gas and anisotropic etching gas. The isotropic etching gas is introduced into the etching gas of the first etching process, so that the first etching process can not only form the buffer groove 203, but also etch the buffer layer 201 in a direction parallel to the substrate 200, so that the chamfer position can be better exposed in the subsequent process steps, and a good process foundation can be provided for the subsequent processes. The anisotropic etching gas is introduced, so that the first etching process can also etch the buffer layer 201 in a direction perpendicular to the surface of the substrate 200, so that the morphology of the formed buffer groove 203 can be effectively guaranteed, and the process efficiency can be guaranteed. The etching gases used in this embodiment include CH2F2, SF6 and HBr. Through isotropic etching gas and anisotropic etching gas, combined with the process parameters of the first etching, a buffer groove 203 with a concave arc-shaped groove wall can be formed, so that the angle between the groove wall at the bottom of the buffer groove 203 and the substrate 200 is greater than 90°, so that the chamfer position can be better exposed in the subsequent process steps, facilitating the formation of a smooth chamfered opening.

[0051] The thickness of the buffer layer 201 is between The buffer layer 201 has a relatively large thickness, which enables the subsequent etching of the buffer layer 201 to facilitate the formation of a buffer layer 201 with a concave arc-shaped groove wall. The groove wall and the substrate 200 have an inclination angle greater than 90°, which is also beneficial for controlling the inclination angle of the initial isolation groove 204 formed by the subsequent etching and optimizing the morphology of the initial isolation groove 204.

[0052] In this embodiment, the setting of etching gas and process parameters in the first etching process can make the etching rate of the silicon material of the substrate 200 in the first etching process lower than the etching rate of the silicon oxide material of the buffer layer 201 , thereby being more conducive to controlling the morphology of the initial isolation trench 204 .

[0053] Then, step S103 is performed: a second etching process is performed on the bottom of the buffer trench 203 to form an initial isolation trench 204 on the substrate 200; wherein the notch where the initial isolation trench 204 and the buffer trench 203 meet is a smooth chamfered configuration.

[0054] Furthermore, the etching gas used in the second etching process includes: isotropic etching gas and anisotropic etching gas.

[0055] Furthermore, the isotropic etching gas includes, but is not limited to, one or more of SF6, CH2F2 and C4F8.

[0056] Furthermore, the anisotropic etching gas includes but is not limited to: one or two of Cl 2 and HBr.

[0057] Furthermore, the gases used in the second etching treatment include: Cl2, CH2F2, O2 and HBr; the etching conditions of the second etching treatment include: the flow rate of Cl2 is between 50sccm and 100sccm; the flow rate of CH2F2 is between 0sccm and 60sccm; the flow rate of O2 is between 0 and 10sccm; the flow rate of HBr is between 0 and 40sccm; the etching time is between 10s and 30s; the electric field parameters of the second etching treatment include: the reaction pressure is between 20mtorr and 50mtorr; the bias power of the reaction chamber is between 200W and 400W.

[0058] Specifically, in the embodiment of the present invention, a second etching process is performed at the bottom of the buffer trench 203, and the substrate 200 at the bottom of the buffer trench 203 is formed. Figure 7 The initial isolation groove 204 shown. The etching gas used in the second etching process includes: isotropic etching gas and anisotropic etching gas. The isotropic etching gas is introduced in the second etching process, so that the second etching process can round the exposed opening corners while forming the initial isolation groove 204, thereby forming a smooth chamfer. The integrity and thickness uniformity of the gate oxide layer formed on the initial isolation groove 204 are improved, and the performance reliability of the semiconductor structure is improved. The anisotropic etching gas is introduced in the second etching process, so that the second etching process can also etch the substrate 200 in a direction perpendicular to the surface of the substrate 200. By combining the isotropic etching gas and the anisotropic etching gas, and then by adjusting the etching parameters, a smooth chamfer configuration can be formed at the notch of the initial isolation groove 204 close to the buffer groove 203. The depth of the initial isolation groove 204 is positively correlated with the time of the second etching process. The second etching process also introduces a protective gas, which includes O2, N2 or He, etc., for protecting the substrate 200 on the sidewalls of the initial isolation trench 204 during the second etching process.

[0059] In this embodiment, the etching gas and process parameters of the second etching process are set so that the etching rate of the silicon material of the substrate 200 in the second etching process is greater than the etching rate of the silicon oxide material of the buffer layer 201, so as to avoid excessive loss of the buffer layer 201 during the second etching process.

[0060] Then, step S104 is performed: performing a third etching process on the bottom of the initial isolation trench 204 to deepen the depth of the initial isolation trench 204 and form an isolation trench 205 on the substrate 200 .

[0061] Furthermore, the etching gas used in the third etching process includes anisotropic etching gas.

[0062] Furthermore, the anisotropic etching gas includes but is not limited to: one or two of Cl 2 and HBr.

[0063] Furthermore, the gases used in the third etching treatment include: Cl2, O2 and HBr; the etching conditions of the third etching treatment include: the flow rate of O2 is between 0 and 10 sccm; the flow rate of Cl2 is between 50 sccm and 200 sccm; the flow rate of HBr is between 20 sccm and 100 sccm; the etching time is between 40s and 60s; the reaction pressure is between 5mtorr and 20mtorr; and the bias power of the reaction chamber is between 100W and 400W.

[0064] Specifically, in the embodiment of the present invention, after the initial isolation trench 204 is formed, a third etching process is performed at the bottom of the initial isolation trench 204 to deepen the depth of the initial isolation trench 204 to form Figure 8 Isolation trench 205 is shown.

[0065] The etching gas used in the third etching process includes an anisotropic etching gas. The third etching process is used to form an isolation trench 205 with a high aspect ratio. The use of anisotropic etching is conducive to forming an isolation trench 205 with a high aspect ratio. A protective gas is also used in the third etching process, and the protective gas includes O2. The protective gas is used to protect the substrate 200 exposed on the sidewall of the isolation trench 205 during the third etching process.

[0066] Finally, step S105 is performed: filling the isolation trench 205 to form a shallow trench isolation 206 .

[0067] Specifically, in the embodiment of the present invention, after the isolation trench 205 is formed, a dielectric material can be directly filled in the isolation trench 205 to form Fig. 9 The shallow trench isolation 206 shown in FIG. does not need to form a linear layer on the surface of the isolation trench 205 and then form the isolation structure 206 on the linear layer, thereby simplifying the process flow.

[0068] A second aspect of the present invention provides a semiconductor device, wherein the semiconductor device comprises a shallow trench isolation formed by the shallow trench isolation forming method described above.

[0069] A third aspect of the present invention provides a chip, which includes the semiconductor device described above.

[0070] The preferred embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, a variety of simple modifications can be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.

[0071] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.

[0072] In addition, various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.

Claims

1. A shallow trench isolation forming method, characterized in that: The shallow trench isolation forming method comprises: Providing a substrate, and sequentially forming a buffer layer and a stop layer having an etching window on the upper surface of the substrate; wherein the etching window can expose the buffer layer; Performing a first etching process on the buffer layer through an etching window to form a buffer groove in the buffer layer; wherein the groove wall of the buffer groove is a concave arc-shaped configuration; and the buffer groove can expose the substrate; Performing a second etching process on the bottom of the buffer trench to form an initial isolation trench on the substrate; wherein the notch where the initial isolation trench connects with the buffer trench is a smooth chamfered configuration; Performing a third etching process on the bottom of the initial isolation trench to deepen the initial isolation trench and form an isolation trench on the substrate; The isolation trench is filled to form a shallow trench isolation.

2. The shallow trench isolation forming method according to claim 1, characterized in that: The etching gas used in the first etching process includes: isotropic etching gas and anisotropic etching gas.

3. The shallow trench isolation forming method according to claim 1, characterized in that: The etching gas used in the second etching process includes: isotropic etching gas and anisotropic etching gas.

4. The shallow trench isolation forming method according to claim 2 or 3, characterized in that: The isotropic etching gas includes, but is not limited to, one or more of SF6, CH2F2 and C4F8.

5. The shallow trench isolation forming method according to claim 1, characterized in that: The etching gas used in the third etching process includes anisotropic etching gas.

6. The shallow trench isolation forming method according to claim 2, 3 or 5, characterized in that: The anisotropic etching gas includes, but is not limited to, one or both of Cl2 and HBr.

7. The shallow trench isolation forming method according to claim 1, characterized in that: The gases used in the first etching process include: CH2F2, SF6 and HBr; The etching conditions of the first etching treatment include: the flow rate of CH2F2 is between 0 and 60 sccm; the flow rate of SF6 is between 0 and 60 sccm; the flow rate of HBr is between 0 and 40 sccm; the etching time is between 20s and 40s; the reaction pressure is between 5mtorr and 20mtorr; and the bias power of the reaction chamber is between 100W and 400W.

8. The shallow trench isolation forming method according to claim 1, characterized in that: The gases used in the second etching process include: Cl2, CH2F2, O2 and HBr; The etching conditions of the second etching treatment include: the flow rate of Cl2 is between 50sccm and 100sccm; the flow rate of CH2F2 is between 0sccm and 60sccm; the flow rate of O2 is between 0 and 10sccm; the flow rate of HBr is between 0 and 40sccm; the etching time is between 10s and 30s; the electric field parameters of the second etching treatment include: the reaction pressure is between 20mtorr and 50mtorr; the bias power of the reaction chamber is between 200W and 400W.

9. The shallow trench isolation forming method according to claim 1, characterized in that: The gases used in the third etching process include: Cl2, O2 and HBr; The etching conditions of the third etching treatment include: the flow rate of O2 is between 0 and 10 sccm; the flow rate of Cl2 is between 50 sccm and 200 sccm; the flow rate of HBr is between 20 sccm and 100 sccm; the etching time is between 40s and 60s; the reaction pressure is between 5mtorr and 20mtorr; and the bias power of the reaction chamber is between 100W and 400W.

10. The shallow trench isolation forming method according to claim 1, characterized in that: The thickness of the buffer layer is between 11. A semiconductor device, characterized in that: The semiconductor device includes a shallow trench isolation formed by the shallow trench isolation forming method according to any one of claims 1 to 10.

12. A chip, characterized in that: The chip includes the semiconductor device according to claim 11.

Images