Method for enabling double-layer copper-plated deep groove capacitor to be compatible with silicon core coaxial silicon through hole

Abstract

The invention discloses a method for enabling a double-layer copper-plated deep groove capacitor to be compatible with a silicon core coaxial silicon through hole, and relates to the technical field of semiconductor preparation. The method comprises the following steps of: S1, simultaneously etching a silicon through hole and a deep groove capacitor on a silicon wafer; s2, depositing a first insulating layer on the inner wall of the engraved hole; s3, sputtering a first seed layer; s4, depositing a first metal layer; s5, depositing a dielectric layer; s6, sputtering a second seed layer; s7, depositing a second metal layer; s8, depositing a dielectric material to form a dielectric layer; s9, thinning the silicon wafer; s10, depositing a second insulating layer on the upper surface and the lower surface of the silicon wafer; s11, etching the second insulating layer to expose the first metal layer and the second metal layer; and S12, performing metal layer interconnection. According to the method for compatibility of the double-layer copper-plated deep groove capacitor and the silicon core coaxial through silicon via, the through silicon via and the deep groove capacitor can be manufactured at the same time, process steps are saved, and the overall performance of a system is improved.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor preparation, and in particular to a method for a double-layer copper-plated deep trench capacitor compatible with a silicon core coaxial through silicon via. Background Art

[0002] Through Silicon Via (TSV) is a microstructure technology for vertical electrical interconnection, mainly used in three-dimensional integrated circuit (3DIC) packaging. Electrical connections between silicon wafers are achieved by etching holes in the silicon wafer and filling them with conductive materials (such as copper).

[0003] Deep trench capacitor (DTC) is a technology that uses deep trench structures in silicon wafers as capacitor energy storage units and is widely used in analog circuits and RF circuits. DTC etches deep trenches on silicon wafers and deposits high dielectric constant materials to form large capacitance values ​​with the conductive layer.

[0004] The current preparation process of DTC (H. Johari and F. Ayazi, "High-Density Embedded Deep Trench Capacitors in Silicon With Enhanced Breakdown Voltage," in IEEE Transactions on Components and Packaging Technologies, vol. 32, no. 4, pp. 808-815, Dec. 2009, doi: 10.1109 / TCAPT.2009.2024210.) is as follows: DTC is plated with two layers of copper and filled with dielectric material in the middle.

[0005] Won-Chul Lee et al. (Lee WC, Min BW, Kim JC, et al. Silicon-core coaxial through silicon via for low-loss RF Si-interposer [J]. IEEE Microwave and Wireless Components Letters, 2017, 27 (5): 428-430.) improved the manufacturing process of deep trench capacitors (DTCs) and used the characteristics of forming deep trench structures in silicon wafers to prepare through silicon vias (TSVs) to achieve electrical interconnection. The process steps are as follows: The manufacturing process steps of silicon core coaxial through silicon vias are as follows: (a) silicon cavity etching, (b) core layer and ground metal patterning, (c) organic stacking and laser drilling, (d) pad patterning and passivation, (e) wafer thinning and solder ball formation. The process only plates a layer of copper.

[0006] In the existing semiconductor manufacturing technology, TSV and DTC are generally performed independently (TSV first and then DTC, or DTC first and then TSV). TSV first and then DTC will require etching and filling processes near TSV, which may cause the metal layer of TSV to be affected by factors such as thermal expansion, reducing its structural stability and conductive performance. DTC first and then TSV may interfere with the dielectric layer and capacitor structure of DTC, so a new method that can be compatible with both processes is needed. Based on this, the present invention provides a double-layer copper-plated deep trench capacitor compatible with silicon core coaxial silicon via method. Summary of the invention

[0007] In view of the shortcomings of the prior art, the present invention provides a method for a double-layer copper-plated deep trench capacitor compatible with a silicon core coaxial through silicon via. Specifically, the method includes the following technical solutions:

[0008] A method for providing a double-layer copper-plated deep trench capacitor compatible with a silicon core coaxial through silicon via is provided, comprising the following steps:

[0009] S1. Carry out through-silicon vias and deep trench capacitors on a silicon wafer simultaneously;

[0010] S2. Depositing a first insulating layer on the inner walls of the through silicon via and the deep trench capacitor;

[0011] S3. sputtering a first seed layer on the first insulating layer;

[0012] S4. depositing a first metal layer on the first seed layer;

[0013] S5. depositing a dielectric layer on the first metal layer;

[0014] S6. sputtering a second seed layer on the dielectric layer;

[0015] S7. depositing a second metal layer on the second seed layer;

[0016] S8. Depositing a dielectric material on the second metal layer to form a dielectric layer;

[0017] S9. Thinning silicon wafer;

[0018] S10. Depositing a second insulating layer on the upper and lower surfaces of the silicon wafer;

[0019] S11. Etching the second insulating layer to expose the first metal layer and the second metal layer;

[0020] S12. Perform metal layer interconnection between the first metal layer and the second metal layer, thereby completing the double-layer copper-plated deep trench capacitor compatible with the silicon core coaxial through silicon via method.

[0021] Furthermore, the engraved holes are annular cylindrical holes.

[0022] Specifically, the shape of the engraved hole is a vertical cylindrical hole.

[0023] Furthermore, in step S1, laser etching or deep reactive ion etching is used to simultaneously etch through silicon vias and deep trench capacitors on a silicon wafer.

[0024] Preferably, the doping concentration of the silicon material used in the silicon wafer is 10 15 ~10 18 cm -3 The deep reactive ion etching method is a Bosch deep reactive ion etching (Bosch DRIE) process; specifically, the process includes: first forming a patterned photoresist layer (not shown) on a semiconductor silicon wafer; using the photoresist layer as a mask, alternately introducing an etching gas and a protective gas, thereby alternately etching the silicon wafer and protecting the sidewalls formed after etching until an etched hole of a predetermined size is formed; and finally removing the photoresist layer.

[0025] Furthermore, the insulating material of the first insulating layer and the second insulating layer is one of silicon dioxide, silicon nitride, aluminum oxide and hafnium dioxide.

[0026] Preferably, the first insulating layer and the second insulating layer are deposited by chemical vapor deposition (CVD) or thermal oxidation. Chemical vapor deposition is to introduce a gas containing a deposition substance (precursor gas) into a reaction chamber, decompose the gas by heat, plasma or other excitation methods, generate a deposition substance, and deposit it on the substrate surface to form a thin film.

[0027] Furthermore, the materials of the first seed layer and the second seed layer are both selected from the group consisting of copper, titanium, titanium-copper alloy, cobalt, and nickel.

[0028] The provision of the first seed layer and the second seed layer can enhance the adhesion between metal and silicon and promote the uniformity of subsequent electroplating.

[0029] Preferably, the sputtering of the first seed layer and the second seed layer is carried out by physical vapor deposition (PVD) or electron beam evaporation coating method.

[0030] Furthermore, the material of the dielectric layer is one of aluminum oxide, silicon dioxide, silicon nitride, silicon oxynitride, and organic polymer.

[0031] Preferably, the method for depositing the dielectric layer in step S5 is atomic layer deposition (ALD) or chemical vapor deposition. The thickness of each deposition of atomic layer deposition can be precisely controlled, usually at the nanometer level or even the atomic level, which is very suitable for applications requiring extremely thin films and high-precision thickness.

[0032] Furthermore, the materials of the first metal layer and the second metal layer are both copper, tungsten and gold.

[0033] Preferably, the first metal layer and the second metal layer are deposited by physical vapor deposition or electroplating.

[0034] If the thickness of the first metal layer or the second metal layer is less than 1 μm, physical vapor deposition can be used, but physical vapor deposition takes a long time. When the thickness of the metal layer is relatively high, electroplating is more efficient. Electroplating is a technology that reduces metal ions and deposits them on the surface of the substrate through electric current, and the deposition rate is relatively high.

[0035] Furthermore, the dielectric material is one of aluminum oxide, silicon dioxide, silicon nitride, silicon oxynitride, and organic polymer.

[0036] Preferably, the organic polymer is benzocyclobutene (BCB).

[0037] Preferably, if the dielectric material is benzocyclobutene (BCB), the method of depositing the dielectric material in step S8 is a selective spin coating method.

[0038] Furthermore, in step S9, the thinning of the silicon wafer is performed by performing chemical mechanical planarization (CMP) double-sided grinding on the silicon wafer.

[0039] Preferably, in step S11, etching the second insulating layer is performed by plasma etching or deep reactive ion etching, wherein plasma etching uses gas plasma to react with the etching material to form volatile substances that are carried away from the surface, thereby removing the material.

[0040] Furthermore, in step S12, the metal layer interconnection is to interconnect and lead out the upper exposed first metal layer and the second metal layer using metal materials.

[0041] The beneficial effects of the present invention are:

[0042] The present invention provides a double-layer copper-plated deep trench capacitor compatible with silicon core coaxial silicon via method, which can realize the simultaneous production of silicon via and deep trench capacitor, saves process steps, improves the overall performance of the system, reduces the complexity of later packaging and assembly, and reduces costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying any creative work.

[0044] Figure 1 The schematic diagram of the process of the double-layer copper-plated deep trench capacitor compatible with silicon core coaxial silicon via method of embodiment 1 and embodiment 2 of the present invention is shown in FIG. Figure 1 ;

[0045] Figure 2 The schematic diagram of the process of the double-layer copper-plated deep trench capacitor compatible with silicon core coaxial silicon via method of embodiment 1 and embodiment 2 of the present invention is shown in FIG. Figure 2 ;

[0046] Figure 3 The schematic diagram of the process of the double-layer copper-plated deep trench capacitor compatible with silicon core coaxial silicon via method of embodiment 1 and embodiment 2 of the present invention is shown in FIG. Figure 3 ;

[0047] Figure 4 The schematic diagram of the process of the double-layer copper-plated deep trench capacitor compatible with silicon core coaxial silicon via method of embodiment 1 and embodiment 2 of the present invention is shown in FIG. Figure 4 ;

[0048] Figure 5 The schematic diagram of the process of the double-layer copper-plated deep trench capacitor compatible with silicon core coaxial silicon via method of embodiment 1 and embodiment 2 of the present invention is shown in FIG. Figure 5 ;

[0049] Figure 6 The schematic diagram of the process of the double-layer copper-plated deep trench capacitor compatible with silicon core coaxial silicon via method of embodiment 1 and embodiment 2 of the present invention is shown in FIG. Figure 6 ;

[0050] Figure 7 The schematic diagram of the process of the double-layer copper-plated deep trench capacitor compatible with silicon core coaxial silicon via method of embodiment 1 and embodiment 2 of the present invention is shown in FIG. Figure 7 ;

[0051] Figure 8 The schematic diagram of the process of the double-layer copper-plated deep trench capacitor compatible with silicon core coaxial silicon via method of embodiment 1 and embodiment 2 of the present invention is shown in FIG. Figure 8 ;

[0052] Fig. 9 The schematic diagram of the process of the double-layer copper-plated deep trench capacitor compatible with silicon core coaxial silicon via method of embodiment 1 and embodiment 2 of the present invention is shown in FIG. Figure 9 ;

[0053] Fig.10 The schematic diagram of the process of the double-layer copper-plated deep trench capacitor compatible with silicon core coaxial silicon via method of embodiment 1 and embodiment 2 of the present invention is shown in FIG. Figure 10 ;

[0054] Fig.11 The schematic diagram of the process of the double-layer copper-plated deep trench capacitor compatible with silicon core coaxial silicon via method of embodiment 1 of the present invention is as follows Figure 10 one;

[0055] Fig.12 The schematic diagram of the process of the double-layer copper-plated deep trench capacitor compatible with silicon core coaxial silicon via method of embodiment 1 of the present invention is as follows Figure 10 two;

[0056] Fig.13 Schematic diagram of the process of the double-layer copper-plated deep trench capacitor compatible with silicon core coaxial silicon via method according to embodiment 2 of the present invention Figure 10 one;

[0057] Fig.14 Schematic diagram of the process of the double-layer copper-plated deep trench capacitor compatible with silicon core coaxial silicon via method according to embodiment 2 of the present invention Figure 10 two;

[0058] Fig.15 Schematic diagram of a simulation model of Embodiment 1 of the present invention;

[0059] Fig.16 Schematic diagram of a simulation model of Embodiment 2 of the present invention;

[0060] Fig.17 It is a schematic diagram of a simulation model of Comparative Example 1 of the present invention;

[0061] Fig.18 It is a comparison curve diagram of S21 parameters of Examples 1-2 and Comparative Example 1 of the present invention;

[0062] Description of the symbols in the figure:

[0063] 1-silicon wafer; 2-holes for through-silicon vias; 3-holes for deep trench capacitors; 4-first insulating layer; 5-first seed layer; 6-first metal layer; 7-dielectric layer; 8-second seed layer; 9-second metal layer; 10-dielectric layer; 11-second insulating layer; 12-first copper wire; 13-third copper wire; 14-fourth copper wire; 15-second copper wire. DETAILED DESCRIPTION

[0064] The technical solutions in the embodiments of the present invention are described clearly and completely below. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0065] It should be understood that when used in this specification and the appended claims, the terms "include" and "comprises" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0066] It should also be understood that the terms used in this specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the specification of the present invention and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0067] It should be further understood that the term "and / or" used in the present description and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0068] In order to more fully understand the technical content of the present invention, the technical solution of the present invention is further introduced and illustrated in conjunction with specific embodiments below.

[0069] Example 1

[0070] A double-layer copper-plated deep trench capacitor compatible with silicon core coaxial silicon via method, such as Figure 1-Figure 12 As shown, the following steps are included:

[0071] S1. Figure 1 As shown, a through silicon via and a deep trench capacitor are simultaneously etched on a silicon wafer 1 by deep reactive ion etching, forming a through silicon via 2 and a deep trench capacitor 3, both of which are vertical cylindrical holes; wherein the through silicon via 2 has a depth of 169.3 μm; and the doping concentration of the silicon material used in the silicon wafer 1 is 10 15 cm -3 , thickness is 380μm;

[0072] S2. Figure 2 As shown, a first insulating layer 4 is deposited on the inner wall of the through silicon via hole 2 and the deep trench capacitor hole 3 by chemical vapor deposition; the insulating material of the first insulating layer 4 is silicon dioxide, and the thickness is 0.3 μm;

[0073] S3. Figure 3 As shown, a first seed layer 5 is sputtered on the first insulating layer 4 by physical vapor deposition; the material of the first seed layer 5 is a titanium-copper alloy with a thickness of 0.2 μm;

[0074] S4. Figure 4As shown, a first metal layer 6 is deposited on the first seed layer 5 by electroplating; the material of the first metal layer 6 is copper and the thickness is 2.8 μm;

[0075] S5. Figure 5 As shown, an atomic layer deposition dielectric layer 7 is used on the first metal layer 6; the material of the dielectric layer 7 is aluminum oxide, and the thickness is 3 μm;

[0076] S6. Figure 6 As shown, a second seed layer 8 is sputtered on the dielectric layer 7 by physical vapor deposition; the material of the second seed layer 8 is titanium-copper alloy, and the thickness is 0.2 μm;

[0077] S7. Figure 7 As shown, a second metal layer 9 is deposited on the second seed layer 8 by electroplating; the material of the second metal layer 9 is copper and the thickness is 2.8 μm;

[0078] S8. Figure 8 As shown, a dielectric material is deposited on the second metal layer 9 by spin coating to form a dielectric layer 10; the dielectric material is benzocyclobutene (BCB);

[0079] S9. Fig. 9 As shown, the silicon wafer 1 is thinned, and the front and back sides of the silicon wafer 1 are subjected to chemical mechanical planarization (CMP) double-sided grinding, and the copper core (the first metal layer 6 and the second metal layer 9) is exposed on the back side of the through silicon via hole 2. After grinding, the overall thickness is 160 μm;

[0080] S10. Fig.10 As shown, a second insulating layer 11 is deposited on the upper and lower surfaces of the silicon wafer 1 by chemical vapor deposition; the insulating material of the second insulating layer 11 is silicon dioxide and has a thickness of 0.3 μm;

[0081] S11. Fig.11 As shown, the second insulating layer 11 is etched by plasma to expose the first metal layer 6 and the second metal layer 9; the first metal layer includes the first copper wire 12 and the second copper wire 15, and the second metal layer includes the third copper wire 13 and the fourth copper wire 14, wherein the first copper wire 12, the second copper wire 15, the third copper wire 13 and the fourth copper wire 14 are not connected to each other, and the metal layers on the upper and lower surfaces of the first copper wire 12, the second copper wire 15, the third copper wire 13 and the fourth copper wire 14 are exposed by etching;

[0082] S12. Fig.12As shown, the first metal layer 6 and the second metal layer 9 are interconnected by metal layers, and the upper exposed first metal layer 6 and the second metal layer 9 are interconnected and led out by using metal materials, that is, the double-layer copper-plated deep trench capacitor compatible with the silicon core coaxial silicon through-hole method is completed. In this embodiment, the metal layer interconnection between the first metal layer 6 and the second metal layer 9 is specifically to connect the metal layers of the first copper wire 12 and the third copper wire 13, and the metal layers of the fourth copper wire 14 and the second copper wire 15 together by electron beam evaporation coating method.

[0083] Example 2

[0084] A double-layer copper-plated deep trench capacitor compatible with silicon core coaxial silicon via method, such as Figure 1-Figure 10 , Figure 13-14 As shown, the following steps are included:

[0085] S1. Figure 1 As shown, a through silicon via and a deep trench capacitor are simultaneously etched on a silicon wafer 1 by deep reactive ion etching, forming a through silicon via 2 and a deep trench capacitor 3, both of which are vertical cylindrical holes; wherein the through silicon via 2 has a depth of 169.3 μm; and the doping concentration of the silicon material used in the silicon wafer 1 is 10 15 cm -3 , thickness is 380μm;

[0086] S2. Figure 2 As shown, a first insulating layer 4 is deposited on the inner wall of the through silicon via hole 2 and the deep trench capacitor hole 3 by chemical vapor deposition; the insulating material of the first insulating layer 4 is silicon dioxide, and the thickness is 0.3 μm;

[0087] S3. Figure 3 As shown, a first seed layer 5 is sputtered on the first insulating layer 4 by physical vapor deposition; the material of the first seed layer 5 is a titanium-copper alloy with a thickness of 0.2 μm;

[0088] S4. Figure 4 As shown, a first metal layer 6 is deposited on the first seed layer 5 by electroplating; the material of the first metal layer 6 is copper and the thickness is 2.8 μm;

[0089] S5. Figure 5 As shown, an atomic layer deposition dielectric layer 7 is used on the first metal layer 6; the material of the dielectric layer 7 is aluminum oxide, and the thickness is 3 μm;

[0090] S6. Figure 6 As shown, a second seed layer 8 is sputtered on the dielectric layer 7 by physical vapor deposition; the material of the second seed layer 8 is titanium-copper alloy, and the thickness is 0.2 μm;

[0091] S7. Figure 7 As shown, a second metal layer 9 is deposited on the second seed layer 8 by electroplating; the material of the second metal layer 9 is copper and the thickness is 2.8 μm;

[0092] S8. Figure 8 As shown, a dielectric material is deposited on the second metal layer 9 by spin coating to form a dielectric layer 10; the dielectric material is benzocyclobutene (BCB);

[0093] S9. Fig. 9 As shown, the silicon wafer 1 is thinned, and the front and back sides of the silicon wafer 1 are subjected to chemical mechanical planarization (CMP) double-sided grinding, and the copper core (the first metal layer 6 and the second metal layer 9) is exposed on the back side of the through silicon via hole 2. After grinding, the overall thickness is 160 μm;

[0094] S10. Fig.10 As shown, a second insulating layer 11 is deposited on the upper and lower surfaces of the silicon wafer 1 by chemical vapor deposition; the insulating material of the second insulating layer 11 is silicon dioxide and has a thickness of 0.3 μm;

[0095] S11. Fig.13 As shown, the second insulating layer 11 is etched by plasma to expose the first metal layer 6 and the second metal layer 9; the first metal layer includes the first copper wire 12 and the second copper wire 15, and the second metal layer includes the third copper wire 13 and the fourth copper wire 14, wherein the first copper wire 12, the second copper wire 15, the third copper wire 13 and the fourth copper wire 14 are not connected to each other, and the metal layers on the upper and lower surfaces of the first copper wire 12, the third copper wire 13 and the fourth copper wire 14 are exposed by etching; the upper surface of the second copper wire 15 is blocked by the second insulating layer 11 (silicon dioxide);

[0096] S12. Fig.14 As shown, the first metal layer 6 and the second metal layer 9 are interconnected by metal layers, and the upper exposed first metal layer 6 and the second metal layer 9 are interconnected and led out by using metal materials, that is, the double-layer copper-plated deep trench capacitor compatible with the silicon core coaxial silicon through-hole method is completed. In this embodiment, the metal layer interconnection between the first metal layer 6 and the second metal layer 9 is specifically to connect the metal layers of the first copper wire 12 and the third copper wire 13 together by electron beam evaporation coating method.

[0097] Comparative Example 1

[0098] Comparative Example 1 is a traditional coaxial TSV.

[0099] Performance Testing

[0100] The double-layer copper-plated deep trench capacitor compatible silicon core coaxial through silicon via method of Example 1-2 was used to prepare the simulation model of Example 1-2. The simulation model of Comparative Example 1 was prepared. Fig.15 Schematic diagram of the simulation model of embodiment 1 of the present invention. Fig.16 Schematic diagram of the simulation model of embodiment 2 of the present invention. Fig.17 Schematic diagram of the simulation model of comparative example 1 of the present invention.

[0101] Among them, the difference between Comparative Example 1 and Example 1 is that:

[0102] 1. Comparative Example 1 is a cylindrical hole, and Example 1 is an annular cylindrical hole;

[0103] 2. The central signal line of Comparative Example 1 is a cylindrical copper core with a diameter of 19.3 μm and a height of 174 μm, while the central signal line of Example 1 is a cylindrical assembly with a diameter of 19.3 μm and a height of 174 μm, which is composed of two layers of copper, a layer of aluminum oxide and a silicon core;

[0104] 3. The outer ground wire of comparative example 1 is a pure copper cylindrical ring with an outer diameter of 82.981 μm, an inner diameter of 73.981 μm, and a height of 174 μm. The outer ground wire of embodiment 1 is a cylindrical ring assembly comprising two layers of copper and one layer of aluminum oxide with an outer diameter of 82.981 μm, an inner diameter of 73.981 μm, and a height of 174 μm. Apart from this, the other conditions are the same.

[0105] Compared with Example 2, Comparative Example 1 has the following differences:

[0106] 1. Comparative Example 1 is a cylindrical hole, and Example 2 is an annular cylindrical hole;

[0107] 2. The central signal line of Comparative Example 1 is a cylindrical copper core with a diameter of 19.3 μm and a height of 174 μm, and the central signal line of Example 2 is a cylindrical assembly with a diameter of 19.3 μm and a height of 174 μm, which is composed of two layers of copper, one layer of aluminum oxide, two layers of silicon dioxide and a silicon core;

[0108] 3. The outer ground wire of comparative example 1 is a pure copper ring column with an outer diameter of 82.981 μm, an inner diameter of 73.981 μm, and a height of 174 μm. The outer ground wire of embodiment 2 is a ring-shaped columnar assembly comprising two layers of copper and one layer of aluminum oxide with an outer diameter of 82.981 μm, an inner diameter of 73.981 μm, and a height of 174 μm. Apart from this, the other conditions are the same.

[0109] The simulation models of Examples 1-2 and Comparative Example 1 were simplified, and a three-dimensional model was established for simulation. The S21 parameter analysis was performed from 2GHz to 50GHz with a step size of 0.1GHz, and a S21 parameter comparison curve was obtained. The S21 parameter comparison curve of Examples 1-2 and Comparative Example 1 (traditional coaxial TSV) of the present invention is shown in FIG. Fig.18 As shown. Among them, S21 is a negative value, indicating insertion loss, Fig.18 The S21 in the figure represents the insertion loss of the TSV. When S21=0, it means that the transmission signal has no attenuation and the insertion loss is 0. Fig.18 It can be seen that the S21 curve of Example 1-2 of the present invention is closer to 0 than that of Comparative Example 1, indicating better transmission performance. In summary, the present invention provides a double-layer copper-plated deep trench capacitor compatible with silicon core coaxial silicon via method, which simultaneously manufactures silicon via and deep trench capacitor, saves preparation process steps, improves the transmission performance of silicon via, and can reduce the complexity of later packaging and assembly.

[0110] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A method for a double-layer copper-plated deep trench capacitor compatible with a silicon core coaxial through silicon via, characterized in that: The following steps are involved: S1. Carry out through-silicon vias and deep trench capacitors on a silicon wafer simultaneously; S2. Depositing a first insulating layer on the inner walls of the through silicon via and the deep trench capacitor; S3. sputtering a first seed layer on the first insulating layer; S4. depositing a first metal layer on the first seed layer; S5. depositing a dielectric layer on the first metal layer; S6. sputtering a second seed layer on the dielectric layer; S7. depositing a second metal layer on the second seed layer; S8. Depositing a dielectric material on the second metal layer to form a dielectric layer; S9. Thinning silicon wafer; S10. Depositing a second insulating layer on the upper and lower surfaces of the silicon wafer; S11. Etching the second insulating layer to expose the first metal layer and the second metal layer; S12. Perform metal layer interconnection between the first metal layer and the second metal layer, thereby completing the double-layer copper-plated deep trench capacitor compatible with the silicon core coaxial through silicon via method.

2. The method for a double-layer copper-plated deep trench capacitor compatible with silicon core coaxial through silicon vias as claimed in claim 1, characterized in that: The engraved holes are annular cylindrical holes.

3. The method for a double-layer copper-plated deep trench capacitor compatible with silicon core coaxial through silicon vias as claimed in claim 1, characterized in that: In step S1, laser etching or deep reactive ion etching is used to simultaneously etch through silicon vias and deep trench capacitors on a silicon wafer.

4. The method for a double-layer copper-plated deep trench capacitor compatible with a silicon core coaxial through silicon via as claimed in claim 1, characterized in that: The insulating material of the first insulating layer and the second insulating layer is one of silicon dioxide, silicon nitride, aluminum oxide and hafnium dioxide.

5. The method for making a double-layer copper-plated deep trench capacitor compatible with a silicon core coaxial through silicon via as claimed in claim 1, characterized in that: The materials of the first seed layer and the second seed layer are both selected from the group consisting of copper, titanium, titanium-copper alloy, cobalt and nickel.

6. The method for double-layer copper-plated deep trench capacitor compatible with silicon core coaxial through silicon via according to claim 1, characterized in that: The material of the dielectric layer is one of aluminum oxide, silicon dioxide, silicon nitride, silicon oxynitride and organic polymer.

7. The method for double-layer copper-plated deep trench capacitor compatible with silicon core coaxial through silicon via according to claim 1, characterized in that: The materials of the first metal layer and the second metal layer are copper, tungsten and gold.

8. The method for double-layer copper-plated deep trench capacitor compatible with silicon core coaxial through silicon via according to claim 1, characterized in that: The dielectric material is one of aluminum oxide, silicon dioxide, silicon nitride, silicon oxynitride and organic polymer.

9. The method for double-layer copper-plated deep trench capacitor compatible with silicon core coaxial through silicon via according to claim 1, characterized in that: In step S9, the thinning of the silicon wafer is to perform chemical mechanical planarization and double-sided grinding on the silicon wafer.

10. The method for double-layer copper-plated deep trench capacitor compatible with silicon core coaxial through silicon via according to claim 1, characterized in that: In step S12, the metal layer interconnection is to interconnect and lead out the exposed first metal layer and the second metal layer on the upper layer by using metal materials.

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