High-density and high-reliability system-on-chip structure and assembling method thereof

Abstract

The invention belongs to the technical field of integrated circuit packaging, and particularly relates to a high-density and high-reliability system-on-chip structure and an assembling method thereof. Comprising a glass wafer, the front surface of which is sequentially provided with a front surface rewiring layer and a high-density bonding pad; a back surface rewiring layer and a BGA solder ball are sequentially arranged on the back surface of the substrate; a TGV through hole is vertically formed in the base; a chip is arranged in the wafer-level plastic package body; high-density bumps in one-to-one correspondence with the high-density bonding pads are arranged on the surface of the chip, and the wafer-level plastic package body is subjected to plastic package on the front surface of the glass wafer through bonding of the high-density bumps and the high-density bonding pads; the wafer-level heat dissipation system is assembled with the front surface of the wafer-level plastic package body through high-thermal-conductivity glue; the wafer-level heat dissipation system comprises a micro-channel wafer and a cover plate wafer, and a liquid inlet and a liquid outlet are formed in the cover plate wafer; the wafer level configuration system is bonded with the back surface of the glass wafer through a BGA (Ball Grid Array) solder ball; the technical problems of large integration warping, low integration density, low reliability and the like of the on-chip system can be effectively solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit packaging, and in particular relates to a high-density and high-reliability on-chip system structure and an assembling method thereof. Background Art

[0002] The characteristic size of transistors is close to the quantum penetration effect and is approaching the physical limit. Moore's Law is gradually becoming invalid. Semiconductors have entered the post-Moore era. The industry has conducted a lot of exploration on the technology route beyond Moore. System on Wafter (SoW) takes a new perspective from the perspective of system engineering. With the significant advantages of high bandwidth, low latency, and low power consumption of wafer-level advanced packaging, it integrates "prefabricated" particles such as computing, storage, sensing, RF, and communication into the same wafer instead of traditional PCB boards, subverting the traditional "chip-module-casing-rack-system" step-by-step stacking engineering technology route mode, achieving exponential improvement in comprehensive performance such as bandwidth, latency, and power consumption, which is one of the effective means to continue Moore's Law.

[0003] One of the existing fan-out packaging technologies reconstructs the D1 chip to form a wafer-on-wafer system DoJo. The fan-out rewiring layer number reaches 6 layers, the wafer warpage and yield are difficult to control, and the chip integration density is low; another fan-out packaging technology uses the C2W hot-compression bonding process to bond the GPU module to the silicon wafer to form a wafer-on-wafer system. The silicon wafer is brittle and has low mechanical strength and reliability. Therefore, in order to prepare a wafer-on-wafer system with high integration density, low warpage and high reliability, it is urgent to develop a high-density and high-reliability wafer-on-wafer system integration method. Summary of the invention

[0004] The object of the present invention is to provide a high-density and high-reliability on-wafer system structure and an assembly method thereof, which can effectively solve the technical problems of large on-wafer system integration warping, low integration density and low reliability.

[0005] In order to solve the above technical problems, the present invention provides a high-density and high-reliability on-chip system structure, comprising:

[0006] The glass wafer has a front rewiring layer and a high-density solder pad on its front side in sequence; a back rewiring layer and a BGA solder ball on its back side in sequence; and a TGV through hole is vertically arranged inside;

[0007] A wafer-level plastic package body, wherein a chip is arranged inside, and the chip includes a functional chip and an I / O chip; a surface of the chip is provided with high-density bumps corresponding to the high-density pads one by one, and the high-density bumps are bonded to the high-density pads to plastic-seal the wafer-level plastic package body onto the front side of the glass wafer;

[0008] The wafer-level heat dissipation system is assembled with the front of the wafer-level plastic package through a high thermal conductivity adhesive; it includes a microchannel wafer and a cover wafer, and the cover wafer is provided with a liquid inlet and a liquid outlet for communicating with the microchannel inside the microchannel wafer;

[0009] The wafer-level configuration system is bonded to the back side of the glass wafer via BGA solder balls; the wafer-level configuration system includes a power module, an I / O module and a test module.

[0010] Preferably, the glass wafer has a size of 8 inches or 12 inches and a thickness of 300 μm to 1 mm; and the aperture of the TGV through hole is 30 μm to 70 μm.

[0011] Preferably, the number of wiring layers of the front rewiring layer is ≥ 4; the pitch between two adjacent high-density pads is ≤ 5 μm, and the layout density of the high-density pads is ≥ 4×10 4 Pieces / mm 2 .

[0012] Preferably, the number of wiring layers of the back-side rewiring layer is ≥2 layers; the diameter of the BGA solder ball is ≥500 μm, and the material of the BGA solder ball is Sn63Pb37.

[0013] Preferably, the thickness of the wafer-level plastic package is 100 μm to 300 μm.

[0014] Preferably, the chip thickness is 100 μm to 300 μm, the pitch between two adjacent high-density bumps is ≤ 5 μm, and the layout density of the high-density bumps is ≥ 4×10 4 Pieces / mm 2 , the minimum distance between two adjacent chips is ≤50μm.

[0015] The present invention also provides a method for assembling a high-density, high-reliability system-on-chip structure, and preparing a high-density, high-reliability system-on-chip structure as described above, comprising the following steps:

[0016] Step S1: providing a glass wafer, a temporary bonding wafer carrier and a temporary bonding adhesive;

[0017] Step S2: Spin-coating a temporary bonding adhesive onto the back side of the glass wafer, and temporarily bonding the temporary bonding wafer carrier to the back side of the glass wafer via the temporary bonding adhesive;

[0018] Step S3: bonding the chip to the front side of the glass wafer by a C2W hybrid bonding process;

[0019] Step S4: performing wafer-level plastic packaging on the bonded chips to form a wafer-level plastic packaging body;

[0020] Step S5: thinning the wafer-level plastic package until the surface of the chip is exposed;

[0021] Step S6: debonding the temporary bonding adhesive and removing the temporary bonding wafer carrier;

[0022] Step S7: performing wafer-level ball implantation on the back side of the glass wafer;

[0023] Step S8: bonding the glass wafer to the wafer-level configuration system through a W2W bonding process;

[0024] Step S9: coating a high thermal conductivity adhesive on the surface of the wafer-level plastic package body, and assembling the wafer-level heat dissipation system and the wafer-level plastic package body through the high thermal conductivity adhesive to form an on-wafer system.

[0025] Preferably, in step S3, the C2W hybrid bonding process temperature is 150°C to 180°C.

[0026] Preferably, in step S4, the curing temperature of the molding compound of the wafer-level molding body is 120° C. to 130° C.

[0027] Preferably, in step S7, the temperature of wafer-level ball planting is 220°C; and in step S8, the temperature of W2W bonding process is 220°C.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] 1. The present invention adopts glass material with a dielectric constant of only about 1 / 3 of that of silicon material and a loss factor 2 to 3 orders of magnitude lower than that of silicon material, thereby greatly reducing substrate loss and parasitic effects and effectively improving the integrity of on-wafer system transmission signals.

[0030] 2. The glass wafer of the present invention has high mechanical strength and stability, and is protected by wafer-level plastic packaging, which can greatly improve the mechanical strength and reliability of the on-wafer system.

[0031] 3. The present invention adopts C2W low-temperature hybrid bonding process to complete chip to glass wafer bonding, which can significantly reduce wafer warping.

[0032] 4. The chip of the present invention has a high bump density and a small chip spacing, which can greatly shorten the chip interconnection distance and improve the integration density, effectively improve the signal transmission rate and reduce the delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 Schematic diagram of the glass wafer of the present invention.

[0034] Figure 2 It is a schematic diagram of bonding a temporary bonding wafer carrier to a glass wafer by using a temporary bonding adhesive according to the present invention.

[0035] Figure 3 Schematic diagram of C2W hybrid bonding of a chip to a glass wafer according to the present invention.

[0036] Figure 4 The schematic diagram of the present invention is to complete the wafer-level molding.

[0037] Figure 5 The schematic diagram of the present invention is to complete wafer-level plastic packaging material thinning.

[0038] Figure 6 The schematic diagram of the present invention is to complete the debonding of temporary bonding glue.

[0039] Figure 7 The schematic diagram of the present invention is to complete wafer-level ball implantation.

[0040] Figure 8 Schematic diagram of completing W2W bonding of a glass wafer to a wafer-level configuration system according to the present invention.

[0041] Fig. 9 It is a schematic diagram of assembling a wafer-level heat dissipation system to a glass wafer according to the present invention.

[0042] In the figure: 1-wafer level heat dissipation system, 11-liquid inlet, 12-cover wafer, 13-microchannel wafer, 14-liquid outlet, 15-high thermal conductivity adhesive, 2-wafer level plastic package, 21-high density bumps, 22-resin plastic package, 23-chip, 3-glass wafer, 31-high density pads, 32-TGV through holes, 33-front rewiring layer, 34-back rewiring layer, 35-BGA solder balls, 4-wafer level configuration system, 5-temporary bonding wafer carrier. DETAILED DESCRIPTION

[0043] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0044] Example 1

[0045] like Fig. 9 As shown, an embodiment of the present invention provides a high-density and high-reliability on-chip system structure, including:

[0046] The glass wafer 3 has a front rewiring layer 33 and a high-density solder pad 31 on its front side, a back rewiring layer 34 and a BGA solder ball 35 on its back side, and a TGV through hole 32 vertically arranged inside.

[0047] A wafer-level plastic package 2 is provided with a chip 23 inside, and the chip 23 includes a functional chip and an I / O chip; a high-density bump 21 corresponding to a high-density pad 31 is provided on the surface of the chip 23, and the high-density bump 21 is bonded to the high-density pad 31 to plastic-seal the wafer-level plastic package 2 on the front side of the glass wafer 3;

[0048] The wafer-level heat dissipation system 1 is assembled with the front of the wafer-level plastic package 2 through a high thermal conductive adhesive 15; it includes a microchannel wafer 13 and a cover wafer 12, and the cover wafer 12 is provided with a liquid inlet 11 and a liquid outlet 14 for communicating with the microchannel inside the microchannel wafer 13;

[0049] The wafer-level configuration system 4 is bonded to the back side of the glass wafer 3 via the BGA solder balls 35 ; the wafer-level configuration system 4 includes a power module, an I / O module and a test module.

[0050] The specification of the glass wafer 3 is 8 inches or 12 inches, and the thickness is 300 μm to 1 mm; the aperture of the TGV through hole 32 is 30 μm to 70 μm.

[0051] The number of wiring layers of the front rewiring layer 33 is ≥ 4; the pitch between two adjacent high-density pads 31 is ≤ 5 μm, and the layout density of the high-density pads 31 is ≥ 4×10 4 Pieces / mm 2 .

[0052] The number of wiring layers of the back-side rewiring layer 34 is ≥2 layers; the diameter of the BGA solder ball 35 is ≥500 μm, and the material of the BGA solder ball 35 is Sn63Pb37.

[0053] The thickness of the wafer-level plastic package 2 is 100 μm to 300 μm.

[0054] The thickness of the chip 23 is 100 μm to 300 μm, the pitch between two adjacent high-density bumps 21 is ≤ 5 μm, and the layout density of the high-density bumps 21 is ≥ 4×10 4 Pieces / mm 2 , the minimum distance between two adjacent chips 23 is ≤50 μm.

[0055] Example 2

[0056] like Figures 1 to 9 As shown, the embodiment of the present invention also provides a method for assembling a high-density system-on-chip structure, comprising the following steps:

[0057] Step S1: providing a glass wafer 3, a temporary bonding wafer carrier 5 and a temporary bonding adhesive;

[0058] Step S2: Spin-coating a temporary bonding adhesive onto the back side of the glass wafer 3, and temporarily bonding the temporary bonding wafer carrier 5 to the back side of the glass wafer 3 via the temporary bonding adhesive;

[0059] Step S3: bonding the chip 23 to the front side of the glass wafer 3 by a C2W (Chip to Wafer) hybrid bonding process;

[0060] Step S4: performing wafer-level plastic packaging on the bonded chips 23 to form a wafer-level plastic packaging body 2;

[0061] Step S5: thinning the wafer-level plastic package 2 until the surface of the chip 23 is exposed;

[0062] Step S6: debonding the temporary bonding adhesive and removing the temporary bonding wafer carrier 5;

[0063] Step S7: performing wafer-level ball implantation on the back side of the glass wafer 3;

[0064] Step S8: bonding the glass wafer 3 to the wafer-level configuration system 4 through a W2W (Wafer to Wafer) bonding process;

[0065] Step S9: coating a high thermal conductivity adhesive 15 on the surface of the wafer-level plastic package 2, and assembling the wafer-level heat dissipation system 1 and the wafer-level plastic package 2 through the high thermal conductivity adhesive 15 to form an on-wafer system.

[0066] In step S3, the C2W hybrid bonding process temperature is 150°C to 180°C.

[0067] In step S4, the curing temperature of the resin molding material 22 of the wafer-level molding body 2 is 120°C to 130°C.

[0068] In step S7, the temperature of wafer-level ball planting is about 220°C; in step S8, the temperature of W2W bonding process is about 220°C.

[0069] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A high-density and high-reliability on-chip system structure, characterized in that: include: The glass wafer has a front rewiring layer and a high-density solder pad on its front side in sequence; a back rewiring layer and a BGA solder ball on its back side in sequence; and a TGV through hole is vertically arranged inside; A wafer-level plastic package body, wherein a chip is arranged inside, and the chip includes a functional chip and an I / O chip; a surface of the chip is provided with high-density bumps corresponding to the high-density pads one by one, and the high-density bumps are bonded to the high-density pads to plastic-seal the wafer-level plastic package body onto the front side of the glass wafer; A wafer-level heat dissipation system is assembled with the front of the wafer-level plastic package through a high thermal conductivity adhesive; the wafer-level heat dissipation system comprises a microchannel wafer and a cover wafer, and the cover wafer is provided with a liquid inlet and a liquid outlet for communicating with the microchannel inside the microchannel wafer; The wafer-level configuration system is bonded to the back side of the glass wafer via BGA solder balls; the wafer-level configuration system includes a power module, an I / O module and a test module.

2. A high-density and high-reliability on-chip system structure as claimed in claim 1, characterized in that: The glass wafer has a specification of 8 inches or 12 inches and a thickness of 300 μm to 1 mm; the aperture of the TGV through hole is 30 μm to 70 μm.

3. A high-density and high-reliability on-chip system structure as claimed in claim 1, characterized in that: The number of wiring layers of the front rewiring layer is ≥ 4; the pitch between two adjacent high-density pads is ≤ 5 μm, and the layout density of the high-density pads is ≥ 4×10 4 Pieces / mm 2 .

4. A high-density and high-reliability on-chip system structure as claimed in claim 1, characterized in that: The number of wiring layers of the back-side rewiring layer is ≥2 layers; the diameter of the BGA solder ball is ≥500 μm, and the material of the BGA solder ball is Sn63Pb37.

5. The high-density and high-reliability on-chip system structure according to claim 1, characterized in that: The thickness of the wafer-level plastic package is 100 μm to 300 μm.

6. The high-density and high-reliability on-chip system structure according to claim 1, characterized in that: The thickness of the chip is 100 μm to 300 μm, the pitch between two adjacent high-density bumps is ≤ 5 μm, and the layout density of the high-density bumps is ≥ 4×10 4 Pieces / mm 2 , the minimum distance between two adjacent chips is ≤50μm.

7. A method for assembling a high-density and high-reliability system-on-chip structure, preparing a high-density and high-reliability system-on-chip structure as claimed in any one of claims 1 to 6, characterized in that: The steps include: Step S1: providing a glass wafer, a temporary bonding wafer carrier and a temporary bonding adhesive; Step S2: Spin-coating a temporary bonding adhesive onto the back side of the glass wafer, and temporarily bonding the temporary bonding wafer carrier to the back side of the glass wafer via the temporary bonding adhesive; Step S3: bonding the chip to the front side of the glass wafer by a C2W hybrid bonding process; Step S4: performing wafer-level plastic packaging on the bonded chips to form a wafer-level plastic packaging body; Step S5: thinning the wafer-level plastic package until the surface of the chip is exposed; Step S6: debonding the temporary bonding adhesive and removing the temporary bonding wafer carrier; Step S7: performing wafer-level ball implantation on the back side of the glass wafer; Step S8: bonding the glass wafer to the wafer-level configuration system through a W2W bonding process; Step S9: coating a high thermal conductivity adhesive on the surface of the wafer-level plastic package body, and assembling the wafer-level heat dissipation system and the wafer-level plastic package body through the high thermal conductivity adhesive to form an on-wafer system.

8. The method for assembling a high-density system-on-chip structure according to claim 7, characterized in that: In step S3, the C2W hybrid bonding process temperature is 150° C. to 180° C.

9. The method for assembling a high-density system-on-chip structure according to claim 7, characterized in that: In step S4, the curing temperature of the molding compound of the wafer-level molding body is 120° C. to 130° C.

10. The method for assembling a high-density system-on-chip structure according to claim 7, characterized in that: In the step S7, the temperature of wafer-level ball planting is 220°C; in the step S8, the temperature of W2W bonding process is 220°C.

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