Chip packaging structure and chip packaging method
By using low-modulus organic sealant and transition heat sink layer in the SiC chip packaging structure, the problem of excessive thermal stress caused by CTE mismatch is solved, which significantly reduces the risk of chip cracking and improves the reliability of the chip.
Patent Information
- Application Number
- CN202311301679.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-08
- Publication Date
- 2025-04-08
AI Technical Summary
The existing SiC chip packaging structures are too high due to CTE mismatch, which can easily lead to chip cracking and affect reliability.
Adhes to the front of the chip, a buffer layer is formed to absorb thermal stress, and a transition heat sink layer is added to the back to reduce CTE mismatch.
It effectively reduces the thermal stress the chip is subjected to, reduces the risk of cracking, and improves the reliability of the chip.
Smart Images
Figure CN119786445A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of chip packaging, and in particular, to a chip packaging structure and a chip packaging method. Background Art
[0002] As a key component of power electronic systems, power semiconductor devices are mainly used in power equipment for power conversion and control circuits. In the past few decades, silicon-based power devices have made great progress, and their application areas and people's understanding of them have also expanded greatly.
[0003] Silicon Carbide (SiC), as a wide bandgap semiconductor material, has higher thermal and electronic properties. This allows power semiconductor devices with SiC as the base material to operate at higher temperatures, frequencies and voltages. At the same time, SiC devices also have smaller switching losses and have greater potential in the field of power devices. The existing packaging structure of SiC chips is usually a three-layer structure of plastic layer-chip-copper frame, that is, the back of the bare chip is connected to the copper frame, which is electrically connected to the circuit board through the copper frame, and the front of the bare chip is wrapped by the plastic layer.
[0004] Since the coefficient of thermal expansion (CTE) of SiC is much lower than the CTE of plastic and copper, this packaging structure will cause a serious CTE mismatch during the packaging process, thereby inducing greater thermal stress. SiC itself has a very high modulus, which not only causes the SiC chip to induce greater thermal stress, but also its own resistance to thermal strain is very weak. Therefore, it is very likely that the four corners of the SiC chip will crack when the device temperature changes, which has a huge impact on the reliability of the device. Therefore, how to construct a new packaging structure to reduce the thermal stress from the package on the SiC chip has become an urgent problem to be solved. Summary of the invention
[0005] The embodiment of the present application provides a chip packaging structure and a chip packaging method, which forms a buffer layer by adhering a low modulus organic sealant on the front of the chip to absorb the thermal stress that should be borne by the chip itself. At the same time, the low modulus organic sealant will also reduce the thermal stress induced in the packaging process, further reducing the thermal stress borne by the chip itself. This will reduce the occurrence of chip cracking, thereby playing a role in protecting the chip.
[0006] In a first aspect, an embodiment of the present application provides a chip packaging structure, the chip packaging structure comprising:
[0007] A copper frame, a bare chip, an organic sealant layer and a plastic sealing layer are stacked in sequence. The bare chip is located between the copper frame and the plastic sealing layer, the back of the bare chip is connected to the copper frame, and the pad on the front of the bare chip is connected to the copper frame through a lead. A layer of organic sealant is adhered to the front of the bare chip to form an organic sealant layer, and the plastic sealing layer is covered on the organic sealant layer. The modulus of the organic sealant layer is less than the modulus of the plastic sealing layer.
[0008] Among them, the modulus of the material is used to characterize the material's ability to resist deformation. The low-modulus organic sealant layer is prone to deformation and is more flexible than the high-modulus chip substrate. In this way, the organic sealant layer can act as a buffer layer to absorb the thermal stress that should be borne by the chip itself. At the same time, the thermal stress between the low-modulus organic sealant layer and the chip will be greatly reduced, and the thermal stress borne by the chip will be greatly reduced, which alleviates the problem of chip warping during the packaging process and reduces the occurrence of chip cracking, thereby protecting the chip.
[0009] In an optional embodiment, the organic sealant is cured to form an organic sealant layer, and the modulus of the organic sealant layer is lower than 1 GPa. In this way, the modulus of the organic sealant layer will be much lower than the modulus of the plastic sealing layer, and the thermal stress induced by the organic sealant layer will be greatly reduced, and the thermal stress borne by the chip will also be greatly reduced.
[0010] In an optional embodiment, the material of the organic sealant layer may include one or more of silicone rubber including siloxane bonds in the molecular structure, silicone resin including siloxane bonds in the molecular structure, and organic high molecular polymers containing two or more epoxy groups in the molecular structure. These materials not only have low modulus, but also greatly reduce the induced thermal stress. At the same time, they also have good thermal stability, flexibility and excellent insulation properties. In addition, they are tolerant to harsh environments and can form a double-layer structure with the plastic encapsulation material to jointly resist corrosion / water vapor erosion of the chip, thereby further protecting the chip.
[0011] In an optional embodiment, a transition heat sink layer may also exist between the back side of the chip and the copper frame. Specifically, a layer of transition heat sink is bonded to the copper frame to form a transition heat sink layer. Then the solder joints on the back side of the bare chip are connected to the transition heat sink layer. Among them, the thermal expansion coefficient CTE of the transition heat sink layer is between the thermal expansion coefficient CTE of the substrate of the bare chip and the thermal expansion coefficient CTE of copper. In this way, the transition heat sink layer can alleviate the problem of CTE imbalance. The CTE gap between the back side of the chip and the transition heat sink layer will be much smaller than the CTE gap between the back side of the chip and the copper frame, so that the thermal stress induced between the interfaces will be greatly reduced, further reducing the thermal stress borne by the chip.
[0012] In an optional embodiment, the material of the transition heat sink layer can be a metal / alloy material, or a composite material of a metal / alloy material and a ceramic material. These materials can not only reduce the thermal stress on the chip, but also have good thermal conductivity, which can help the chip to quickly dissipate heat to improve chip performance.
[0013] In an optional embodiment, the organic sealant layer can be omitted between the bare chip and the plastic sealing layer, and only the transition heat sink layer between the copper frame and the bare chip is used to reduce the thermal stress on the back of the bare chip. The thermal expansion coefficient CTE of the transition heat sink layer is between the thermal expansion coefficient CTE of the substrate of the bare chip and the thermal expansion coefficient CTE of copper. In this way, the transition heat sink layer can reduce thermal stress by alleviating the CTE gap to protect the chip.
[0014] In a second aspect, an embodiment of the present application provides a chip packaging method, the packaging method comprising:
[0015] First, the back of the bare chip is connected to the copper frame, and then the pad on the front of the bare chip is connected to the copper frame through a lead. Next, a layer of organic sealant is adhered to the front of the bare chip and then cured to form an organic sealant layer. Finally, the bare chip adhered with the organic sealant is plastic-sealed to form a plastic sealing layer, completing the entire packaging process. Among them, the modulus of the cured organic sealant layer is smaller than the modulus of the plastic sealing layer.
[0016] Among them, the low modulus organic sealant layer is easy to deform and has better flexibility than the high modulus chip substrate. In this way, the organic sealant layer can act as a buffer layer to absorb the thermal stress that should be borne by the chip itself. At the same time, the thermal stress between the low modulus organic sealant layer and the chip will be greatly reduced, and the thermal stress borne by the chip will be greatly reduced, which alleviates the problem of chip warping during the packaging process and reduces the occurrence of chip cracking, thereby playing a role in protecting the chip.
[0017] In an optional embodiment, the modulus of the organic sealant layer is lower than 1 GPa. In this way, the modulus of the organic sealant layer will be much lower than the modulus of the plastic encapsulation layer, and the thermal stress induced by the organic sealant layer will be greatly reduced, and the thermal stress borne by the chip will also be greatly reduced.
[0018] In an optional embodiment, the material of the organic sealant layer may include one or more of silicone rubber including siloxane bonds in the molecular structure, silicone resin including siloxane bonds in the molecular structure, and organic high molecular polymers containing two or more epoxy groups in the molecular structure. These materials not only have low modulus, but also greatly reduce the induced thermal stress. At the same time, they also have good thermal stability, flexibility and excellent insulation properties. In addition, they are tolerant to harsh environments and can form a double-layer structure with the plastic encapsulation material to jointly resist corrosion / water vapor erosion of the chip, thereby further protecting the chip.
[0019] In an optional embodiment, when the back side of the bare chip is connected to the copper frame, a layer of transition heat sink can be first bonded to the copper frame to form a transition heat sink layer. Then, the bare chip is connected to the transition heat sink layer through the solder joints on the back side of the bare chip. Among them, the thermal expansion coefficient CTE of the transition heat sink layer is between the thermal expansion coefficient CTE of the substrate of the bare chip and the thermal expansion coefficient CTE of copper. In this way, the transition heat sink layer can alleviate the problem of CTE imbalance. The CTE gap between the back side of the chip and the transition heat sink layer will be much smaller than the CTE gap between the back side of the chip and the copper frame, so that the thermal stress induced between the interfaces will be greatly reduced, further reducing the thermal stress borne by the chip.
[0020] In a third aspect, an embodiment of the present application provides an electronic device, which includes any one of the chip packaging structures and a circuit board provided in the first aspect above, wherein the copper frame in the chip packaging structure is connected to the circuit board, and the chip in the chip packaging structure is electrically connected to the circuit board through the copper frame. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 A schematic diagram of a chip packaging structure shown in an embodiment of the present application;
[0022] Figure 2 A schematic diagram of a chip packaging structure provided in an embodiment of the present application;
[0023] Figure 3 A schematic diagram of another chip packaging structure provided in an embodiment of the present application;
[0024] Figure 4 A schematic diagram of another chip packaging structure provided in an embodiment of the present application;
[0025] Figure 5 A schematic diagram of a chip packaging method provided in an embodiment of the present application;
[0026] Fig. 6A A schematic diagram of a chip packaging process provided by an embodiment of the present application;
[0027] Figure 6B A schematic diagram of a chip packaging process provided by an embodiment of the present application;
[0028] Figure 6C A schematic diagram of a chip packaging process provided by an embodiment of the present application;
[0029] Fig.6D A schematic diagram of a chip packaging process provided by an embodiment of the present application;
[0030] Figure 7 A schematic diagram of a process flow of another chip packaging method provided in an embodiment of the present application;
[0031] Fig. 8A A schematic diagram of a chip packaging process provided by an embodiment of the present application;
[0032] Figure 8B A schematic diagram of a chip packaging process provided by an embodiment of the present application;
[0033] Figure 8C A schematic diagram of a chip packaging process provided by an embodiment of the present application;
[0034] Fig.8D A schematic diagram of a chip packaging process provided by an embodiment of the present application;
[0035] Fig. 8E A schematic diagram of a chip packaging process provided in an embodiment of the present application. DETAILED DESCRIPTION
[0036] The embodiment of the present application provides a chip packaging structure and a chip packaging method, which forms a buffer layer by adhering a low modulus organic sealant on the front of the chip to absorb the thermal stress that should be borne by the chip itself. At the same time, the low modulus organic sealant will also reduce the thermal stress induced in the packaging process, further reducing the thermal stress borne by the chip itself. This will reduce the occurrence of chip cracking, thereby playing a role in protecting the chip.
[0037] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0038] The terms "first", "second", etc. in the specification embodiments, claims and drawings of the present application are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one (item)" means one or more, and "multiple" means two or more. "Installation", "connection", "connected", etc. should be understood in a broad sense, for example, it can be an electrical connection or a mechanical connection; it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or it can be indirect through an intermediate medium, or it can be the internal connection of two elements. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, including a series of steps or units. Methods, systems, products or devices are not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or inherent to these processes, methods, products or devices. "Up", "down", "left", "right", etc. are only used relative to the orientation of the components in the drawings. These directional terms are relative concepts. They are used for description and clarification relative to the description, which may change accordingly according to the change of the orientation of the components in the drawings.
[0039] An embodiment of the present application provides an electronic device, which may be a consumer electronic product, a household electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, etc., and the present application does not impose any restrictions on this.
[0040] Indicatively, the above-mentioned consumer electronic products can be mobile phones, tablet computers, laptop computers, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smart watches, smart bracelets, etc.), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products can be smart door locks, TVs, smart speakers, refrigerators, sweeping robots, etc. Car-mounted electronic products can be car-mounted navigators, car-mounted displays, etc. Financial terminal products can be automated teller machines (ATMs), electronic devices for self-service transactions, etc. Communication electronic products can be servers, storage devices, radars, base stations, and other communication equipment.
[0041] The electronic device includes a printed circuit board (PCB) and a chip electrically connected to the circuit board. The chip packaging structure adopts a three-layer structure of plastic sealing layer-chip-copper frame. The back of the bare chip is connected to the copper frame, and the electrical connection with the circuit board is achieved through the copper frame, while the front of the bare chip is adhered with a layer of low modulus organic sealant, and then the plastic sealing layer wraps the chip adhered with the organic sealant. The low modulus organic sealant layer can not only form a buffer layer to absorb the thermal stress that should be borne by the chip itself, but also reduce the thermal stress induced in the packaging process, thereby greatly reducing the thermal stress borne by the chip itself. This will reduce the occurrence of chip cracking, thereby playing a role in protecting the chip.
[0042] The chip packaging structure provided in the embodiment of the present application is described in detail below in combination with the prior art.
[0043] Figure 1 A schematic diagram of a chip packaging structure provided in an embodiment of the present application. Figure 1 As shown, the chip packaging structure includes a copper frame 11, a bare chip 12 and a plastic layer 13.
[0044] Schematically, the front side of the bare chip 12 is the side where the circuit layer is located, which includes a solder pad. The back side of the bare chip 12 is the side where the wafer is located under the substrate, which includes a plurality of solder joints. Among them, the material of the substrate is SiC, which is the base for carrying integrated circuits. The back side of the bare chip is connected to the copper frame 11 through solder joints, and the copper frame 11 is connected to the circuit board. Among them, the functions of the copper frame 11 are: first, to achieve electrical connection between the circuit layer of the bare chip 12 and the circuit board. Secondly, it plays a fixing role, fixing the bare chip 12 on the circuit board to prevent the bare chip 12 from shaking. Finally, it also plays a role in heat dissipation. The copper frame 11 can conduct the heat generated by the bare chip 12 to achieve heat dissipation.
[0045] Schematically, the pads on the front side of the bare chip 12 are connected to the copper frame 11 through wires to achieve electrical connection between the bare chip 12 and the copper frame 11. The front side of the bare chip 12 is encapsulated by the plastic encapsulation layer 13.
[0046] In the above packaging structure, the thermal expansion coefficient CTE of the plastic packaging material of the plastic packaging layer 13 is generally 10ppm / K (10 to the negative 12th power meter / Kelvin), and the CTE of the copper of the copper frame 11 is generally 16.7ppm / K. However, the SiC substrate of the bare chip 12 has a very small CTE, generally 4ppm / K. This leads to a more serious CTE mismatch phenomenon in the chip packaging structure, which will induce very large thermal stress.
[0047] Among them, thermal stress refers to the expansion and contraction deformation of an object caused by temperature changes. However, due to the internal mutual constraints and external boundary constraints of the object, this deformation cannot occur freely, thus generating thermal stress. It can be understood that the plastic encapsulation layer 13 and the copper frame 11 are in contact with the bare chip 12 and are constrained by the bare chip 12, so thermal stress will be generated. The greater the difference in thermal expansion coefficients, the greater the difference in deformation between the materials, and the greater the thermal stress will be generated. Therefore, in the above chip packaging structure, the bare chip 12 needs to withstand very large thermal stress.
[0048] However, the modulus of SiC in the bare chip 12 is very high. Among them, modulus refers to the ratio of stress to strain of a material under stress, which is used to characterize the rigidity of the material. It can be understood that the higher the modulus of a material, the harder the material is, and the less likely it is to deform when subjected to stress, while the lower the modulus of a material, the better the flexibility of the material, and the more it can overcome stress by deformation. Since SiC is a high modulus material, the bare chip 12 will not only increase the thermally induced stress, but its own ability to resist thermal stress is also very weak. This causes the four corners of the SiC chip to crack very easily when the device temperature changes, which has a huge impact on the reliability of the chip.
[0049] Based on this, the present application embodiment provides a new chip packaging structure, referring to Figure 2 As shown, the chip packaging structure includes a copper frame 11, a bare chip 12, an organic sealant layer 14 and a plastic sealing layer 13 which are stacked in sequence.
[0050] The back of the bare chip 12 is still connected to the copper frame 11, and is electrically connected to the circuit board through the copper frame 11. On the front of the bare chip 12, there is a pad, which is connected to the copper frame 11 through a lead.
[0051] A layer of organic sealant is adhered to the front of the bare chip 12 to form an organic sealant layer 14. Then the plastic sealing layer 13 is covered on the sealant layer 14 to achieve the encapsulation of the bare chip 12. The modulus of the organic sealant of the organic sealant layer 14 is less than the modulus of the plastic sealing material of the plastic sealing layer 13.
[0052] Next, the principle of the organic sealant layer 14 protecting the bare chip 12 and reducing the cracking of the bare chip 12 is described:
[0053] When the CTE of two connected materials differ, the entire material will warp regardless of whether the temperature is increased or decreased, which will cause the contact surface to experience greater tension or contraction. Specifically, the formula that characterizes the degree of warping is:
[0054]
[0055] Among them, k is the warpage characterization value, t is the material thickness, Ea is the modulus of the first material, Eb is the modulus of the second material, and T is the temperature. αb is the CTE of the second material, αa is the CTE of the first material, and αb-αa is used to characterize the CTE difference between the two materials.
[0056] From the above formula, we can know that in order to reduce the degree of material warping without changing the material thickness, either the CTE of the two connected materials needs to be made as consistent as possible, or the modulus of one of them needs to be significantly reduced.
[0057] Based on the above description, an organic sealant layer 14 is added to the chip packaging structure so that the front of the bare chip 12 is no longer in direct contact with the plastic sealing layer 13. In this way, the organic sealant layer 14 contacts the plastic sealing layer 13 as a buffer layer, and can absorb the thermal stress that should be borne by the chip itself. At the same time, since the front of the bare chip 12 contacts the organic sealant layer 14, and the modulus of the organic sealant layer 14 is lower than the modulus of the plastic sealing layer 13, the thermal stress induced between the organic sealant layer 14 and the bare chip 12 will be greatly reduced, and the degree of chip warping will be greatly reduced, so that the occurrence of chip cracking can be reduced, thereby playing a role in protecting the chip.
[0058] As shown, the modulus of the organic sealant layer 14 needs to be lower than 1 GPa. Thus, the modulus of the organic sealant layer 14 will be much lower than the modulus of the plastic sealing layer 13 . Thus, the thermal stress on the front side of the bare chip 12 will be greatly reduced.
[0059] As shown, the material of the organic sealant layer 14 can be silicone rubber containing siloxane bonds (Si-O-Si bonds), silicone resin containing siloxane bonds, organic high molecular polymers containing more than two epoxy groups in the molecular structure, etc. These materials not only have very low modulus, but also have the characteristics of high thermal stability, good flexibility, and strong insulation performance. Therefore, these materials can greatly reduce the thermal stress borne by the chip while also improving the tolerance of the chip to harsh environments. It can form a double-layer structure with the plastic encapsulation material to resist corrosion / water vapor erosion, and play a physical protection role for the chip. At the same time, these materials can withstand the secondary heating of the plastic encapsulation material after curing, and are also feasible in terms of technology.
[0060] As shown, the organic sealant layer 14 may include one or more of the above materials, and may also be a mixture of the above materials with various fillers added, which is not limited here. In addition, an organic sealant with a high thermal conductivity may also be selected, so that while relieving the stress on the bare chip 12, it can also have the effect of uniformly distributing the heat source on the surface of the bare chip 12. In this way, the heat generated by the bare chip 12 can be quickly transferred to other heat dissipation paths, thereby increasing the heat dissipation area of the bare chip 12 in disguised form.
[0061] Based on the above, refer to Figure 3 As shown, another new chip packaging structure provided by the embodiment of the present application comprises a copper frame 11, a transition heat sink layer 15, a bare chip 12, an organic sealant layer 14 and a plastic sealing layer 13 which are stacked in sequence.
[0062] The back of the bare chip 12 is no longer in direct contact with the copper frame 11, but is electrically connected to the copper frame 11 through the transition heat sink layer 15. The front of the bare chip 12 is still adhered to the organic sealant layer 14, and the plastic sealing layer 13 covers the sealant layer 14 to achieve the encapsulation of the bare chip 12.
[0063] As shown, the modulus of the organic sealant of the organic sealant layer 14 is smaller than the modulus of the plastic sealant of the plastic sealant layer 13. This can make the front of the bare chip 12 no longer directly contact the plastic sealant layer 13. In this way, the organic sealant layer 14, as a buffer layer, can absorb the thermal stress that should be borne by the chip itself to relieve the thermal stress borne by the front of the bare chip 12. Specifically, the content of the organic sealant layer 14 refers to the content of the above embodiment, and will not be repeated here.
[0064] As shown, the back side of the bare chip 12 has an additional transition heat sink layer 15 compared to the above embodiment. Specifically, the transition heat sink layer 15 is located between the bare chip 12 and the copper frame 11, and the back side of the bare chip 12 is connected to the copper frame 11 through the transition heat sink layer 15. The CTE of the transition heat sink layer 15 is between the CTE of the substrate (SiC) of the bare chip 12 and the CTE of copper.
[0065] It can be understood that, compared with the direct connection between the back side of the bare chip 12 and the copper frame 11, its connection with the transition heat sink layer 15 can greatly reduce the CTE difference between the contact interfaces, thereby alleviating the CTE mismatch problem. In this way, the induced thermal stress will be greatly reduced, and the thermal stress on the back side of the bare chip 12 will also be greatly reduced, further alleviating the problem of cracking of the bare chip 12.
[0066] As shown, the material of the transition heat sink layer 15 can be an alloy material such as CPC, molybdenum copper, tungsten copper, diamond copper, or a composite material of metal / alloy material combined with ceramic materials such as AlN, Si3N4, Al2O3 and ZTA. These materials can not only relieve the thermal stress on the back of the bare chip 12, but also have good thermal conductivity, and can quickly conduct the heat generated by the bare chip 12 to the copper frame 11 at the bottom to achieve a better heat dissipation effect. At the same time, these materials have good mechanical properties and are also feasible in terms of process.
[0067] Based on the above description, refer to Figure 4 As shown, another new chip packaging structure provided by the embodiment of the present application is shown. The chip packaging structure includes a copper frame 11, a transition heat sink layer 15, a bare chip 12 and a plastic packaging layer 13 which are stacked in sequence.
[0068] Understandably, Figure 3 Compared with the embodiment shown, the front side of the bare chip 12 may not adhere to the organic sealant, and the thermal stress on the back side of the bare chip 12 is relieved only by the transition heat sink layer 15. By reducing the CTE difference between the contact interfaces, the induced thermal stress is reduced, thereby reducing the thermal stress on the back side of the bare chip 12, and further alleviating the problem of cracking of the bare chip 12.
[0069] Indicatively, the present application also provides a packaging method for the aforementioned chip, such as Figure 5 As shown, the packaging method may include:
[0070] 501 . Connect the back side of the bare chip 12 to the copper frame 11 .
[0071] refer to Fig. 6A As shown, there may be a plurality of solder joints on the back of the bare chip 12 , and the bare chip 12 may be soldered to the copper frame 11 through the solder joints to achieve electrical connection between the bare chip 12 and the copper frame 11 .
[0072] 502. Connect the pad on the front side of the bare chip 12 and the copper frame 11 through wires.
[0073] refer to Figure 6B Then, the pads on the front side of the bare chip 12 and the copper frame 11 are connected through wires.
[0074] 503 . Adhere an organic sealant to the front side of the bare chip 12 , and cure the organic sealant to form an organic sealant layer 14 .
[0075] refer to Figure 6C A layer of organic sealant is applied on the front side of the bare chip 12 , and then the organic sealant is cured, thereby forming an organic sealant layer 14 on the front side of the bare chip 12 .
[0076] Illustratively, the material of the organic sealant layer 14 can be silicone rubber containing siloxane bonds (Si-O-Si bonds), silicone resin containing siloxane bonds, organic high molecular polymers containing two or more epoxy groups in their molecular structure, and the like.
[0077] 504 , plastic-encapsulate the bare chip 12 to form a plastic-encapsulation layer 13 .
[0078] refer to Fig.6D After the organic sealant layer 14 is cured, the bare chip 12 is plastic-sealed to form a plastic-sealing layer 13 .
[0079] Schematically, the modulus of the material of the organic sealant layer 14 is smaller than the modulus of the plastic sealing layer 13 .
[0080] As shown, the organic sealant layer 14 can prevent the front of the bare chip 12 from directly contacting the plastic sealing layer 13. In this way, the organic sealant layer 14, as a buffer layer, contacts the plastic sealing layer 13 and can absorb the thermal stress that should be borne by the chip itself. At the same time, since the front of the bare chip 12 contacts the organic sealant layer 14, and the modulus of the organic sealant layer 14 is lower than the modulus of the plastic sealing layer 13, the thermal stress induced between the organic sealant layer 14 and the bare chip 12 will be greatly reduced, and the degree of chip warping will be greatly reduced, so that the occurrence of chip cracking can be reduced, thereby playing a role in protecting the chip.
[0081] As shown, the modulus of the organic sealant layer 14 needs to be lower than 1 GPa. Thus, the modulus of the organic sealant layer 14 will be much lower than the modulus of the plastic sealing layer 13 . Thus, the thermal stress on the front side of the bare chip 12 will be greatly reduced.
[0082] As shown, the organic sealant layer 14 can also form a double-layer structure with the plastic encapsulation material to resist corrosion / water vapor erosion and provide physical protection for the chip. In addition, if the thermal conductivity of the organic sealant layer 14 is high, the organic sealant layer 14 can relieve the stress on the bare chip 12 and also have the effect of uniformly distributing the heat source on the surface of the bare chip 12. In this way, the heat generated by the bare chip 12 can be quickly transferred to other heat dissipation paths, thereby increasing the heat dissipation area of the bare chip 12 in disguised form.
[0083] As an illustration, the present application also provides another packaging method for the aforementioned chip, such as Figure 7 As shown, the packaging method may include:
[0084] 701 . Bond the transition heat sink layer 15 onto the copper frame 11 .
[0085] refer to Fig. 8A A transition heat sink layer 15 is bonded to the copper frame 11 .
[0086] The thermal expansion coefficient CTE of the transition heat sink layer 15 is greater than the thermal expansion coefficient CTE of the bare chip 12 , and the thermal expansion coefficient CTE of the transition heat sink layer 15 is less than the thermal expansion coefficient CTE of copper.
[0087] Illustratively, the material of the transition heat sink layer 15 can be an alloy material such as CPC, molybdenum copper, tungsten copper, diamond copper, etc., or a composite material combining a metal / alloy material with a ceramic material such as AlN, Si3N4, Al2O3 and ZTA.
[0088] Schematically, the transition heat sink layer 15 can be connected to the copper frame 11 by bonding methods such as solder, adhesive, sintered silver, conductive silver glue, etc., which are not limited here.
[0089] 702 . Connect the back side of the bare chip 12 to the transition heat sink layer 15 .
[0090] refer to Figure 8B As shown, there may be a plurality of solder joints on the back side of the bare chip 12 , and the bare chip 12 may be soldered to the transition heat sink layer 15 through the solder joints to achieve electrical connection between the bare chip 12 and the copper frame 11 .
[0091] It can be understood that, compared with the direct connection between the back side of the bare chip 12 and the copper frame 11, its connection with the transition heat sink layer 15 can greatly reduce the CTE difference between the contact interfaces, thereby alleviating the CTE mismatch problem. In this way, the induced thermal stress will be greatly reduced, and the thermal stress on the back side of the bare chip 12 will also be greatly reduced, further alleviating the problem of cracking of the bare chip 12.
[0092] 703. Connect the pads on the front side of the bare chip 12 and the copper frame 11 through wires.
[0093] refer to Figure 8C Then, the pads on the front side of the bare chip 12 and the copper frame 11 are connected through wires.
[0094] 704 . Adhere an organic sealant to the front side of the bare chip 12 , and cure the organic sealant to form an organic sealant layer 14 .
[0095] refer to Fig.8D A layer of organic sealant is applied on the front side of the bare chip 12 , and then the organic sealant is cured, thereby forming an organic sealant layer 14 on the front side of the bare chip 12 .
[0096] Illustratively, the material of the organic sealant layer 14 can be silicone rubber containing siloxane bonds (Si-O-Si bonds), silicone resin containing siloxane bonds, organic high molecular polymers containing two or more epoxy groups in their molecular structure, and the like.
[0097] 705 . Plastic-encapsulate the bare chip 12 to form a plastic-encapsulation layer 13 .
[0098] refer to Fig. 8E After the organic sealant layer 14 is cured, the bare chip 12 is plastic-sealed to form a plastic-sealing layer 13 .
[0099] Schematically, the modulus of the material of the organic sealant layer 14 is smaller than the modulus of the plastic sealing layer 13 .
[0100] As shown, the organic sealant layer 14 can prevent the front of the bare chip 12 from directly contacting the plastic sealing layer 13. In this way, the organic sealant layer 14, as a buffer layer, contacts the plastic sealing layer 13 and can absorb the thermal stress that should be borne by the chip itself. At the same time, since the front of the bare chip 12 contacts the organic sealant layer 14, and the modulus of the organic sealant layer 14 is lower than the modulus of the plastic sealing layer 13, the thermal stress induced between the organic sealant layer 14 and the bare chip 12 will be greatly reduced, and the degree of chip warping will be greatly reduced, so that the occurrence of chip cracking can be reduced, thereby playing a role in protecting the chip.
[0101] The chip packaging method provided in the embodiment of the present application reduces the thermal stress on the chip itself by adhering a low modulus organic sealant on the front of the chip and adding a transition heat sink on the back of the chip. This will reduce the occurrence of chip cracking, thereby playing a role in protecting the chip.
[0102] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.
[0103] For other related contents in the above-mentioned manufacturing method, you can refer to the corresponding parts in the above-mentioned chip structure embodiment, which will not be repeated here; for other setting structures in the above-mentioned chip structure embodiment, you can refer to the above-mentioned manufacturing method and related manufacturing methods for adjustment, which will not be repeated here one by one.
[0104] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.
Claims
1. A chip packaging structure, characterized in that: The chip packaging structure comprises: Copper frame, bare chip, organic sealant layer, and plastic layer; The bare chip is located between the copper frame and the plastic packaging layer; the front side of the bare chip includes a pad, and the pad is connected to the copper frame through a lead; the back side of the bare chip is connected to the copper frame; The organic sealant layer is adhered to the front side of the bare chip; the modulus of the organic sealant layer is smaller than the modulus of the plastic sealing layer.
2. The structure according to claim 1, characterized in that: The modulus of the organic sealant layer is lower than 1 GPa.
3. The structure according to any one of claims 1 to 2, characterized in that: The material of the organic sealant layer includes one or more of silicone rubber including siloxane bonds in its molecular structure, silicone resin including siloxane bonds in its molecular structure, and organic high molecular polymer containing two or more epoxy groups in its molecular structure.
4. The structure according to claim 3, characterized in that The chip packaging structure also includes a transition heat sink layer; Wherein, the transition heat sink layer is located between the bare chip and the copper frame; The back side of the bare chip is connected to the copper frame through the transition heat sink layer; wherein the thermal expansion coefficient CTE of the transition heat sink layer is greater than the thermal expansion coefficient CTE of the substrate of the bare chip, and the thermal expansion coefficient CTE of the transition heat sink layer is less than the thermal expansion coefficient CTE of copper.
5. The structure according to claim 4, characterized in that: The material of the transition heat sink layer is a metal / alloy material, or a composite material combining a metal / alloy material and a ceramic material.
6. A chip packaging method, characterized in that: The method comprises: Attach the back side of the bare chip to the copper frame; Connecting the pad on the front side of the bare chip to the copper frame through leads; Adhere an organic sealant to the front side of the bare chip, and cure the organic sealant to form an organic sealant layer; The bare chip with the organic sealant layer adhered to the surface is plastic-sealed to form a plastic-sealing layer; wherein the modulus of the material of the organic sealant layer is smaller than the modulus of the plastic-sealing layer.
7. The method according to claim 6, characterized in that The modulus of the organic sealant layer is lower than 1 GPa.
8. The method according to any one of claims 6 to 7, characterized in that: The material of the organic sealant layer includes one or more of silicone rubber including siloxane bonds in its molecular structure, silicone resin including siloxane bonds in its molecular structure, and organic high molecular polymer containing two or more epoxy groups in its molecular structure.
9. The method according to claim 8, characterized in that Before the step of connecting the back side of the bare chip to the copper frame, the method further comprises: A transition heat sink layer is bonded to the copper frame; wherein the back side of the bare chip is connected to the copper frame through the transition heat sink layer; the thermal expansion coefficient CTE of the transition heat sink layer is greater than the thermal expansion coefficient CTE of the substrate of the bare chip, and the thermal expansion coefficient CTE of the transition heat sink layer is less than the thermal expansion coefficient CTE of copper.
10. An electronic device, characterized in that: The electronic device comprises a circuit board and a chip packaging structure as claimed in any one of claims 1 to 5; the circuit board and the chip packaging structure are electrically connected.