Chip superposition packaging process and packaging structure of semiconductor discharge diode

Abstract

The invention discloses a chip superposition packaging technology and packaging structure of a semiconductor discharge diode, which comprises a chip set and a sealing assembly arranged outside the chip set, and is characterized in that the chip set comprises a bottom-layer chip and a middle-layer chip arranged above the bottom-layer chip, the top layer chip is arranged above the middle layer chip; the bottom layer chip, the middle layer chip and the bottom layer chip are different in power and size; the bottom layer chip, the middle layer chip and the bottom layer chip are connected through connecting sheets; the sealing assembly comprises heat dissipation substrates which correspond to the positions of the top layer chip, the middle layer chip and the bottom layer chip respectively, the space structures of the layers are different, deformation or damage under the action of external force is effectively prevented, and the overall stability of the packaging structure is greatly improved due to the addition of reinforcing ribs. And all-around protection and support are provided for chip packaging together.

Description

Technical Field

[0001] The invention relates to a chip stacking packaging process, and in particular to a chip stacking packaging process for a semiconductor discharge diode and a packaging structure thereof. Background Art

[0002] In the field of gardening tool manufacturing, pruning blades are important cutting parts, and their quality and production efficiency directly affect the effect and cost of gardening operations. The traditional assembly process of pruning blades mainly relies on manual operation, including the placement of parts and the tightening of screws. This is not only labor-intensive, but also inefficient and prone to unstable assembly quality due to human factors.

[0003] With the rapid development of automation technology, more and more manufacturing fields have begun to introduce automation equipment to improve production efficiency and product quality. However, for small and precise gardening tool parts such as pruning blades, automated assembly technology still faces many challenges. For example, how to ensure the precise positioning and clamping of parts, how to achieve fast and accurate tightening of screws, and how to design a flexible system that can adapt to the assembly of different types of pruning blades are all technical problems that need to be solved urgently.

[0004] Therefore, an automatic screw locking device suitable for pruning blade assembly is developed. Summary of the invention

[0005] The present invention overcomes the shortcomings of the prior art and provides a chip stacking packaging process and a packaging structure of a semiconductor discharge diode.

[0006] To achieve the above object, the technical solution adopted by the present invention is: a chip stacking packaging structure of a semiconductor discharge diode, comprising: a chipset, a sealing component arranged outside the chipset, characterized in that:

[0007] The chipset includes a bottom chip, a middle chip disposed above the bottom chip, and a top chip disposed above the middle chip; the bottom chip, the middle chip and the bottom chip have different powers and sizes, and are stacked in a V-shape on the sealing component in sequence; the bottom chip, the middle chip and the bottom chip are connected by a connecting sheet;

[0008] The sealing component includes a heat dissipation substrate and a frame located above the heat dissipation substrate; the frame is provided with a top space, a middle space and a bottom space, which respectively correspond to the positions of the top chip, the middle chip and the bottom chip, and the structure of each space is different.

[0009] In a preferred embodiment of the present invention, the sizes of the bottom chip, the middle chip and the top chip are set in order of decreasing the maximum and increasing the maximum.

[0010] In a preferred embodiment of the present invention, the power of the bottom chip, the middle chip and the top chip are set to decrease gradually.

[0011] In a preferred embodiment of the present invention, the frame is arranged in a trapezoidal shape, and a through hole is arranged on the top of the frame. The through hole is used to fill epoxy resin to form a sealing structure for the internal chip.

[0012] In a preferred embodiment of the present invention, an elastic element is provided at the junction of the middle space with the top space and the bottom space. The elastic element is made of elastic material and is hollowed out. The elastic material is selected from silicone rubber, polyurethane or polyimide.

[0013] In a preferred embodiment of the present invention, reinforcing ribs are arranged around the butting portion on the heat dissipation substrate, and the bottom chip is arranged inside the reinforcing ribs.

[0014] A chip stacking packaging process for a semiconductor discharge diode comprises the following steps:

[0015] S1: Preheat the welding area to 45-55°C;

[0016] S2: welding the bottom chip, the middle chip and the top chip step by step;

[0017] S3: Inject epoxy resin through the through hole at the top of the frame so that the epoxy resin covers the chip.

[0018] In a preferred embodiment of the present invention, in S2, the specific welding steps are:

[0019] S21: placing the connecting piece and the bottom chip from the top of the frame into the reinforcing rib and welding them;

[0020] S22: placing the connecting sheet and the middle layer chip in the middle layer space above the bottom layer chip and welding them again;

[0021] S23: Place the connecting piece and the top chip on the middle chip and solder them again.

[0022] In a preferred embodiment of the present invention, in S21, the welding temperature is 145-165°C, the time is 2-4s, the pressure is 0.1-0.2MPa, and the welding material is low-temperature solder; in S22, the welding temperature is 140-150°C, the time is 1-2s, and the pressure is 0.06-0.1MPa; in S23, the welding temperature is 135-145°C, the welding time is 1-2s, and the pressure is 0.04-0.08MPa.

[0023] In a preferred embodiment of the present invention, the connecting sheet is made of polyimide, silicone or silicone oil.

[0024] The present invention solves the defects existing in the background technology and has the following beneficial effects:

[0025] (1) The present invention provides a chip stacking packaging structure for a semiconductor discharge diode. The bottom chip, the middle chip and the top chip are stacked in a V-shape in sequence, thereby optimizing the heat dissipation path of the packaging structure. Compared with the traditional planar stacking, the V-shaped stacking can more effectively utilize the space, reduce the close contact between the chips, reduce the heat accumulation, and improve the heat dissipation efficiency. At the same time, the heat dissipation substrate is made of copper, which can quickly conduct the heat generated by the chip. The reinforcing ribs not only increase the strength and rigidity of the packaging structure, but also optimize the heat dissipation path, so that the heat can be more smoothly transferred to the outside of the package. The hollow elastic element not only reduces the material usage, but also provides an additional heat dissipation channel. At the same time, the elastic element can absorb and relieve the stress between the chips in each layer, prevent the damage of the packaging structure caused by stress concentration, and thus indirectly protect the heat dissipation structure of the chip.

[0026] (2) The present invention provides a chip stacking packaging structure for a semiconductor discharge diode. By welding the bottom chip, the middle chip and the top chip in steps, it ensures that each chip can be stably and reliably connected during the packaging process. At the same time, the precise control of the welding temperature and time effectively reduces welding defects and significantly improves the welding quality. In addition, the connecting piece made of materials such as polyimide, silicone or silicone oil can perfectly adapt to the slight deformation and temperature changes of the chip during operation due to its excellent flexibility and high temperature resistance, thereby ensuring the long-term stability of the electrical connection between chips. In addition, the provision of elastic elements further enhances the seismic resistance of the packaging structure and effectively prevents deformation or damage under the action of external forces. The addition of reinforcing ribs greatly improves the overall stability of the packaging structure, and together provides all-round protection and support for chip packaging.

[0027] (3) The present invention provides a chip stacking packaging structure for a semiconductor discharge diode. In the packaging structure, the power of the bottom chip, the middle chip and the top chip are designed to be gradually reduced in sequence, which not only significantly reduces the power consumption of the entire packaging structure during operation, but also greatly improves the energy utilization efficiency. At the same time, by reducing the power of each layer of chips, the thermal interference of high-power chips on surrounding chips is effectively reduced, ensuring the thermal balance between each layer of chips, and further improving the overall stability and reliability of the packaging structure.

[0028] (4) The present invention provides a chip stacking packaging structure for a semiconductor discharge diode. By matching a V-shaped stacking structure with a trapezoidal frame, the packaging volume is significantly reduced, and the integration is greatly improved, so that more chips can be efficiently accommodated in a limited packaging space, perfectly meeting the application requirements of high performance and high integration. In addition, the hollow design of the elastic element further reduces the weight of the packaging structure, reduces the cost, and provides a more superior heat dissipation channel, ensuring the stability and reliability of the packaging structure under high-performance operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work.

[0030] Figure 1 is a three-dimensional structural diagram of a preferred embodiment of the present invention;

[0031] In the figure: 1. Chip set; 2. Sealing component; 3. Heat dissipation substrate; 4. Frame; 5. Bottom chip; 6. Middle chip; 7. Top chip; 8. Elastic element; 9. Reinforcement ribs; 10. Epoxy resin; 11. Connecting piece. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0033] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein. Therefore, the protection scope of the present invention is not limited to the specific embodiments disclosed below.

[0034] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the scope of protection of the present application. In addition, the terms "first", "second", etc. are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, features defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the invention, unless otherwise specified, "multiple" means two or more.

[0035] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood by specific circumstances.

[0036] As shown in the figure, a chip stacking packaging structure of a semiconductor discharge diode includes: a chipset, a sealing component arranged outside the chipset,

[0037] The chipset includes a bottom chip, a middle chip disposed above the bottom chip, and a top chip disposed above the middle chip; the bottom chip, the middle chip and the bottom chip have different powers and sizes, and are stacked in a V-shape on the sealing component in sequence; the bottom chip, the middle chip and the bottom chip are connected by a connecting sheet;

[0038] In a preferred embodiment of the present invention, the sizes of the bottom chip, the middle chip and the top chip are set to be the largest and then smaller and then larger; the powers of the bottom chip, the middle chip and the top chip are set to be gradually smaller; the frame is set in a trapezoidal shape, and a through hole is set on the top of the frame, and the through hole is used to fill epoxy resin to form a sealing structure for the internal chip.

[0039] It should be noted that the chipset is the core part of the packaging structure, which is composed of multiple layers of chips. The bottom chip is the bottom chip in the chipset, with the largest size and the highest power. As the foundation of the entire packaging structure, the bottom chip bears the weight and electrical connection of the upper chip. The middle chip is located above the bottom chip, is smaller in size than the bottom chip, and has relatively lower power. The middle chip plays a role of transition and connection in the packaging structure. The top chip is located above the middle chip and is the top chip in the chipset. Although the size of the top chip will not exceed that of the bottom chip. The top chip is responsible for connecting with the external circuit to realize signal transmission.

[0040] The bottom chip, middle chip and top chip are stacked in a V shape on the sealing component. This stacking method helps to optimize the heat dissipation performance of the package structure while reducing the package volume. In the V-shaped stacking structure, the space between the chips is used more effectively. Compared with the traditional planar stacking, the V-shaped stacking can reduce the close contact between the chips, thereby reducing the accumulation of heat between the chips. This design makes it easier for heat to pass through the heat dissipation channel or heat dissipation structure. When the chip is working, the heat generated will be transferred to the outside of the package structure along the surface of the chip. Since the V-shaped stacking increases the surface area of ​​the chip (relative to the planar stacking), the heat dissipation area is also increased accordingly. This helps to speed up the heat transfer speed and improve the heat dissipation efficiency. The bottom chip, middle chip and top chip are electrically connected through the connecting piece. The connecting piece can ensure the signal transmission and power supply between the chips of each layer.

[0041] The sizes of the bottom chip, the middle chip and the top chip are the largest, reduced and increased again. This size setting helps to achieve higher integration and better heat dissipation performance in a limited packaging space. The top chip is larger in size and can provide a larger heat dissipation area. When the chip is working, the heat generated can be dissipated to the surrounding environment through the surface of the top chip. The middle chip is smaller in size, which can reduce the heat conduction between it and the bottom chip, thereby reducing the interference of the bottom chip on the heat dissipation of the top chip. Although the bottom chip is the largest in size, it can dissipate heat through the bottom or side of the packaging structure because it is located at the bottom of the packaging structure. This size setting can form a more reasonable heat dissipation path. For example, the heat generated by the top chip can be guided to the outside of the packaging structure by setting heat dissipation channels, heat sinks and other structures in the packaging structure. At the same time, since the middle chip is smaller in size, the obstruction to the heat dissipation path can be reduced, making it easier for the heat to be dissipated to the surrounding environment through the heat dissipation structure. The chip will generate thermal stress during operation. If the chip sizes are the same or similar, the thermal stresses may be superimposed on each other, causing deformation or damage to the packaging structure. By adjusting the chip size, the thermal stress distribution between the chips in each layer can be made more uniform, reducing the risk of damage to the packaging structure due to concentrated thermal stress.

[0042] The power of the bottom chip, the middle chip and the top chip is set to gradually decrease in sequence. This power setting can ensure that the chips on each layer will not interfere with each other during operation, while improving the stability and reliability of the entire package structure. The power of each layer of chips gradually decreases, which means that the electrical energy they consume during operation will also gradually decrease, thereby reducing the power consumption of the entire package structure and improving energy utilization efficiency. As the chip with higher power generates more heat during operation. By gradually reducing the power of each layer of chips, the accumulation of heat can be reduced and the temperature inside the package structure can be reduced. Lower temperatures help maintain the stability and reliability of the chip and extend its service life. The heat generated by high-power chips will cause thermal interference to the surrounding chips, affecting their normal operation. By reducing the power of each layer of chips, this thermal interference can be reduced. The reduction of thermal interference helps to maintain the thermal balance between the chips on each layer and improve the overall stability of the package structure. The gradual reduction of the power of each layer of chips helps to reduce the temperature gradient inside the package structure, thereby reducing the generation of thermal stress. The reduction of thermal stress helps to maintain the integrity of the package structure and prevent deformation or damage caused by excessive thermal stress.

[0043] The frame is set in a trapezoidal shape, matching the V-shaped stacking of the chipset, ensuring that the package structure is more stable when subjected to force while reducing the package volume. A through hole is set on the top of the frame, and the through hole is filled with epoxy resin. After curing, the epoxy resin forms a sealing structure to protect the internal chip. This sealing structure can prevent external contaminants such as moisture and dust from entering the package, ensuring the stability and reliability of the chip.

[0044] The sealing component includes a heat dissipation substrate and a frame located above the heat dissipation substrate; the frame is provided with a top space, a middle space and a bottom space, which correspond to the positions of the top chip, the middle chip and the bottom chip respectively, and the structure of each space is different.

[0045] In the present invention, an elastic element is arranged at the junction of the middle space with the top space and the bottom space. The elastic element is made of elastic material and is hollowed out. The elastic material is selected from silicone rubber, polyurethane or polyimide. Reinforcing ribs are arranged around the docking part on the heat dissipation substrate, and the bottom chip is arranged inside the reinforcing ribs. An elastic element is arranged at the junction of the middle space with the top space and the bottom space.

[0046] It should be noted that the sealing component is mainly composed of two parts: a heat dissipation substrate and a frame located above the heat dissipation substrate. The heat dissipation substrate is the basis of the packaging structure, and its main function is to dissipate heat. By effectively conducting away the heat generated by the chip, the chip is kept within a suitable operating temperature range. The heat dissipation substrate is made of a material with high thermal conductivity, namely copper, to ensure rapid heat conduction. The frame is located above the heat dissipation substrate and is used to fix and support each layer of chips. The frame is provided with a top space, a middle space and a bottom space, which correspond to the positions of the top chip, the middle chip and the bottom chip respectively. The structure of each layer of space is different to meet the size, shape and heat dissipation requirements of different chips. The elastic element is made of elastic material, such as silicone rubber, polyurethane or polyimide. These materials have good elasticity and high temperature resistance, and can adapt to the slight deformation and temperature changes of the chip during operation. The elastic element is hollowed out, which helps to reduce the amount of material used, reduce weight and cost. At the same time, the hollow design can also provide a better heat dissipation channel, which helps to dissipate heat. The setting of the elastic element can absorb and relieve the stress between the chips in each layer, and prevent damage to the packaging structure caused by stress concentration. In addition, it can also improve the shock resistance of the packaging structure, ensuring that the chip can still work normally in harsh working environments.

[0047] The ribs are additional structures set on the heat dissipation substrate to increase the strength and rigidity of the package structure. The bottom chip is set inside the ribs, which can ensure that the bottom chip is fully supported and protected during the packaging process. The design of the ribs can improve the overall stability of the package structure and prevent deformation or damage caused by external forces. At the same time, it can also optimize the heat dissipation path and improve the heat dissipation efficiency.

[0048] A chip stacking packaging process for a semiconductor discharge diode comprises the following steps:

[0049] S1: Preheat the welding area to 45-55°C;

[0050] S2: Weld the bottom chip, middle chip and top chip step by step; place the connecting piece and the bottom chip from the top of the frame into the reinforcing ribs and weld them; place the connecting piece and the middle chip in the middle space above the bottom chip and weld them again; place the connecting piece and the top chip on the middle chip and weld them again.

[0051] S3: Inject epoxy resin through the through hole at the top of the frame so that the epoxy resin covers the chip.

[0052] In a preferred embodiment of the present invention, in S21, the welding temperature is 145-165°C, the time is 2-4s, the pressure is 0.1-0.2MPa, and the welding material is low-temperature solder; in S22, the welding temperature is 140-150°C, the time is 1-2s, and the pressure is 0.06-0.1MPa; in S23, the welding temperature is 135-145°C, the welding time is 1-2s, and the pressure is 0.04-0.08MPa.

[0053] In a preferred embodiment of the present invention, the connecting piece is made of polyimide, silicone or silicone oil.

[0054] It should be noted that

[0055] Embodiment 1:

[0056] Preheat the welding area to 50℃ to reduce thermal shock during welding. Step-by-step welding, place the connecting piece and the bottom chip from the top of the frame into the reinforcing ribs and weld them at a welding temperature of 150℃, a time of 3s, a pressure of 0.15MPa, and a welding material of low-temperature solder; place the connecting piece and the middle chip in the middle space above the bottom chip and weld them again at a welding temperature of 145℃, a time of 1.5s, and a pressure of 0.08MPa; place the connecting piece and the top chip on the middle chip and weld them again at a welding temperature of 150℃, a welding time of 1.5s, and a pressure of 0.06MPa. Inject epoxy resin through the through hole to fill the gap and solidify it. After welding, a heat sink or heat dissipation coating can be added to the connecting piece to further improve the heat dissipation effect.

[0057] The above is based on the ideal embodiment of the present invention. Through the above description, relevant personnel can make various changes and modifications without departing from the technical concept of the present invention. The technical scope of the present invention is not limited to the content in the specification, and the technical scope must be determined according to the scope of the claims.

Claims

1. A chip stacking packaging structure of a semiconductor discharge diode, comprising: A chipset, and a sealing component disposed outside the chipset, characterized in that: The chipset includes a bottom chip, a middle chip disposed above the bottom chip, and a top chip disposed above the middle chip; the bottom chip, the middle chip and the bottom chip have different powers and sizes, and are stacked in a V-shape on the sealing component in sequence; the bottom chip, the middle chip and the bottom chip are connected by a connecting sheet; The sealing component includes a heat dissipation substrate and a frame located above the heat dissipation substrate; the frame is provided with a top space, a middle space and a bottom space, which respectively correspond to the positions of the top chip, the middle chip and the bottom chip, and the structure of each space is different.

2. The chip stacking packaging structure of a semiconductor discharge diode according to claim 1, characterized in that: The sizes of the bottom chip, the middle chip and the top chip are set in order of decreasing the maximum and then increasing.

3. The chip stacking packaging structure of a semiconductor discharge diode according to claim 1, characterized in that: The power of the bottom chip, the middle chip and the top chip is set to decrease gradually.

4. The chip stacking packaging structure of a semiconductor discharge diode according to claim 1, characterized in that: The frame is arranged in a trapezoidal shape, and a through hole is arranged on the top of the frame. The through hole is used to fill epoxy resin to form a sealing structure for the internal chip.

5. The chip stacking packaging structure of a semiconductor discharge diode according to claim 1, characterized in that: The middle space is provided with an elastic element at the junction with the top space and the bottom space. The elastic element is made of elastic material and is hollowed out. The elastic material is selected from silicone rubber, polyurethane or polyimide.

6. The chip stacking packaging structure of a semiconductor discharge diode according to claim 1, characterized in that: A reinforcing rib is arranged around the butting portion on the heat dissipation substrate, and the bottom chip is arranged inside the reinforcing rib.

7. A chip stacking packaging process for a semiconductor discharge diode, based on the packaging structure according to any one of claims 1 to 6, characterized in that: The following steps are involved: S1: Preheat the welding area to 45-55°C; S2: welding the bottom chip, the middle chip and the top chip step by step; S3: Inject epoxy resin through the through hole at the top of the frame so that the epoxy resin covers the chip.

8. The chip stacking packaging process of a semiconductor discharge diode according to claim 7, characterized in that: In said S2, the specific welding steps are: S21: placing the connecting piece and the bottom chip from the top of the frame into the reinforcing rib and welding them; S22: placing the connecting sheet and the middle layer chip in the middle layer space above the bottom layer chip and welding them again; S23: Place the connecting piece and the top chip on the middle chip and solder them again.

9. The chip stacking packaging process of a semiconductor discharge diode according to claim 8, characterized in that: In the S21, the welding temperature is 145-165°C, the time is 2-4s, the pressure is 0.1-0.2MPa, and the welding material is low-temperature solder; in the S22, the welding temperature is 140-150°C, the time is 1-2s, and the pressure is 0.06-0.1MPa; in the S23, the welding temperature is 135-145°C, the welding time is 1-2s, and the pressure is 0.04-0.08MPa.

10. The chip stacking packaging process of a semiconductor discharge diode according to claim 1, characterized in that: The connecting piece is made of polyimide, silicone or silicone oil.

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