AI computing power chip vertical power supply structure

Abstract

The invention discloses a vertical power supply structure of an AI computing power chip. The vertical power supply structure comprises the AI computing power chip, a silicon through hole adapter plate, an organic adapter plate and a low-inductance gallium nitride module, the AI computing power chip, the through-silicon-via adapter plate, the organic adapter plate and the low-inductance gallium nitride module are sequentially distributed from top to bottom, a plurality of output capacitors are arranged between the organic adapter plate and the through-silicon-via adapter plate, a first group of solder balls are arranged between the adjacent output capacitors, a first chip inductor and a second chip inductor are further arranged below the organic adapter plate, and the first chip inductor and the second chip inductor are connected with the first chip inductor. And a second group of solder balls are arranged between the first chip inductor and the organic adapter plate, between the second chip inductor and the organic adapter plate, and between the low-inductance gallium nitride module and the organic adapter plate. The structure can avoid the problems of line loss and large voltage dynamic oscillation amplitude caused by a long power supply loop.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor integrated chip power supply and relates to a vertical power supply structure for an AI computing chip. Background Art

[0002] With the continuous development of modern information technology, applications such as artificial intelligence, data centers, and autonomous driving usually need to process massive amounts of data, which puts forward new requirements for the computing power of computing devices such as CPUs and GPUs; with the increase in the scale and types of computing device chips, the power supply systems of integrated chips such as CPUs and GPUs face major challenges; taking the AI ​​computing chip GB200 as an example, the power consumption of a single chip is 1000W, the power supply voltage is as low as 0.6V, and the power supply current exceeds 1000A, which greatly increases the conduction loss of the power distribution network and reduces the tolerance of the power supply voltage variation; for future integrated chips with hundreds of chips, the power supply demand will reach several kilowatts or even tens of thousands of watts. Therefore, the development of new vertical low-power power supply currents based on the characteristics of integrated chips is the key to solving the problem faced by large-scale chip integration.

[0003] The existing power supply circuit adopts a discrete power supply architecture. In the discrete case, due to the low switching frequency of silicon power devices, passive components such as inductors and capacitors are large in size and cannot be directly integrated into the back of computing chips such as CPUs and GPUs, resulting in a longer power supply loop, causing large line losses and voltage dynamic oscillation amplitudes, thus affecting the reliable application of AI high-computing power chips. Summary of the invention

[0004] The purpose of the present invention is to overcome the shortcomings of the above-mentioned prior art and provide a vertical power supply structure for an AI computing chip, which can avoid the problems of line loss and large voltage dynamic oscillation amplitude caused by a long power supply loop.

[0005] To achieve the above-mentioned purpose, the present invention discloses a vertical power supply structure of an AI computing chip, including an AI computing chip, a through silicon via adapter plate, an organic adapter plate and a low-sensitivity gallium nitride module;

[0006] The AI ​​computing chip, through silicon via adapter board, organic adapter board and low-sensitivity gallium nitride module are distributed from top to bottom. Several output capacitors are arranged between the organic adapter board and the through silicon via adapter board. A first group of solder balls are arranged between adjacent output capacitors. A first chip inductor and a second chip inductor are also arranged under the organic adapter board. A second group of solder balls are arranged between the first chip inductor and the organic adapter board, between the second chip inductor and the organic adapter board, and between the low-sensitivity gallium nitride module and the organic adapter board.

[0007] Furthermore, the low-sensitivity gallium nitride module includes a fourth conductive layer, a fifth conductive layer and a plurality of decoupling capacitors;

[0008] One side of each decoupling capacitor is connected to the fourth conductive layer, and the other side of each decoupling capacitor is connected to the fifth conductive layer. A first conductive layer, a second conductive layer, a third conductive layer, a first gallium nitride device and a second gallium nitride device are arranged below the decoupling capacitor, wherein the first conductive layer, the second conductive layer and the third conductive layer are distributed in sequence and are located in the same plane, one side of the first gallium nitride device is connected to the third conductive layer, the other side of the first gallium nitride device is connected to the second conductive layer, one side of the second gallium nitride device is connected to the second conductive layer, and the other side of the second gallium nitride device is connected to the first conductive layer.

[0009] Furthermore, one side of the first conductive layer is a first comb-tooth structure, one side of the second conductive layer is a second comb-tooth structure, the other side of the second conductive layer is a third comb-tooth structure, and one side of the third conductive layer is a fourth comb-tooth structure, and the comb teeth in the first comb-tooth structure are alternately distributed with the comb teeth in the second comb-tooth structure, and the comb teeth in the third comb-tooth structure are alternately distributed with the comb teeth in the fourth comb-tooth structure.

[0010] Furthermore, it also includes a plurality of first vias and a plurality of second vias, a decoupling capacitor corresponds to a comb tooth in the first comb-tooth structure, a comb tooth in the fourth comb-tooth structure, a first via and a second via, wherein one side of each decoupling capacitor is connected to the corresponding comb tooth in the first comb-tooth structure through the corresponding first via hole, and the other side of each decoupling capacitor is connected to the corresponding comb tooth in the fourth comb-tooth structure through the corresponding second via hole.

[0011] Furthermore, the current direction of each comb tooth in the first comb-tooth structure is opposite to the current direction of each comb tooth in the second comb-tooth structure.

[0012] Furthermore, the current direction of each comb tooth in the third comb-tooth structure is opposite to the current direction of each comb tooth in the fourth comb-tooth structure.

[0013] Furthermore, the low-inductance gallium nitride module, the first chip inductor and the second chip inductor form a voltage regulation module.

[0014] Furthermore, the thickness of the voltage regulating module is less than or equal to 5 mm.

[0015] Furthermore, the power supply voltage output by the voltage regulation module passes through the organic adapter board, output capacitor, solder ball, through silicon via adapter board in sequence, and finally reaches the AI ​​computing chip.

[0016] Furthermore, when applied to high-power AI computing chips, multiple gallium nitride devices and multiple chip inductors are integrated on the bottom surface of the organic adapter board.

[0017] The present invention has the following beneficial effects:

[0018] During specific operation of the vertical power supply structure of the AI ​​computing power chip described in the present invention, the power supply voltage output by the voltage regulation module passes through the organic adapter board, output capacitor, solder ball and silicon via adapter board in sequence, and finally reaches the AI ​​computing power chip. Compared with the traditional power supply method, the power supply distance is significantly shortened, the line loss can be reduced, the amplitude of the voltage dynamic oscillation is reduced, and the dynamic response characteristics of the power supply voltage are improved; and the volume of the entire system is reduced, and higher-density integration is achieved, which greatly promotes the development of technologies in related fields such as artificial intelligence, cloud computing, data centers, and autonomous driving.

[0019] Furthermore, the current on the low-sensitivity gallium nitride module flows out from one end of the decoupling capacitor, passes through the fourth conductive layer, the first via, the first conductive layer, the first gallium nitride device, the second conductive layer, the second gallium nitride device, the third conductive layer, the second via, and the fifth conductive layer in sequence, and finally flows back to the other end of the decoupling capacitor. This interconnection form can significantly reduce the parasitic inductance of the gallium nitride module, increase the switching frequency of the gallium nitride device, and thereby reduce the volume of the passive device. The voltage regulation module composed of the low-sensitivity gallium nitride module and the small-volume passive device is directly integrated on the back of the AI ​​computing power chip, and the power supply voltage output by the voltage regulation module is directly supplied to the AI ​​computing power chip through the organic adapter board, the output capacitor, the solder ball and the silicon through-hole adapter board. The power supply loop is greatly shortened, the line loss is reduced, and the voltage dynamic oscillation amplitude is reduced, thereby ensuring that the AI ​​computing power chip can operate reliably and stably. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the accompanying drawings:

[0021] Figure 1 It is a schematic diagram of the main structure of the present invention;

[0022] Figure 2 Schematic diagram of the low-inductance interconnect structure of the gallium nitride device in the present invention.

[0023] Among them, 100 is a first gallium nitride device, 101 is a second gallium nitride device, 102 is a first conductive layer, 103 is a second conductive layer, 104 is a third conductive layer, 105 is a first via, 106 is a second via, 107 is a fourth conductive layer, 108 is a fifth conductive layer, 109 is a decoupling capacitor, 200 is a low-inductance gallium nitride module, 201 is a first chip inductor, 202 is a second chip inductor, 203 is an output capacitor, 204 is an AI computing chip, 205 is an organic adapter board, 207 is a solder ball, and 208 is a through silicon via adapter board. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] In the description of the present invention, it should be understood that the terms “include” and “comprises” indicate the presence of described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or collections thereof.

[0026] It should also be understood that the terms used in the present specification are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the present specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0027] It should be further understood that the term "and / or" used in the present specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in the present invention generally indicates that the associated objects are in an "or" relationship.

[0028] It should be understood that, although the terms first, second, third, etc. may be used to describe preset ranges, etc. in the embodiments of the present invention, these preset ranges should not be limited to these terms. These terms are only used to distinguish preset ranges from each other. For example, without departing from the scope of the embodiments of the present invention, the first preset range may also be referred to as the second preset range, and similarly, the second preset range may also be referred to as the first preset range.

[0029] The word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to determining" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)", depending on the context.

[0030] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. The components of the embodiments of the present invention described and shown in the drawings here can usually be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0031] Various structural schematic diagrams of the embodiments disclosed in the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0032] The vertical power supply structure of the AI ​​computing chip described in the present invention aims to reduce the volume of the voltage regulation module and realize vertical power supply on the back. First, the parasitic inductance, parasitic capacitance and thermal resistance of different interconnect structures of gallium nitride devices are analyzed to obtain a quantitative description method; the influence of different interconnect structures on the dynamic characteristics and electrothermal characteristics of gallium nitride devices is analyzed, and a new interconnect structure with low parasitic parameters and high thermal conductivity is studied and combined with advanced packaging technology to realize high-frequency, efficient and reliable application of gallium nitride devices; the increase in the switching frequency of power devices can reduce the volume of passive devices, so the second step is to study the passive device structure for high-density power supply, establish a mathematical model for electromagnetic analysis, and combine simulation to study the influence of device structure and core material on parameters such as DC resistance and core loss, study the optimization direction of device structure, and combine existing processes to realize the preparation of ultra-thin, high-current and low-loss passive devices; finally, combined with advanced packaging technology, the integration of CPU and GPU direct power supply circuits with low parasitic effects and fast dynamic response is realized.

[0033] By optimizing the layout and interconnection method of GaN devices, low-inductance and reliable interconnection of GaN devices can be achieved, thereby promoting the high-frequency application of GaN devices; the high-frequency of power devices can significantly reduce the volume of passive devices, and high-density integration of ultra-thin chip inductor arrays and low-inductance GaN modules 200 can be used to achieve miniaturization and lightweight of voltage regulation modules. The new ultra-thin voltage regulation module is integrated into the back of AI computing chips 204 such as CPU and GPU to achieve ultra-short distance vertical power supply, reduce the amplitude of voltage dynamic oscillation, and improve power supply efficiency and voltage dynamic response speed.

[0034] Embodiment 1

[0035] refer to Figure 1 Based on the above analysis, the present embodiment discloses a vertical power supply structure of an AI computing chip, including an AI computing chip 204, a through silicon via adapter board 208, an organic adapter board 205 and a low-sensitivity gallium nitride module 200; the AI ​​computing chip 204, the through silicon via adapter board 208, the organic adapter board 205 and the low-sensitivity gallium nitride module 200 are arranged in sequence from top to bottom, a plurality of output capacitors 203 are arranged between the organic adapter board 205 and the through silicon via adapter board 208, and a first group of solder balls 207 are arranged between adjacent output capacitors 203, and a first chip inductor 201 and a second chip inductor 202 are also arranged below the organic adapter board 205, wherein a second group of solder balls 207 are arranged between the first chip inductor 201 and the organic adapter board 205, between the second chip inductor 202 and the organic adapter board 205, and between the low-sensitivity gallium nitride module 200 and the organic adapter board 205.

[0036] Embodiment 2

[0037] refer to Figure 1 The vertical power supply structure of the AI ​​computing chip of the present invention includes a low-sensitivity gallium nitride module 200, a first chip inductor 201, a second chip inductor 202, an output capacitor 203, an AI computing chip 204, an organic adapter board 205, a solder ball 207 and a through silicon via adapter board 208;

[0038] The AI ​​computing chip 204, the through silicon via adapter board 208, the organic adapter board 205 and the low-sensitivity gallium nitride module 200 are arranged in sequence from top to bottom. A plurality of output capacitors 203 are arranged between the organic adapter board 205 and the through silicon via adapter board 208. A first group of solder balls 207 are arranged between adjacent output capacitors 203. A first chip inductor 201 and a second chip inductor 202 are also arranged below the organic adapter board 205. A second group of solder balls 207 are arranged between the first chip inductor 201 and the organic adapter board 205, between the second chip inductor 202 and the organic adapter board 205, and between the low-sensitivity gallium nitride module 200 and the organic adapter board 205.

[0039] refer to Figure 2The low-sensitivity gallium nitride module 200 includes a first gallium nitride device 100, a second gallium nitride device 101, a first conductive layer 102, a second conductive layer 103, a third conductive layer 104, a first via 105, a second via 106, a fourth conductive layer 107, a fifth conductive layer 108 and a decoupling capacitor 109;

[0040] One side of each decoupling capacitor 109 is connected to the fourth conductive layer 107 , and the other side of each decoupling capacitor 109 is connected to the fifth conductive layer 108 .

[0041] A first conductive layer 102 , a second conductive layer 103 , a third conductive layer 104 , a first gallium nitride device 100 , and a second gallium nitride device 101 are disposed below the decoupling capacitor 109 , wherein the first conductive layer 102 , the second conductive layer 103 , and the third conductive layer 104 are distributed in sequence and located in the same plane.

[0042] As an embodiment of the present invention, one side of the first conductive layer 102 is a first comb-tooth structure, one side of the second conductive layer 103 is a second comb-tooth structure, the other side of the second conductive layer 103 is a third comb-tooth structure, and one side of the third conductive layer 104 is a fourth comb-tooth structure, wherein the teeth in the first comb-tooth structure are alternately distributed with the teeth in the second comb-tooth structure, and the teeth in the third comb-tooth structure are alternately distributed with the teeth in the fourth comb-tooth structure.

[0043] As an embodiment of the present invention, one side of the first gallium nitride device 100 is connected to the third conductive layer 104 , the other side of the first gallium nitride device 100 is connected to the second conductive layer 103 , one side of the second gallium nitride device 101 is connected to the second conductive layer 103 , and the other side of the second gallium nitride device 101 is connected to the first conductive layer 102 .

[0044] As an embodiment of the present invention, a decoupling capacitor 109 corresponds to a comb tooth in the first comb-tooth structure, a comb tooth in the fourth comb-tooth structure, a first via 105 and a second via 106, wherein one side of each decoupling capacitor 109 is connected to the corresponding comb tooth in the first comb-tooth structure through the corresponding first via 105, and the other side of each decoupling capacitor 109 is connected to the corresponding comb tooth in the fourth comb-tooth structure through the corresponding second via 106.

[0045] As an implementation mode of the present invention, the current direction of each comb tooth in the first comb-tooth structure is opposite to the current direction of each comb tooth in the second comb-tooth structure; the current direction of each comb tooth in the third comb-tooth structure is opposite to the current direction of each comb tooth in the fourth comb-tooth structure, thereby achieving magnetic cancellation and significantly reducing the interconnection parasitic inductance of the gallium nitride device; at the same time, by adopting advanced packaging technology, the length of the first via 105 and the second via 106 can be reduced, and the area of ​​the current loop is minimized, thereby reducing the interconnection parasitic inductance of the gallium nitride device, promoting the high-frequency application of gallium nitride devices, and further reducing the volume of passive devices such as inductors.

[0046] As an implementation of the present invention, it should be noted that the low-inductance gallium nitride module 200 , the first chip inductor 201 and the second chip inductor 202 form a voltage regulation module, and the thickness of the voltage regulation module is less than or equal to 5 mm.

[0047] As an embodiment of the present invention, in addition, when applied to a high-power AI computing chip 204 , a plurality of gallium nitride devices and a plurality of chip inductors are integrated on the bottom surface of the organic adapter board 205 .

[0048] Since the switching frequency of the low-sensitivity gallium nitride module 200 mentioned above can reach several megahertz or even higher, an ultra-thin chip inductor array (a first chip inductor 201 and a second chip inductor 202) can be used to prepare a voltage regulation module. After the above optimization, the maximum thickness of the voltage regulation module is less than 5 mm; the power supply voltage output by the voltage regulation module passes through the organic adapter board 205, the output capacitor 203, the solder ball 207, the silicon through-hole adapter board 208 in sequence, and finally reaches the AI ​​computing power chip 204. Compared with the traditional power supply method, the power supply distance is significantly shortened, the line loss can be reduced, the amplitude of the voltage dynamic oscillation is reduced, and the dynamic response characteristics of the power supply voltage are improved; and the volume of the entire system is reduced to achieve higher density integration.

[0049] The present invention is applicable to all information chips, including but not limited to CPU, GPU, NPU, HBM, FPGA, etc.; at the same time, the vertical power supply structure of the present invention can simultaneously power multiple information chips in the computing power system. When the power supply demand is large, the number of gallium nitride devices and chip inductors can be increased.

[0050] The present invention significantly reduces the volume of the voltage regulation module by optimizing the layout of gallium nitride devices and the volume of magnetic parts, and can be integrated into the back of the CPU and GPU to realize vertical power supply, shorten the power supply distance, and improve the power supply efficiency and the dynamic response characteristics of the power supply voltage; at the same time, it ensures that the CPU, GPU and other computing power chips can work reliably and stably, and provides underlying technical support for the further development of CPU, GPU and other computing power chips, and promotes the development of technologies in related fields such as artificial intelligence, cloud computing, data centers, and autonomous driving.

[0051] Those skilled in the art will readily appreciate other embodiments of the present invention after considering the specification and disclosure of the invention. This application is intended to cover any variations, uses or adaptations of the present invention that follow the general principles of the present invention and include common knowledge or customary techniques in the art that are not disclosed by the present invention. The specification and examples are to be considered exemplary only, and the true scope and spirit of the present invention are indicated by the following claims.

[0052] It should be understood that the present invention is not limited to the exact construction that has been described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

[0053] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any simple modification, change and equivalent structural change made to the above embodiment based on the technical essence of the present invention still falls within the protection scope of the technical solution of the present invention.

Claims

1. A vertical power supply structure for an AI computing chip, characterized in that: It includes an AI computing chip (204), a through silicon via adapter plate (208), an organic adapter plate (205) and a low-sensitivity gallium nitride module (200); The AI ​​computing chip (204), the through silicon via adapter board (208), the organic adapter board (205) and the low-sensitivity gallium nitride module (200) are sequentially arranged from top to bottom. A plurality of output capacitors (203) are arranged between the organic adapter board (205) and the through silicon via adapter board (208). A first group of solder balls (207) are arranged between adjacent output capacitors (203). A first chip inductor (201) and a second chip inductor (202) are also arranged below the organic adapter board (205). A second group of solder balls (207) are arranged between the first chip inductor (201) and the organic adapter board (205), between the second chip inductor (202) and the organic adapter board (205), and between the low-sensitivity gallium nitride module (200) and the organic adapter board (205).

2. The vertical power supply structure of the AI ​​computing chip according to claim 1 is characterized in that: The low-sensitivity gallium nitride module (200) comprises a fourth conductive layer (107), a fifth conductive layer (108) and a plurality of decoupling capacitors (109); One side of each decoupling capacitor (109) is connected to the fourth conductive layer (107), and the other side of each decoupling capacitor (109) is connected to the fifth conductive layer (108). A first conductive layer (102), a second conductive layer (103), a third conductive layer (104), a first gallium nitride device (100), and a second gallium nitride device (101) are arranged below the decoupling capacitor (109), wherein the first conductive layer (102), the second conductive layer (103), and the third conductive layer (104) are distributed in sequence and located in the same plane, one side of the first gallium nitride device (100) is connected to the third conductive layer (104), the other side of the first gallium nitride device (100) is connected to the second conductive layer (103), one side of the second gallium nitride device (101) is connected to the second conductive layer (103), and the other side of the second gallium nitride device (101) is connected to the first conductive layer (102).

3. The vertical power supply structure of the AI ​​computing chip according to claim 2 is characterized in that: One side of the first conductive layer (102) is a first comb-tooth structure, one side of the second conductive layer (103) is a second comb-tooth structure, the other side of the second conductive layer (103) is a third comb-tooth structure, and one side of the third conductive layer (104) is a fourth comb-tooth structure, wherein the comb teeth in the first comb-tooth structure are arranged alternately with the comb teeth in the second comb-tooth structure, and the comb teeth in the third comb-tooth structure are arranged alternately with the comb teeth in the fourth comb-tooth structure.

4. The vertical power supply structure of the AI ​​computing chip according to claim 3 is characterized in that: It also includes a plurality of first via holes (105) and a plurality of second via holes (106), a decoupling capacitor (109) corresponding to a comb tooth in the first comb-tooth structure, a comb tooth in the fourth comb-tooth structure, a first via hole (105) and a second via hole (106), wherein one side of each decoupling capacitor (109) is connected to a corresponding comb tooth in the first comb-tooth structure via the corresponding first via hole (105), and the other side of each decoupling capacitor (109) is connected to a corresponding comb tooth in the fourth comb-tooth structure via the corresponding second via hole (106).

5. The vertical power supply structure of the AI ​​computing chip according to claim 4 is characterized in that: The current direction of each comb tooth in the first comb tooth structure is opposite to the current direction of each comb tooth in the second comb tooth structure.

6. The vertical power supply structure of the AI ​​computing chip according to claim 5, characterized in that: The current direction of each comb tooth in the third comb-tooth structure is opposite to the current direction of each comb tooth in the fourth comb-tooth structure.

7. The vertical power supply structure of the AI ​​computing chip according to claim 1, characterized in that: The low-inductance gallium nitride module (200), the first chip inductor (201) and the second chip inductor (202) form a voltage regulation module.

8. The vertical power supply structure of the AI ​​computing chip according to claim 7, characterized in that: The thickness of the voltage regulation module is less than or equal to 5 mm.

9. The vertical power supply structure of the AI ​​computing chip according to claim 8, characterized in that: The power supply voltage output by the voltage regulation module passes through the organic adapter board (205), the output capacitor (203), the solder ball (207), the through silicon via adapter board (208) in sequence, and finally reaches the AI ​​computing chip (204).

10. The vertical power supply structure of the AI ​​computing chip according to claim 1, characterized in that: When applied to a high-power AI computing chip (204), multiple gallium nitride devices and multiple chip inductors are integrated on the bottom surface of the organic adapter plate (205).

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