Semiconductor structure and forming method

Abstract

The invention provides a semiconductor structure and a forming method, and the semiconductor structure comprises a substrate, an interconnection structure, a plurality of first contact plugs, and a conductive plug. Wherein the conductive plug penetrates through the substrate and is connected to the interconnection structure through the plurality of first contact plugs; wherein a part of the plurality of first contact plugs are arranged in a concentric ring shape. In this way, the formation process of the conductive plug can be prevented from damaging the interconnection structure and the dielectric medium between the metal layers. In addition, the first contact plugs are arranged in a concentric ring shape, so that the deformation of the first contact plugs and the conductive plugs can be avoided.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] Through Silicon Via (TSV) technology can improve data transmission efficiency, reduce power consumption, and achieve miniaturization and high-density integration. However, there are challenges in the manufacturing process, such as hole filling technology, thermal management and stress issues, and electrical isolation. In addition, it may cause interconnection structure failures, such as bulges, filling voids, and cracking and delamination, which need to be solved during the manufacturing and application process. Summary of the invention

[0003] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same to prevent through-silicon vias from causing failure of the interconnect structure.

[0004] The technical solution of the present disclosure is achieved as follows:

[0005] An embodiment of the present disclosure provides a semiconductor structure, including: a substrate, an interconnect structure, a plurality of first contact plugs and a conductive plug; wherein the conductive plug penetrates the substrate and is connected to the interconnect structure through the plurality of first contact plugs; wherein a portion of the plurality of first contact plugs are arranged in concentric rings.

[0006] In the above solution, another portion of the plurality of first contact plugs are arranged radially.

[0007] In the above scheme, each of the contact plugs includes: a first section, a second section and a third section; wherein the first section is respectively connected to the conductive plug and the second section; the third section is respectively connected to the second section and the interconnection structure; the contact area between the first section and the conductive plug is greater than the contact area between the first section and the second section; the contact area between the third section and the interconnection structure is greater than the contact area between the third section and the second section.

[0008] In the above solution, the hardness of the first contact plug is greater than that of the interconnection structure.

[0009] In the above solution, the semiconductor structure further includes: a first isolation structure; wherein the first isolation structure is located in the substrate and is configured to surround the conductive plug and the contact portions of the plurality of first contact plugs.

[0010] In the above solution, the semiconductor structure further includes: a second isolation structure; wherein the second isolation structure is arranged between the conductive plug and the interconnect structure; wherein the second isolation structure and the plurality of the first contact plugs are at the same level.

[0011] In the above scheme, the semiconductor structure also includes: a plurality of second contact plugs and a microelectronic device; wherein the microelectronic device is connected to the interconnect structure through the plurality of second contact plugs; wherein the second sections of the plurality of second contact plugs and the plurality of first contact plugs are at the same level.

[0012] The embodiment of the present disclosure also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming contact plugs and an interconnection structure on the substrate in sequence; wherein the contact plugs include a plurality of the first contact plugs; a portion of the plurality of the first contact plugs are arranged in concentric rings; forming a through-silicon via in the substrate; wherein the through-silicon via penetrates the substrate and exposes the plurality of the first contact plugs; filling the through-hole to form a conductive plug; wherein the conductive plug penetrates the substrate and is connected to the interconnection structure through the plurality of the first contact plugs.

[0013] In the above scheme, forming the contact plug on the substrate includes: sequentially forming a plurality of first sections, second sections and third sections of the first contact plugs; wherein the first section of each of the first contact plugs is connected to the conductive plug, and the third section of each of the first contact plugs is connected to the interconnect structure; the contact area between the first section and the conductive plug is greater than the contact area between the first section and the second section; and the contact area between the third section and the interconnect structure is greater than the contact area between the third section and the second section.

[0014] In the above scheme, the formation method also includes: before forming the contact plug on the substrate, forming a first isolation structure in the substrate; after forming the second section on the substrate, forming a second isolation structure; wherein the material of the second isolation structure and the metal interlayer dielectric are different; and the dielectric constant of the second isolation structure is smaller than that of the metal interlayer dielectric.

[0015] The embodiment of the present disclosure provides a semiconductor structure, including: a substrate, an interconnection structure, a plurality of first contact plugs and a conductive plug; wherein the conductive plug penetrates the substrate and is connected to the interconnection structure through the plurality of first contact plugs; wherein a portion of the plurality of first contact plugs are arranged in concentric rings. In this way, the conductive plug in the embodiment of the present disclosure only needs to penetrate the substrate to be connected to the interconnection structure, which can avoid the formation process of the conductive plug causing damage to the interconnection structure and the dielectric between the metal layers. In addition, the first contact plugs arranged in concentric rings can evenly distribute stress within the ring, which can avoid deformation of the first contact plug and the conductive plug, and improve the reliability and service life of the connection portion between the first contact plug and the conductive plug. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure Figure 1 ;

[0017] Figure 2 It is a structural schematic diagram of the prior art;

[0018] Figure 3A Schematic diagram of the arrangement structure of the first contact plug provided in the embodiment of the present disclosure Figure 1 ;

[0019] Figure 3B Schematic diagram of the arrangement structure of the first contact plug provided in the embodiment of the present disclosure Figure 2 ;

[0020] Figure 4A Schematic diagram 3 of the arrangement structure of the first contact plug provided in the embodiment of the present disclosure;

[0021] Figure 4B Schematic diagram 4 of the arrangement structure of the first contact plug provided in the embodiment of the present disclosure;

[0022] Figure 5A Schematic diagram 5 of the arrangement structure of the first contact plug provided in the embodiment of the present disclosure;

[0023] Figure 5B Schematic diagram of the arrangement structure of the first contact plug provided in the embodiment of the present disclosure Figure 6 ;

[0024] Figure 6 A schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure Figure 2 ;

[0025] Figure 7 A schematic diagram of the structure of the first contact plug provided in the embodiment of the present disclosure Figure 1 ;

[0026] Figure 8A schematic diagram of the structure of the first contact plug provided in the embodiment of the present disclosure Figure 2 ;

[0027] Fig. 9 A schematic diagram of a process for forming a semiconductor structure provided by an embodiment of the present disclosure;

[0028] Fig. 10A A schematic diagram of a process for forming an interconnect structure according to an embodiment of the present disclosure Figure 1 ;

[0029] Fig. 10B A schematic diagram of a process for forming an interconnect structure according to an embodiment of the present disclosure Figure 2 ;

[0030] Fig. 10C A third structural diagram of the interconnection structure forming process provided by the embodiment of the present disclosure;

[0031] Fig.11A A schematic diagram of a conductive plug forming process according to an embodiment of the present disclosure Figure 1 ;

[0032] Fig. 11B A schematic diagram of a conductive plug forming process according to an embodiment of the present disclosure Figure 2 ;

[0033] Fig. 11C A third structural diagram of a conductive plug forming process provided by an embodiment of the present disclosure;

[0034] Fig. 12A A fourth structural diagram of a conductive plug forming process provided by an embodiment of the present disclosure;

[0035] Fig. 12B Structural schematic diagram 5 of the conductive plug forming process provided by the embodiment of the present disclosure;

[0036] Fig. 12C A schematic diagram of a conductive plug forming process according to an embodiment of the present disclosure Figure 6 ;

[0037] Fig.12D A schematic diagram of a conductive plug forming process according to an embodiment of the present disclosure Figure 7 ;

[0038] Fig.13A A schematic diagram of a contact plug forming process according to an embodiment of the present disclosure Figure 1 ;

[0039] Fig. 13B A schematic diagram of a contact plug forming process according to an embodiment of the present disclosure Figure 2 ;

[0040] Fig. 13C A third structural diagram of a contact plug forming process provided by an embodiment of the present disclosure;

[0041] Fig.14A A fourth structural diagram of a contact plug forming process provided by an embodiment of the present disclosure;

[0042] Fig. 14B Structural schematic diagram 5 of the contact plug forming process provided by the embodiment of the present disclosure;

[0043] Fig.15A A schematic diagram of a contact plug forming process according to an embodiment of the present disclosure Figure 6 ;

[0044] Fig. 15B A schematic diagram of a contact plug forming process according to an embodiment of the present disclosure Figure 7 . DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0046] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0047] If similar descriptions of “first / second” appear in the application documents, the following description is added. In the following description, the terms “first / second / third” involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that “first / second / third” can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0049] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, semiconductor structure, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, semiconductor structure, article or device. In the absence of more restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, semiconductor structure, article or device including the element.

[0050] Figure 1 is a schematic diagram of an optional semiconductor structure 100 provided in an embodiment of the present disclosure, with reference to Figure 1 , the semiconductor structure 100 includes a substrate 10, an interconnect structure (Interconnect) 20, a plurality of first contact plugs (Contact) 30 and a conductive plug 40. The interconnect structure 20 connects the microelectronic devices such as transistors formed on the substrate 10 through the second contact plug 70 to ensure that the microelectronic devices can work normally. The interconnect structure 20 includes a plurality of wirings 23 and a plurality of metal fillings 24. The plurality of wirings 23 are respectively distributed in a plurality of metal layers. The plurality of metal fillings 24 are formed by filling vias (Via) between a plurality of metal layers. The plurality of metal fillings 24 are used to connect the plurality of wirings 23. An intermetallic dielectric (IMD) 21 is provided between each two adjacent metal layers. The barrier layer 22 is used to prevent metal diffusion and oxidation in the process of stacking metal layers layer by layer, and to protect the metal layer to avoid damage to the metal layer caused by the etching process. The conductive plug 40 is formed by filling through silicon vias (TSV). The plurality of first contact plugs 30 are used to connect the interconnect structure 20 to the substrate 10.

[0051] Figure 2 is a schematic diagram of the structure of the conductive plug in the prior art. It should be noted that, referring to Figure 2 In order to reduce the overall thickness of the device, the metal layer of the interconnect structure is usually designed to be thinner, and the closer the metal layer is to the substrate, the thinner it is. In order to avoid the risk of breakdown during the etching process of the through-silicon via, the through-silicon via is usually landed on a metal layer far away from the substrate, for example, in metal layers M6 to M8. However, the etching process of the through-silicon via will cause damage such as cracks and delamination to the interconnect structure and the intermetallic dielectric, thereby affecting the performance of the semiconductor structure. For example, the intermetallic dielectric is usually a porous material with a low dielectric constant. In the etching and filling process of the through-silicon via, it is easy for the filling metal and water vapor in the cleaning process to penetrate into the intermetallic dielectric, affecting the performance of the intermetallic dielectric.

[0052] In the embodiments of the present disclosure, reference Figure 1 , the conductive plug 40 penetrates the substrate 10. The conductive plug 40 is connected to the interconnect structure 20 through the plurality of first contact plugs 30. That is, the embodiment of the present disclosure lands the conductive plug 40 on the plurality of first contact plugs 30. In this way, the conductive plug 40 in the embodiment of the present disclosure only needs to penetrate the substrate 10 to be connected to the interconnect structure 20, and does not need to penetrate the metal layer and the intermetallic dielectric 21. Thus, it is possible to avoid the formation process of the conductive plug 40 from damaging the interconnect structure 20 and the intermetallic dielectric 21.

[0053] It should be noted that the reference Figure 1 The stress concentration at the contact parts of the plurality of first contact plugs 30 and the conductive plugs 40 may lead to uneven pressure distribution between the first contact plugs 30 and the conductive plugs 40. In the area with greater stress, excessive extrusion may occur, causing the contact parts of the first contact plugs 30 and the conductive plugs 40 to undergo structural deformation, sinking, damage, or other collapse phenomena.

[0054] Figure 3A , Figure 4A and Figure 5A is a schematic diagram of an optional arrangement structure of the first contact plugs provided in the embodiment of the present disclosure. It should be noted that: Figure 3A The first contact plug 30a located in the center may be octagonal or octagonal ring. Figure 5A The first contact plug 30f located at the center may be in the shape of a ring or a circle. The first contact plug may also be in the shape of concentric rings of other shapes, which is not limited here.

[0055] In the embodiment of the present disclosure, a portion of the plurality of first contact plugs are arranged in a concentric ring shape. For example, Figure 3A The first contact plugs 30a, 30b and 30c are all octagonal rings and are arranged in concentric rings.

[0056] Figure 4A The first contact plugs 30d and 30e are both quadrangular rings and are arranged in concentric rings.

[0057] Figure 5A The first contact plugs 30f, 30g and 30h are all circular rings and arranged in concentric rings. In this way, the first contact plugs arranged in concentric rings can make the stress evenly distributed in the rings. Therefore, the first contact plugs and the conductive plugs can be prevented from being deformed, thereby improving the reliability and service life of the connection parts of the first contact plugs and the conductive plugs.

[0058] In some embodiments of the present disclosure, another portion of the plurality of first contact plugs is arranged radially. Another portion of the plurality of first contact plugs is connected to the first contact plugs arranged in a concentric ring shape. For example, Figure 3B The four first contact plugs 30i are arranged radially and connect the first contact plugs 30a, 30b and 30c. For another example, Figure 4B The eight first contact plugs 30j are arranged radially, and each first contact plug 30j is connected to the first contact plugs 30d and 30e. For another example, Figure 5B The four first contact plugs 30k are arranged radially and connect the first contact plugs 30f, 30g and 30h. In this way, the first contact plugs arranged radially can better disperse stress, thereby further reducing the risk of damage caused by stress concentration.

[0059] It should be noted that the arrangement of the contact portions of the plurality of first contact plugs and the interconnection structure can refer to Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A and Figure 5B The plurality of first contact plugs may also be arranged radially, or the plurality of first contact plugs may also be arranged concentrically, which is not limited here.

[0060] In some embodiments of the present disclosure, reference Figure 1 , the hardness of the first contact plug 30 is greater than that of the interconnection structure 20. For example, the material of the first contact plug 30 may be tungsten. The material of the interconnection structure 20 may be copper. In this way, the first contact plug 30 has a high hardness, can maintain its own shape, and is less likely to be damaged, thereby effectively preventing problems such as poor connection caused by deformation of the first contact plug 30, and improving the electrical performance and mechanical stability of the contact portion between the conductive plug 40 and the first contact plug 30.

[0061] Figure 6 It is a schematic structural diagram of another optional semiconductor structure 100 provided in an embodiment of the present disclosure.

[0062] In some embodiments of the present disclosure, reference Figure 6 The semiconductor structure 100 further includes a first isolation structure 50. The first isolation structure 50 is located in the substrate 10. For example, the first isolation structure 50 may be a shallow trench isolation (STI).

[0063] In the embodiments of the present disclosure, reference Figure 6, the first isolation structure 50 is configured to surround the contact portion between the conductive plug 40 and the plurality of first contact plugs 30. In this way, when the conductive plug 40 and the plurality of first contact plugs 30 expand or contract, the first isolation structure 50 surrounds the contact portion between the conductive plug 40 and the plurality of first contact plugs 30, and can provide support for the conductive plug 40 and the plurality of first contact plugs 30, and limit the volume change of the two. Thus, the structural damage caused by the mechanical stress between the conductive plug 40 and the plurality of first contact plugs 30 is avoided, and the problems of cracks or delamination are avoided.

[0064] In some embodiments of the present disclosure, reference Figure 6 The semiconductor structure 100 further includes a plurality of second contact plugs 70 and a microelectronic device. The microelectronic device may be one or more of a transistor, a capacitor, a resistor, or the like. The microelectronic device may be formed in the active region 11 of the substrate 10. The microelectronic device is connected to the interconnect structure 20 through the plurality of second contact plugs 70. In other words, the plurality of second contact plugs 70 are used to connect the interconnect structure 20 with microelectronic devices such as transistors formed on the substrate 10.

[0065] In the embodiments of the present disclosure, reference Figure 6 , the plurality of second contact plugs 70 and the plurality of first contact plugs 30 are in the same layer. In this way, the embodiment of the present disclosure can simultaneously form the plurality of first contact plugs 30 during the process of forming the plurality of second contact plugs 70 . Thus, the process can be further simplified.

[0066] Figure 7 is a schematic diagram of the structure of an optional contact plug 30 provided in an embodiment of the present disclosure. It should be noted that: Figure 7 The first contact plugs 30 shown are each formed by filling a through hole. Figure 7 The first contact plug 30 shown may also be implemented by filling a trench, which is not limited here.

[0067] In some embodiments of the present disclosure, reference Figure 7 Each first contact plug 30 includes a first section 31, a second section 32 and a third section 33. The first section 31 is connected to the conductive plug 40 and the second section 32 respectively. The third section 33 is connected to the second section 32 and the interconnection structure 20 respectively.

[0068] In the embodiments of the present disclosure, reference Figure 7, the contact area between the first section 31 and the conductive plug 40 is greater than the contact area between the first section 31 and the second section 32. The contact area between the third section 33 and the interconnect structure 20 is greater than the contact area between the third section and the second section. In this way, the embodiment of the present disclosure can increase the contact area between the first contact plug 30 and the conductive plug 40. Thus, the contact resistance between the first contact plug 30 and the conductive plug 40 can be reduced, the heat generated by excessive contact resistance can be reduced, and the power consumption of the semiconductor structure can be reduced. At the same time, the landing area of ​​the conductive plug 40 is larger, and the local pressure on each first contact plug 30 is smaller, so that the deformation of the first contact plug 30 and the conductive plug 40 can be avoided, and the contact portion between the conductive plug 40 and the first contact plug 30 can be prevented from collapsing.

[0069] Figure 8 is a schematic diagram of another optional contact plug 30 provided in an embodiment of the present disclosure. It should be noted that: Figure 8 The first contact plugs 30 shown are each formed by filling a through hole. Figure 8 The first contact plug 30 shown may also be implemented by filling a trench, which is not limited here.

[0070] In the embodiments of the present disclosure, reference Figure 8 , the contact area between the third section 33 and the interconnect structure 20 is greater than the contact area between the third section 33 and the second section 32. In this way, the embodiment of the present disclosure can increase the contact area between the first contact plug 30 and the interconnect structure 20. Thus, the contact resistance between the first contact plug 30 and the interconnect structure 20 can be reduced, the heat generated due to excessive contact resistance can be reduced, and the power consumption of the semiconductor structure can be reduced.

[0071] In some embodiments of the present disclosure, reference Figure 8 , the semiconductor structure 100 further includes a second isolation structure 60. The second isolation structure 60 may be at the same level as the third sections 33 of the plurality of first contact plugs 30. The dielectric constant of the second isolation structure 60 may be smaller than that of the first isolation structure 50. The second isolation structure 60 is disposed between the conductive plug 40 and the interconnect structure 20. Thus, the second isolation structure 60 can reduce the parasitic capacitance between the conductive plug 40 and the interconnect structure 20.

[0072] Fig. 9 is a schematic flow chart of an optional method for forming a semiconductor structure provided by an embodiment of the present disclosure, which is combined with Fig. 9 The steps shown are explained. Fig. 9 The formation method shown can be used to form the semiconductor structure 100 of any of the above embodiments.

[0073] S101. Provide a substrate.

[0074] S102, forming contact plugs and interconnect structures on the substrate in sequence; wherein the contact plugs include a plurality of first contact plugs; and a portion of the plurality of first contact plugs are arranged in concentric rings.

[0075] Fig. 10A , Fig. 10B and Fig. 10C is an optional structural schematic diagram of a semiconductor structure forming process provided by an embodiment of the present disclosure. It should be noted that: Fig. 10A , Fig. 10B and Fig. 10C All are cross-sectional views. Fig. 10A and Fig. 10B The first contact plug 30 and the second contact plug 70, and the wiring 23 of the interconnection structure are illustrated. Fig. 10C The metal filling 24 of the interconnect structure is illustrated.

[0076] In the embodiments of the present disclosure, reference Fig. 10A The substrate 10 may be a semiconductor substrate; specifically, it may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art, and may also include other substrates containing semiconductor materials, such as a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, a polycrystalline semiconductor layer on an insulating layer, a silicon-germanium substrate, a SiC substrate, etc.

[0077] In the embodiments of the present disclosure, reference Fig. 10A , Fig. 10A The plurality of first contact plugs 30 are Figure 4A The plurality of first contact plugs 30 may also be arranged as shown. Figure 3A , Figure 3B , Figure 4B , Figure 5A and Figure 5B The arrangement can be performed as shown in any one of the above, without limitation.

[0078] In the present disclosure, Fig. 10A and Fig. 10BAfter forming the first contact plug 30 and the second contact plug 70 on the substrate, a metal layer M0 is deposited, and the metal layer M0 is etched to form a wiring 23 corresponding to the metal layer M0. Then, a barrier layer 22 and an intermetallic dielectric 21 are sequentially deposited on the metal layer M0, and the barrier layer 22 and the intermetallic dielectric 21 are etched by dry etching or wet etching technology to form a plurality of through holes 25. The material of the barrier layer 22 may be a material such as silicon carbon nitride (SiCN). The material of the intermetallic dielectric 21 may be a material such as silicon dioxide (SiO2). The material of the metal layer M0 may be a metal material such as copper (Cu). The barrier layer 22 and the intermetallic dielectric 21 may be formed on the metal layer M0 by processes such as plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD). The wiring 23 may first be exposed and developed by photoresist to determine the direction, and then transferred by a hard mask (Hard Mask), providing a template for its processing to achieve accurate construction and arrangement.

[0079] In the present disclosure, Fig. 10B and Fig. 10C , using copper (Cu) and other metal materials to fill Fig. 10B The through hole 25 shown in FIG. Fig. 10B The metal filling 24 is shown. Then, according to Fig. 10A , Fig. 10B and Fig. 10C The method shown gradually forms Figure 1 or Figure 6 An interconnect structure 20 is shown.

[0080] Fig. 10A , Fig. 10B and Fig. 10C Only the wiring on the metal layer M0 and the metal filling connecting the wiring on the metal layer M0 are illustrated. The formation process of the remaining wiring and metal filling of the interconnect structure can refer to Fig. 10A , Fig. 10B and Fig. 10C Please understand and I will not elaborate on it here.

[0081] S103 , forming a through silicon via in the substrate; wherein the through silicon via penetrates the substrate and exposes a plurality of first contact plugs.

[0082] S104, filling the through silicon via to form a conductive plug; wherein the conductive plug penetrates the substrate and is connected to the interconnect structure through a plurality of first contact plugs.

[0083] Fig.11A , Fig. 11B and Fig. 11C is an optional structural schematic diagram of a semiconductor structure forming process provided by an embodiment of the present disclosure. It should be noted that: Fig.11A , Fig. 11Band Fig. 11C All are cross-sectional views, with examples showing Figure 1 The steps of forming the conductive plug 40 in the semiconductor structure 100 are shown in FIG. Fig. 11B The through silicon via 42a and the sidewall insulating layer 41a in the intermediate state are illustrated. Fig. 11C The example shows a through silicon via 42 and a sidewall insulating layer 41. The sidewall insulating layer 41 can prevent leakage between the filling material (such as copper) of the through silicon via and the substrate 10. The material of the sidewall insulating layer 41 can be an insulating material such as silicon dioxide (SiO2).

[0084] In the embodiments of the present disclosure, reference Fig.11A and Fig. 11B , a protective layer 43a is formed on the second surface of the substrate 10, and the protective layer 43a prevents damage to the second surface of the substrate 10. The protective layer 43a can be an insulating material such as silicon dioxide (SiO2). The protective layer 43a can be transferred Figure 1 After etching to a certain depth along the protection layer 43a, a through silicon via 42a in an intermediate state is formed.

[0085] Then, an insulating material such as silicon dioxide (SiO2) is deposited on the sidewall of the through silicon via 42a in the intermediate state by a process such as chemical vapor deposition to form a Fig. 11B The sidewall insulating layer 41a in the intermediate state is shown. Etching is continued along the protective layer 43a until the first contact plug 30 is exposed, forming a Fig. 11C The sidewall insulating layer 41 and the final through silicon via 42 are shown. Then, a metal material (such as copper) is used to fill the through silicon via 42 to form a Figure 1 The conductive plug 40 is shown.

[0086] It can be understood that the conductive plug 40 in the embodiment of the present disclosure only needs to penetrate the substrate 10 to connect to the interconnect structure 20, and does not need to penetrate the metal layer and the intermetallic dielectric 21. Therefore, it is possible to avoid the formation process of the conductive plug 40 from damaging the interconnect structure 20 and the intermetallic dielectric 21. In addition, the first contact plugs arranged in concentric rings can make the stress evenly distributed within the ring. Therefore, it is possible to avoid deformation of the first contact plug and the conductive plug, thereby improving the reliability and service life of the connection portion of the first contact plug and the conductive plug.

[0087] Fig. 12A , Fig. 12B , Fig. 12C and Fig.12D is an optional structural schematic diagram of a semiconductor structure forming process provided by an embodiment of the present disclosure. It should be noted that: Fig. 12A , Fig. 12B , Fig. 12C and Fig.12DAll are cross-sectional views, with examples showing Figure 6 The steps of forming the conductive plug 40 in the semiconductor structure 100 are shown.

[0088] In the present disclosure, Fig. 12A and Fig. 12B , a protective layer 43b is formed along the second surface of the substrate 10 and etched until the first isolation structure 50 is exposed, thereby forming an intermediate through silicon via 42b. Then, an intermediate sidewall insulating layer 41b is deposited on the sidewall of the intermediate through silicon via 42b. Finally, the first isolation structure 50 is further etched along the protective layer 43c until the first contact plug 30 is exposed, thereby forming a through silicon via 42b. Fig. 12C The sidewall insulating layer 41 and the through silicon via 42 are shown.

[0089] In the present disclosure, Fig. 12C and Fig.12D , a metal material (such as copper) is used to fill the through silicon via 42 to form a Fig.12D Then, the conductive plug 40a in the intermediate state is subjected to chemical mechanical polishing (CMP) to form a conductive plug 40a in the intermediate state. Figure 6 The conductive plug 40 is shown.

[0090] In some embodiments of the present disclosure, S201 can be implemented Fig. 9 S102 shown will be described in conjunction with each step.

[0091] S201, sequentially forming a first section, a second section and a third section of a plurality of first contact plugs; wherein the first section of each first contact plug is connected to a conductive plug, and the third section of each first contact plug is connected to an interconnection structure; and a contact area between the first section and the conductive plug is greater than a contact area between the first section and the second section.

[0092] Fig.13A , Fig. 13B and Fig. 13C is an optional structural schematic diagram of a semiconductor structure forming process provided by an embodiment of the present disclosure. It should be noted that: Fig.13A , Fig. 13B and Fig. 13C All are cross-sectional views, with examples showing Figure 7 The step of forming the first contact plug 30 is shown in FIG. Fig.13A The first section 31 of the first contact plug 30 is illustrated. Fig. 13B The second section 32 of the first contact plug 30 is illustrated. Fig. 13C The third section 33 of the first contact plug 30 is illustrated.

[0093] In the embodiments of the present disclosure, reference Fig.13A, the sacrificial layer 21b transfers the pattern of the hard mask forming the contact plug. In the process of etching along the sacrificial layer 21b, different shapes of through holes or grooves are formed on the first isolation structure 50 and the substrate 10 respectively by utilizing the different materials of the first isolation structure 50 and the substrate 10. Then, a metal material (such as tungsten) is used to fill the through hole or the groove to form the first section 70a of the second contact plug and the first section 31 of the first contact plug. For example, the etching solution for forming the through hole or the groove can be hydrofluoric acid (HF). The material of the first isolation structure 50 can be silicon dioxide. The cross section of the first section 70a of the second contact plug is rectangular, and the cross section of the first section 31 of the first contact plug is an inverted trapezoid.

[0094] In the present disclosure, Fig.13A and Fig. 13B A sacrificial layer 21c is formed on the sacrificial layer 21b. The sacrificial layer 21c transfers the pattern of the hard mask for forming the contact plug. A through hole or trench of the sacrificial layer 21c is filled with a metal material (such as tungsten) to form a Fig. 13B The second section 70b of the second contact plug and the second section 32 of the first contact plug are shown. The second section 70b of the second contact plug and the second section 32 of the first contact plug both have rectangular cross sections.

[0095] In the present disclosure, Fig. 13B and Fig. 13C A sacrificial layer 21d is formed on the sacrificial layer 21c. The sacrificial layer 21d transfers the pattern of the hard mask for forming the contact plug. The through hole or trench of the sacrificial layer 21d is filled with a metal material (such as tungsten) to form a Fig. 13C The third section 70c of the second contact plug and the third section 33 of the first contact plug are shown. The third section 70c of the second contact plug and the third section 33 of the first contact plug both have rectangular cross sections.

[0096] It should be noted that, combined with Fig.13A and Fig. 13C , the disclosed embodiments can also be Fig.13A Only one deposition and one etching operation are performed on the sacrificial layer 21b to form sacrificial layers 21c and 21d. Thus, the embodiment of the present disclosure can simultaneously form the second section 32 and the third section 33 of the first contact plug, and the second section 70b and the third section 70c of the second contact plug.

[0097] Fig.14A and Fig. 14B is an optional structural schematic diagram of a semiconductor structure forming process provided by an embodiment of the present disclosure. It should be noted that: Fig.14A and Fig. 14B All are cross-sectional views. Fig.14A The first section 31 of the first contact plug 30 is illustrated. Fig. 14B The second section 32 of the first contact plug 30 is illustrated.

[0098] In the present disclosure, Fig.14A and Fig. 14B , the embodiments of the present disclosure can be implemented according to Fig.14A In the manner shown in FIG. 1 , the first section 31 of the first contact plug 30 is formed. Then, a sacrificial layer 21e is deposited to transfer the pattern of the hard mask for forming the contact plug. Finally, a metal material (such as tungsten) is used to fill the through hole or trench of the sacrificial layer 21e to form a Fig. 14B The second contact plug 70 and the remaining section 30a of the first contact plug are shown. The remaining section 30a can refer to Fig. 13C The second section 32 and the third section 33 in the sacrificial layer 21e are understood as the difference in the materials of the substrate 10 and the first section 31. During the etching of the through hole or the groove of the sacrificial layer 21e, the groove portion of the second contact plug 70 is formed in the second substrate 10, thereby ensuring that the second contact plug 70 can be connected to the substrate 10. In this way, the embodiment of the present disclosure can simplify the formation process of the contact plug.

[0099] In some embodiments of the present disclosure, the method for forming a semiconductor structure may be implemented through S301 and S302 , which will be described in conjunction with each step.

[0100] S301 , before forming a contact plug on a substrate, forming a first isolation structure in the substrate.

[0101] In the embodiments of the present disclosure, reference Fig.13A Before forming the contact plug on the substrate 10, a first isolation structure 50 is formed in the substrate 10. In this way, the embodiment of the present disclosure can utilize the difference in the materials of the first isolation structure 50 and the substrate 10 to form through holes or trenches of different shapes on the first isolation structure 50 and the substrate 10. Thus, the first section 31 of the first contact plug can be formed into a regular trapezoidal structure, etc., to increase the contact area between the first contact plug and the conductive plug.

[0102] S302 , after forming the second section on the substrate, forming a second isolation structure; wherein the second isolation structure and the metal interlayer dielectric are made of different materials; and the dielectric constant of the second isolation structure is smaller than that of the metal interlayer dielectric.

[0103] Fig.15A and Fig. 15B is an optional structural schematic diagram of a semiconductor structure forming process provided by an embodiment of the present disclosure. It should be noted that: Fig.15A and Fig. 15B All are cross-sectional views, with examples showing Figure 8 The step of forming the first contact plug 30 is shown in FIG. Fig.15AThe second isolation structure 60 is illustrated. Fig. 15B The third section 33 of the first contact plug 30 is illustrated.

[0104] In the present disclosure, Fig. 13B and Fig.15A After forming the second section 32 of the first contact plug, a sacrificial layer 21f may be formed. The sacrificial layer 21f transfers the pattern of the conductive plug 40. Then, the groove of the sacrificial layer 21f is filled to form a second isolation structure 60. In this way, the embodiment of the present disclosure can utilize the difference in the materials of the second isolation structure 60 and the sacrificial layer 21f (i.e., the intermetallic dielectric) to form through holes or grooves of different shapes on the second isolation structure 60 and the sacrificial layer 21f, respectively.

[0105] In the present disclosure, Fig.15A and Fig. 15B , utilizing the difference in the materials of the sacrificial layer 21f and the second isolation structure 60, through holes or grooves of different shapes are formed on the sacrificial layer 21f and the second isolation structure 60, respectively. Then, a metal material (such as tungsten) is used to fill the through hole or groove to form the third section 70c of the second contact plug and the third section 33 of the first contact plug. For example, the etching solution for forming the through hole or groove may be hydrofluoric acid (HF). The material of the sacrificial layer 21f may be silicon dioxide. The material of the second isolation structure 60 may be silicon nitride. The cross section of the third section 33 of the first contact plug is a regular trapezoid. In this way, the contact area between the third section 33 and the interconnection structure 20 is greater than the contact area between the third section 33 and the second section 32. Thus, the third section 32 of the first contact plug can be formed into a structure such as an inverted trapezoid, thereby increasing the contact area between the first contact plug and the interconnection structure.

[0106] The above description of the formation method is similar to the description of the above semiconductor structure embodiment, and has similar beneficial effects as the semiconductor structure embodiment. For technical details not disclosed in the formation method embodiment of the present disclosure, please refer to the description of the semiconductor structure embodiment of the present disclosure for understanding.

[0107] It should be noted that in the present disclosure, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, semiconductor structure, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, semiconductor structure, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, semiconductor structure, article or device including the element.

[0108] The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments. The semiconductor structures disclosed in the several semiconductor structure embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new semiconductor structure embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several semiconductor structure or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new semiconductor structure embodiments or device embodiments.

[0109] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, an interconnect structure, a plurality of first contact plugs and a conductive plug; wherein, The conductive plug penetrates the substrate and is connected to the interconnect structure through a plurality of the first contact plugs; wherein a portion of the plurality of the first contact plugs are arranged in a concentric ring shape.

2. The semiconductor structure according to claim 1, characterized in that: Another portion of the plurality of first contact plugs are arranged radially.

3. The semiconductor structure according to claim 1 or 2, characterized in that: Each of the contact plugs comprises: a first section, a second section and a third section; wherein, The first section is connected to the conductive plug and the second section respectively; The third section is connected to the second section and the interconnection structure respectively; The contact area between the first section and the conductive plug is greater than the contact area between the first section and the second section; A contact area between the third section and the interconnection structure is greater than a contact area between the third section and the second section.

4. The semiconductor structure according to claim 1, characterized in that: The first contact plug has a harderness than that of the interconnect structure.

5. The semiconductor structure according to claim 3, characterized in that: Also includes: A first isolation structure; wherein, The first isolation structure is located in the substrate and is configured to surround the conductive plug and contact portions of the first contact plugs.

6. The semiconductor structure according to claim 3, characterized in that: Also includes: The second isolation structure; wherein, The second isolation structure is disposed between the conductive plug and the interconnect structure; wherein the second isolation structure and the first contact plugs are at the same level.

7. The semiconductor structure according to claim 3, characterized in that: Also includes: A plurality of second contact plugs and a microelectronic device; wherein, The microelectronic device is connected to the interconnect structure through a plurality of the second contact plugs; wherein, The second plurality of contact plugs and the second sections of the first plurality of contact plugs are in the same level.

8. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; A contact plug and an interconnect structure are sequentially formed on the substrate; wherein the contact plug comprises a plurality of first contact plugs; a portion of the plurality of first contact plugs are arranged in a concentric ring shape; forming a through silicon via in the substrate; wherein the through silicon via penetrates the substrate and exposes the plurality of first contact plugs; The through hole is filled to form a conductive plug, wherein the conductive plug passes through the substrate and is connected to the interconnect structure through a plurality of the first contact plugs.

9. The forming method according to claim 8, characterized in that: Forming the contact plug on the substrate includes: A plurality of first sections, second sections and third sections of the first contact plugs are formed in sequence; wherein the first section of each of the first contact plugs is connected to the conductive plug, and the third section of each of the first contact plugs is connected to the interconnect structure; and a contact area between the first section and the conductive plug is greater than a contact area between the first section and the second section.

10. The forming method according to claim 9, characterized in that: The forming method further comprises: Before forming the contact plug on the substrate, forming a first isolation structure in the substrate; After forming the second section on the substrate, a second isolation structure is formed; wherein the second isolation structure and the intermetallic dielectric are made of different materials; and the dielectric constant of the second isolation structure is smaller than that of the intermetallic dielectric.

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