Flower-shaped VCSEL chip and preparation method thereof

Abstract

The present invention discloses a flower-shaped VCSEL chip and a preparation method thereof, which relates to the technical field of VCSEL chips, and aims to solve the problem that the structures of the current VCSEL chips are basically the same, but the same structure and shape are not conducive to the current injection efficiency in the VCSEL chips, and the overall working efficiency is reduced. The key points of the technical solution are as follows: the N-type substrate is fixedly connected to the upper end of the N-type substrate with a buffer layer, the upper end of the buffer layer is fixedly connected to an N-DBR layer, the upper end of the N-DBR layer is fixedly connected to an N-type doping layer, the upper end of the N-type doping layer is fixedly connected to an active region layer, the upper end of the active region layer is fixedly connected to a P-type doping layer, the upper end of the P-type doping layer is fixedly connected to an oxidized aperture layer, the upper end of the oxidized aperture layer is fixedly connected to a P-DBR layer, and the upper end of the P-DBR layer is fixedly connected to an ohmic contact layer. The electrodes are independent of each other, and the current and working sequence of each electrode can be regulated.

Description

Technical Field

[0001] The present invention relates to the technical field of VCSEL chips, and in particular to a flower-shaped VCSEL chip and a preparation method thereof. Background Art

[0002] Vertical-Cavity Surface-Emitting Laser (VCSEL) is a semiconductor that emits laser perpendicular to the top surface. It is different from edge-emitting lasers that are generally manufactured using a cut independent chip process and emit laser from the edge.

[0003] VCSELs have many advantages over edge-emitting lasers in the manufacturing process. Edge-emitting lasers need to be tested after they are manufactured. If an edge-emitting laser fails to work, whether due to poor contact or poor quality of material growth, it will waste the processing time of the manufacturing process and material processing. However, VCSELs can be tested and troubleshooted at any time during the manufacturing process. Because the laser of VCSELs is emitted perpendicular to the reaction area, as opposed to parallel to the reaction area of ​​edge-emitting lasers, tens of thousands of VCSELs can be processed simultaneously on a three-inch gallium arsenide chip. In addition, even though VCSELs require more labor and finer materials in the manufacturing process, the production results are controllable and more predictable.

[0004] A combined VCSEL chip with application number CN202010598726.5 includes a first VCSEL chip, the first VCSEL chip and a second VCSEL chip, the first VCSEL chip and the second VCSEL chip are arranged back to back so that the laser emission direction of the first VCSEL chip is opposite to the laser emission direction of the second VCSEL chip, and the first VCSEL chip and the second VCSEL chip share a negative conductive layer. In this way, the combined VCSEL chip integrates different types of VCSEL chips at the structural level, has the advantages of different types of VCSEL chips, and has a relatively small thickness.

[0005] The above-mentioned prior art solutions have the following defects: the structures of current VCSEL chips are basically the same, but the same structure and shape are not conducive to the current injection efficiency in the VCSEL chip, thereby reducing the overall working efficiency. Summary of the invention

[0006] The purpose of the present invention is to provide a flower-shaped VCSEL chip and a preparation method thereof.

[0007] To achieve the above object, the present invention provides the following technical solutions: A flower-shaped VCSEL chip comprises an N-type substrate, a buffer layer, an N-DBR layer, an N-type doped layer, an active region layer, a P-type doped layer, an oxidized aperture layer, a P-DBR layer and an ohmic contact layer, wherein the upper end of the N-type substrate is fixedly connected with the buffer layer, the upper end of the buffer layer is fixedly connected with the N-DBR layer, the upper end of the N-DBR layer is fixedly connected with the N-type doped layer, the upper end of the N-type doped layer is fixedly connected with the active region layer, the upper end of the active region layer is fixedly connected with the P-type doped layer, the upper end of the P-type doped layer is fixedly connected with the oxidized aperture layer, the upper end of the oxidized aperture layer is fixedly connected with the P-DBR layer, and the upper end of the P-DBR layer is fixedly connected with the ohmic contact layer.

[0008] Furthermore, an N-electrode is fixedly connected to the upper end of the N-type substrate, and the N-electrode is located outside the buffer layer.

[0009] Furthermore, a P electrode is fixedly connected to the upper end of the ohmic contact layer.

[0010] Furthermore, the P-type doped layer, the oxidized aperture layer, the P-DBR layer and the ohmic contact layer are petal-shaped pillar structures, and the number of the petal-shaped P-type doped layer, the oxidized aperture layer, the P-DBR layer and the ohmic contact layer is greater than or equal to one.

[0011] Furthermore, the P electrode is adapted in shape and size to the P-type doping layer, the oxidized aperture layer, the P-DBR layer and the ohmic contact layer, and the P electrode is a drop-shaped structure with decreasing size from the outside to the inside, and each P electrode is independent of each other.

[0012] Furthermore, a method for preparing a flower-shaped VCSEL chip is as follows: S1: Provide N-type substrate; S2: sequentially growing a buffer layer, an N-DBR layer, an N-type doped layer, an active region layer, a P-type doped layer, an oxidized aperture layer, a P-DBR layer and an ohmic contact layer on an N-type substrate; S3: using an etching method to etch out a first circular pillar, etching from the ohmic contact layer to the P-type doping layer; S4: The oxidized aperture layer is oxidized from the outside to the inside by a wet oxidation method, and finally an aperture with a diameter of 3 to 10 um is left in the center of the first circular column.

[0013] S5: using photoresist or silicon oxide, silicon nitride, aluminum oxide and other media as a mask to shield the central area of ​​the first circular pillar, with a shielding range of 10um to 20um in diameter, exposing the outer area of ​​the first circular pillar, and using ion implantation and other methods to form a high resistance area in the area; S6: using an etching method to etch a second flower-shaped pillar on the basis of the first circular pillar, the etching depth being the same as that of the first circular pillar; S7: using an etching method, etching a third circular pillar outside the first circular pillar and the second flower-shaped pillar, the etching depth being from the ohmic contact layer 9 to the P-DBR layer 8 or the N-type substrate 1 layer; S8: Grow a dielectric film, open an electrode window, and produce a P-type electrode and an N-type electrode.

[0014] In summary, the beneficial technical effects of the present invention are: 1. While ensuring the normal luminescence performance of the VCSEL chip, the present invention improves the current injection efficiency, reduces the parasitic capacitance and parasitic resistance, and provides a transverse coupling cavity to achieve optical-optical resonance, thereby improving the modulation bandwidth of the VCSEL chip; 2. The present invention has multiple P electrodes, each of which is independent of each other, and can bring richer application scenarios to the VCSEL chip by regulating the current and working timing of each electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of the three-dimensional structure of the present invention; Figure 2 It is a schematic diagram of the cross-sectional structure of the present invention.

[0016] In the figure, 1, N-type substrate; 2, buffer layer; 3, N-DBR layer; 4, N-type doped layer; 5, active area layer; 6, P-type doped layer; 7, oxide aperture layer; 8, P-DBR layer; 9, ohmic contact layer; 10, N electrode; 11, P electrode. DETAILED DESCRIPTION

[0017] The present invention is further described in detail below in conjunction with the accompanying drawings.

[0018] Reference Figure 1 and Figure 2 A flower-shaped VCSEL chip comprises an N-type substrate 1, a buffer layer 2, an N-DBR layer 3, an N-type doped layer 4, an active region layer 5, a P-type doped layer 6, an oxidized aperture layer 7, a P-DBR layer 8 and an ohmic contact layer 9, wherein the upper end of the N-type substrate 1 is fixedly connected with the buffer layer 2, the upper end of the buffer layer 2 is fixedly connected with the N-DBR layer 3, the upper end of the N-DBR layer 3 is fixedly connected with the N-type doped layer 4, the upper end of the N-type doped layer 4 is fixedly connected with the active region layer 5, and the active region layer 5 is fixedly connected with the active region layer 5. The upper end is fixedly connected to a P-type doped layer 6, the upper end of the P-type doped layer 6 is fixedly connected to an oxidized aperture layer 7, the upper end of the oxidized aperture layer 7 is fixedly connected to a P-DBR layer 8, and the upper end of the P-DBR layer 8 is fixedly connected to an ohmic contact layer 9. The material is etched from the top to the P-type doped layer 6 in one step, and then oxidation and ion implantation processes are performed. Then, the outer area of ​​the pillar is etched into a petal shape, and a P electrode 11 is made on each petal. The size of each electrode gradually decreases from the outside to the inside of the petal.

[0019] Reference Figure 2 The upper end of the N-type substrate 1 is fixedly connected with an N-electrode 10, and the N-electrode 10 is located outside the buffer layer 2. The upper end of the ohmic contact layer 9 is fixedly connected with a P-electrode 11. The P-type doped layer 6, the oxidized aperture layer 7, the P-DBR layer 8 and the ohmic contact layer 9 are petal-shaped pillar structures, and the number of the petal-shaped P-type doped layer 6, the oxidized aperture layer 7, the P-DBR layer 8 and the ohmic contact layer 9 is greater than or equal to 3. The P-electrode 11 is adapted to the shape and size of the P-type doped layer 6, the oxidized aperture layer 7, the P-DBR layer 8 and the ohmic contact layer 9, and the P-electrode 11 is a water drop-shaped structure with a decreasing size from the outside to the inside, and each P-electrode 11 is independent of each other. While ensuring the normal light-emitting performance of the VCSEL chip, the current injection efficiency is improved, the parasitic capacitance and the parasitic resistance are reduced, and a lateral coupling cavity is provided to realize optical-optical resonance, thereby improving the modulation bandwidth of the VCSEL chip. Moreover, each electrode is independent of each other, and can bring more abundant application scenarios to the VCSEL chip by regulating the current and working sequence of each electrode.

[0020] Working principle: First, an N-type substrate 1 is provided, and then a buffer layer 2, an N-DBR layer 3, an N-type doped layer 4, an active region layer 5, a P-type doped layer 6, an oxidized aperture layer 7, a P-DBR layer 8 and an ohmic contact layer 9 are grown on the N-type substrate 1 in sequence, and the first circular pillar is etched out by etching from the ohmic contact layer 9 to the P-type doped layer 6, and then the oxidized aperture layer 7 is oxidized from the outside to the inside by wet oxidation, and finally an aperture with a diameter of 3~10um is left in the center of the first circular pillar, and a photoresist or a medium such as silicon oxide, silicon nitride, or aluminum oxide is used as a mask to shield the first circular pillar. The central area of ​​a circular pillar has a shielding range of 10um~20um in diameter, exposing the outer area of ​​the first circular pillar, and using ion implantation and other methods to form a high resistance area in this area, and then using the etching method to etch a second flower-shaped pillar on the basis of the first circular pillar, the etching depth is the same as the first circular pillar, and then using the etching method, a third circular pillar is etched outside the first circular pillar and the second flower-shaped pillar, and the etching depth is from the ohmic contact layer 9 to the P-DBR layer 8 or the N-type substrate 1 layer, and finally a dielectric film is grown, an electrode window is opened, and a P-type electrode and an N-type electrode are produced.

[0021] The embodiments of this specific implementation method are all preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Therefore, all equivalent changes made based on the structure, shape, and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A flower-shaped VCSEL chip, comprising an N-type substrate (1), a buffer layer (2), an N-DBR layer (3), an N-type doping layer (4), an active region layer (5), a P-type doping layer (6), an oxidized aperture layer (7), a P-DBR layer (8) and an ohmic contact layer (9), characterized in that: The upper end of the N-type substrate (1) is fixedly connected to a buffer layer (2), the upper end of the buffer layer (2) is fixedly connected to an N-DBR layer (3), the upper end of the N-DBR layer (3) is fixedly connected to an N-type doping layer (4), the upper end of the N-type doping layer (4) is fixedly connected to an active region layer (5), the upper end of the active region layer (5) is fixedly connected to a P-type doping layer (6), the upper end of the P-type doping layer (6) is fixedly connected to an oxidized aperture layer (7), the upper end of the oxidized aperture layer (7) is fixedly connected to a P-DBR layer (8), and the upper end of the P-DBR layer (8) is fixedly connected to an ohmic contact layer (9).

2. The flower-shaped VCSEL chip according to claim 1, characterized in that: An N-electrode (10) is fixedly connected to the upper end of the N-type substrate (1), and the N-electrode (10) is located outside the buffer layer (2).

3. The flower-shaped VCSEL chip according to claim 2, characterized in that: The upper end of the ohmic contact layer (9) is fixedly connected to a P electrode (11).

4. The flower-shaped VCSEL chip according to claim 3, characterized in that: The P-type doped layer (6), the oxidized aperture layer (7), the P-DBR layer (8) and the ohmic contact layer (9) are petal-shaped pillar structures, and the number of the petal-shaped P-type doped layer (6), the oxidized aperture layer (7), the P-DBR layer (8) and the ohmic contact layer (9) is greater than or equal to three.

5. The flower-shaped VCSEL chip according to claim 4, characterized in that: The P electrode (11) is adapted in shape and size to the P-type doping layer (6), the oxidized aperture layer (7), the P-DBR layer (8) and the ohmic contact layer (9), and the P electrode (11) is a water droplet-shaped structure with a decreasing size from the outside to the inside, and each P electrode (11) is independent of each other.

6. The method for preparing a flower-shaped VCSEL chip according to claim 5, characterized in that: The method is as follows: S1: providing an N-type substrate (1); S2: sequentially growing a buffer layer (2), an N-DBR layer (3), an N-type doping layer (4), an active region layer (5), a P-type doping layer (6), an oxidized aperture layer (7), a P-DBR layer (8), and an ohmic contact layer (9) on an N-type substrate (1); S3: using an etching method to etch out a first circular pillar, etching from the ohmic contact layer (9) to the P-type doped layer (6); S4: using a wet oxidation method, oxidizing the oxidized aperture layer (7) from the outside to the inside, and finally leaving an aperture with a diameter of 3-10 um in the center of the first circular pillar; S5: using photoresist or silicon oxide, silicon nitride, aluminum oxide and other media as a mask to shield the central area of ​​the first circular pillar, with a shielding range of 10um to 20um in diameter, exposing the outer area of ​​the first circular pillar, and using ion implantation and other methods to form a high resistance area in the area; S6: using an etching method to etch a second flower-shaped pillar on the basis of the first circular pillar, the etching depth being the same as that of the first circular pillar; S7: using an etching method, etching a third circular pillar outside the first circular pillar and the second flower-shaped pillar, wherein the etching depth is from the ohmic contact layer (9) to the P-DBR layer (8) or the N-type substrate (1) layer; S8: Grow a dielectric film, open an electrode window, and produce a P-type electrode and an N-type electrode.

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