Short-circuit protection circuit

Abstract

The invention relates to a short-circuit protection circuit. The short-circuit protection circuit comprises a comparator, an One-Shot Trigger 1, an One-Shot Trigger 2, an One-Shot Trigger 3, a D trigger 1, an RS trigger 1, a Hiccup Timing, an OR gate 1, an OR gate 2, an AND gate 1, an AND gate 2, a phase inverter 1, a Delay 1 and a SoftStartCircuit which are integrated on a PCB (Printed Circuit Board), two input ends of the comparator are respectively connected with a 250mV reference voltage and an output feedback voltage VFB, an input end of the SoftStartCircuit is connected with an output end of the AND gate 2, and an input end of the AND gate 2 is connected with a chip enable end EN and an output signal SCPCTR of the RS trigger 1. An output feedback voltage VFB is compared with a set short-circuit reference voltage 250mV through a comparator, if the output feedback voltage VFB is reduced to 250mV, the circuit is in a short-circuit state, a short-circuit protection mechanism is triggered, a time control module Delay1 can generate a 170us shutdown signal SCPCTR, and the signal controls the circuit to enter an intermittent working mode so as to prevent damage caused by continuous short circuit, so that the service life of the circuit is prolonged, and the service life of the circuit is prolonged. Compared with the prior art, the power consumption is reduced, the chip area is saved, and stable starting is achieved.

Description

Technical Field

[0001] The invention relates to the technical field of short circuit protection, and in particular to a short circuit protection circuit. Background Art

[0002] In recent years, with the rapid development of portable, wearable devices and IoT terminals, the market has put forward higher requirements for the efficiency, safety, reliability and stability of power supply systems. As a result, the demand for short-circuit protection circuits in power supply systems has greatly increased. Traditional short-circuit protection circuits may increase additional power consumption during detection and response, resulting in low efficiency. At the same time, traditional short-circuit protection circuits may require additional external components, such as detection resistors and amplifiers, to achieve complete protection functions. Soft start and protection are often independent modules, which will increase the area of ​​PCB and are not conducive to the integration and miniaturization of the entire system. In addition, traditional soft start circuits cannot achieve smooth system startup. Traditional soft start circuits usually gradually increase the output voltage linearly when the circuit is turned on, but when a short circuit occurs, the recovery process may directly trigger full power operation, resulting in overshoot or unstable startup. At the same time, traditional soft start circuits cannot determine whether the short circuit has been removed, which may easily cause the system to try to start when the short circuit has not been completely eliminated, resulting in oscillation or failure. In addition, in the case of a short circuit, traditional circuits may continue to maintain high current output or switch frequently, which will put a heavy burden on power components and make the startup process unstable. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a short circuit protection circuit to overcome the deficiencies in the above-mentioned prior art.

[0004] The technical solution of the present invention to solve the above technical problem is as follows: a short circuit protection circuit, comprising a comparator, One-Shot Trigger1, One-Shot Trigger2, One-Shot Trigger3, D trigger 1, RS trigger 1, Hiccup Timing, OR gate 1, OR gate 2, AND gate 1, AND gate 2, inverter 1, Delay1 and Soft_Start_Circuit integrated on a PCB board;

[0005] The two input terminals of the comparator are connected to the 250mV reference voltage and the output feedback voltage V FB, the output of the comparator is connected to the input of One-Shot Trigger2, the output of One-Shot Trigger2 is connected to an input of OR Gate 2, the output of OR Gate 2 is connected to the S of RS Trigger 1, the Q of RS Trigger 1 is connected to the ENP of Hiccup Timing; the R of RS Trigger 1 is connected to the output of OR Gate 1, one input of OR Gate 1 is connected to the chip enable EN through One-Shot Trigger1; the other input of OR Gate 2 is connected to the output of Delay1 through One-Shot Trigger3, the input of Delay1 is connected to the Q of D Trigger 1, the CP of D Trigger 1 is connected to the output of Soft_Start_Circuit;

[0006] The CLR terminal of D flip-flop 1 is connected to the output terminal of AND gate 1, one input terminal of AND gate 1 is connected to the chip enable terminal EN, the other input terminal of AND gate 1 is connected to the output terminal of inverter 1, the input terminal of inverter is connected to the output terminal of Hiccup Timing and the other input terminal of OR gate 1;

[0007] The input end of Soft_Start_Circuit is connected to the output end of AND gate 2, and the input end of AND gate 2 is connected to the chip enable end EN and the output signal SCP_CTR of RS trigger 1.

[0008] Based on the above technical solution, the present invention can also be improved as follows.

[0009] Furthermore, AND gate 2 is a five-input AND gate circuit, and the five input terminals of AND gate 2 are respectively:

[0010] Bandgap hysteresis delay signal T_DET, Bandgap ready signal BG_OK, undervoltage output lock signal UVLO_OUT, chip enable terminal EN and RS trigger 1 output signal SCP_CTR.

[0011] Further, Soft_Start_Circuit includes a cascade structure formed by a plurality of D flip-flops connected in series, a delay module Delay2 and a multi-input logic gate;

[0012] Cascade structure, used to implement a multi-stage soft start process, each stage of the trigger is delayed in turn by the transmission of the input signal, thereby generating a gradually increasing start-up time;

[0013] The delay module Delay2 is used to add an initialization delay to the soft start process to prevent the circuit from starting unstablely when the external signal changes.

[0014] Multi-input logic gates, including multiple inverters, NAND gates, and AND gate logic modules, combined with external input signals OCP_170US, ENP, and CPN, are used to logically determine and manage the startup conditions of soft start and short-circuit protection.

[0015] Furthermore, the number of D flip-flops is ten.

[0016] Further, the Hiccup Timing circuit includes NMOS tubes N1, N2, N3, N4, N5, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15, N16, N17, N18, N19, N20, N21, PMOS tubes P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, RS trigger 2, CMOS transmission gate, inverter 4, inverter 5, inverter 6, inverter 7, AND gate 4, capacitor C1, resistor R1, chip enable terminal EN input pin, PIBI input pin, VREF_BG input pin, ENP input pin, SW_VO input pin, SS_OUT_N output pin, SS_OUT_P output pin and SS output pin;

[0017] RS flip-flop 2 The terminal is connected to an input terminal of the AND gate 4, the R terminal of the RS trigger 2 is connected to the output terminal of the inverter 4, and the input terminal of the inverter 4 is connected to the gate of P11, the drain of P10, the gate of N11 and the drain of N10;

[0018] The source of P11 is connected to the drain of P9 and the source of P10, the source of N11 is connected to the source of N10 and the drain of N12, and the gate of P9 is connected to the gate of P10, the gate of N10, the gate of N12, the drain of P8, the drain of P5, and the drain of N9;

[0019] The gate of P5 is connected to the drain of P2, the gate of P4, the drain of P1, the gate of P3, the source of P3, the gate of P12 and the drain of N3, and the drain of P4 is connected to the source of P6 and the source of P7;

[0020] The drain of P7 is connected to the gate of N9 and the drain of N8, and the drain of P6 is connected to the source of N7, the gate of N7 and the gate of N8;

[0021] The source of N3 is connected to the drain of N5, the gate of N5 is connected to the drain of N6, the gate of N4, the source of N4 and the source of N2, and the drain of N2 is connected to the source of N1;

[0022] The drain of P12 is connected to the drain of N13, the drain of P13, the gate of N18, the drain of N17, the drain of N15 and one end of C1;

[0023] The source of N13 is connected to the source of N14, the source of N16, the source of N15, the source of N17, the source of N19 and the source of N20, and the other end of C1 is connected to the drain of N14, the gate of N14, the drain of N16 and the gate of N15;

[0024] The source of N18 is connected to one end of R1, the drain of P14 and the first end of the CMOS transmission gate, the other end of R1 is connected to the drain of N19 and the drain of N20, the second end of the CMOS transmission gate is connected to the drain of N21 and the SS output pin, and the gate of N13 is connected to the S end of the RS trigger 2 and the output end of the inverter 5;

[0025] The drain of N4, the source of N5, the source of N6, the drain of N7, the source of N8, the source of N9, the source of N12, the drain of P11, and the source of N21 are connected to GND;

[0026] The drain of P3, the source of P1, the source of P2, the source of P4, the source of P5, the source of P8, the source of P9, the drain of N11, the source of P12, the source of P13, the drain of N18, the source of P14, and the gate of N3 are connected to AVDD;

[0027] The other input end of the AND gate 4 is connected to the input end of the inverter 6, the gate of P2 and the chip enable terminal EN input pin, the output end of the inverter 6 is connected to the gate of N17, the input end of the inverter 7 is connected to the SW_VO input pin, the output end of the inverter 7 is connected to the gate of N21 and the third end of the CMOS transmission gate, and the input end of the inverter 5 is connected to the ENP input pin;

[0028] The gate of N16 is connected to the gate of N20, the gate of N2, the gate of N19, the gate of P8, the gate of P1, the gate of P13 and the gate of P14 are connected to the SS_OUT_N output pin, the gate of N1 is connected to the chip enable input pin EN, the drain of N1 is connected to the PIBI input pin, the gate of P6 is connected to the VREF_BG input pin, the Q end of the RS trigger is connected to the SS_OUT_N output pin, the output end of AND gate 4 and the gate of N6 are connected to the SS_OUT_P output pin, the gate of P7 is connected to the SS output pin, and the fourth end of the CMOS transmission gate is connected to the SW_VO input pin.

[0029] Furthermore, One-Shot Trigger 1, One-Shot Trigger 2, and One-Shot Trigger 3 include an inverter 2, an inverter 3, a capacitor C2, a Schmitt trigger 1, a Schmitt trigger 2, and an AND gate 3 which are electrically connected in sequence.

[0030] The beneficial effect of the present invention is that the output feedback voltage V FBCompared with the set short-circuit reference voltage 250mV, if the output feedback voltage V FB When it drops to 250mV, the circuit is in a short-circuit state, triggering the short-circuit protection mechanism. The comparator outputs a short-circuit signal SCP, and then generates a short pulse signal through the single-pulse generator One-Shot Trigger2 to reset the RS trigger 1, thereby triggering the Hiccup Timing timing module in the circuit; the time control module Delay1 will generate a 170us shutdown signal SCP_CTR, which will control the circuit to enter intermittent working mode to prevent damage caused by continuous short circuit.

[0031] Specifically, the single-shot trigger 2 generates a short pulse signal, which makes the S-terminal input of the RS trigger 1 logic 1, and the output SCP_CTR of the RS trigger 1 is set to 1, and then the Hiccup_Timing circuit realizes a delay of 170us, and is fed back to the R-terminal of the RS trigger 1 through the OR gate 1. At this time, R=1, SCP_CTR=0, and SCP_170us is fed back to the CLR terminal of the D trigger 1. SS_OUT_P is the circuit soft start completion signal. If V FB When a soft start is completed, it has not yet escaped from the short circuit state (V FB <250mV), then Hiccup_Timing will continue to delay for 170us, and the circuit will soft-start again for 1ms. This state will continue until V FB When the detection voltage is greater than 250mV, the circuit is out of the short-circuit state, and SCP outputs a low level. At this time, the Q terminal of RS trigger 1 = SCP = 0, and the S terminal is 1. As long as the circuit is not in the short-circuit state (V FB >250mV), SCP is always 0, and S is always high, then SCR_CTR=1, SCR_CTR is the output logic signal of short-circuit protection.

[0032] The present invention also includes a soft start circuit Soft_Start_Circuit with a delay of 1 ms, which is used to gradually increase the current and output voltage after the system starts or recovers from a short circuit to achieve smooth system startup, effectively avoid the large current impact at the startup moment, and protect the load and power supply.

[0033] Reduce power consumption: After a short circuit occurs, the intermittent protection mechanism will periodically disconnect the load current, allowing the circuit to enter a dormant state (Hiccup), and restart only after a specified time. This avoids the energy loss of traditional protection circuits when working with continuous high current.

[0034] In addition, in intermittent protection, the circuit will enter a period of sleep after each soft start failure to prevent overheating of the chip or system due to continuous short circuit.

[0035] Saving chip area: Based on timing (such as 170μs and 1ms) and logic judgment, the present invention avoids the complex design of high current protection circuits in traditional circuits (such as additional current sampling or comparison circuits) by using one-shot triggers and logic gates. Using logic and timing circuits usually saves more area than directly using high-power analog circuits (such as linear comparators and constant current sources).

[0036] The "soft start circuit" and "short circuit protection" in the circuit share some logic and trigger modules, reducing the area of ​​repeated design.

[0037] In addition, in the discontinuous protection mode, a large current is not continuously output when a short circuit occurs, thereby reducing the need to drive a high-power MOSFET, thereby reducing the size of the current sampling and power management modules.

[0038] Smooth start: When a short circuit occurs, the circuit enters the hiccup protection mode, stops outputting for a period of time, and then tries to restart. The soft start circuit is activated only when the system meets all the start conditions (such as the short circuit has been removed, the input voltage is normal, etc.), avoiding forced start when the short circuit has not been removed. This coordination mechanism ensures that the conditions for each soft start are correct, avoiding start failure or system instability. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 is an overall circuit diagram of the short-circuit protection circuit of the present invention;

[0040] Figure 2 It is an oscillogram of the operation of the overall short-circuit protection circuit of the present invention;

[0041] Figure 3 It is a schematic diagram of the internal structure of the One-Shot single pulse generator of the present invention;

[0042] Figure 4 It is a schematic diagram of the internal structure of the Hiccup_Timing timing circuit of the present invention;

[0043] Figure 5 It is a schematic diagram of the internal structure of the Soft_Start_Circuit soft start circuit of the present invention. DETAILED DESCRIPTION

[0044] The principles and features of the present invention are described below in conjunction with the accompanying drawings. The examples given are only used to explain the present invention and are not used to limit the scope of the present invention.

[0045] like Figure 1 to Figure 5 As shown, in embodiment 1, a short circuit protection circuit includes a comparator, One-Shot Trigger 1 (single pulse generator), One-Shot Trigger 2, One-Shot Trigger 3, D trigger 1, RS trigger 1, Hiccup Timing (timing module), OR gate 1, OR gate 2, AND gate 1, AND gate 2, inverter 1, Delay 1 (delay module) and Soft_Start_Circuit (soft start circuit) integrated on a PCB board;

[0046] The two input terminals of the comparator are connected to the 250mV reference voltage and the output feedback voltage V FB , the output of the comparator is connected to the input of One-Shot Trigger2, the output of One-Shot Trigger2 is connected to an input of OR Gate 2, the output of OR Gate 2 is connected to the S of RS Trigger 1, the Q of RS Trigger 1 is connected to the ENP of Hiccup Timing; the R of RS Trigger 1 is connected to the output of OR Gate 1, one input of OR Gate 1 is connected to the chip enable EN through One-Shot Trigger1; the other input of OR Gate 2 is connected to the output of Delay1 through One-Shot Trigger3, the input of Delay1 is connected to the Q of D Trigger 1, the CP of D Trigger 1 is connected to the output of Soft_Start_Circuit;

[0047] The CLR terminal of D flip-flop 1 is connected to the output terminal of AND gate 1, one input terminal of AND gate 1 is connected to the chip enable terminal EN, the other input terminal of AND gate 1 is connected to the output terminal of inverter 1, the input terminal of inverter is connected to the output terminal of Hiccup Timing and the other input terminal of OR gate 1;

[0048] The input end of Soft_Start_Circuit is connected to the output end of AND gate 2, and the input end of AND gate 2 is connected to the chip enable end EN and the output signal SCP_CTR of RS trigger 1.

[0049] The output feedback voltage V FB Compared with the set short-circuit reference voltage 250mV, if the output feedback voltage V FBWhen it drops to 250mV, the circuit is in a short-circuit state, triggering the short-circuit protection mechanism. The comparator outputs a short-circuit signal SCP, and then generates a short pulse signal through the single-pulse generator One-Shot Trigger2 to reset the RS trigger 1, thereby triggering the Hiccup Timing timing module in the circuit; the time control module Delay1 will generate a 170us shutdown signal SCP_CTR, which will control the circuit to enter intermittent working mode to prevent damage caused by continuous short circuit.

[0050] Specifically, the single-shot trigger 2 generates a short pulse signal, which makes the S-terminal input of the RS trigger 1 logic 1, and the output SCP_CTR of the RS trigger 1 is set to 1, and then the Hiccup_Timing circuit realizes a delay of 170us, and is fed back to the R-terminal of the RS trigger 1 through the OR gate 1. At this time, R=1, SCP_CTR=0, and SCP_170us is fed back to the CLR terminal of the D trigger 1. SS_OUT_P is the circuit soft start completion signal. If V FB When a soft start is completed, it has not yet escaped from the short circuit state (V FB <250mV), then Hiccup_Timing will continue to delay for 170us, and the circuit will soft-start again for 1ms. This state will continue until V FB When the detection voltage is greater than 250mV, the circuit is out of the short-circuit state, and SCP outputs a low level. At this time, the Q terminal of RS trigger 1 = SCP = 0, and the S terminal is 1. As long as the circuit is not in the short-circuit state (V FB >250mV), SCP is always 0, and S is always high, then SCR_CTR=1, SCR_CTR is the output logic signal of short-circuit protection.

[0051] The present invention also includes a soft start circuit Soft_Start_Circuit with a delay of 1 ms, which is used to gradually increase the current and output voltage after the system starts or recovers from a short circuit to achieve smooth system startup, effectively avoid the large current impact at the startup moment, and protect the load and power supply.

[0052] Reduce power consumption: After a short circuit occurs, the intermittent protection mechanism will periodically disconnect the load current, allowing the circuit to enter a dormant state (Hiccup), and restart only after a specified time. This avoids the energy loss of traditional protection circuits when working with continuous high current.

[0053] In addition, in intermittent protection, the circuit will enter a period of sleep after each soft start failure to prevent overheating of the chip or system due to continuous short circuit.

[0054] Saving chip area: Based on timing (such as 170μs and 1ms) and logic judgment, the present invention avoids the complex design of high current protection circuits in traditional circuits (such as additional current sampling or comparison circuits) by using one-shot triggers and logic gates. Using logic and timing circuits usually saves more area than directly using high-power analog circuits (such as linear comparators and constant current sources).

[0055] The "soft start circuit" and "short circuit protection" in the circuit share some logic and trigger modules, reducing the area of ​​repeated design.

[0056] In addition, in the discontinuous protection mode, a large current is not continuously output when a short circuit occurs, thereby reducing the need to drive a high-power MOSFET, thereby reducing the size of the current sampling and power management modules.

[0057] Smooth start: When a short circuit occurs, the circuit enters the hiccup protection mode, stops outputting for a period of time, and then tries to restart. The soft start circuit is activated only when the system meets all the start conditions (such as the short circuit has been removed, the input voltage is normal, etc.), avoiding forced start when the short circuit has not been removed. This coordination mechanism ensures that the conditions for each soft start are correct, avoiding start failure or system instability.

[0058] Embodiment 2: This embodiment is a further improvement on the basis of embodiment 1, and its details are as follows:

[0059] AND gate 2 is a five-input AND gate circuit. The five input terminals of AND gate 2 are:

[0060] Bandgap hysteresis delay signal T_DET, Bandgap ready signal BG_OK, undervoltage output lock signal UVLO_OUT, chip enable terminal EN and RS trigger 1 output signal SCP_CTR.

[0061] The soft start circuit is controlled by AND gates of multiple logic signals, and the system is allowed to restart only when all conditions are met. The short circuit protection circuit of the present invention can effectively protect components that are sensitive to excessive current or voltage, greatly prolong the service life of the chip, and improve the reliability and safety of the power management chip.

[0062] When the other four inputs of the AND gate circuit are all 1, the enable terminal ENP of the soft start circuit is determined by SCP_CTR. When SCP_CTR is a rising edge signal, ENP is 1, and the soft start circuit starts to work. At this time, the soft start gradually increases the output voltage by gradually pulling up the SS_OUT_P signal. This process is about 1.2 to 1.4ms to control the start speed. As the output SS_OUT_P becomes a high potential, it indicates that the soft start is completed. There are two situations when SS_OUT_P outputs 0: one is that the enable terminal ENP of the soft start circuit is 0, and the soft start will not be executed; the other is that ENP is 1 and the soft start has not been completed.

[0063] Embodiment 3, this embodiment is a further improvement on the basis of embodiment 1, and its details are as follows:

[0064] Soft_Start_Circuit includes a cascade structure formed by multiple D flip-flops connected in series, a delay module Delay2 and a multi-input logic gate;

[0065] Cascade structure, used to implement a multi-stage soft start process, each stage of the trigger is delayed in turn by the transmission of the input signal, thereby generating a gradually increasing start-up time;

[0066] The delay module Delay2 is used to add an initialization delay to the soft start process to prevent the circuit from starting unstablely when the external signal changes.

[0067] The multi-input logic gates, including multiple inverters, NAND gates, and AND gate logic modules, are used to logically determine and manage the startup conditions of soft start and short-circuit protection in combination with external input signals OCP_170US, ENP, and CPN.

[0068] The circuit is linked with the short-circuit protection logic, such as the OCP_170US signal, to achieve a close combination of soft start and protection processes, thereby improving the overall stability and safety of the system;

[0069] 1. Smooth startup process: Through the gradually increasing soft start signal, the surge current generated by the load circuit when it is powered on is effectively avoided, and the reliability of the circuit is improved;

[0070] 2. Flexibility of start-up time: The design of multi-level D flip-flop and delay module allows flexible adjustment of soft start time according to application requirements to adapt to different load conditions;

[0071] 3. Close integration with protection logic: The circuit works with the short-circuit protection logic to ensure smooth entry into the soft-start state after the protection is released, thus improving the overall stability of the power management system;

[0072] 4. Avoid damage to the load caused by transient impact: Multi-level timing control can effectively suppress damage to the load and power devices caused by transient impact current, thus extending the service life of the system;

[0073] 5. Low power consumption design: The low power consumption characteristics of CMOS circuit make the soft start module consume very low energy in standby or working state, which is very suitable for portable and high-efficiency systems.

[0074] The internal structure of the soft start circuit is shown in the attached Figure 5 As shown in the figure, the circuit is mainly composed of EN signal control terminal, current mirror, voltage reference and current comparison structure. There are 1μA and 2μA current sources in this circuit, which are used to provide current for the soft start stage. The combination of 1μA and 2μA determines the time constant of soft start, which affects the rising speed of SS signal. The current source slowly pulls up SS_OUT_P by charging the capacitor, so that the output increases steadily. VREF_BG is the reference voltage of the circuit, which is compared with the voltage generated during the soft start process to ensure that the voltage rise in the soft start stage meets the requirements and avoids being too fast or too slow. In general, the soft start circuit gradually increases the current and output voltage by controlling the opening of the EN signal to achieve smooth system startup and avoid current shock during startup.

[0075] Embodiment 4: This embodiment is a further improvement on the basis of embodiment 1, and its details are as follows:

[0076] The number of D flip-flops is 10.

[0077] Ten D flip-flops are used to achieve a timing of 170us while ensuring high robustness, accuracy, and stability of the timing circuit. Although the counting range of only 8 D flip-flops is sufficient, for safety margin considerations, additional flip-flops can be used to handle errors or ensure circuit stability for redundancy or protection. At the same time, more refined control can be achieved. Increasing the number of D flip-flops can provide finer-grained time control for the circuit and ensure more accurate overcurrent protection action.

[0078] Embodiment 5, this embodiment is a further improvement on the basis of embodiment 1, and its details are as follows:

[0079] The Hiccup Timing (timing module) circuit includes NMOS tubes N1, N2, N3, N4, N5, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15, N16, N17, N18, N19, N20, N21, PMOS tubes P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, RS trigger 2, CMOS transmission gate, inverter 4, inverter 5, inverter 6, inverter 7, AND gate 4, capacitor C1, resistor R1, chip enable terminal EN input pin, PIBI input pin, VREF_BG input pin, ENP input pin, SW_VO input pin, SS_OUT_N output pin, SS_OUT_P output pin and SS output pin;

[0080] RS flip-flop 2 The terminal is connected to an input terminal of the AND gate 4, the R terminal of the RS trigger 2 is connected to the output terminal of the inverter 4, and the input terminal of the inverter 4 is connected to the gate of P11, the drain of P10, the gate of N11 and the drain of N10;

[0081] The source of P11 is connected to the drain of P9 and the source of P10, the source of N11 is connected to the source of N10 and the drain of N12, and the gate of P9 is connected to the gate of P10, the gate of N10, the gate of N12, the drain of P8, the drain of P5, and the drain of N9;

[0082] The gate of P5 is connected to the drain of P2, the gate of P4, the drain of P1, the gate of P3, the source of P3, the gate of P12 and the drain of N3, and the drain of P4 is connected to the source of P6 and the source of P7;

[0083] The drain of P7 is connected to the gate of N9 and the drain of N8, and the drain of P6 is connected to the source of N7, the gate of N7 and the gate of N8;

[0084] The source of N3 is connected to the drain of N5, the gate of N5 is connected to the drain of N6, the gate of N4, the source of N4 and the source of N2, and the drain of N2 is connected to the source of N1;

[0085] The drain of P12 is connected to the drain of N13, the drain of P13, the gate of N18, the drain of N17, the drain of N15 and one end of C1;

[0086] The source of N13 is connected to the source of N14, the source of N16, the source of N15, the source of N17, the source of N19 and the source of N20, and the other end of C1 is connected to the drain of N14, the gate of N14, the drain of N16 and the gate of N15;

[0087] The source of N18 is connected to one end of R1, the drain of P14 and the first end of the CMOS transmission gate, the other end of R1 is connected to the drain of N19 and the drain of N20, the second end of the CMOS transmission gate is connected to the drain of N21 and the SS output pin, and the gate of N13 is connected to the S end of the RS trigger 2 and the output end of the inverter 5;

[0088] The drain of N4, the source of N5, the source of N6, the drain of N7, the source of N8, the source of N9, the source of N12, the drain of P11, and the source of N21 are connected to GND;

[0089] The drain of P3, the source of P1, the source of P2, the source of P4, the source of P5, the source of P8, the source of P9, the drain of N11, the source of P12, the source of P13, the drain of N18, the source of P14, and the gate of N3 are connected to AVDD;

[0090] The other input end of the AND gate 4 is connected to the input end of the inverter 6, the gate of P2 and the chip enable terminal EN input pin, the output end of the inverter 6 is connected to the gate of N17, the input end of the inverter 7 is connected to the SW_VO input pin, the output end of the inverter 7 is connected to the gate of N21 and the third end of the CMOS transmission gate, and the input end of the inverter 5 is connected to the ENP input pin;

[0091] The gate of N16 is connected to the gate of N20, the gate of N2, the gate of N19, the gate of P8, the gate of P1, the gate of P13 and the gate of P14 are connected to the SS_OUT_N output pin, the gate of N1 is connected to the chip enable input pin EN, the drain of N1 is connected to the PIBI input pin, the gate of P6 is connected to the VREF_BG input pin, the Q end of the RS trigger is connected to the SS_OUT_N output pin, the output end of AND gate 4 and the gate of N6 are connected to the SS_OUT_P output pin, the gate of P7 is connected to the SS output pin, and the fourth end of the CMOS transmission gate is connected to the SW_VO input pin.

[0092] Hiccup Timing (timing module) circuit diagram Figure 4, based on the time control of charge and discharge: the capacitor C1 and the resistor R1 in the circuit form a charge and discharge circuit, which is used to generate an adjustable time constant. By controlling the charging and discharging speed of the capacitor, the soft start time delay of 1.2 to 1.4ms is achieved, and the timing control of the soft start process is realized; power consumption design: a small current bias (such as 1μA, 2μA) is used in the circuit for bias circuit design, which greatly reduces the power consumption to meet the requirements of high power efficiency; feedback control ensures reliability: EN and ENP signals are used as the core input of the control logic, and the start and stop of each module of the circuit are controlled by inverters and logic gates to ensure the reliable operation of the entire protection logic; at the same time, the feedback path contains a CMOS transmission gate to ensure stable signal transmission and reduce noise interference; the start function is combined with short-circuit protection: the circuit not only provides the time control function of the soft start, but also links with the short-circuit protection circuit to automatically start the soft start process when the short circuit is detected.

[0093] Flexible and adjustable delay, taking into account the protection circuit: The values ​​of capacitor C1 and resistor R1 can be adjusted to change the soft start time and the delay of Hiccup Timing, adapt to the load startup requirements in different situations, and improve the circuit reliability; at the same time, the Hiccup Timing circuit intermittently attempts to start the circuit, which can effectively prevent continuous power-on when the short circuit is not released, protecting the power device and the load;

[0094] Low power consumption, suitable for low-power devices: The low bias current design makes the power consumption of this circuit extremely low in standby and operation, which is very suitable for portable, embedded and other power-sensitive application scenarios, improving the overall efficiency and also suitable for low-power devices;

[0095] High integration and reduced peripheral components: Integrating soft start, short circuit protection and delay control together reduces the dependence on external components and contributes to the miniaturization of circuit design;

[0096] The system has high smoothness and responsiveness: When the short circuit is released, the circuit can immediately enter the soft start state, avoiding output fluctuations caused by protection logic switching, which is beneficial to the continuity of short circuit protection and soft start, and improves the smoothness and responsiveness of the system.

[0097] Figure 2 In, V FB During the soft start period, it rises slowly and gradually reaches the gate threshold of 250mV or more after multi-level time control. The SCP signal changes from high to low, triggering the operation of the entire protection and soft start circuit.

[0098] Short circuit detection: When the load is short-circuited, the comparator detects V FBLower than 250mV, and trigger the SCP signal; in the short-circuit state, the SCP signal generates a protection window through the 170us delay logic, and SCP_170us is triggered when the delay reaches 170us;

[0099] The RS flip-flop is used to maintain the state of the short-circuit protection and control the output of the protection signal SCP_CTR;

[0100] When the short circuit is released and the input detection signal (such as TDET, UVLOOUT, BGOK) meets the conditions, the RS trigger is reset and SCP_CTR returns to a low level; through the Hiccup Timing controller, intermittent attempts are made to restart the load, and the 1ms time window is used to evaluate whether the short circuit is released;

[0101] The Hiccup Timing mechanism will repeatedly try to restart the load every 170us+1ms until the short circuit is removed; the delay window after the short circuit is triggered is 170us, and the subsequent protection state lasts for 1ms.

[0102] Embodiment 6: This embodiment is a further improvement on the basis of embodiment 1, and its details are as follows:

[0103] One-Shot Trigger 1, One-Shot Trigger 2, and One-Shot Trigger 3 are electrically connected in sequence to inverter 2, inverter 3, capacitor C2, Schmitt trigger 1, Schmitt trigger 2, and AND gate 3. See the circuit diagram for details. Figure 3 .

[0104] 1. High anti-interference ability, simple and flexible design: The hysteresis characteristics of the Schmitt trigger greatly improve the anti-interference ability of the input signal and avoid false triggering caused by noise or glitches.

[0105] By adjusting the delay of the Schmitt trigger or external components, the output pulse width can be flexibly set to meet different application requirements;

[0106] 2. Modular design facilitates integration and is suitable for a variety of application scenarios: This module has a simple structure and only requires a small number of components to complete the single trigger function. It is very suitable for integration with other circuit modules to improve the simplicity of system design;

[0107] The One-Shot Trigger module can be applied to short-circuit protection, timing control, soft start and other scenarios, and has strong functional versatility. The output is a single pulse signal with a fixed width, which can be reliably used to control other modules, such as timing circuits or protection logic. The one-shot trigger only responds to the rising or falling edge of the input signal during edge detection, avoiding misoperation caused by continuous signals, ensuring the accuracy of the trigger, and high reliability.

[0108] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A short circuit protection circuit, characterized in that: Including comparator, One-ShotTrigger1, One-Shot Trigger2, One-Shot Trigger3, D flip-flop 1, RS flip-flop 1, HiccupTiming, OR gate 1, OR gate 2, AND gate 1, AND gate 2, inverter 1, Delay1 and Soft_Start_Circuit integrated on the PCB board; The two input terminals of the comparator are connected to the 250mV reference voltage and the output feedback voltage V FB , the output end of the comparator is connected to the input end of the One-Shot Trigger2, the output end of the One-Shot Trigger2 is connected to an input end of the OR gate 2, the output end of the OR gate 2 is connected to the S end of the RS trigger 1, and the Q end of the RS trigger 1 is connected to the ENP end of the Hiccup Timing; the R end of the RS trigger 1 is connected to the output end of the OR gate 1, and one input end of the OR gate 1 is connected to the chip enable end EN through the One-Shot Trigger1; the other input end of the OR gate 2 is connected to the output end of the Delay1 through the One-Shot Trigger3, the input end of the Delay1 is connected to the Q end of the D trigger 1, and the CP end of the D trigger 1 is connected to the output end of the Soft_Start_Circuit; The CLR terminal of the D flip-flop 1 is connected to the output terminal of the AND gate 1, one input terminal of the AND gate 1 is connected to the chip enable terminal EN, the other input terminal of the AND gate 1 is connected to the output terminal of the inverter 1, and the input terminal of the inverter is connected to the output terminal of the Hiccup Timing and the other input terminal of the OR gate 1; The input end of the Soft_Start_Circuit is connected to the output end of the AND gate 2, and the input end of the AND gate 2 is connected to the chip enable end EN and the output signal SCP_CTR of the RS trigger 1.

2. A short circuit protection circuit according to claim 1, characterized in that: The AND gate 2 is a five-input AND gate circuit, and the five input terminals of the AND gate 2 are respectively: Bandgap hysteresis delay signal T_DET, Bandgap ready signal BG_OK, undervoltage output lock signal UVLO_OUT, chip enable terminal EN and RS trigger 1 output signal SCP_CTR.

3. A short circuit protection circuit according to claim 2, characterized in that: The Soft_Start_Circuit includes a cascade structure formed by a plurality of D flip-flops connected in series, a delay module Delay2 and a multi-input logic gate; The cascade structure is used to implement a multi-stage soft start process, where each stage of the trigger is delayed in turn by the transmission of the input signal, thereby generating a gradually increasing start time; The delay module Delay2 is used to add an initialization delay to the soft start process to prevent the circuit from starting unstablely when the external signal changes. The multi-input logic gate includes multiple inverters, NAND gates, and AND gate logic modules, which are combined with external input signals OCP_170US, ENP, and CPN to perform logical judgment and management on the start-up conditions of soft start and short-circuit protection.

4. A short circuit protection circuit according to claim 3, characterized in that: The number of the D flip-flops is ten.

5. A short circuit protection circuit according to claim 1, characterized in that: The Hiccup Timing circuit includes NMOS tubes N1, N2, N3, N4, N5, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15, N16, N17, N18, N19, N20, N21, PMOS tubes P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, RS trigger 2, CMOS transmission gate, inverter 4, inverter 5, inverter 6, inverter 7, AND gate 4, capacitor C1, resistor R1, chip enable terminal EN input pin, PIBI input pin, VREF_BG input pin, ENP input pin, SW_VO input pin, SS_OUT_N output pin, SS_OUT_P output pin and SS output pin; The RS flip-flop 2 The R end of the RS trigger 2 is connected to an input end of the AND gate 4, the R end of the RS trigger 2 is connected to the output end of the inverter 4, and the input end of the inverter 4 is connected to the gate of the P11, the drain of the P10, the gate of the N11 and the drain of the N10; The source of P11 is connected to the drain of P9 and the source of P10, the source of N11 is connected to the source of N10 and the drain of N12, and the gate of P9 is connected to the gate of P10, the gate of N10, the gate of N12, the drain of P8, the drain of P5 and the drain of N9; The gate of P5 is connected to the drain of P2, the gate of P4, the drain of P1, the gate of P3, the source of P3, the gate of P12 and the drain of N3, and the drain of P4 is connected to the source of P6 and the source of P7; The drain of P7 is connected to the gate of N9 and the drain of N8, and the drain of P6 is connected to the source of N7, the gate of N7 and the gate of N8; The source of N3 is connected to the drain of N5, the gate of N5 is connected to the drain of N6, the gate of N4, the source of N4 and the source of N2, and the drain of N2 is connected to the source of N1; The drain of P12 is connected to the drain of N13, the drain of P13, the gate of N18, the drain of N17, the drain of N15 and one end of C1; The source of N13 is connected to the source of N14, the source of N16, the source of N15, the source of N17, the source of N19 and the source of N20, and the other end of C1 is connected to the drain of N14, the gate of N14, the drain of N16 and the gate of N15; The source of N18 is connected to one end of R1, the drain of P14 and the first end of the CMOS transmission gate, the other end of R1 is connected to the drain of N19 and the drain of N20, the second end of the CMOS transmission gate is connected to the drain of N21 and the SS output pin, and the gate of N13 is connected to the S end of the RS trigger 2 and the output end of the inverter 5; The drain of N4, the source of N5, the source of N6, the drain of N7, the source of N8, the source of N9, the source of N12, the drain of P11, and the source of N21 are connected to GND; The drain of P3, the source of P1, the source of P2, the source of P4, the source of P5, the source of P8, the source of P9, the drain of N11, the source of P12, the source of P13, the drain of N18, the source of P14, and the gate of N3 are connected to AVDD; Another input end of the AND gate 4 is connected to the input end of the inverter 6, the gate of P2 and the chip enable end EN input pin, the output end of the inverter 6 is connected to the gate of N17, the input end of the inverter 7 is connected to the SW_VO input pin, the output end of the inverter 7 is connected to the gate of N21 and the third end of the CMOS transmission gate, and the input end of the inverter 5 is connected to the ENP input pin; The gate of N16 is connected to the gate of N20, the gate of N2, the gate of N19, the gate of P8, the gate of P1, the gate of P13 and the gate of P14 are connected to the SS_OUT_N output pin, the gate of N1 is connected to the chip enable terminal EN input pin, the drain of N1 is connected to the PIBI input pin, the gate of P6 is connected to the VREF_BG input pin, the Q end of the RS trigger is connected to the SS_OUT_N output pin, the output end of the AND gate 4 and the gate of N6 are connected to the SS_OUT_P output pin, the gate of P7 is connected to the SS output pin, and the fourth end of the CMOS transmission gate is connected to the SW_VO input pin.

6. A short circuit protection circuit according to claim 1, characterized in that: The One-Shot Trigger 1, One-Shot Trigger 2 and One-Shot Trigger 3 include an inverter 2, an inverter 3, a capacitor C2, a Schmitt trigger 1, a Schmitt trigger 2 and an AND gate 3 which are electrically connected in sequence.

Images