Electronic device and method for overcurrent detection

Abstract

This article discloses an electronic device and method for overcurrent detection. The electronic device induces a high-side offset voltage drop and converts the voltage difference between a first voltage and a first voltage drop at an input end of an upper bridge power element of a power stage into a first current, wherein the first voltage drop is a superposition of a first balanced voltage drop and a high-side offset voltage drop. The electronic device further performs the following operations: converting the voltage difference between a second voltage and a second balanced voltage drop at an output end of the upper bridge power element into a second current, comparing the first current with the second current, and when the first current is stronger than the second current, generating a high-side overcurrent protection (OCP) signal with a logic high potential for a driver of the power stage, thereby causing the driver to shut down the upper bridge power element accordingly.

Description

Technical Field

[0001] The present disclosure relates to an electronic device and method for overcurrent detection. More specifically, the present disclosure relates to an electronic device and method for overcurrent detection of a medium voltage or high voltage power stage using low voltage hardware. Background Art

[0002] Different charging systems can operate at different voltage levels depending on their specific applications and the requirements of the device being charged. Charging systems can generally be divided into three common voltage levels, namely low voltage (LV) charging, medium voltage (MV) charging, and high voltage (HV) charging. Low voltage charging generally refers to a charging system that operates at a relatively low voltage level (often less than 48 volts). Medium voltage charging systems operate at higher voltage levels (usually ranging from 48 volts to several hundred volts). High voltage charging systems can operate at voltage levels in excess of 800 volts, such as high-power charging stations that can provide hundreds of kilowatts of power to quickly charge electric vehicles.

[0003] There are usually three main components in a charging system, namely the controller, the power stage and the driver of the power stage. The power stage mainly handles the power conversion or amplification tasks, while the driver is responsible for providing the required electrical signals to efficiently control and drive the power stage. As for the controller, it can regulate and control the operation of the power system (for example, by controlling the driver).

[0004] In the past, the three main components (i.e., controller, power stage, and driver (of the power stage)) were designed and implemented separately in most cases. Therefore, when these components were designed or implemented together for a multi-chip module (MCM), the compatibility between the components was never considered. For example, since a conventional low-voltage controller cannot handle (withstand) the current flowing in a medium-voltage power stage or even a high-voltage power stage and therefore will not be able to monitor and detect abnormalities in the current, how to implement overcurrent detection and protection (i.e., overcurrent protection (OCP)) for a medium-voltage power stage or a high-voltage power stage (e.g., allowing a voltage level of up to about 5 volts to 10 volts, such as a power stage based on gallium nitride (GaN) material) with a low-voltage controller (e.g., allowing a voltage level of up to about 100 volts) is a problem.

[0005] In view of this, there is an urgent need in the technical field to which the present invention belongs for a good solution for providing OCP for medium voltage (or even high voltage) power stages using low voltage hardware. Summary of the invention

[0006] In order to at least solve the above problems, the present disclosure provides an electronic device for overcurrent detection. The electronic device may include at least a high-side voltage-to-current (V2I) converter, a high-side voltage offset element coupled to the high-side V2I converter and a first high-side comparator, a first high-side comparator coupled to the high-side V2I converter, and a high-side OCP signal generator coupled to the first high-side comparator. The high-side voltage offset element can be used to induce a high-side offset voltage drop. The high-side V2I converter can be used to convert a voltage difference between a first voltage drop and a first voltage at an input end of an upper bridge power element of a power stage into a first current, the first voltage drop being a superposition of the high-side offset voltage drop and a first balancing voltage drop induced by the high-side OCP signal generator. The high-side V2I converter can also be used to convert a voltage difference between a second voltage at an output end of the upper bridge power element and a second balancing voltage drop induced by the first high-side comparator into a second current. As for the first high-side comparator, it can be used to compare the first current and the second current, and the high-side OCP signal generator can be used to generate a high-side OCP signal with a logic high potential (logic high) when the first current is stronger than the second current, thereby causing a driver of the power stage to turn off the upper bridge power element accordingly.

[0007] In order to at least solve the above problems, the present disclosure also provides an overcurrent detection method. The method may include the following steps:

[0008] A high-side voltage offset element causes a high-side offset voltage drop;

[0009] A voltage difference between a first voltage drop and a first voltage at an input terminal of an upper bridge power element of a power stage is converted into a first current by a high-side voltage-to-current (V2I) converter, wherein the first voltage drop is a superposition of a first balancing voltage drop caused by a high-side OCP signal generator and a high-side offset voltage drop;

[0010] The high-side V2I converter converts a voltage difference between a second voltage at an output end of the upper bridge power element and a second balancing voltage drop caused by a first high-side comparator into a second current, wherein the first high-side comparator is coupled to the high-side V2I converter;

[0011] comparing the first current and the second current by a first high-side comparator; and

[0012] A high-side OCP signal generator generates a high-side OCP signal with a logic high potential for a driver of the power stage when the first current is stronger than the second current, thereby causing the driver to turn off the upper bridge power element accordingly.

[0013] The present disclosure enables a low voltage OCP circuit to handle the high side OCP of a medium voltage power stage or even a high voltage power stage, which is mainly due to the low voltage OCP circuit shifting the voltage across the two terminals of the upper bridge power element from a high voltage / medium voltage domain to a low voltage domain by means of the first V2I converter as described above. This arrangement enables the components of the electronic device of the present disclosure (such as a comparator) to operate in a low voltage domain and can therefore be manufactured in the low voltage domain. This is not only cost-effective, but also relatively easy to implement. Therefore, the present disclosure provides that a multi-chip module (MCM) including a low voltage OCP circuit and a medium voltage power stage can be designed and implemented, and also ensures that the high side OCP of the power stage can be achieved. That is, the OCP circuit and the power stage can be integrated into one package and still operate correctly.

[0014] The present invention generally describes the core concepts of the present invention and covers the problems to be solved, the means to solve the problems and the effects of the present invention, so that those skilled in the art to which the present invention belongs have a basic understanding of the present invention. However, it should be understood that the present invention is not intended to cover all embodiments of the present invention, but is only used to present the core concepts of the present invention in a simple form and serve as an introduction to the following detailed description. In order to enable those skilled in the art to which the present invention belongs to have a good understanding of the features of the claimed invention, the detailed techniques and preferred embodiments implemented for the subject matter of the present invention are described in the following paragraphs in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings are provided to illustrate embodiments of the present disclosure, in which:

[0016] Figure 1 A schematic diagram of an electronic device for over-current detection according to one or more embodiments of the present disclosure is shown.

[0017] Figure 2 Draw Figure 1 A schematic diagram of a high-voltage side overcurrent detection circuit of an electronic device in FIG.

[0018] Figure 3 Draw Figure 2 A schematic diagram of an alternative scheme for a high-voltage side overcurrent detection circuit of an electronic device in FIG.

[0019] Figure 4 Draw Figure 1 A schematic diagram of a low-voltage side overcurrent detection circuit of an electronic device in FIG.

[0020] Figure 5 An over-current detection method according to one or more embodiments of the present disclosure is illustrated.

[0021] Figures 1 to 5 The contents shown in the figures are only used to help illustrate the embodiments of the present disclosure, and are not used to limit the scope of the present disclosure.

[0022]

Explanation of symbols

[0023] As shown below:

[0024] 1: Electronic devices

[0025] 2: Power Level

[0026] 3: Driver

[0027] 5: Methods

[0028] 11: High-voltage side overcurrent detection circuit

[0029] 12: Low voltage side overcurrent detection circuit

[0030] 21: Upper bridge power components

[0031] 22: Lower bridge power components

[0032] 111: High-side V2I converter

[0033] 112: High-voltage side voltage offset element / voltage offset element

[0034] 113: First high-voltage side comparator

[0035] 114: High-voltage side OCP signal generator

[0036] 114G: AND gate

[0037] 114M: Second high-voltage side comparator

[0038] 114V: First inverter

[0039] 121: Low voltage side V2I converter

[0040] 122: Low voltage side voltage offset element

[0041] 123: Low voltage side comparator

[0042] 124: Low voltage side OCP signal generator

[0043] 124G: Second AND gate

[0044] 124V: Second inverter

[0045] 501, 502, 503, 504, 505: Steps

[0046] C01, C02: Current

[0047] C1: Current / First Current

[0048] C2: Current / Second Current

[0049] C3: The third current

[0050] C10: offset current

[0051] CS2, CS11, CS12: Output

[0052] HS1: High voltage side OCP signal

[0053] L1: Load

[0054] LG: Lower bridge control signal

[0055] LS1: Low voltage side OCP signal

[0056] N1, N2, N3, N4, N5, N6: nodes

[0057] PS1: Power supply

[0058] R1: The first resistor

[0059] R2: Second resistor

[0060] R3: The third resistor

[0061] RC1: First reference current source

[0062] RC2: Second reference current source

[0063] T0, T1, T2, T3, T4, T5, T6: transistors

[0064] UG: upper bridge control signal

[0065] V1: first voltage

[0066] V2: Second voltage

[0067] V3: The third voltage

[0068] VOS1: High side offset voltage drop

[0069] VOS2: Low side offset voltage drop DETAILED DESCRIPTION

[0070] Figure 1 FIG. 1 is a schematic diagram of an electronic device for overcurrent detection according to one or more embodiments of the present disclosure. Figure 1, an electronic device 1 for overcurrent detection disclosed in the present invention (hereinafter referred to as "electronic device 1") can be coupled with a power stage 2 and a driver 3 of the power stage 2. The electronic device 1 can generally be used to monitor a current C01 flowing from an upper bridge power element 21 of the power stage 2 to a load L1 and / or a current C02 flowing from the load L1 to a lower bridge power element 22 of the power stage 2 (e.g. Figure 4 ), and respectively perform high-voltage side overcurrent detection and low-voltage side overcurrent detection on current C01 and current C02. Correspondingly, the electronic device 1 may include a high-voltage side overcurrent detection circuit 11 and a low-voltage side overcurrent detection circuit 12. When a high-voltage side overcurrent event occurs, the high-voltage side overcurrent detection circuit 11 can usually detect the high-voltage side overcurrent event and provide a high-voltage side OCP signal HS1, thereby allowing the driver 3 to take necessary actions. Similarly, when a low-voltage side overcurrent event occurs, the low-voltage side overcurrent detection circuit 12 can usually detect the low-voltage side overcurrent event and provide a low-voltage side OCP signal LS1, thereby allowing the driver 3 to take necessary actions.

[0071] The power stage 2 may be implemented based on wide bandgap semiconductors such as gallium nitride (GaN), silicon carbide (SiC), vertical double-diffused metal-oxide-semiconductor (VDMOS), lateral double-diffused metal-oxide-semiconductor (LDMOS), etc. The wide bandgap characteristics enable the power stage 2 to operate in a medium voltage domain or a high voltage domain (e.g., from a few hundred volts to even more than 1,000 volts).

[0072] The upper bridge power element 21 can be coupled to a direct current (DC) power source PS1 and a load L1, and can be turned on / off by applying an upper bridge control signal UG to the upper bridge control signal terminal of the upper bridge power element 21. The lower bridge power element 22 can be coupled to the load L1 and a ground level, and can be turned on / off by applying a lower bridge control signal LG to the lower bridge control signal terminal of the lower bridge power element 22. When the upper bridge power element 21 is turned on, current flows from the positive terminal of the power source PS1 through the load L1, and then returns to the negative terminal of the power source PS1. When the upper bridge power element 21 is turned off, the lower bridge power element 22 is turned on and allows current to flow as Figure 4 Flow in the opposite direction is shown.

[0073] The load L1 may be one or more electronic devices that receive power supplied from the power stage 2 , and may be, for example, any element used in an audio system.

[0074] Driver 3 can usually be used to provide the required electrical signals to efficiently control and / or drive power stage 2. Fast charging devices such as GaN chargers usually have high gate capacitance and require precise voltage and current waveforms to switch quickly. Driver 3 can ensure that the gate voltage and current are properly controlled, thereby enabling the charging device to operate optimally.

[0075] The overcurrent detection on the high-voltage side of the electronic device 1 mainly focuses on the upper bridge power element 21, while the overcurrent detection on the low-voltage side mainly focuses on the lower bridge power element 22. Once an overcurrent event on the high-voltage side occurs, the electronic device 1 can detect the event and thus provide a high-voltage side OCP signal HS1 with a logic high potential, thereby causing the driver 3 to shut down the upper bridge power element 21. Similarly, when an overcurrent event on the low-voltage side occurs, the electronic device 1 can detect the event and thus provide a low-voltage side OCP signal LS1 with a logic high potential, thereby causing the driver 3 to shut down the lower bridge power element 22.

[0076] Figure 2 Draw Figure 1 A schematic diagram of a feasible structure of a high-voltage side overcurrent detection circuit 11 of an electronic device 1 in FIG. Figure 1 and Figure 2 In addition, the high-side overcurrent detection circuit 11 may basically include a high-side V2I converter 111, a voltage shift element 112, a first high-side comparator 113 and a high-side OCP signal generator 114. The voltage shift element 112 may be coupled to the high-side V2I converter 111. The first high-side comparator 113 may be coupled to the voltage shift element 112, the high-side V2I converter 111 and the high-side OCP signal generator 114.

[0077] In order to monitor the current flowing through the upper bridge power element 21 after the upper bridge power element 21 is turned on, the high-side V2I converter 111 can be connected to an input terminal (ie, Figure 2 The node N1 shown) and an output terminal (ie, Figure 2 The input end of the upper bridge power element 21 may refer to a terminal where the current from the power source PS1 enters the upper bridge power element 21, and the output end may refer to a terminal where the current from the power source PS1 leaves the upper bridge power element 21.

[0078] The voltage offset element 112 may be used to induce a high-side offset voltage drop VOS1, and the high-side V2I converter 111 may be used to convert a voltage difference between a first voltage V1 observed at the node N1 and a superposition of the high-side offset voltage drop VOS1 and a first balancing voltage drop induced by the high-side OCP signal generator 114 into a first current C1. On the other hand, the high-side V2I converter 111 may also be used to convert a voltage difference between a second voltage V2 observed at the node N2 and a second balancing voltage drop induced by the first high-side comparator 113 into a second current C2.

[0079] like Figure 2 As shown, the high-side V2I converter 111 may include a first resistor R1 coupled to the node N1 and a second resistor R2 coupled to the node N2. According to different implementations, the first resistor R1 and the second resistor R2 may each be a single resistor or a combination of multiple resistors coupled in series.

[0080] Depending on the implementation, the voltage shift element 112 may include a single transistor, or a plurality of transistors coupled in series. In some embodiments, each transistor of the voltage shift element 112 may be a diode-connected MOSFET (i.e., a MOSFET with a gate connected to a drain) or a diode-connected bipolar junction transistor (i.e., a BJT with a base connected to a collector). A transistor having a diode-connected structure can conduct current in both directions, just like a diode. In addition, a transistor having a diode-connected structure causes a voltage drop (i.e., a gate-source voltage of the diode-connected transistor) when a current flows through the transistor, just like a diode.

[0081] The first high-side comparator 113 may be implemented as a current mirror including two transistors T1 and T2 as a master transistor and a slave transistor, respectively. Transistor T1 may be coupled to a second resistor R2. Transistor T1 may also be a diode-connected MOSFET or a diode-connected BJT, and thus will inevitably introduce a voltage drop previously referred to as a "second balancing voltage drop" (i.e., the gate-source voltage of the diode-connected transistor T1) to form the second current C2. In response, in addition to the high-side offset voltage drop VOS1, the same amount of voltage drop may be introduced to form the first current C1, thereby keeping the "competition" between the first current C1 and the second current C2 fair, and this is where the high-side OCP signal generator 114 comes into play.

[0082] The high-side OCP signal generator 114 may include an AND gate 114G, a first inverter 114V, and a second high-side comparator 114M coupled to the first high-side comparator 113 and the first inverter 114V, wherein the second high-side comparator 114M may be implemented as another current mirror, which includes two transistors T3 and T4 as a master transistor and a slave transistor, respectively. Transistor T3 may be the same as transistor T1, which means that transistor T3 may also be diode-connected and may cause the same amount of voltage drop. Therefore, transistor T3 may cause a voltage drop to form a first current C1, thereby balancing the voltage drop caused by the diode-connected transistor T1. The voltage drop caused by transistor T3 is previously referred to as a "first balancing voltage drop" and has the same amount as the voltage drop caused by transistor T1.

[0083] The formation of currents C1 and C2 is further described below. Figure 1 and Figure 2 , the first voltage V1 is at approximately the same voltage level (e.g., about 100 volts) as the power supply PS1. The high-side voltage offset element 112 may be used to form or induce a high-side offset voltage drop VOS1 to act as a voltage drop offset by the first voltage V1. A first resistor R1 having a certain resistance value (e.g., 500,000 ohms) may be used to convert a voltage difference between the first voltage V1 and a superposition of the high-side offset voltage drop VOS1 and the first balancing voltage drop into a current form (i.e., a first current C1). On the other hand, a second resistor R2 having a certain resistance value may be used to convert a second voltage V2 into a second current C2. The second resistor R2 may include the same amount of resistance value as the first resistor R1 (e.g., 500,000 ohms).

[0084] Therefore, the current magnitude of the first current C1 and the current magnitude of the second current C2 can be expressed by the following equations:

[0085]

[0086]

[0087] in:

[0088] “I C1 ” represents the current value of the first current C1;

[0089] “I C2 ” represents the current value of the second current C2;

[0090] “V N1 ” represents the voltage level observed at node N1, which is Figure 2 The voltages provided by the power supply PS1 in the case shown are almost the same;

[0091] “VN2 ” represents the voltage level observed at node N2 and is equal to “V N1 Subtract the voltage drop V caused by the upper bridge power element 21 DS ”;

[0092] “V OS1 ” represents the voltage across the high-voltage side voltage shift element 112;

[0093] “V t ” respectively means “I C1 ” and “I C2 "A first equilibrium pressure drop and a second equilibrium pressure drop;

[0094] “R R1 ” represents the resistance value of the first resistor R1; and

[0095] “R R2 ” represents the resistance value of the second resistor R2.

[0096] It should be noted that the first voltage V1 and the second voltage V2 indicate a high voltage (e.g., about 100 volts) due to the high voltage power supply PS1, and therefore cannot be directly measured and compared by a conventional low voltage controller that only allows, for example, about 5 volts to 10 volts, not to mention the mechanism for triggering the high-side OCP. To overcome this problem, the first resistor R1 (cooperating with the high-side voltage shift element 112) and the second resistor R2 of the high-side V2I converter 111 can be used as a clamping mechanism to ensure that the remaining components of the high-side overcurrent detection circuit 11 can work well in the low voltage domain.

[0097] The high side offset voltage drop VOS1 can be generally regarded as a voltage drop caused by the upper bridge power element 21 (ie, “V DS That is, when the voltage drop caused by the upper bridge power element 21 is greater than the voltage drop caused by the high-side voltage shift element 112, a high-side overcurrent event can be detected (for example, the current C01 is about 100 amps at this time), which means that the current flowing to the load L1 is abnormally large at this time.

[0098] The first high-side comparator 113 can be used to compare the first current C1 with the second current C2 and generate / output an output CS11 accordingly. Specifically, the transistor T1 can be coupled in series with the second resistor R2 to receive the second current C2, and the transistor T2 can be coupled in series with the high-side voltage shift element 112 to receive the first current C1. Utilizing the function of the current mirror, the second current C2 can be copied from the current input end of the current mirror to the current output end of the current mirror. Therefore, the first current C1 and the sensed / copied second current C2 intersect and "compete" at a node N3 between the high-side voltage shift element 112 and the transistor T2, and together form the output CS11 of the first high-side comparator 113 at the node N3. In other words, the output CS11 of the first high-side comparator 113 is equal to "the first current C1 minus the second current C2".

[0099] In some embodiments, there may be another transistor T0 coupled between the second resistor R2 and the transistor T1, and the gate of the transistor T0 is controlled by the upper bridge control signal UG. When the lower bridge power element 22 is turned on (i.e., the upper bridge power element 21 is turned off), the upper bridge control signal UG will also turn off the transistor T0. Therefore, the transistor T0 can prevent the current C02 from flowing to the high-voltage side overcurrent detection circuit 11 during the period when the lower bridge power element 22 is turned on.

[0100] like Figure 2 As shown, when the first current C1 is stronger than the second current C2, there will be a current flowing from the node N3 to the high-side OCP signal generator 114 of the electronic device 1, and therefore, the output CS11 of the first high-side comparator 113 presents a logic high potential. On the contrary, when the first current C1 is weaker than the second current C2, there will be a current flowing from the high-side OCP signal generator 114 to the node N3, and therefore, the output CS11 of the first high-side comparator 113 presents a logic low potential.

[0101] The output CS11 of the first high-side comparator 113 can indicate to some extent whether a high-side overcurrent event has been detected. More specifically, based on equations 1 and 2, the comparison between the first current C1 and the second current C2 can be further represented by the following equation:

[0102]

[0103] When "R R1 ” is equal to “R R2 ”, we can further draw the following conclusion: “I C1 ” and “I C2 The difference between the two will become the same as "V DS ” (i.e., the voltage drop caused by the upper bridge power element 21) and “V OS1” (i.e., the voltage drop caused by the high-side voltage offset element 112). In this case, “I C1 " is greater than "I C2 " means "V DS " is greater than "V OS1 ”, which further means that the voltage drop caused by the upper bridge power element 21 is greater than the predetermined threshold value of the voltage drop represented by the high-side offset voltage drop VOS1. This means that too much current has flowed through the upper bridge power element 21 and is then supplied to the load L1.

[0104] It should be noted that even when “R R1 " is not equal to "R R2 ”, “I C1 ” and “I C2 "The difference between them can still represent "V OS1 ” and “V DS ", and those skilled in the art to which the present invention belongs can determine how to make specific adjustments based on Equation 3 and the above related instructions.

[0105] The second high-side comparator 114M can be used to compare the output CS11 of the first high-side comparator 113 with a first reference current of a first reference current source RC1 and provide an output CS12 for an input of the first inverter 114V. To this end, the transistor T3 can provide a current input terminal of the current mirror, and the current input terminal is coupled to the node N3 to receive the output CS11 of the first high-side comparator 113. Using the function of the current mirror, the output CS11 of the first high-side comparator 113 can be copied from the current input terminal of the current mirror to the current output terminal of the current mirror provided by the transistor T4. In addition, the transistor T4 can be coupled in series with the first reference current source RC1 to receive the first reference current. Therefore, the output CS11 of the first high-side comparator 113 and the first reference current meet and "compete" at a node N4, and together form the output CS12 of the second high-side comparator 114M as the input of the first inverter 114V. In other words, the output CS12 of the second high-side comparator 114M is equal to the first reference current minus the output CS11 of the first high-side comparator 113 .

[0106] like Figure 2As shown, when the first reference current is stronger than the output CS11 of the first high-side comparator 113, the output CS12 of the second high-side comparator 114M will present a logic high potential, and when the first reference current is weaker than the output CS11 of the first high-side comparator 113, the output CS12 of the second high-side comparator 114M will present a logic low potential. Therefore, when the output CS12 of the second high-side comparator 114M presents a logic low potential, that is, when the output CS11 of the first high-side comparator 113 is stronger than the first reference current, the output of the first inverter 114V presents a logic high potential.

[0107] The output signal of the first inverter 114V can be provided to the AND gate 114G as one of the inputs of the AND gate 114G, and the upper bridge control signal UG can be provided as the other input of the AND gate 114G. When both the output signal of the first inverter 114V and the upper bridge control signal UG are at a logic high level, the high-side OCP signal HS1 will present a logic high level, and will trigger the driver 3 to correspondingly turn off the upper bridge power element 21 to achieve over-current protection.

[0108] In some embodiments, the upper bridge control signal UG may be debounced within a certain period (e.g., 100 nanoseconds) to avoid misjudging an overcurrent event in the initial stage of the upper bridge. More specifically, for high-side overcurrent detection, debounce of the upper bridge control signal UG needs to include setting the voltage between the drain and source of the transistor. For example, Figure 2 In the system shown, the first voltage V1 provided by the power supply PS1 is about 100 volts, and the second voltage V2 will rise from 0 volts to 100 volts. According to different system configurations, the anti-shake time should be able to cover the slew rate of the difference between the second voltage V2 from 0 volts to at least 100 volts and "I*RDS" (i.e., the product of the current flowing through the upper bridge power element 21 and the voltage of the upper bridge power element), and the anti-shake time may exceed 100 nanoseconds or be around 100 nanoseconds. The anti-shake time can be fine-tuned according to different types of applications.

[0109] The first reference current provided by the first reference current source RC1 as described above can serve as an additional threshold value for determining whether a high-side overcurrent event occurs. In this case, when not only the first current C1 is stronger than the second current C2, but also the output CS11 of the first high-side comparator 113 (also referred to as the difference between the first current C1 and the second current C2) is stronger than the first reference current (for example, 1 microampere (uA) when the resistance value of the first resistor R1 is 500,000 ohms), a high-side overcurrent event will be detected. This means that the threshold value for evaluating / estimating the voltage drop caused by the upper bridge power element 21 is adjusted from "only the high-side offset voltage drop VOS1" to "the voltage drop caused by the first reference current (cooperating with the first resistor R1) plus the high-side offset voltage drop VOS1", which can be represented by the following equation:

[0110] V DSI1 =V oS1 +V RE1 ×R R1 =V OS1 +V ADJ1 (Equation 4)

[0111] in:

[0112] “V DSI1 ” represents the threshold value of the voltage drop of the upper bridge power element 21;

[0113] “V OS1 ” represents the voltage drop caused by the high-side voltage shift element 112;

[0114] “I RE1 ” represents the current value of the first reference current;

[0115] “R R1 ” represents the resistance value of the first resistor R1; and

[0116] “V ADJ1 " indicates that "I RE1 ” and “R R1 ” caused by the pressure drop.

[0117] It can be seen from equation 4 that as the threshold is increased by the first reference current, the voltage drop caused by the upper bridge power device 21 (ie, V DS ) needs to be greater than the voltage drop in the past when there is no threshold adjustment mechanism, unless the first reference current is set to only slightly above 0 amps. In some embodiments, the voltage drop caused by the first reference current and the first resistor R1 (i.e., “V ADJ1”) can typically be set to, for example but not limited to, 2 volts, while in some other embodiments, the voltage drop caused by the first reference current and the first resistor R1 can be set to a bare minimum value (i.e., just slightly above 0 volts), thereby making it almost impossible to further adjust the threshold value of the voltage drop.

[0118] As previously described, depending on different implementations, the voltage shift element 112 may include a single transistor, or a plurality of transistors coupled in series in some embodiments. However, in some other embodiments, the voltage shift element 112 may instead include a shift resistor, such as Figure 3 According to different implementations, the offset resistor may be a single resistor or a combination of multiple resistors coupled in series.

[0119] Figure 3 Draw Figure 2 A schematic diagram of an alternative scheme of the high-voltage side overcurrent detection circuit 11 of the electronic device in FIG. Figure 3 The high-side offset voltage drop VOS1 can be provided by the offset resistor and an additional offset current C10 flowing through the offset resistor, because the voltage across a circuit is equal to the product of the current flowing through the circuit and the resistance value of the circuit. The resistance value of the offset resistor can be determined based on the estimated voltage drop caused by the upper bridge power element 21 taking into account the offset current C10.

[0120] Since the offset current C10 is added, the current magnitude of the first current C1 can be adjusted according to the following equation:

[0121]

[0122] in:

[0123] “I C1 ” represents the current value of the first current C1;

[0124] “V N1 ” represents the voltage level observed at node N1, which is Figure 2 In the case shown the voltages provided by the power supply PS1 are almost the same;

[0125] “V OS1 ” represents the voltage drop caused by the voltage shift element 112;

[0126] “V t ” indicates the first equilibrium pressure drop;

[0127] “R R1 ” represents the resistance value of the first resistor R1; and

[0128] “I OS ” represents the magnitude (current value) of the offset current C10.

[0129] In response to adding the offset current C10 to the first current C1, an equal amount of current is also added to the second current C2 described in equation 2. This ensures that the comparison between the first current C1 and the second current C2 remains equal. Therefore, the current magnitude of the second current C2 can also be adjusted according to the following equation:

[0130]

[0131] in:

[0132] “I C2 ” represents the current value of the second current C2;

[0133] “V N2 ” represents the voltage level observed at node N2 and is equal to “V N1 ” minus the voltage drop caused by the upper bridge power element 21 “V DS ”;

[0134] “V t ” represents the second equilibrium pressure drop;

[0135] “R R2 ” represents the resistance value of the second resistor R2; and

[0136] “I OS ” represents the current value of the offset current C10.

[0137] Figure 4 Draw Figure 1 A schematic diagram of a feasible structure of a low-voltage side overcurrent detection circuit 12 of an electronic device in FIG. Figure 1 and Figure 4 Secondly, the low-voltage side overcurrent detection circuit 12 can be coupled with the lower bridge power element 22 of the power stage 2 to monitor the current C02 flowing through the lower bridge power element 22 when the lower bridge power element 22 is turned on (i.e., the upper bridge power element 21 is turned off), thereby enabling the lower bridge power element 22 to be turned off in a timely manner after a low-voltage side overcurrent event occurs.

[0138] The low-side overcurrent detection circuit 12 may include a low-side V2I converter 121 coupled to the lower bridge power element 22, a low-side voltage offset element 122 coupled to the low-side V2I converter 121, a low-side comparator 123 coupled to the low-side voltage offset element 122, and an output (i.e., Figure 4 A node N6 is shown coupled to a low-side OCP signal generator 124.

[0139] The low-side voltage offset element 122 can be used to induce a low-side offset voltage drop VOS2, and the low-side V2I converter 121 can be used to convert the low-side power element 22 at an input terminal (ie, at Figure 4 The voltage difference between a third voltage V3 observed at a node N5 (shown in FIG. 1 ) and the low-side offset voltage drop VOS2 is converted into a third current C3. The low-side V2I converter 121 may include a third resistor R3 coupled to the low-side voltage offset element 122. According to different implementations, the third resistor R3 may be a single resistor, or a combination of multiple resistors coupled in series. The low-side offset voltage drop VOS2 may be induced / formed based on the low-side voltage offset element 122, and the third resistor R3 having a certain resistance value (e.g., 1,000 ohms) may be used to convert the voltage difference between the low-side offset voltage drop VOS2 and the third voltage V3 into the third current C3.

[0140] The current value of the third current C3 can be expressed by the following equation:

[0141]

[0142] in:

[0143] “I C3 ” represents the current value of the third current C3;

[0144] “V N5 ” represents the voltage level observed at the node N5 (ie, the third voltage V3);

[0145] “V OS2 ” represents the voltage drop caused by the low voltage side voltage shifting element 122; and

[0146] “R R3 ” represents the resistance value of the third resistor R3.

[0147] In some embodiments, the low-side voltage offset element 122 may include one or more transistors coupled in series, just like the high-side voltage offset element 112. In some embodiments, the low-side voltage offset element 122 and the low-side comparator 123 may share a common Figure 4 When the low-side voltage offset element 122 and the low-side comparator 123 share the transistor T5, the gate-source voltage of the transistor T5 (eg, about 0.7 volts) may include the voltage “V OS2 ”. Each transistor of the low-side voltage shifting element 122 and the transistor T5 may be a diode-connected MOSFET or a diode-connected BJT.

[0148] In some embodiments, the low-side V2I converter 121 can use the second resistor R2 of the high-side V2I converter 111 as the third resistor R3 because the two circuits work alternately in a time-wise manner. It should be noted that when the high-side V2I converter 111 and the low-side V2I converter 121 share the second resistor R2, the resistance value “R R3 ” is equal to “R” in Equation 2, Equation 3 and Equation 6 R2 ”.

[0149] The low-side comparator 123 can generally be used to compare the third current C3 with a second reference current provided by a second reference current source RC2. In some embodiments, like the first high-side comparator 113 and the second high-side comparator 114M, the low-side comparator 123 can also be implemented as a current mirror, which includes two transistors T5 and T6 as a master transistor and a slave transistor, respectively. Transistor T5 can be coupled in series with the low-side voltage shift element 122 to receive the third current C3. Using the function of the current mirror, the third current C3 can be copied from the current input end of the current mirror (provided by transistor T5) to the current output end of the current mirror (provided by transistor T6). In addition, transistor T6 can be coupled in series with the second reference current source RC2 to receive the second reference current. Therefore, the third current C3 and the second reference current intersect and "compete" at the node N6, and together form an output CS2 of the low-side comparator 123 at the node N6. In other words, the output CS2 of the low-side comparator 123 is equal to the second reference current minus the third current C3.

[0150] The low-side comparator 123 can provide an output CS2 according to the "competition" result at the node N6. Specifically, when the second reference current at the node N6 is stronger than the third current C3, the output CS2 of the low-side comparator 123 will present a logic high potential. When the third current C3 at the node N6 is stronger than the second reference current, the output CS2 of the low-side comparator 123 will present a logic low potential.

[0151] The low-side OCP signal generator 124 may include a second inverter 124V and a second AND gate 124G. The second inverter 124V may be coupled to the low-side comparator 123 at the node N6, and the second AND gate 124G may be coupled to an output of the second inverter 124V and the low-bridge control signal terminal of the low-bridge power element 22. When a low-side overcurrent event is detected, the second AND gate 124G may output a low-side OCP signal LS1 having a logic high potential, thereby causing the driver 3 to turn off the low-bridge power element 22.

[0152] like Figure 4As shown, when the lower bridge control signal LG presents a logic high level and the output CS2 of the low voltage side comparator 123 presents a logic low level, the low voltage side OCP signal LS1 will present a logic high level. In some embodiments, the lower bridge control signal LG may be de-jittered within a certain period (e.g., 100 nanoseconds) to avoid misjudging a low voltage side overcurrent event at the initial stage of the lower bridge.

[0153] The output CS2 of the low-side comparator 123 is a logic low level, which not only means that the third voltage V3 is stronger than the low-side offset voltage drop VOS2, but also means that the third current C3 is stronger than the second reference current of the second reference current source RC2. This generates two threshold values ​​for determining whether a low-side overcurrent event occurs, namely, the low-side offset voltage drop VOS2 and the second reference current.

[0154] When a low voltage side overcurrent (or short circuit) event has been detected, at the input terminal of the lower bridge power element 22 (i.e., at Figure 4 The voltage level observed at the node N5 (shown in FIG. 1 ) (which should remain low to near the ground level) will be pulled up to an undesirable high level, such as close to the voltage level of the power supply PS1. Therefore, even during the period when the upper bridge power element 21 is turned off, there may be an undesirable current output to the load L1. The low-side offset voltage drop VOS2 (e.g., 1.4 volts, which is equal to twice the gate-source voltage) can serve as a threshold value for estimating the voltage level observed at the node N5.

[0155] As for the second reference current, in some embodiments, it can be set to a minimum value (e.g., just slightly above 0 amperes) for triggering the function of the low-side comparator 123, thereby determining a low-side overcurrent event based only on the third current C3. However, in some other embodiments, like the first reference current source RC1, the second reference current can act as an adjustment mechanism for the threshold value to determine whether a low-side overcurrent event occurs. In this case, when the third current C3 is stronger than the second reference current (e.g., 1 microampere when the resistance value of the second resistor R2 or the third resistor R3 is 500,000 ohms), a low-side overcurrent event will be detected. This means that the threshold value for evaluating / estimating the voltage level at the lower bridge power element 22 is adjusted from "only the low-side offset voltage drop VOS2" to "the low-side offset voltage drop VOS2 plus the voltage drop caused by the second reference current (cooperating with the third resistor R3)", which can be represented by the following equation:

[0156] V DSI2 =V OS2 +I RE2 ×R R3 =V OS2 +V ADJ2 (Equation 8)

[0157] in:

[0158] “V DSI2 ” represents the threshold value of the voltage level observed at the node N5;

[0159] “V OS2 ” represents the voltage drop caused by the low voltage side voltage shift element 122;

[0160] “I RE2 ” represents the current value of the second reference current;

[0161] “R R3 ” represents the resistance value of the third resistor R3; and

[0162] “V ADJ2 " indicates that "I RE2 ” and “R R3 ” caused by the pressure drop.

[0163] It should be noted that in the embodiment where the high-side V2I converter 111 and the low-side V2I converter 121 share the second resistor R2, the resistance value “R R3 ” is also equal to “R” in Equation 2, Equation 3 and Equation 6 R2 ”.

[0164] In some embodiments, the electronic device 1, the power stage 2 and the driver 3 may be implemented in the same package, which may be implemented based on technologies such as wafer level fan-out (WLFO) packaging, low thermal resistance thermal conductive lead frame, additional substrate, etc.

[0165] Based on the above description, the electronic device 1 disclosed in the present invention provides a good method for implementing high-voltage side overcurrent detection and protection and low-voltage side overcurrent detection and protection, and both high-voltage side overcurrent detection and protection and low-voltage side overcurrent detection and protection can be achieved through level shifting and V2I mechanisms in low-voltage hardware.

[0166] As disclosed herein, resistors are used to withstand and cope with high voltage levels, thereby enabling the high-side overcurrent detection circuit 11 and the low-side overcurrent detection circuit 12 of the electronic device 1 of the present disclosure to smoothly shift the high voltage level applied to the upper bridge power element 21 to a low voltage domain. Therefore, the voltage applied to the electronic device 1 can be clamped at a low voltage level, thereby enabling the components of the electronic device 1 to operate well in the low voltage domain.

[0167] As disclosed herein, a V2I mechanism is used to convert the relevant voltages used to determine whether an overcurrent event occurs into currents (i.e., the first current C1, the second current C2, and the third current C3), and thus, overcurrent detection and protection can be achieved in a current form rather than a voltage form. The proposed method is far superior to the conventional method of using a partial voltage signal for overcurrent detection and protection because when attempting to shift a high voltage signal (e.g., 100 volts) to a low voltage signal (5 volts) and when the voltage difference of the high voltage signal is very small (e.g., 2 millivolts between 100 volts and 98 volts), the proposed method can prevent the target voltage difference from being "diluted" to a partial voltage that is too small to be implemented. The conversion and comparison of the current implemented in the present disclosure jointly "reflect" the condition of the voltage drop caused by the upper bridge power element 21 (i.e., whether it is the case) (as shown in the above equation 5), and the offset mechanism implemented in the present disclosure ensures the comparison between the voltage drop caused by the upper bridge power element 21 and the threshold value, thereby achieving an OCP effect based on current comparison.

[0168] Figure 5 An overcurrent detection method according to one or more embodiments of the present disclosure is illustrated. Figure 5 , the overcurrent detection method 5 (referred to as "method 5") may include the following steps:

[0169] A high-side voltage offset element induces a high-side offset voltage drop (marked as step 501);

[0170] Converting a voltage difference between a first voltage drop and a first voltage at an input terminal of an upper bridge power element of a power stage into a first current by a high-side voltage-to-current (V2I) converter, wherein the first voltage drop is a superposition of a first balancing voltage drop caused by a high-side OCP signal generator and a high-side offset voltage drop (marked as step 502);

[0171] The high-side V2I converter converts a voltage difference between a second voltage at an output terminal of the upper bridge power element and a second balancing voltage drop caused by a first high-side comparator into a second current, wherein the first high-side comparator is coupled to the high-side V2I converter (marked as step 503);

[0172] Comparing the first current with the second current by a first high-side comparator (labeled as step 504); and

[0173] The high-side OCP signal generator generates a high-side OCP signal with a logic high level for a driver of the power stage when the first current is stronger than the second current, thereby causing the driver to turn off the upper bridge power element accordingly (marked as step 505).

[0174] In some embodiments, regarding method 5, the voltage difference between the first voltage and the superposition of the high-side offset voltage drop and the first balancing voltage drop can be converted into a first current via a first resistor of the high-side V2I converter, and the first resistor is coupled to the high-side voltage offset element. In addition, the second voltage is converted into a second current via a second resistor of the high-side V2I converter, and the second resistor is coupled to the output end of the upper bridge power element and the first high-side comparator. In some embodiments, the first high-side comparator can also be a first current mirror, and the first current mirror can also include a first transistor coupled to the second resistor and a second transistor coupled to the high-side voltage offset element, and the second balancing voltage drop can be induced by the first transistor.

[0175] In some embodiments, regarding method 5, the voltage difference between the first voltage and the superposition of the high-side offset voltage drop and the first balancing voltage drop can be converted into a first current via a first resistor of the high-side V2I converter, and the first resistor is coupled to the high-side voltage offset element. In addition, the second voltage is converted into a second current via a second resistor of the high-side V2I converter, and the second resistor is coupled to the output end of the upper bridge power element and the first high-side comparator. In addition, in some embodiments, the high-side voltage offset element may further include at least one diode-connected metal oxide semiconductor field effect transistor or at least one diode-connected bipolar junction transistor to induce the high-side offset voltage drop.

[0176] In some embodiments, regarding method 5, the voltage difference between the first voltage and the superposition of the high-side offset voltage drop and the first balancing voltage drop can be converted into a first current via a first resistor of the high-side V2I converter, and the first resistor is coupled to the high-side voltage offset element. In addition, the second voltage is converted into a second current via a second resistor of the high-side V2I converter, and the second resistor is coupled to the output end of the upper bridge power element and the first high-side comparator. In addition, in some embodiments, the high-side voltage offset element may further include an offset resistor, and the high-side offset voltage drop is induced by an offset current flowing through the offset resistor, and the first current and the second current may each include an offset current.

[0177] In some embodiments, regarding method 5, the voltage difference between the first voltage and the superposition of the high-side offset voltage drop and the first balancing voltage drop can be converted into a first current via a first resistor of the high-side V2I converter, and the first resistor is coupled to the high-side voltage offset element. In addition, the second voltage is converted into a second current via a second resistor of the high-side V2I converter, and the second resistor is coupled to the output end of the upper bridge power element and the first high-side comparator. In some embodiments, method 5 may further include the following steps: "a second high-side comparator of a high-side OCP signal generator compares an output of the first high-side comparator with a first reference current of a first reference current source"; "a second high-side comparator provides an output of the second high-side comparator to an input of a first inverter of the high-side OCP signal generator, wherein the first inverter is coupled to the second high-side comparator, and when the output of the first high-side comparator is stronger than the first reference current, the output of the second high-side comparator is a logic low potential; and "a first AND gate of the high-side OCP signal generator outputs a high-side OCP signal with a logic high potential, thereby causing the driver to turn off the upper bridge power element, wherein the first AND gate is coupled to an output of the first inverter and an upper bridge control signal terminal of the upper bridge power element". In addition, in some embodiments, the second high-side comparator may be a second current mirror, and the second current mirror may include a third transistor coupled to the second transistor of the first current mirror and a fourth transistor coupled to the first reference current source, thereby making the output of the first high-side comparator and the first reference current jointly form the output of the second high-side comparator.

[0178] In some embodiments, method 5 may further include the following steps: "causing a low-side offset voltage drop by a low-side voltage offset element coupled to the low-side comparator"; "converting a voltage difference between the low-side offset voltage drop and a third voltage at an input terminal of a lower bridge power element of the power stage into a third current by a low-side V2I converter, the low-side V2I converter being coupled to the low-side voltage offset element and the lower bridge power element"; and "comparing the third current with a second reference current by a low-side comparator coupled to the low-side V2I converter, and generating an output representing that a low-side overcurrent event has been detected when the third current is stronger than the second reference current, thereby causing the driver to shut down the lower bridge power element". In addition, in some further embodiments, method 5 may further include the following steps: "outputting a low-side OCP signal having a logic high potential by a second AND gate of a low-side OCP signal generator, thereby causing the driver to shut down the lower bridge power element accordingly". In such further embodiments, the second AND gate may be coupled to an output of a second inverter of the low-voltage side OCP signal generator and a low-bridge control signal terminal of the low-bridge power element, and the second inverter may be coupled to the low-voltage side comparator to receive the output of the low-voltage side comparator, wherein when the third current is stronger than the second reference current, the output of the low-voltage side comparator is a logic low voltage.

[0179] Each embodiment of method 5 substantially corresponds to a specific embodiment of electronic device 1. Therefore, even if all embodiments of method 5 are not described in detail above, those skilled in the art to which the present invention belongs can fully understand and implement all corresponding embodiments of method 5 only by referring to the above description of electronic device 1.

[0180] The above disclosure is about the detailed technical content and inventive features of the present disclosure. A person skilled in the art may make various modifications and substitutions based on the disclosure and suggestions of the present invention described without departing from the characteristics of the present invention. However, although such modifications and substitutions are not fully disclosed in the above description, they are essentially covered by the following attached claims.

Claims

1. An electronic device for overcurrent detection, comprising a high-side voltage-to-current (V2I) converter, a high-side voltage offset element, a first high-side comparator, and a high-side overcurrent protection (OCP) signal generator, wherein: The high-side voltage offset element is coupled to the high-side V2I converter and the first high-side comparator, and the high-side voltage offset element is used to induce a high-side offset voltage drop; The high-side V2I converter is used to: Converting a voltage difference between a first voltage drop and a first voltage at an input end of an upper bridge power element of the power stage into a first current, wherein the first voltage drop is a superposition of the high-side offset voltage drop and a first balancing voltage drop caused by the high-side OCP signal generator; and Converting a voltage difference between a second voltage at the output end of the upper bridge power element and a second balanced voltage drop caused by the first high-side comparator into a second current; The first high-side comparator is coupled to the high-side V2I converter, and the first high-side comparator is used to compare the first current with the second current; and The high-side OCP signal generator is coupled to the first high-side comparator, and is used to generate a high-side OCP signal with a logic high potential when the first current is stronger than the second current, thereby allowing the driver of the power stage to turn off the upper bridge power element accordingly.

2. The electronic device according to claim 1, wherein: The high-side V2I converter contains: A first resistor is coupled to the high-side voltage offset element and the input end of the upper bridge power element, and the first resistor is used to convert a voltage difference between a second voltage drop and the first voltage into the first current, wherein the second voltage drop is a superposition of the high-side offset voltage drop and the first balance voltage drop; as well as The second resistor is coupled to the output end of the upper bridge power element and the first high-side comparator, and is used to convert the voltage difference between the second voltage and the second balanced voltage drop into the second current.

3. The electronic device as claimed in claim 2, wherein: The first high-side comparator is a first current mirror, and the first current mirror includes a first transistor coupled to the second resistor and a second transistor coupled to the high-side voltage offset element; and The second balancing voltage drop is caused by the first transistor.

4. The electronic device as claimed in claim 2, wherein: The high-side voltage offset element includes at least one diode-connected metal oxide semiconductor field effect transistor or at least one diode-connected bipolar junction transistor, thereby inducing the high-side offset voltage drop.

5. The electronic device as claimed in claim 2, wherein: The high-side voltage offset element includes an offset resistor, and the high-side offset voltage drop is induced by an offset current flowing through the offset resistor; and The first current and the second current each include the offset current.

6. The electronic device as claimed in claim 3, wherein: The high-side OCP signal generator includes: A first inverter; a second high-side comparator coupled to the first high-side comparator and the first inverter, the second high-side comparator being used to compare the output of the first high-side comparator with a first reference current of a first reference current source, and provide the output of the second high-side comparator to the input of the first inverter, wherein when the output of the first high-side comparator is stronger than the first reference current, the output of the second high-side comparator is a logic low potential; and The first AND gate is coupled to the output of the first inverter and the upper bridge control signal terminal of the upper bridge power element, and the first AND gate is used to output the high-voltage side OCP signal with a logic high potential, thereby allowing the driver to turn off the upper bridge power element.

7. The electronic device as claimed in claim 6, wherein: The second high-side comparator is a second current mirror, and the second current mirror includes a third transistor coupled to the second transistor of the first current mirror and a fourth transistor coupled to the first reference current source, so that the output of the first high-side comparator and the first reference current together constitute the output of the second high-side comparator; and The first balancing voltage drop is caused by the third transistor.

8. The electronic device as claimed in claim 1, further comprising: A low-voltage side voltage offset element for inducing a low-voltage side offset voltage drop; A low-side V2I converter is coupled to the low-side voltage offset element and the lower bridge power element of the power stage, and the low-side V2I converter is used to convert a voltage difference between the low-side offset voltage drop and a third voltage at the input end of the lower bridge power element into a third current; A low-voltage side comparator coupled to the low-voltage side V2I converter, the low-voltage side comparator being used to compare the third current with a second reference current; as well as The low-voltage side OCP signal generator is coupled to the low-voltage side comparator and is used to generate a low-voltage side OCP signal of a logic high potential when the third current is stronger than the second reference current, thereby causing the driver to turn off the lower bridge power element.

9. The electronic device as claimed in claim 8, wherein: The low voltage side OCP signal generator comprises: a second inverter coupled to the low-side comparator to receive an output of the low-side comparator, wherein when the third current is stronger than the second reference current, the output of the low-side comparator is a logic low potential; and A second AND gate is coupled to the output of the second inverter and the lower bridge control signal end of the lower bridge power element. The second AND gate is used to output the low-voltage side OCP signal of a logic high potential when the third current is stronger than the second reference current and the lower bridge control signal at the lower bridge control signal end is a logic high potential, thereby causing the driver to shut down the lower bridge power element.

10. A method for overcurrent detection, comprising the following steps: A high-side offset voltage drop is caused by a high-side voltage offset element; The voltage difference between the first voltage drop and the first voltage at the input end of the upper bridge power element of the power stage is converted into a first current by a high-side voltage-to-current (V2I) converter, wherein: The first voltage drop is a superposition of the high-side offset voltage drop and a first balancing voltage drop caused by a high-side over-current protection (OCP) signal generator; The high-side V2I converter converts a voltage difference between a second voltage at the output end of the upper bridge power element and a second balanced voltage drop caused by a first high-side comparator into a second current, and the first high-side comparator is coupled to the high-side V2I converter; comparing the first current and the second current by the first high-side comparator; and When the first current is stronger than the second current, the high-side OCP signal generator generates a high-side OCP signal with a logic high potential for the driver of the power stage, thereby allowing the driver to turn off the upper bridge power element accordingly.

11. The method of claim 10, wherein: A voltage difference between a second voltage drop and the first voltage is converted into the first current by a first resistor in the high-side V2I converter, wherein the second voltage drop is a superposition of the high-side offset voltage drop and the first balancing voltage drop, and the first resistor is coupled to the high-side voltage offset element; and The voltage difference between the second voltage and the second balanced voltage drop is converted into the second current by a second resistor in the high-side V2I converter, wherein the second resistor is coupled to the output end of the upper bridge power element and the first high-side comparator.

12. The method of claim 11, wherein: The first high-side comparator is a first current mirror, and the first current mirror includes a first transistor coupled to the second resistor and a second transistor coupled to the high-side voltage offset element; and The second balancing voltage drop is caused by the first transistor.

13. The method of claim 11, wherein: The high-side voltage offset element includes at least one diode-connected metal oxide semiconductor field effect transistor or at least one diode-connected bipolar junction transistor, thereby inducing the high-side offset voltage drop.

14. The method of claim 11, wherein: The high-side voltage offset element includes an offset resistor, and the high-side offset voltage drop is induced by an offset current flowing through the offset resistor; and The first current and the second current each include the offset current.

15. The method of claim 12, further comprising: The second high-side comparator of the high-side OCP signal generator compares the output of the first high-side comparator with the first reference current of the first reference current source; The second high-side comparator provides an output of the second high-side comparator to an input of a first inverter of the high-side OCP signal generator, wherein the first inverter is coupled to the second high-side comparator, and when the output of the first high-side comparator is stronger than the first reference current, the output of the second high-side comparator is a logic low potential; and The high-side OCP signal having a logic high potential is outputted by the first AND gate of the high-side OCP signal generator, thereby allowing the driver to turn off the upper bridge power element, wherein, The first AND gate is coupled to the output of the first inverter and the upper bridge control signal terminal of the upper bridge power element.

16. The method of claim 15, wherein: The second high-side comparator is a second current mirror, and the second current mirror includes a third transistor coupled to the second transistor of the first current mirror and a fourth transistor coupled to the first reference current source, so that the output of the first high-side comparator and the first reference current together constitute the output of the second high-side comparator; and The first balancing voltage drop is caused by the third transistor.

17. The method of claim 10, further comprising: A low-voltage side offset voltage drop is caused by a low-voltage side voltage offset element; The voltage difference between the low-voltage side offset voltage drop and the third voltage at the input end of the lower bridge power element of the power stage is converted into a third current by the low-voltage side V2I converter, wherein: The low-side V2I converter is coupled to the low-side voltage offset element and the lower bridge power element; The third current is compared with a second reference current by a low-voltage side comparator, wherein the low-voltage side comparator is coupled to the low-voltage side V2I converter; as well as The low-side comparator generates an output indicating that a low-side overcurrent event has been detected when the third current is stronger than the second reference current, thereby causing the driver to shut down the low-bridge power device.

18. The method of claim 17, further comprising: The second AND gate of the low-voltage side OCP signal generator outputs a low-voltage side OCP signal of a logic high potential, thereby causing the driver to correspondingly turn off the lower bridge power element; in, The second AND gate is coupled to the output of the second inverter of the low-voltage side OCP signal generator and the low-bridge control signal terminal of the low-bridge power element, and the second inverter is coupled to the low-voltage side comparator to receive the output of the low-voltage side comparator, wherein when the third current is stronger than the second reference current, the output of the low-voltage side comparator is a logic low potential.

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