Control circuit, power chip and electronic device for switching power supply upper tube

Abstract

The present disclosure provides a control circuit, a power chip and an electronic device for a switching power supply upper tube, and relates to the field of power drive technology, wherein the control circuit includes a first logic control module, a second logic control module and an RS trigger. The first logic control module is connected to the signal feedback point of the second logic control module to generate an S-terminal signal. When the upper tube control signal changes from a low level to a high level, the first logic control module determines the level of the generated S-terminal signal according to the level of the signal feedback point. The second logic control module generates an R-terminal signal. When the duration of the high level of the upper tube control signal exceeds a set threshold, the signal feedback point changes from a low level to a high level, and when the upper tube control signal changes from a high level to a low level, the R-terminal signal changes from a low level to a high level. The RS trigger controls the working state of the upper tube of the switching power supply according to the S-terminal signal and the R-terminal signal. The control circuit can prevent the upper tube of the switching power supply from being constantly turned on due to abnormally short pulses of the upper tube control signal.

Description

Technical Field

[0001] The present disclosure relates to the field of power drive technology, and in particular to a control circuit, a power chip and an electronic device for a switching power supply upper tube. Background Art

[0002] Power chips are generally designed with an external enable signal (EN signal) to control the startup of the chip. At the same time, the EN signal will control the alternating opening / closing of the field effect transistor inside the chip through the control circuit inside the chip to complete the charging of the inductor device, thereby providing a voltage signal to the peripheral load.

[0003] The internal structure of the power chip in the electronic device is as follows Figure 1 As shown in the figure, the EN signal controls the upper switch power supply tube Q1 and the lower switch power supply tube Q2 to work alternately through the control circuit inside the power chip to complete the charging of the inductor device, thereby supplying power to the external load. In actual applications, the EN signal is prone to abnormal short pulses, causing the upper switch power supply tube Q1 to be abnormally always on, causing abnormal functions of the power chip or even burning. The power chip needs to be redesigned to avoid the problem, which will lead to project delays and increase chip design costs.

[0004] Currently, no effective solution has been proposed to the technical problem that the upper tube Q1 of the switching power supply is abnormally always on due to the abnormal short pulse of the EN signal, resulting in abnormal function of the power chip. Summary of the invention

[0005] The main purpose of the present invention is to provide a control circuit, a power chip and an electronic device for a switching power supply upper tube, so as to solve the technical problem in the related art that the switching power supply upper tube Q1 is abnormally always on due to the abnormal short pulse of the EN signal, resulting in abnormal function of the power chip.

[0006] In order to achieve the above-mentioned object, a first aspect of the present disclosure provides a control circuit of an upper tube of a switching power supply, wherein an input end of the control circuit is connected to an upper tube control signal, an output end of the control circuit is connected to a gate of an upper tube of the switching power supply, and the control circuit comprises a first logic control module, a second logic control module and an RS trigger;

[0007] The first logic control module is connected to a signal feedback point in the second logic control module, and the first logic control module is used to generate an S-terminal signal of the RS trigger according to the upper tube control signal; wherein, when the upper tube control signal changes from a low level to a high level, the first logic control module determines the level of the generated S-terminal signal according to the level of the signal feedback point;

[0008] A second logic control module is configured to generate an R-terminal signal of the RS trigger according to the upper tube control signal; wherein, when the duration of the high level of the upper tube control signal exceeds a set threshold, the signal feedback point changes from a low level to a high level, and then when the upper tube control signal changes from a high level to a low level, the R-terminal signal generated by the second logic control module changes from a low level to a high level; and,

[0009] The RS trigger is used to control the working state of the upper tube of the switching power supply according to the S-terminal signal and the R-terminal signal.

[0010] Furthermore, the first logic control module includes:

[0011] A first level conversion unit, wherein an input terminal of the first level conversion unit is connected to the upper tube control signal, and is used to perform a first level conversion on the upper tube control signal;

[0012] A feedback signal acquisition unit, wherein the input terminal of the feedback signal acquisition unit is connected to the signal feedback point, and the output terminal of the feedback signal acquisition unit is connected to the third input terminal of the AND gate unit, for acquiring the feedback signal of the signal feedback point; wherein, when the duration of the high level of the upper tube control signal being at the high level is less than the set threshold, the signal feedback point still maintains a low level; and,

[0013] The AND gate unit, wherein the first input end of the AND gate unit is connected to the output end of the first level conversion unit, the second input end of the AND gate unit is connected to the upper tube control signal; and the output end of the AND gate unit is connected to the S end of the RS trigger.

[0014] Furthermore, the second logic control module includes:

[0015] A second level conversion module, wherein an input terminal of the second level conversion module is connected to the upper tube control signal, and is used to perform a second level conversion on the upper tube control signal;

[0016] A NOR gate unit, wherein a first input terminal of the NOR gate unit is connected to an output terminal of the second level conversion module, a second input terminal of the NOR gate unit is connected to the upper tube control signal, and an output terminal of the NOR gate unit is connected to an R terminal of the RS trigger.

[0017] Further, the first level conversion unit includes a first P-channel field effect transistor, a first N-channel field effect transistor, a first resistor, a first capacitor, a first reverse amplifier, and a second reverse amplifier; and the AND gate unit includes a three-input NAND gate device connected in series and a seventh reverse amplifier; wherein,

[0018] The gates of the first P-channel field effect transistor and the first N-channel field effect transistor are connected to the upper tube control signal respectively; the source of the first P-channel field effect transistor is connected to an external power supply; the drain of the first P-channel field effect transistor is divided into three paths, the first path is connected to the drain of the first N-channel field effect transistor via the first resistor, the second path is grounded via the first capacitor, and the third path is connected to the first input end of the three-input NAND gate device after passing through the first reverse amplifier and the second reverse amplifier in sequence; the source of the first N-channel field effect transistor is grounded.

[0019] Further, the second level conversion unit includes a second P-channel field effect transistor, a second N-channel field effect transistor, a second resistor, a second capacitor, a third reverse amplifier, and a fourth reverse amplifier; and the NOR gate unit includes a three-input NOR gate device; wherein,

[0020] The gate of the second P-channel field effect transistor is connected to the upper tube control signal via the third reverse amplifier, the source of the second P-channel field effect transistor is connected to an external power supply, the drain of the second P-channel field effect transistor is divided into three paths, the first path is connected to the drain of the second N-channel field effect transistor via the second resistor, the second path is grounded via the second capacitor, and the third path is connected to the first input terminal of the three-input NOR gate device via the fourth reverse amplifier;

[0021] The gate of the second N-channel field effect transistor is connected to the upper tube control signal via the third reverse amplifier, and the source of the second N-channel field effect transistor is grounded.

[0022] Furthermore, the feedback signal acquisition unit includes a fifth reverse amplifier and a sixth reverse amplifier; wherein,

[0023] The third input terminal of the AND gate unit is connected to the drain of the second P-channel field effect transistor, the input terminal of the second capacitor, and the input terminal of the fourth reverse amplifier respectively after passing through the sixth reverse amplifier and the fifth reverse amplifier in sequence.

[0024] Further, the first resistor and the second resistor have the same resistance value, both are R; the first capacitor and the second capacitor have the same capacitance value, both are C; the first P-channel field effect transistor, the first N-channel field effect transistor, the second P-channel field effect transistor, and the second N-channel field effect transistor have the same internal resistance, both are Rh; and,

[0025] The set threshold is Rh×C;

[0026] The upper tube control signal is a rectangular pulse, and within a pulse cycle, the time period at the high level exceeds Rh×C, and the time period at the low level exceeds R×C.

[0027] The second aspect of the present disclosure provides a power supply chip, comprising the control circuit described in the first aspect of the present disclosure, and a power switch circuit; wherein:

[0028] The power switch circuit is provided with an upper switch power supply tube and a lower switch power supply tube; wherein the gate of the upper switch power supply tube is connected to the output end of the control circuit.

[0029] Furthermore, the power switch circuit also includes an amplifier and a bandgap reference power supply.

[0030] A third aspect of the present disclosure provides an electronic device, comprising the power chip described in the second aspect of the present disclosure.

[0031] In the control circuit provided by the embodiment of the present disclosure, the input of the RS trigger is generated by two logic control modules, and finally a scenario is generated that only responds to the period when the upper tube control signal is at a high level exceeding the set threshold, and a new output signal representing the start-up information and closing is generated for the control of the upper tube of the switching power supply. Therefore, in the scenario of an abnormal short pulse in which the upper tube control signal is at a high level for a period lower than the set threshold, the abnormal short pulse will not be recognized by the control circuit, and the S end of the RS trigger is still maintained in a normal working state, which can normally turn off the upper tube of the switching power supply, and will not cause the upper tube of the switching power supply to be abnormally always on. Therefore, the purpose of preventing signal interference and accurately responding to the upper tube control signal is achieved, thereby achieving the technical effect of accurately controlling the startup and shutdown of the upper tube of the switching power supply according to the upper tube control signal, and further solving the technical problem of abnormal power chip function caused by abnormal short pulse of the EN signal causing abnormal constant opening of the upper tube of the switching power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the specific embodiments of the present disclosure or the technical solutions in the related technologies, the drawings required for use in the specific embodiments or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1 It is a schematic diagram of the internal structure of an existing power chip;

[0034] Figure 2 A schematic diagram of a control circuit provided in an embodiment of the present disclosure;

[0035] Figure 3 A schematic diagram of the composition of a first logic control module provided in an embodiment of the present disclosure;

[0036] Figure 4 A schematic diagram of the composition of a second logic control module provided in an embodiment of the present disclosure;

[0037] Figure 5 A specific example schematic diagram of a control circuit provided in an embodiment of the present disclosure;

[0038] Figure 6 is a comparative circuit diagram of a control circuit of an embodiment of the present disclosure;

[0039] Figure 7 A schematic block diagram of a power chip provided in an embodiment of the present disclosure;

[0040] Figure 8 A schematic diagram of a specific example of a power chip provided in an embodiment of the present disclosure;

[0041] Fig. 9 Another specific example schematic diagram of a power chip provided in an embodiment of the present disclosure;

[0042] Fig.10 A block diagram of an electronic device provided in accordance with an embodiment of the present disclosure.

[0043] Reference numerals

[0044] PMOS1-the first P-channel field effect transistor; NMOS1-the first N-channel field effect transistor;

[0045] PMOS2-the second P-channel field effect transistor; NMOS2-the second N-channel field effect transistor;

[0046] R1-first resistor; C1-first capacitor; R2-second resistor; C2-second capacitor; Rh-internal resistance;

[0047] A1-first reverse amplifier; A2-second reverse amplifier; A3-third reverse amplifier;

[0048] A4-the fourth reverse amplifier; A5-the fifth reverse amplifier; A6-the sixth reverse amplifier;

[0049] A7-the seventh inverting amplifier; B1-a three-input NAND gate device; B2-a three-input NOR gate device;

[0050] Q1-upper tube of switching power supply; Q2-lower tube of switching power supply; HS_gate-output signal; HS_ON-upper tube control signal; P1, P2, P3, P4, P5-sampling points; VCC-external power supply; VIN-input voltage; VOUT-output voltage; L-inductor device; C_OUT-capacitor device; C_BOOT-boost capacitor; C_IN-capacitor device at the input end; D1-first unidirectional diode; D2-second unidirectional diode; Bandgrap-bandgap reference power supply; RS Flip Flop-RS trigger. DETAILED DESCRIPTION

[0051] In order to enable those skilled in the art to better understand the scheme of the present disclosure, the technical scheme in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in the field without creative work should fall within the scope of protection of the present disclosure.

[0052] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0053] In the present disclosure, the terms "upper", "lower", "left", "right", "front", "back", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings. These terms are mainly used to better describe the present disclosure and its embodiments, and are not used to limit the indicated devices, elements or components to have a specific orientation, or to be constructed and operated in a specific orientation.

[0054] In addition, some of the above terms may be used to express other meanings in addition to indicating orientation or positional relationship. For example, the term "on" may also be used to express a certain dependency or connection relationship in some cases. For those of ordinary skill in the art, the specific meanings of these terms in this disclosure can be understood according to specific circumstances.

[0055] In addition, the terms "connect" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0056] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0057] The prior art has a technical problem that the abnormal short pulse of the EN signal causes the upper tube Q1 of the switching power supply to be abnormally always on, resulting in abnormal function of the power chip.

[0058] In order to solve the above technical problems, the present disclosure provides a control circuit for a switching power supply upper tube. Figure 2 As shown, the input end of the control circuit 100 is connected to the upper tube control signal HS_ON, and the output end of the control circuit 100 is connected to the gate of the upper tube Q1 of the switching power supply. The control circuit 100 includes a first logic control module 110, a second logic control module 120, and an RS trigger 130.

[0059] The first logic control module 110 is connected to a signal feedback point in the second logic control module 120. The first logic control module 110 is used to generate an S-terminal signal of the RS trigger 130 according to the upper tube control signal HS_ON. When the upper tube control signal HS_ON changes from a low level to a high level, the first logic control module 110 determines the level of the generated S-terminal signal according to the level of the signal feedback point.

[0060] The second logic control module 120 is used to generate an R-terminal signal of the RS trigger 130 according to the upper tube control signal HS_ON. When the duration of the high level of the upper tube control signal HS_ON exceeds the set threshold, the signal feedback point changes from a low level to a high level, and then when the upper tube control signal HS_ON changes from a high level to a low level, the R-terminal signal generated by the second logic control module 120 changes from a low level to a high level.

[0061] The RS trigger 130 is used to control the working state of the upper tube of the switching power supply according to the S terminal signal and the R terminal signal.

[0062] Among them, the length of the period during which the S-terminal signal is at a high level depends on the structure of the first logic control module 110, and the length of the period during which the R-terminal signal is at a high level depends on the structure of the second logic control module 120. The specific period is generally not limited, and the parameters of the first logic control module 110 and the second logic control module 120 can also be set according to actual needs to achieve better use effects. The output of the RS trigger 130 depends on the S-terminal signal and the R-terminal signal input by the RS trigger 130. Specifically, when the R-terminal signal is at a low level and the S-terminal signal is at a high level, the output of the RS trigger 130 is at a high level, and the switch power supply upper tube Q1 is turned on. In this state, the RS trigger 130 is called a set state, and the S-terminal is the turn-on end of the switch power supply upper tube Q1. When the R-terminal signal is at a high level and the S-terminal signal is at a low level, the output of the RS trigger 130 is at a low level, and the switch power supply upper tube Q1 is turned off. In this state, the RS trigger 130 is called a reset state, and the R-terminal is the turn-off end of the switch power supply upper tube. When the R-terminal signal is at a low level and the S-terminal signal is at a low level, the output of the RS trigger 130 remains unchanged.

[0063] As an optional connection method, such as Figure 2 As shown, the first input terminal of the first logic control module 110 is connected to the upper tube control signal HS_ON, the second input terminal of the first logic control module 110 is connected to the signal feedback point in the second logic control module 120, and the output terminal of the first logic control module 110 is connected to the S terminal of the RS trigger 130. The input terminal of the second logic module 120 is connected to the upper tube control signal HS_ON, and the output terminal of the second logic module 120 is connected to the R terminal of the RS trigger 130. The output terminal (Q terminal or the other terminal) of the RS trigger 130 serves as the output terminal of the control circuit 100, and receives the upper tube of the switch power supply to be controlled.

[0064] It should be noted that the control circuit 100 has other optional connection modes. For example, the first input terminal of the first logic control module 110 is connected to the upper tube control signal HS_ON and other control signals, the second input terminal of the first logic control module 110 is connected to the signal feedback point in the second logic control module 120, and the output terminal of the first logic control module 110 is connected to the S terminal of the RS trigger 130 through other modules. The input terminal of the second logic module 120 is connected to the upper tube control signal HS_ON and other control signals, and the output terminal of the second logic module 120 is connected to the R terminal of the RS trigger 130 through other modules. In the embodiment of the present disclosure, the control circuit 100 may also include more or fewer modules, such as a signal processing module, etc., and the connection relationship between the modules is not limited and can be set according to actual needs.

[0065] The control circuit disclosed in the present invention is applicable to any existing application scenario of the upper tube of the switching power supply, and the embodiments of the present invention are not limited to this. For example, in the control scenario of the power supply chip, the control circuit disclosed in the present invention is applied to the above-mentioned scenario compared with the prior art, and the level conversion occurs only in the scenario where the period of time when the upper tube control signal HS_ON is at a high level exceeds the set threshold, and the output signal is generated for the control of the upper tube of the switching power supply, turning it on or off. Therefore, in the scenario where the upper tube control signal HS_ON appears to be at a high level for a period of time lower than the set threshold, the abnormal short pulse (short pulse) will not be recognized by the control circuit, and the S end of the RS trigger is still maintained in a normal working state, which will not cause the upper tube Q1 of the switching power supply to turn on abnormally. Therefore, the purpose of preventing signal interference and accurately responding to the upper tube control signal HS_ON is achieved, thereby achieving the technical effect of accurately controlling the startup and shutdown of the upper tube of the switching power supply according to the upper tube control signal HS_ON, thereby solving the technical problem of abnormal function of the power supply chip caused by the abnormal short pulse of the EN signal causing the upper tube Q1 of the switching power supply to be abnormally open.

[0066] Figure 3 FIG. 1 is a schematic diagram of the composition of the first logic control module provided in the embodiment of the present disclosure. Figure 3 As shown, the first logic control module 110 includes a first level conversion unit 111 , an AND gate unit 112 , and a feedback signal acquisition unit 113 .

[0067] The first level conversion unit 111 , wherein an input terminal of the first level conversion unit 111 is connected to the upper tube control signal HS_ON, and is used to perform a first level conversion on the upper tube control signal HS_ON.

[0068] The feedback signal acquisition unit 113, wherein the input terminal of the feedback signal acquisition unit 113 is connected to the signal feedback point in the second logic control module 120, and the output terminal of the feedback signal acquisition unit 113 is connected to the third input terminal of the AND gate unit 112, for acquiring the feedback signal of the signal feedback point. When the duration of the high-level control signal HS_ON being at the high level is less than the set threshold, the signal feedback point still maintains a low level.

[0069] An AND gate unit 112, wherein a first input terminal of the AND gate unit 112 is connected to an output terminal of the first level conversion unit, a second input terminal of the AND gate unit 112 is connected to a tube control signal HS_ON, a third input terminal of the AND gate unit is connected to a signal feedback point in the second logic control module via a feedback signal acquisition unit 113, and an output terminal of the AND gate unit 112 is connected to an S terminal of an RS trigger.

[0070] The structural design of the first level conversion unit 111 is not unique, and the specific structure can be set according to actual needs. As long as the software module or hardware structure that can realize the above functions can be used as the first level conversion unit 111. In addition to amplitude adjustment, the first level conversion can also include phase adjustment, elimination of level offset, etc., which can be set according to actual needs.

[0071] The AND gate unit 112 may be constructed by using a three-input AND gate device, or by using a three-input NAND gate device B1 and a seventh inverting amplifier A7 connected in series, such as Figure 5 As shown. Among them, as long as one of the input signals of the three-input AND gate device is at a low level ("0"), the output is a low level ("0"); only when all the input signals are at a high level ("1"), the output is a high level ("1"). As long as one of the input signals of the three-input NAND gate device B1 is at a high level ("1"), the output is a low level ("0"); only when all the input signals are at a low level ("0"), the output is a high level ("1"). The position of the signal feedback point is not limited, as long as the signal feedback point remains at a low level when the duration of the high level of the upper tube control signal HS_ON is less than the set threshold, and the signal feedback point becomes a high level when the duration of the high level of the upper tube control signal HS_ON is more than the set threshold.

[0072] exist Figure 3 Based on the structure shown, the AND gate unit 112 can also be constructed with other components, and then the function of the first logic control module of the present disclosure can be realized by adjusting the structure of the first level conversion unit 111. This adjustment method is also within the protection scope of the present disclosure.

[0073] Figure 4 FIG. 1 is a schematic diagram of the composition of the second logic control module provided in the embodiment of the present disclosure. Figure 4 As shown, the second logic control module 120 includes a second level conversion module 121 and a NOR gate unit 122 .

[0074] The second level conversion module 121 , wherein an input terminal of the second level conversion module 121 is connected to the upper tube control signal HS_ON, and is used to perform a second level conversion on the upper tube control signal HS_ON.

[0075] The NOR gate unit 122 has a first input terminal connected to the output terminal of the second level conversion module 121 , a second input terminal connected to the upper tube control signal HS_ON, and an output terminal of the NOR gate unit 122 connected to the R terminal of the RS trigger 130 .

[0076] The structural design of the second level conversion module 121 is not unique, and the specific structure can be set according to actual needs. As long as the software module or hardware structure that can achieve the above functions can be used as the second level conversion module 121. In addition to amplitude adjustment, the first level conversion can also include phase adjustment, elimination of level offset, etc., which are specifically set according to actual needs.

[0077] exist Figure 4 Based on the structure shown, the NOR gate unit 122 can also be constructed with other components, and then the function of the second logic control module 120 of the present disclosure can be realized by adjusting the structure of the second level conversion module 121. This adjustment method is also within the protection scope of the present disclosure.

[0078] Figure 5 A specific example schematic diagram of a control circuit provided by an embodiment of the present disclosure provides a detailed structure of a first level conversion unit 111 , an AND gate unit 112 , a feedback signal acquisition unit 113 , a second level conversion module 121 , and a NOR gate unit 122 .

[0079] exist Figure 5 In the example shown, the first level conversion unit 111 includes a first P-channel field effect transistor PMOS1, a first N-channel field effect transistor NMOS1, a first resistor R1, a first capacitor C1, a first reverse amplifier A1, and a second reverse amplifier A2. The AND gate unit includes a three-input NAND gate device B1 and a seventh reverse amplifier A7. Among them, the gates of the first P-channel field effect transistor PMOS1 and the first N-channel field effect transistor NMOS1 are respectively connected to the input signal HS_ON. The source of the first P-channel field effect transistor PMOS1 is connected to the external power supply VCC. The drain of the first P-channel field effect transistor PMOS1 is divided into three paths, the first path is connected to the drain of the first N-channel field effect transistor NMOS1 through the first resistor R1, the second path is grounded through the first capacitor C1, and the third path is connected to the first input end of the three-input NAND gate device B1 through the first reverse amplifier A1 and the second reverse amplifier A2 in sequence. The source of the first N-channel field effect transistor NMOS1 is grounded. Through the above circuit structure, the first level conversion unit 111 can output a first rectangular wave signal with a stable level.

[0080] The feedback signal acquisition unit 113 includes a fifth reverse amplifier A5 and a sixth reverse amplifier A6. The third input terminal of the AND gate unit 112 is connected to the drain of the second P-channel field effect transistor PMOS2, the input terminal of the second capacitor C2, and the input terminal of the fourth reverse amplifier A4 respectively after passing through the sixth reverse amplifier A6 and the fifth reverse amplifier A5 in sequence. Through this circuit structure, the level conversion of the feedback signal is consistent with the level conversion of the upper tube control signal HS_ON, but when the upper tube control signal HS_ON is at a high level and the period of time at the high level exceeds the set threshold, it maintains a high level, and when the period of time at the high level of the upper tube control signal HS_ON is less than the set threshold, it maintains a low level and cannot maintain a high level.

[0081] The second input terminal of the three-input NAND gate device B1 is connected to the upper tube control signal HS_ON. The output terminal of the three-input NAND gate device B1 is connected to the S terminal of the RS flip-flop RS Flip Flop via the seventh reverse amplifier A7. Among them, the drain of the second P-channel field effect transistor PMOS2, the input terminal of the second capacitor C2, the input terminal of the fourth reverse amplifier A4 and any point on the line between the three can be the signal feedback point described in the present disclosure.

[0082] exist Figure 5 Based on the structure shown, the initial state of the S-end signal is a low level, and when the current level of the upper tube control signal HS_ON changes from a low level to a high level and the period of time at the high level exceeds the set threshold, it changes to a high level, and the level remains unchanged when the period of time at the high level is less than the set threshold.

[0083] exist Figure 5 In the example shown, the second level conversion unit 121 includes a second P-channel field effect transistor PMOS2, a second N-channel field effect transistor NMOS2, a second resistor R2, a second capacitor C2, a third reverse amplifier A3, and a fourth reverse amplifier A4. The NOR gate unit 122 includes a three-input NOR gate device B2. Among them, the gate of the second P-channel field effect transistor PMOS2 is connected to the tube control signal HS_ON through the third reverse amplifier A3, the source of the second P-channel field effect transistor PMOS2 is connected to the external power supply, and the drain of the second P-channel field effect transistor PMOS2 is divided into three paths, the first path is connected to the drain of the second N-channel field effect transistor NMOS2 through the second resistor R2, the second path is grounded through the second capacitor C2, and the third path is connected to the first input terminal of the three-input NOR gate device B2 through the fourth reverse amplifier A4. The gate of the second N-channel field effect transistor NMOS2 is connected to the tube control signal HS_ON through the third reverse amplifier A3, and the source of the second N-channel field effect transistor NMOS2 is grounded. Through the above circuit structure, the second level conversion unit 121 can output a second rectangular wave signal with a stable level.

[0084] The second input terminal of the three-input NOR gate device B2 is connected to the upper tube control signal HS_ON, and the output terminal of the three-input NOR gate device B2 is connected to the R terminal of the RS flip-flop RS Flip Flop.

[0085] exist Figure 5 Based on the structure shown, the initial state of the R-end signal is a low level, and when the current level of the upper tube control signal HS_ON changes from a high level to a low level and the period of time at the high level exceeds the set threshold, it changes to a high level, and the level remains unchanged when the period of time at the high level is less than the set threshold.

[0086] It should be noted that in Figure 5 Based on the structure shown, the functions of the first logic control module 110 and the second logic control module 120 are realized by adjusting the type of field effect tube, changing the reverse amplifier, the setting position of the field effect tube, etc., which is also within the protection scope of the present disclosure.

[0087] Figure 6 FIG. 1 is a comparative circuit diagram of the control circuit of the embodiment of the present disclosure. Figure 6 In the example shown, compared to Figure 5 The solution does not include the feedback signal acquisition unit 113 composed of the fifth reverse amplifier A5 and the sixth reverse amplifier A6 connected in series.

[0088] Applied inside a certain power chip Figure 6 The control circuit is used to Figure 1 The control of the upper tube (field effect tube Q1) inside the chip realizes the function of the level conversion circuit. The control circuit has an input upper tube control signal HS_ON and an output signal HS_gata, and 5 sampling points are set in the control circuit, namely sampling points P1 to P5, and sampling point P2 is also used as a signal feedback point. The sampling results of the input, output, and sampling points in the control circuit when the power chip is in a normal state are shown in Table 1, and the sampling results of the input, output, and sampling points in the control circuit when the power chip is in an abnormal state are shown in Table 2.

[0089] Table 1 Sampling results of input, output and sampling points in the control circuit when the power chip is in normal state

[0090] HS_ON P1 P2 P3 P4 P5 HS_gata 1 (duration greater than t1) 0 1 0 0 1 1 Changes from 1 to 0 constant constant 0 1 0 0 0 (duration greater than t2) 1 0 1 0 1 1

[0091] Table 2 Sampling results of input, output and sampling points in the control circuit when the power chip is in abnormal state

[0092] HS_ON P1 P2 P3 P4 P5 HS_gata 0 (duration greater than t2) 1 0 1 0 1 1 1 (duration is less than t1) 0 1 0 0 0 1

[0093] The control logic of the control circuit is as follows.

[0094] When the input signal Hs_ON is at the high level 1, the sampling point P1 is at the low level 0, the sampling point P2 is at the high level 1, and the time t1 when the sampling point P2 changes to low is t1 = Rh × C (the time t1 is determined by the internal resistance Rh of the second P-channel MOSFET PMOS2 and the resistance value C of the second capacitor C2). Under normal circumstances, the time when Hs_ON changes to low should be greater than t1, and the sampling point P2 can normally change to the low level 0, so that the state of the sampling point P3 can also stably change to the high level 1.

[0095] When Hs_ON is at the low level 0, the sampling point P1 is at the high level 1, the sampling point P2 changes to the low level 0, and the time t2 when the sampling point P2 changes to low is t2 = R × C (the time t2 is determined by the resistance value R of the second resistor R2 and the resistance value C of the second capacitor C2). Under normal circumstances, the time when Hs_ON changes to low should be greater than t2, and the sampling point P2 can normally change to the high level 1, so that the state of the sampling point P3 can also stably change to low.

[0096] Normal state: The state of the sampling point P4 is jointly determined by the sampling point P3 and HS_ON. When the high-level time T of HS_ON > t1, if the sampling points P3 and HS_ON are both 0 at the same time, then the sampling point P4 is 1, and the upper switch Q1 of the switching power supply is turned on; if the low-level time T of HS_ON > t2, then the point P4 is 0, and at this time the upper switch Q1 of the switching power supply is turned off.

[0097] Abnormal state: However, when the time T when HS_ON is at the high level < t1, at this time the state of the sampling point P2 in the circuit logic part cannot be maintained at 1, resulting in the R-terminal signal always being low, so that the upper switch Q1 of the switching power supply is always turned on to charge the inductor device, resulting in the current passing through the upper switch Q1 of the switching power supply continuously increasing until the upper switch Q1 of the switching power supply is overheated and burned out, and a failure phenomenon of chip burning will occur at the client side.

[0098] To overcome the above failure, the embodiment of the present disclosure Figure 5 of the solution improves the solution of the embodiment Figure 6 by adding a fifth inverting amplifier A5 and a sixth inverting amplifier A6, which can effectively avoid the burning of the upper switch Q1 of the switching power supply. The modification can be referred to Figure 5 the red part shown, and an additional signal is added as the control signal for the third input terminal of the AND gate unit 112. In this way, when a short pulse of T < t1 appears in HS_on, the sampling point P5 will not be interfered by the abnormal short pulse, so that the S terminal of the RS flip-flop still maintains the normal working state of the previous low level, and will not cause the upper switch Q1 of the switching power supply to be abnormally always on.

[0099] On the basis of the structure shown in Figure 5 , other devices can also be added at the front end of the third input terminal of the AND gate unit 112 to achieve further signal processing functions, and this adjustment method is also within the protection scope of the present disclosure.

[0100] In some embodiments of the present disclosure, the resistance values ​​of the first resistor R1 and the second resistor R2 are the same, both are R. The capacitance values ​​of the first capacitor C1 and the second capacitor C2 are the same, both are C. The internal resistances of the first P-channel field effect transistor PMOS1, the first N-channel field effect transistor NMOS1, the second P-channel field effect transistor PMOS2, and the second N-channel field effect transistor NMOS2 are the same, all are Rh. In addition, the threshold is set to t1=Rh×C. The upper tube control signal HS_ON is a rectangular pulse, and within a pulse period, the period at the high level exceeds Rh×C, and the period at the low level exceeds R×C. The setting of the upper tube control signal HS_ON can enable the control circuit 100 to fully respond to the upper tube control signal HS_ON.

[0101] From the above description, it can be seen that the present disclosure achieves the following technical effects:

[0102] 1. Through the detailed design of the first logic control module 110, the second logic control module 120, and the RS trigger 130, the input upper tube control signal HS_ON can be accurately identified, no interference signal is responded to, and an output signal with a stable level is output.

[0103] 2. Through the integrated design of field effect transistors, reverse amplifiers, and gate circuits, a new field effect transistor control scheme is realized.

[0104] 3. By setting the fifth reverse amplifier A5 and the sixth reverse amplifier A6 to increase the control signal of the AND gate unit, the failure phenomenon of chip burning is effectively avoided.

[0105] The present disclosure also provides a power chip using the above control circuit, such as Figure 7 As shown, the power chip 10 includes the control circuit 100 above and the power switch circuit 200. The power switch circuit 200 is provided with a switch power upper tube Q1 and a switch power lower tube Q2, and the gate of the switch power upper tube Q1 is connected to the output end of the control circuit 100. The output end of the power switch circuit 100 is connected to an external load via an output circuit 300.

[0106] It should be noted that, for the sake of clarity and simplicity, the embodiment of the present disclosure does not provide all the components of the power chip 10. To achieve the necessary functions of the power chip 10, those skilled in the art may provide and set other components not shown according to specific needs, and the embodiment of the present disclosure does not limit this.

[0107] Figure 8 A schematic diagram of a specific example of a power chip provided in an embodiment of the present disclosure. Figure 8As shown, the power switch circuit includes an amplifier A6, an upper switch power supply tube Q1, a lower switch circuit tube Q2, and a bandgap reference power supply Bandgrap. Among them, the gate of the upper switch power supply tube Q1 is connected to the output end of the control circuit through the amplifier A6, and the source of the upper switch power supply tube Q1 is divided into two paths, one is connected to the drain of the lower switch power supply tube Q2, and the other is connected to the input end of the output circuit. The power supply end of the amplifier A6 is connected to the bandgap reference power supply Bandgrap. The source of the lower switch power supply tube is grounded. The output circuit includes an inductor device L and a capacitor device C_OUT connected in series. Among them, the port of the capacitor device C_OUT close to the inductor device L is used as the power supply end of the external load, and the port of the capacitor device C_OUT far away from the inductor device L is grounded. The upper switch power supply tube Q1 and the lower switch power supply tube Q2 are both field effect tubes.

[0108] Fig. 9 Another specific example schematic diagram of a power chip provided in an embodiment of the present disclosure. Fig. 9 As shown, in Figure 8 On the basis of the power supply chip, a first unidirectional diode D1, a second unidirectional diode D2, a boost capacitor C_BOOT, and a capacitor device C_IN at the input end can be further added to achieve a further function of eliminating level deviation, and the connection method will not be repeated.

[0109] The present disclosure also provides an electronic device 1, which includes a power chip 10. For example, Fig.10 As shown, the electronic device 1 includes a power chip 10 and a processor 20. The output end of the power chip 10 can be connected to the power supply end of the processor 20 to provide power for the processor 20 to operate. The power chip 10 can also supply power to other components in the electronic device.

[0110] The processor 20 may be a central processing unit (CPU), or other general-purpose processors, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or a combination of the above chips. The general-purpose processor may be a microprocessor or any conventional processor.

[0111] It should be noted that, for the sake of clarity and simplicity, the embodiments of the present disclosure do not provide all components of the electronic device 1. To achieve the necessary functions of the electronic device 1, those skilled in the art may provide and set other components not shown according to specific needs, and the embodiments of the present disclosure do not limit this.

[0112] Although the embodiments of the present disclosure have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A control circuit for a switching power supply upper tube, wherein the input end of the control circuit is connected to the upper tube control signal, and the output end of the control circuit is connected to the gate of the switching power supply upper tube, characterized in that: The control circuit includes a first logic control module, a second logic control module and an RS trigger; wherein, The first logic control module is connected to a signal feedback point in the second logic control module, and the first logic control module is used to generate an S-terminal signal of the RS trigger according to the upper tube control signal; wherein, when the upper tube control signal changes from a low level to a high level, the first logic control module determines the level of the generated S-terminal signal according to the level of the signal feedback point; The second logic control module is used to generate the R-terminal signal of the RS trigger according to the upper tube control signal; wherein, when the duration of the high level of the upper tube control signal exceeds a set threshold, the signal feedback point changes from a low level to a high level, and then when the upper tube control signal changes from a high level to a low level, the R-terminal signal generated by the second logic control module changes from a low level to a high level; and, The RS trigger is used to control the working state of the upper tube of the switching power supply according to the S-terminal signal and the R-terminal signal.

2. The control circuit according to claim 1, characterized in that: The first logic control module includes: A first level conversion unit, wherein an input terminal of the first level conversion unit is connected to the upper tube control signal, and is used to perform a first level conversion on the upper tube control signal; A feedback signal acquisition unit, wherein the input terminal of the feedback signal acquisition unit is connected to the signal feedback point, and the output terminal of the feedback signal acquisition unit is connected to the third input terminal of the AND gate unit, for acquiring the feedback signal of the signal feedback point; wherein, when the duration of the high level of the upper tube control signal being at the high level is less than the set threshold, the signal feedback point still maintains a low level; and, The AND gate unit, wherein the first input end of the AND gate unit is connected to the output end of the first level conversion unit, the second input end of the AND gate unit is connected to the upper tube control signal; and the output end of the AND gate unit is connected to the S end of the RS trigger.

3. The control circuit according to claim 2, characterized in that: The second logic control module includes: A second level conversion module, wherein an input terminal of the second level conversion module is connected to the upper tube control signal, and is used to perform a second level conversion on the upper tube control signal; A NOR gate unit, wherein a first input terminal of the NOR gate unit is connected to an output terminal of the second level conversion module, a second input terminal of the NOR gate unit is connected to the upper tube control signal, and an output terminal of the NOR gate unit is connected to an R terminal of the RS trigger.

4. The control circuit according to claim 3, characterized in that: The first level conversion unit includes a first P-channel field effect transistor, a first N-channel field effect transistor, a first resistor, a first capacitor, a first reverse amplifier, and a second reverse amplifier; and the AND gate unit includes a three-input NAND gate device connected in series and a seventh reverse amplifier; wherein, The gates of the first P-channel field effect transistor and the first N-channel field effect transistor are connected to the upper tube control signal respectively; the source of the first P-channel field effect transistor is connected to an external power supply; the drain of the first P-channel field effect transistor is divided into three paths, the first path is connected to the drain of the first N-channel field effect transistor via the first resistor, the second path is grounded via the first capacitor, and the third path is connected to the first input end of the three-input NAND gate device after passing through the first reverse amplifier and the second reverse amplifier in sequence; the source of the first N-channel field effect transistor is grounded.

5. The control circuit according to claim 4, characterized in that: The second level conversion unit includes a second P-channel field effect transistor, a second N-channel field effect transistor, a second resistor, a second capacitor, a third reverse amplifier, and a fourth reverse amplifier; and the NOR gate unit includes a three-input NOR gate device; wherein, The gate of the second P-channel field effect transistor is connected to the upper tube control signal via the third reverse amplifier, the source of the second P-channel field effect transistor is connected to an external power supply, the drain of the second P-channel field effect transistor is divided into three paths, the first path is connected to the drain of the second N-channel field effect transistor via the second resistor, the second path is grounded via the second capacitor, and the third path is connected to the first input terminal of the three-input NOR gate device via the fourth reverse amplifier; The gate of the second N-channel field effect transistor is connected to the upper tube control signal via the third reverse amplifier, and the source of the second N-channel field effect transistor is grounded.

6. The control circuit according to claim 5, characterized in that: The feedback signal acquisition unit includes a fifth reverse amplifier and a sixth reverse amplifier; wherein, The third input terminal of the AND gate unit is connected to the drain of the second P-channel field effect transistor, the input terminal of the second capacitor, and the input terminal of the fourth reverse amplifier respectively after passing through the sixth reverse amplifier and the fifth reverse amplifier in sequence.

7. The control circuit according to claim 5 or 6, characterized in that: The first resistor and the second resistor have the same resistance value, both are R; the first capacitor and the second capacitor have the same capacitance value, both are C; the first P-channel field effect transistor, the first N-channel field effect transistor, the second P-channel field effect transistor, and the second N-channel field effect transistor have the same internal resistance, both are Rh; and, The set threshold is Rh×C; The upper tube control signal is a rectangular pulse, and within a pulse cycle, the time period at the high level exceeds Rh×C, and the time period at the low level exceeds R×C.

8. A power chip, characterized in that: The invention comprises the control circuit as claimed in any one of claims 1 to 7, and a power switch circuit; wherein: The power switch circuit is provided with an upper switch power supply tube and a lower switch power supply tube; wherein the gate of the upper switch power supply tube is connected to the output end of the control circuit.

9. The power chip according to claim 8, characterized in that: The power switch circuit also includes an amplifier and a bandgap reference power supply.

10. An electronic device, characterized in that: Comprising the power chip described in claim 8 or 9.

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