Power control circuit and method for managing power delivered to load

Abstract

The invention relates to a power control circuit and method for managing power delivered to a load. A power control circuit includes an input connection, an output connection, and a current sensor configured to generate a power signal corresponding to an electrical signal delivered from a power source to a load. The power control circuit is configured to receive a control signal from the controller via the input connection, the control signal comprising a sequence of control signal pulses occurring at a control signal frequency, and to generate an output signal based on the power signal, the sequence of control signal pulses, and the control signal frequency. The power control circuit is configured to deliver an output signal via the output connection to control the gate driver circuit to manage a power signal delivered from the power source to the load.

Description

Technical Field

[0001] The present disclosure relates to circuits for controlling power delivered to a load. Background Art

[0002] Driver circuits are typically used to control voltage, current, or power at a load. For example, a group of semiconductor devices may be part of one or more circuits that provide electrical signals to a load. The group of semiconductor devices may be part of a power converter, a power supply device, a bypass circuit, or other types of circuits. In some cases, a gate driver circuit may control the group of semiconductor devices by delivering electrical signals to corresponding gate terminals of the group of semiconductor devices. One or more circuits may deliver control signals so that the gate driver circuit controls the group of semiconductor devices. Summary of the invention

[0003] In general, the present disclosure relates to devices, systems, and techniques for managing power delivered to a load based on a power signal generated by a current sensor. For example, a power control circuit may include a current sensor that generates a power signal indicating the amount of power delivered to the load from a power source. The power signal may indicate one or both of the current delivered to the load and the voltage delivered to the load. The power control circuit may receive a control signal from a controller. In some cases, the power control circuit may control the power delivered to the load based on the control signal and the power signal generated by the current sensor.

[0004] In some examples, one or more power transistors may be connected to a node between a power source and a load. When one or more transistors are turned on, at least some of the current delivered by the power source may flow through the one or more power transistors without flowing to the load. When one or more transistors are turned off, current may flow from the power source to the load, and at least some of the current does not flow through the one or more power transistors. The power control circuit manages the power delivered to the load by controlling one or more power transistors. For example, the power control circuit may absorb at least a portion of the power from the load by turning on one or more power transistors, and allow power to flow to the load by turning off one or more power transistors.

[0005] The technology of the present disclosure may provide one or more advantages. For example, the power control circuit may manage the power delivered to the load based on the modulated control signal received from the controller and the power signal generated by the current sensor. The power control circuit may more efficiently control the power delivered to the load than a system that uses a controller with a mixed signal circuit device to control the power delivered to the load. That is, using the power control circuit to manage the power delivered to the load may eliminate the need for the controller to include a mixed circuit device for processing the power signal generated by the current sensor.

[0006] In some examples, a power control circuit includes an input connection, an output connection, and a current sensor configured to sense a power signal delivered from a power source to a load. The power control circuit is configured to receive a control signal from a controller via the input connection, the control signal including a control signal pulse train occurring at a control signal frequency, and generate an output signal based on the power signal, the control signal pulse train, and the control signal frequency. The power control circuit is also configured to deliver an output signal via the output connection to control a gate driver circuit to manage the power signal delivered from the power source to the load.

[0007] In some examples, a method includes: sensing, by a current sensor of a power control circuit, a power signal delivered from a power source to a load, and receiving, by the power control circuit, a control signal from a controller via an input connection of the power control circuit, the control signal including a control signal pulse train occurring at a control signal frequency. The method also includes: generating, by the power control circuit, an output signal based on the power signal, the control signal pulse train, and the control signal frequency; and delivering, by the power control circuit, the output signal via an output connection to control a gate driver circuit to manage the power signal delivered from the power source to the load.

[0008] In some examples, a system includes a controller, a gate driver circuit, and a power control circuit. The power control circuit includes an input connection, an output connection, and a current sensor configured to sense a power signal delivered from a power source to a load. The power control circuit is configured to: receive a control signal from the controller via the input connection, the control signal including a control signal pulse train occurring at a control signal frequency; generate an output signal based on the power signal, the control signal pulse train, and the control signal frequency; and deliver the output signal via the output connection to control the gate driver circuit to manage the power signal delivered from the power source to the load.

[0009] This summary is intended to provide an overview of the subject matter described in this disclosure. It is not intended to provide an exclusive or exhaustive explanation of the systems, devices, and methods described in detail in the drawings and the following description. Further details of one or more examples of the present disclosure are set forth in the drawings and in the following description. Other features, objects, and advantages will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram illustrating a system for controlling power delivered to a load according to the present disclosure.

[0011] Figure 2 is a circuit diagram illustrating a system including a power control circuit for controlling power delivered from a power source to a load according to the present disclosure.

[0012] Figure 3 is a circuit diagram illustrating an example configuration of a power control circuit according to the present disclosure.

[0013] Figure 4 is a flow chart illustrating example operations for using a power control circuit to control power to a load based on a control signal and a power signal, in accordance with one or more techniques of this disclosure. DETAILED DESCRIPTION

[0014] Figure 1 is a block diagram illustrating a system 100 for controlling power delivered to a load according to the present disclosure. Figure 1 1 , system 100 includes a controller 110 including control circuitry 111, processing circuitry 112, and memory 114. System 100 also includes power control circuitry 120 including input connections 122, output connections 124, and current sensor 126. System 100 also includes a power source 132, a load 134, a gate driver circuit 136, and a power stage 137 including (one or more) power transistors 138. System 100 also includes a node 142 connected to (one or more) power transistors 138 and a node 144 connected to load 134.

[0015] Controller 110 may include control circuitry 111. In some examples, control circuitry 111 may be configured to control power control circuitry 120 to manage power delivered to load 134 by controlling (one or more) power transistors 138. In some examples, control circuitry 111 may include an analog-to-digital (ADC) converter, other kinds of power converters, a physical processing unit (PPU), a central processing unit (CPU), a timer circuitry, or any combination thereof. In some examples, control circuitry 111 may represent a microcontroller unit (MCU). In some examples, control circuitry 111 may receive an analog signal from node 144. Control circuitry 111 may convert the analog signal into a digital signal for processing, and output the analog signal to power control circuitry 120. In some examples, control circuitry 111 may output a modulated digital signal to the power control circuitry.

[0016] Control circuit device 111 may include processing circuit device 112. Processing circuit device 112 may include, for example, one or more microprocessors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or equivalent discrete or integrated logic circuit devices, or a combination of any of the foregoing devices or circuit devices. Therefore, processing circuit device 112 may include any suitable structure, whether in hardware, software, firmware, or any combination thereof, to perform the functions attributed to controller 110 herein.

[0017] The controller 110 may include a memory 114 in communication with the processing circuitry 112. In some examples, the memory 114 in communication with the processing circuitry 112 includes computer-readable instructions that, when executed by the processing circuitry 112, cause the system 100 to perform various functions attributed herein to the first system 100. The memory 114 may include any volatile, non-volatile, magnetic, optical, or electrical medium, such as a random access memory (RAM), a read-only memory (ROM), a non-volatile RAM (NVRAM), an electrically erasable programmable ROM (EEPROM), flash memory, or any other digital medium capable of storing information.

[0018] The power control circuit 120 may be configured to receive a control signal from the controller 110 via an input connection 122. In some examples, the control signal may represent a modulated signal including a control signal pulse train that occurs at a control signal frequency. In some examples, the modulated signal may include a frequency, a pulse train each including an amplitude, a duty cycle, or any combination thereof. In some examples, the control signal received via the input connection 122 may represent an analog signal, but this is not required. In some examples, the control signal may represent a modulated digital signal. In some cases, the power control circuit 120 may control the power output to the load 134 based on the control signal received from the controller 110 without receiving any other signal from the controller 110. In some cases, the power control circuit 120 may control the power output to the load 134 based on the control signal and one or more other signals received from the controller 110.

[0019] In some examples, the control signal received from the controller 110 can represent a single pulse width modulation (PWM) signal driven by a timer circuit device of the control circuit device 111. The PWM signal can represent a signal that uses a digital signal to achieve an analog result. For example, the PWM signal may include a square pulse sequence, each square pulse in the square pulse sequence including an amplitude and a duration. In some examples, the PWM signal may include pulses other than square pulses, such as triangular pulses. By outputting a control signal including a single PWM signal to the power control circuit 120, the controller 110 can be configured to operate in a closed-loop system, wherein the controller 110 does not need to process the analog power signal generated by the current sensor 126.

[0020] The current sensor 126 can be configured to sense the current output from the power source 132. For example, the current sensor 126 can generate a power signal indicating the current of the electrical signal output from the power source 132, the voltage of the electrical signal output from the power source 132, the magnetic field corresponding to the electrical signal, or any combination thereof. In some examples, the current sensor 126 may include a Hall effect sensor. A Hall effect sensor is a transducer or sensor configured to detect a magnetic field. The Hall effect sensor can use the principle of the Hall effect, which is a phenomenon in which a voltage is generated across a conductor or semiconductor when the conductor or semiconductor is subjected to a perpendicular magnetic field and a current flows through the conductor or semiconductor. This means that the Hall effect can be configured to sense a magnetic field, a current, a voltage, or any combination thereof.

[0021] The Hall effect sensor can indirectly measure the current by detecting the magnetic field generated by the current-carrying conductor. Additionally or alternatively, the Hall effect sensor can measure the current by measuring the magnetic field strength near the conductor. The current sensor 126 may include an open-loop Hall effect sensor and / or a closed-loop Hall effect sensor. The open-loop Hall effect sensor can measure the current by sensing the magnetic field around the current-carrying conductor. For example, an open-loop Hall effect can be located near the conductor carrying the current. When the current flows through the conductor, it generates a magnetic field around the conductor according to Ampere's law. The open-loop Hall effect sensor can detect the magnetic field. The open-loop Hall sensor can convert the detected magnetic field into a voltage (e.g., a Hall voltage). The Hall voltage is proportional to the current passing through the conductor and can be determined accordingly. The output voltage of the open-loop Hall sensor can be amplified and processed to obtain a measurement of the current passing through the conductor.

[0022] Additionally or alternatively, the current sensor 126 may include a closed-loop Hall effect sensor. The closed-loop Hall effect current sensor may be configured for current measurement and provide high accuracy and linearity. The closed-loop Hall effect current sensor operates based on a feedback mechanism to maintain a constant magnetic field within the sensor. The closed-loop Hall sensor may be placed around a current-carrying conductor. For example, the conductor may pass through a central opening in the current sensor 126. The closed-loop Hall sensor may include a magnetic field generator (e.g., a permanent magnet or a current-carrying coil). The internal magnetic field may be maintained at a constant level. When current flows through the conductor, it causes a reverse magnetic field sensed by the closed-loop Hall sensor. The Hall sensor may adjust the output voltage (e.g., Hall voltage) to eliminate the effects of the magnetic field. The Hall voltage required to maintain the internal magnetic field at a constant level is proportional to the current passing through the conductor. The output voltage of the closed-loop Hall sensor may be measured and calibrated to provide a measurement of the current.

[0023] The power source 132 is configured to deliver power to the load 134. In some examples, the power source 132 includes a battery and a power generation circuit to generate operating power. In some examples, the power source 132 is rechargeable to allow extended operation. The power source 132 may include any one or more of a variety of different battery types, such as nickel-cadmium batteries and lithium-ion batteries. In some examples, the maximum voltage output of the power source 132 is about 12V, but this is not required. In some examples, the maximum voltage output of the power source 132 is greater than 100V (e.g., 400V).

[0024] Load 134 can define a collection of electronic components that consume power. In some examples, load 134 includes a collection of circuit components such as resistors, inductors, capacitors, diodes, and other semiconductor elements. Load 134 can include one or more post-regulator circuits. In some examples, load 134 includes motors and other electronic components (e.g., dashboards, control panels, heating / cooling systems, and lights) of a vehicle. Example vehicles include cars, trucks, buses, motorcycles, golf carts, all-terrain vehicles (ATVs), snowmobiles, airplanes, and boats. In other examples, load 134 includes motors and electronic components used in other applications.

[0025] The gate driver circuit 136 may control whether each of the power transistor(s) 138 is turned on or off. To control the power delivered to the load 134, the power control circuit 120 may generate an output signal for delivery to the gate driver circuit 136 to control whether each of the power transistor(s) 138 is turned on or off. For example, the duty cycle of each of the power transistor(s) 138 may determine the amount of current that passes through the power stage 137 instead of through the load 134. The power control circuit 120 may control the duty cycle of each of the power transistor(s) 138 by transmitting the output signal to the gate driver circuit 136 via the output connection 124.

[0026] The power stage 137 can be configured to control the power delivered from the power source 132 to the load 134. The power stage can manage the power delivery to the load (such as a motor, LED, or any other device that requires electrical energy to operate). The power stage 137 can regulate voltage and current to ensure that the load 134 efficiently and reliably receives the correct amount of power. The power stage can be used in various electronic systems, including power supplies, motor control circuits, amplifiers, and voltage regulators. In some examples, the power stage 137 can include (one or more) power transistors 138.

[0027] The power transistors (one or more) 138 may represent semiconductor transistor devices or other types of switches configured for power delivery. In some cases, each of the power transistors (one or more) 138 may include a power switch, such as, but not limited to, any type of field effect transistor (FET), including a metal oxide semiconductor field effect transistor (MOSFET), a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT), a junction field effect transistor (JFET), a high electron mobility transistor (HEMT), or any one or combination of other types of elements controlled using voltage or current. Additionally, each of the power transistors (one or more) 138 may include any one or combination of n-type transistors, p-type transistors, and other types of power transistors. In some examples, each of the power transistors (one or more) 138 includes a vertical transistor, a lateral transistor, and / or a horizontal transistor. In some examples, each of the power transistors (one or more) 138 includes other analog devices, such as diodes and / or thyristors. In some examples, each of the power transistors (one or more) 138 may be used as a switch and / or as an analog device.

[0028] In some examples, each power transistor in (one or more) power transistors 138 includes three terminals: two load terminals and a control terminal. When the power transistor represents a MOSFET, the power transistor may include a drain terminal, a source terminal, and at least one gate terminal, wherein the control terminal is a gate terminal. When the power transistor represents a BJT switch, the control terminal may represent a base terminal. Current may flow between the two load terminals of the power transistor based on the voltage at the corresponding control terminal. Therefore, current may flow across the power transistor based on a control signal delivered to the control terminal of the power transistor. In one example, if the voltage applied to the control terminal of the power transistor is greater than or equal to a voltage threshold, the power transistor may be activated, thereby allowing the power transistor to conduct. In addition, when the voltage applied to the control terminal of the power transistor is lower than a threshold voltage, the power transistor may be deactivated, thereby preventing the power transistor from conducting. The power control circuit 120 may be configured to control each power transistor in (one or more) power transistors 138 by transmitting an output signal to the gate driver circuit 136 via an output connection 124.

[0029] Each of the power transistor(s) 138 may include various material compounds, such as silicon, silicon carbide, gallium nitride, or any other combination of one or more semiconductor materials. In some examples, silicon carbide switches may experience lower switching power losses. Improvements in magnetics and faster switches (such as gallium nitride switches) may allow the power transistors to draw short bursts of current. These higher frequency devices may need to send control signals (e.g., voltage signals delivered to the control terminals of the power transistors) with more precise timing than lower frequency devices.

[0030] In some examples, power transistor(s) 138 may include a single power transistor connected to node 142. In some examples, power transistor(s) 138 may include more than one power transistor. In any case, power transistor(s) 138 may be connected to node 142 such that when power transistor(s) 138 are turned on, at least some current of the electrical signal output from power source 132 may flow through power transistor(s) 138 instead of through load 134. When power transistor(s) 138 are turned off, the current of the electrical signal output from power source 132 may travel to load 134 without a portion of the current flowing through power transistor(s) 138.

[0031] To generate the output signal, the power control circuit 120 may generate the output signal to include a gate control pulse sequence for controlling the (one or more) power transistors 138. Each gate control pulse in the gate control pulse sequence may be configured to cause a power transistor in the (one or more) power transistors 138 to be turned on and off according to a power transistor switching cycle. To deliver the output signal to the gate driver circuit 136, the power control circuit 120 is configured to deliver the output signal to the gate driver circuit 136 so that the gate driver circuit 136 controls the gate terminal of the (one or more) power transistors 138 so that the (one or more) power transistors 138 are turned off and on according to the gate control pulse sequence.

[0032] In some examples, the power control circuit 120 includes a signal summation unit. The power control circuit 120 is configured so that the signal summation unit receives a first signal summation input based on a power signal from the current sensor 126. The power control circuit 120 is configured so that the signal summation unit receives a second signal summation input based on a control signal received from the controller 110 via the input connection 122. The power control circuit can use the signal summation unit to generate a signal summation output based on the first signal summation input and the second signal summation input. The signal summation output may include the sum of the first signal summation input and the second signal summation input. This means that the signal summation unit can combine the control signal received from the controller 110 with the power signal received from the current sensor 126 to generate a combined signal. The power control circuit 120 can generate an output signal transmitted to the gate driver circuit 136 based on the signal summation output.

[0033] In some examples, the power control circuit 120 may include a signal ramp unit. The power control circuit 120 may use the signal ramp unit to generate a second signal sum input for the signal sum unit based on the control signal received via the input connection 122. The second signal sum input may include a ramp signal pulse train corresponding to a control signal pulse train of the control signal occurring at the control signal frequency. This means that in some examples, the signal sum output may include a ramp signal corresponding to the sum of the second signal sum input and the power signal received from the current sensor 126.

[0034] In some examples, the power control circuit 120 may include a comparator. In order to generate an output signal for transmission to the gate driver circuit 136 via the output connection 124, the power control circuit 120 is configured so that the comparator receives a first comparator input and a second comparator input. In some examples, the first comparator input is based on a control signal from the controller 110 and a power signal from the current sensor 126. In some examples, the second comparator input is based on a control signal from the controller 110. The power control circuit 120 can use a comparator to generate a comparator output based on the first comparator input and the second comparator input. The comparator output may include an output signal delivered to the gate driver circuit 136.

[0035] In some examples, the power control circuit 120 may include a first signal ramp unit and a second signal ramp unit. In some examples, the first signal ramp unit may represent a signal ramp unit that generates a second signal sum input for the signal sum unit. In order for the comparator to receive a first comparator input based on a control signal from the controller 110 and a power signal from the current sensor 126, the power control circuit 120 is configured to generate a first ramp signal pulse sequence corresponding to a control signal pulse sequence that occurs at a control signal frequency using the first signal ramp unit. The power control circuit 120 is configured to generate a first comparator input based on the first ramp signal pulse sequence and a power signal from the current sensor 126. In order for the comparator to receive a second comparator input based on a control signal from the controller 110, the power control circuit 120 is configured to generate a second comparator input using the second signal ramp unit to include a second ramp signal pulse sequence corresponding to a control signal pulse sequence that occurs at a control signal frequency.

[0036] In some examples, the control circuit device 111 of the controller 110 can generate a control signal for output to the power control circuit 120 based on the feedback signal received from the node 144. For example, the control circuit device 111 can receive a feedback signal from the node 144, which indicates the current at the node 144, the voltage at the node 144, the magnetic field corresponding to the electrical signal at the node 144, or any combination thereof. This means that the system 100 can represent a closed-loop system. In some examples, the feedback signal can represent an analog signal. In some examples, the control signal output by the controller 110 to the power control circuit 120 can represent an analog signal, but this is not required. In some examples, the control signal output by the controller 110 to the power control circuit 120 can represent a modulated digital signal.

[0037] By controlling the power to the load 134 based on a single control signal received from the controller 110 and a power signal received from the current sensor 126, the power control circuit 120 can control the power to the load 134 more efficiently and with fewer circuit components than a system that relies on the controller to process the control signal and the power signal. In other words, the power control circuit 1200 can efficiently control the power transistor(s) 138 to sink current when necessary and allow current to reach the load 134 when necessary, thereby eliminating the need for complex processing at the controller 110 to process the power signal from the current sensor 126 and the control signal generated by the controller 110 based on the feedback signal.

[0038] Figure 2 2 is a circuit diagram illustrating a system 200 including a power control circuit 220 for controlling power delivered from a power source 232 to a load 234 according to the present disclosure. Figure 2 2, system 200 includes a controller 210 that includes a control circuit 211, a memory 214, an output connection 218, and an input connection 219. The control circuit 211 may include an ADC 215, a processing unit 216, and a timer circuit 217. The ADC 215, the processing unit 216, and the timer circuit 217 may be part of the processing circuit of the control circuit 211. The system 200 also includes a power control circuit 220 that includes an input connection 222 and an output connection 224. The system 200 includes a power source 232, a load 234, a gate driver circuit 236, a power transistor 238, an inductor 252, a diode 254, a capacitor 256, a first resistor 258, and a second resistor 259.

[0039] The controller 210 may be Figure 1 The control circuit device 211 may be an example of a controller 110. Figure 1 The memory 214 may be an example of a control circuit device 111. Figure 1 The power control circuit 220 may be an example of a memory 114. Figure 1 An example of a power control circuit 120 is shown in FIG. 1 . The input connection 222 may be Figure 1 An example of an input connection 122 of . An output connection 224 may be Figure 1 The current sensor 226 may be an example of an output connection 124 of Figure 1 The power source 232 may be an example of a current sensor 126. Figure 1 An example of a power source 132 is shown in FIG. 2 . The load 234 may be Figure 1 The gate driver circuit 236 may be an example of a load 134. Figure 1An example of a gate driver circuit 136 of FIG. 1 is shown in FIG. 2 . The power transistor 238 may be Figure 1 An example of (one or more) power transistors 138.

[0040] Controller 210 may include control circuitry 211. In some examples, control circuitry 211 may be configured to control power control circuitry 220 to manage power delivered to load 234 by controlling power transistor 238. Control circuitry 211 may be configured to generate a control signal output via output connection 218 based on a feedback signal received via input connection 219. This means that control circuitry 211 may be part of a closed-loop system for controlling power delivered from power source 232 to load 234. For example, control circuitry 211 may be configured to output a control signal to power control circuitry 220 via output connection 218 of controller 210 so that power control circuitry 220 controls gate driver circuitry 236 to manage power transistor 238. Whether power transistor 238 is turned on or off may control the amount of power reaching load 234.

[0041] The processing circuitry of control circuitry 211 may include, for example, one or more microprocessors, DSPs, ASICs, FPGAs, or equivalent discrete or integrated logic circuitry, or a combination of any of the foregoing devices or circuitry. Thus, the processing circuitry of control circuitry 211 may include any suitable structure, whether in hardware, software, firmware, or any combination thereof, to perform the functions attributed to controller 210 herein.

[0042] Controller 210 may include memory 214 in communication with processing circuitry of control circuitry 211. In some examples, memory 214 in communication with processing circuitry of control circuitry 211 includes computer-readable instructions that, when executed by processing circuitry of control circuitry 211, cause system 200 to perform various functions attributed herein to system 200. Memory 214 may include any volatile, non-volatile, magnetic, optical, or electrical medium, such as RAM, ROM, NVRAM, EEPROM, flash memory, or any other digital medium capable of storing information.

[0043] The control circuit device 211 may include an ADC 215. The ADC may convert a continuous analog signal into a discrete sequence of digital values ​​for processing by a digital device (such as a microcontroller, a computer, or a digital signal processor). For example, the analog signal may include a voltage signal that varies continuously over time. To convert the voltage signal into a digital signal, the ADC 215 may sample the voltage signal at regular intervals. This may involve taking discrete samples of the continuous analog voltage signal at specific time intervals (e.g., every second, every millisecond (ms), every microsecond (μs), or any other interval).

[0044] In response to the sampled values ​​of the analog signal, the ADC 215 can perform quantization. Quantization may involve mapping each analog value in the sampled analog values ​​to a corresponding discrete digital value. These digital values ​​can represent binary values ​​(0 and 1) and indicate the amplitude of the analog signal at each sampling point. Then, the ADC 215 can encode the quantized digital values ​​into a binary digital format, represented as a binary code. Example encoding schemes include binary code, Gray code, and two's complement. The final output of the ADC 215 is a digital representation of the input analog signal. The digital representation of the input analog is digital data that can be processed, stored, or used for various purposes in a digital system.

[0045] ADC 215 may receive a feedback signal via input connection 219 of controller 210. The feedback signal may represent an analog signal. In some examples, the analog signal may represent a voltage signal, but this is not required. In some examples, the analog signal may represent a current signal or another type of signal that may indicate power. ADC 215 may generate a digital representation of the analog signal for output to processing unit 216. Processing unit 216 may include a PPU and / or a CPU configured to process the digital signal output by ADC 215. Since the digital signal output by ADC 215 may include a digital representation of the analog feedback signal received via input connection 219, processing unit 216 may generate a digital response to the feedback signal for output to timer circuit 217.

[0046] The timer circuit 217 can generate a control signal based on the output from the processing unit 216 for output to the power control circuit 220 via the output connection 218 of the controller 210 and the input connection 222 of the power control circuit 220. The timer circuit 217 can generate the control signal to include a PWM signal for controlling the power transistor 238. The PWM signal can include a pulse train at a certain frequency. The PWM signal output from the timer circuit 217 can control whether the power transistor 238 is turned on or off, which can in turn control the power delivered to the load 234. For example, when the power transistor 238 is turned on, a smaller amount of power can reach the load 234, and when the power transistor 238 is turned off, a larger amount of power can reach the load 234.

[0047] The power source 232 can be configured to deliver power to the load 234 via the current sensor 226 of the power control circuit 220. The power control circuit 220 can receive a control signal from the timer circuit 217 via the input connection 222 of the power control circuit 220. The power control circuit 220 can receive a power signal from the current sensor 226, which indicates one or more parameters of the electrical signal output from the power source 232 to the load 234. For example, the power signal can indicate the current of the electrical signal, the voltage of the electrical signal, the magnetic field associated with the electrical signal, or any combination thereof. Based on the control signal received from the controller 210 and the power signal generated by the current sensor 226, the power control circuit 220 can generate an output signal and transmit the output signal to the gate driver circuit 236 via the output connection 224.

[0048] The gate driver circuit 236 can receive the output signal from the power control circuit 220 and control the power transistor 238 based on the output signal. In some examples, the output signal received by the gate driver circuit 236 from the power control circuit 220 can include a pulse sequence. The pulse sequence can instruct the gate driver circuit 236 to turn on and off the power transistor 238 according to a switching cycle sequence. In some examples, the switching cycle sequence can include an on-cycle sequence and an off-cycle sequence interleaved with the on-cycle sequence.

[0049] When power transistor 238 is turned off, current 241 may pass through node 242 as current 243, while a portion of current 241 does not flow through power transistor 238 as current 243'. This is because when power transistor 238 is turned off, there may be no current path across power transistor 238, so when power transistor 238 is turned off, current cannot pass through power transistor 238. When power transistor 238 is turned on, current 241 may be divided into current 243 and current 243' at node 242. Current 243 may flow across diode 254 to load 234, and current 243' may flow through power transistor 238 without flowing to load 234. This means that when power transistor 238 is turned on, a portion of current 241 may be "sucked" from load 234 through power transistor 238 as current 243'.

[0050] Inductor 252 represents a circuit component that resists changes in the magnitude of current passing through inductor 252. In some examples, inductor 252 is defined by a conductive wire wound into a coil. When current passes through the coil of inductor 252, a magnetic field is generated in the coil, and the magnetic field induces a voltage across the inductor. Inductor 252 defines an inductance value, and the inductance value is the ratio of the voltage across inductor 252 to the rate of change of the current passing through inductor 252.

[0051] Diode 254 can represent a semiconductor device used as a diode. In the field of circuit electronics, a diode includes a semiconductor component that allows current to flow across the diode in a first direction (e.g., a "forward direction") and prevents current from flowing across the diode in a second direction (e.g., a "reverse direction"). The diode may include an anode and a cathode, and the current may be able to pass through the diode in the forward direction from the anode to the cathode. However, the current may not be able to pass through the diode in the reverse direction from the cathode to the anode. For example, current can flow across diode 254 in the forward direction from node 242 to node 244.

[0052] Capacitor 256 is a circuit component configured to store electrical potential energy. In some examples, capacitor 256 can be in a "charged" state, where capacitor 256 stores a maximum amount of electrical potential energy. Additionally, capacitor 256 can be in a "discharged" state, where capacitor 256 stores little or no electrical potential energy. Capacitor 256 can also transition between a charged state and a discharged state. When capacitor 256 is charging, current flows across capacitor 256, thereby increasing the electrical potential energy stored by capacitor 256. When capacitor 256 is discharging, the electrical potential energy stored by capacitor 256 is released, causing capacitor 256 to emit current.

[0053] In some examples, the first resistor 258 and the second resistor 259 can be connected in series to the node 244. In some examples, a portion of the current 243 output from the node 242 can flow as a current 245 across the node 244 to the load 234. In some examples, a portion of the current 243 output from the node 242 can flow as a current 245 across the first resistor 258 and the second resistor 259 as a current 245'. In some examples, the magnitude of the current 245 is greater than the current 245'. In some examples, the first resistor 258 and / or the second resistor 259 can represent a sensor for generating a feedback signal indicating one or more parameters at the node 244 (e.g., a voltage at the node 244, a current at the node 244, or another parameter of the electrical signal at the node 244). For example, the feedback signal can travel from the second resistor 259 to the controller 210 via the input connection 219 of the controller 210.

[0054] The system 200 may include a closed-loop feedback system. For example, the control circuit 211 may generate a control signal for output to the power control circuit 220 based on a feedback signal received via the input connection 219 of the controller 210. The power control circuit 220 may generate an output signal to control the gate driver circuit 236, thereby controlling the power transistor 238 to manage the power delivered by the power source 232 to the load 234. This means that the power control circuit 220 may control the electrical signal at the node 244 based on the control signal received from the controller 210. The controller 210 may receive a feedback signal indicating one or more parameters of the electrical signal at the node 244, and generate a control signal based on the feedback signal, thus completing a closed-loop system.

[0055] Figure 3 is a circuit diagram illustrating an example configuration of a power control circuit 320 according to the present disclosure. Figure 3 As seen in FIG. 1 , the power control circuit 320 includes an input connection 322, an output connection 324, a current sensor 326, a signal summing unit 362, a comparator 366, a first signal ramp unit 368, a second signal ramp unit 369, a first voltage unit 372, a second voltage unit 374, a blank unit 376, a first sample and hold (S&H) circuit 382, ​​and a second S&H circuit 384. The power control circuit 320 may be Figure 1 An example of a power control circuit 120 is shown in FIG. 1 . The input connection 322 may be Figure 1 An example of an input connection 122 of . An output connection 324 may be Figure 1 The current sensor 326 may be an example of an output connection 124 of Figure 1 An example of a current sensor 126 .

[0056] The power control circuit 320 can receive a control signal from the controller 110 via an input connection 322. In some examples, the control signal can represent a PWM signal. In some examples, the control signal can represent an analog signal, but this is not required. In some examples, when the control signal is a PWM signal, the control signal can represent a modulated digital signal. The current sensor 326 of the power control circuit 320 can generate a power signal indicating one or more parameters of an electrical signal (e.g., an electrical signal output from the power source 132). For example, the power signal can indicate a current, a voltage, and / or another parameter of the electrical signal.

[0057] In some examples, the signal summation unit 362 can receive a first signal sum input 361 based on the power signal from the current sensor 326, and receive a second signal sum input 361' based on the control signal received from the controller 110 via the input connection 322. In some examples, the signal summation unit 362 can generate a signal sum output 363 based on the first signal sum input 361 and the second signal sum input 361'. The signal sum output 363 can represent the sum of the first signal sum input 361 and the second signal sum input 361'.

[0058] In some examples, the signal summation unit 362 may represent an analog signal summation unit, and the first signal summation input 361 and the second signal summation input 361' may represent analog signals. The analog signal summation unit may include a circuit that combines multiple analog signals into a single output signal. The signal summation unit 362 may sum the voltages of the input signals to produce a resulting output voltage. For example, the signal summation unit 362 may accept the first signal summation input 361 and the second signal summation input 361' as inputs. In some examples, each input signal may travel to a corresponding input resistor of the signal summation unit 362. The value of the input resistor may determine the weight of each input signal in the final output. In a signal summation unit in which the input signals have equal weights, the input resistors have the same resistance value, but the resistance value may vary for different weighting schemes.

[0059] In some examples, the signal summing unit 362 may include a summing amplifier for performing an addition operation. The summing amplifier may employ an operational amplifier in an inverting configuration. The input resistor of the signal summing unit 362 may be connected to an inverting terminal of the summing amplifier. In some examples, the inverting terminal may be connected to a feedback resistor that provides negative feedback. The output of the summing amplifier may be connected to the inverting terminal via a feedback resistor. The summing amplifier of the signal summing unit 362 may transmit a signal sum output 363 via an output terminal of the summing amplifier. The signal sum output 363 may represent the algebraic sum of the input voltages of the first signal sum input 361 and the second signal sum input 361 'weighted by the resistance value of the input resistor of the signal summing unit 362.

[0060] The comparator 366 may include an electronic circuit that compares the first comparator input 365 and the second comparator input 365' and generates a comparator output 367 based on the comparison. One example function of the comparator 366 is to determine which of the first comparator input 365 and the second comparator input 365' is greater. Another example function of the comparator 366 is to determine whether one of the first comparator input 365 and the second comparator input 365' is above or below a reference voltage. The comparator 366 may include an inverting input (-) and a non-inverting input (+). Figure 3 As seen in FIG. 1 , the first comparator input 365 goes to the non-inverting input and the second comparator input 365 ′ goes to the inverting input.

[0061] In some examples, the inverting input is a terminal that receives an input signal for comparison with another value. In some examples, the non-inverting input is a terminal that receives an input signal for comparison with another value, or receives a reference voltage (the input to the inverting input is compared to the reference voltage). When the voltage at the non-inverting input (+) of the comparator 366 (e.g., the voltage of the first comparator input 365) is greater than the voltage at the inverting input (-) of the comparator 366 (e.g., the voltage of the second comparator input 365'), the output from the comparator 366 can be a high voltage. When the voltage at the inverting input (-) of the comparator 366 (e.g., the voltage of the second comparator input 365') is greater than the voltage at the non-inverting input (+) of the comparator 366 (e.g., the voltage of the first comparator input 365), the output from the comparator 366 can be a low voltage.

[0062] The power control circuit 320 may cause the comparator 366 to receive a first comparator input 365 based on a control signal received from the controller 110 via the input connection 122 and a power signal received from the current sensor 126. In some examples, the first comparator input 365 is substantially equivalent to the signal sum output 363. Since the first comparator input 365 is based on both the control signal from the controller 110 and the power signal from the current sensor 326, the comparator 366 may be configured to generate an output based on both the control signal from the controller 110 and the power signal from the current sensor 326. The power control circuit 320 may cause the comparator 366 to receive a second comparator input 365' based on the control signal received from the controller 110 via the input connection 322. The comparator 366 may generate a comparator output 367 based on the first comparator input 365 and the second comparator input 365'. The comparator output may represent an output signal delivered to the gate driver circuit 136 via the output connection 324.

[0063] In some examples, in response to the first comparator input 365 being greater than the second comparator input 365', the comparator 366 generates the comparator output 367 to include a high voltage that causes the gate driver circuit 136 to turn on the power transistor(s) 138. In some examples, in response to the first comparator input 365 being not greater than the second comparator input 365', the comparator 366 generates the comparator output 367 to include a low voltage that causes the gate driver circuit 136 to turn on the power transistor(s) 138. Since the first comparator input 365 is based at least in part on the power signal from the current sensor 326, this means that the comparator 366 can turn on the power transistor(s) 138 in response to the current across the current sensor 326 being high, and turn off the power transistor(s) 138 in response to the current across the current sensor 326 being low.

[0064] For example, in response to the current across the current sensor 326 being high, the closed-loop system including the power control circuit 320 may turn on the power transistor(s) 138 to sink a portion of the current output from the power source 132 across the power transistor(s) 138. In response to the current across the current sensor 326 being low, the closed-loop system including the power control circuit 320 may turn off the power transistor(s) 138 so that the current output from the power source 132 reaches the load 134 without a portion of the current being sunk across the power transistor(s) 138. The comparator 366 may generate a comparator output 367 to control whether the gate driver circuit 136 turns the power transistor(s) 138 on or off.

[0065] The power control circuit 320 can process the control signal received from the controller 110 via the input connection 322 for input to the signal summing unit 362 and the comparator 366. In some examples, the control signal received from the controller 110 via the input connection 322 can represent a modulated digital signal that includes a square wave sequence at a pulse frequency. The first voltage unit 372 and the second voltage unit 374 can process the control signal received from the controller 110 via the input connection 322. In some examples, the first voltage unit 372 can generate an output for delivery to the first signal ramp unit 368 and the second signal ramp unit 369. In some examples, the second voltage unit 374 can generate an output for delivery to the first S&H circuit 382.

[0066] In some examples, the first signal ramp unit 368 can generate a first ramp pulse train based on a control signal received from the controller 110 via the input connection 322. In some examples, in order for the comparator 366 to receive a first comparator input 365 based on the control signal from the controller 110 and the power signal from the current sensor 326, the power control circuit 320 is configured to use the first signal ramp unit 368 to generate a first ramp signal pulse train corresponding to a control signal pulse train occurring at a control signal frequency. For example, the control signal can include a control signal pulse train occurring at a control signal frequency. The first signal ramp unit 368 can generate a second signal sum input 361' to include a first ramp signal pulse train, so that the signal sum unit 362 generates a signal sum output 363 based on the first signal sum input 361 and the second signal sum input 361'.

[0067] In order to generate a ramp signal from a square wave sequence, the first signal ramp unit 368 can use a circuit that integrates a square wave input to generate a linear voltage ramp. The integration process may involve accumulating charge over time, thereby generating a ramp voltage. For example, the square wave can alternate between two voltage levels (e.g., a high voltage and a low voltage) at a pulse frequency. The first signal ramp unit 368 may include an integrator, which includes an operational amplifier and a capacitor. The integrator can generate an output including a voltage proportional to the integral of the input voltage over time. When the input to the first signal ramp unit 368 is a high voltage (e.g., during each square pulse in a square pulse sequence), the integrator of the first signal ramp unit 368 can charge the capacitor at a constant rate. This may result in a linear increase in the voltage across the capacitor. When the input to the first signal ramp unit 368 is a low voltage (e.g., between consecutive square pulses in a square pulse sequence), the capacitor can be discharged through a resistor, resulting in a voltage reduction.

[0068] The second signal ramp unit 369 can be substantially the same as the first signal ramp unit 368, except that the second signal ramp unit 369 generates an output for delivery to the first S&H circuit 382, ​​while the first signal ramp unit 368 generates an output for delivery to the signal summing unit 362. In some examples, in order for the comparator 366 to receive a second comparator input based on the control signal from the controller 110, the power control circuit 320 is configured to generate an output using the second signal ramp unit 369 to include a second ramp signal pulse train corresponding to the control signal pulse train of the control signal occurring at the control signal frequency. In some examples, the second ramp signal pulse train output from the second signal ramp unit 369 can be further processed by the first S&H circuit 382 and the second S&H circuit 384 to generate a second comparator input 365'.

[0069] The first S&H circuit 382 can capture and store a signal at a particular moment, making it available as a constant voltage for further processing or conversion. For example, the first S&H circuit 382 can sample an input analog signal. A sampling switch, typically controlled by a clock signal or a trigger, can be used to connect the input signal to a storage capacitor. During the sampling phase, the input signal can be connected to the capacitor. The storage capacitor can be charged to the voltage level of the input signal. This can allow the first S&H circuit to capture a snapshot of the voltage of the input signal at a particular moment. In some examples, after the sampling phase, the first S&H circuit 382 can open the sampling switch, thereby disconnecting the input signal from the storage capacitor. The first S&H circuit 382 can close the holding switch, thereby connecting the capacitor to the output of the first S&H circuit. In some examples, a buffer amplifier can be placed between the storage capacitor and the output. The buffer can maintain the sampled voltage and reduce the load on the storage capacitor, thereby ensuring that the voltage remains relatively constant during the holding phase.

[0070] The second S&H circuit 384 may be substantially the same as the first S&H circuit, except that the second S&H circuit 384 receives inputs from the first voltage unit 372 and the first S&H circuit 382, ​​while the first S&H circuit 382 receives inputs from the second voltage unit 374 and the second signal ramp unit 369. The blank unit 376 may receive inputs from the first voltage unit 372 and generate an output to the comparator 366.

[0071] Figure 4 is a flow chart illustrating example operations for using a power control circuit to control power to a load based on a control signal and a power signal, in accordance with one or more techniques of this disclosure. Figure 1 Description of System 100 Figure 4 .However, Figure 4The techniques of may be performed by different components of system 100, or by additional or alternative systems.

[0072] The power control circuit 120 can use the current sensor 126 to generate a power signal (402) corresponding to the electrical signal delivered from the power source 132 to the load 134. For example, the power source 132 can deliver an electrical signal to the load 134, which passes through the current sensor 126 of the power control circuit 120. In some examples, the electrical signal includes a current and a voltage. In some examples, a magnetic field is associated with the electrical signal. It may be beneficial for the power control circuit 120 to control the power delivered to the load 134 based on the power signal generated by the current sensor 126. For example, it may be beneficial to prevent the current and / or voltage at the load 134 from exceeding a high threshold or falling below a low threshold.

[0073] The power control circuit 120 may receive a control signal from the controller 110 via an input connection 122 of the power control circuit 120, the control signal comprising a control signal pulse train occurring at a control signal frequency (404). In some examples, the control signal pulse train may comprise a square pulse train. In some examples, the control signal may represent a digital PWM signal. In some examples, the control signal frequency may represent a frequency used to control the power transistor(s) 138. That is, the power control circuit 120 may control the power transistor(s) 138 based in part on the control signal comprising a control signal pulse train occurring at the control signal frequency.

[0074] The power control circuit 120 may generate an output signal based on the power signal, the control signal pulse train, and the control signal frequency (406). For example, the power control circuit 120 may generate an output signal based on the power signal and the control signal. For example, the control signal may include a frequency for controlling the (one or more) power transistors 138. The power signal may indicate a need to absorb power from the load 134. For example, when the power signal indicates a higher current, it may be beneficial to control the (one or more) power transistors 138 to absorb current from the load 134, and when the power signal indicates a lower current, it may be beneficial to control the (one or more) power transistors 138 not to absorb current from the load 134. The power control circuit 120 may deliver the output signal via the output connection 124 of the power control circuit 120 to control the gate driver circuit 136 to manage the power signal delivered from the power source 132 to the load 134 (408).

[0075] The following numbered clauses may describe one or more aspects of the present disclosure.

[0076] Clause 1: A power control circuit includes an input connection, an output connection, and a current sensor configured to generate a power signal corresponding to an electrical signal delivered from a power source to a load. The power control circuit is configured to receive a control signal from a controller via the input connection, the control signal including a control signal pulse train occurring at a control signal frequency, and to generate an output signal based on the power signal, the control signal pulse train, and the control signal frequency. The power control circuit is configured to deliver the output signal via the output connection to control a gate driver circuit to manage the power signal delivered from the power source to the load.

[0077] Item 2: A power control circuit according to Item 1, wherein to generate an output signal, the power control circuit is configured to generate the output signal to include a gate control pulse sequence, wherein each gate control pulse in the gate control pulse sequence is configured to cause the power transistor to turn on and off according to a power transistor switching cycle, and wherein to deliver the output signal, the power control circuit is configured to deliver the output signal to a gate driver circuit such that the gate driver circuit controls a gate terminal of the power transistor such that the power transistor is turned off and on according to the gate control pulse sequence.

[0078] Item 3: A power control circuit according to Item 2, wherein the power transistor is connected to a node located between a power source and a load, such that when the power control circuit delivers an output signal to a gate driver circuit to control the power transistor, the power control circuit is configured to: in response to the power transistor being turned on, cause at least a portion of the power signal to flow through the power transistor; and in response to the power transistor being turned off, cause the power signal to flow from the power source to the load without flowing through the power transistor.

[0079] Clause 4: A power control circuit according to any one of clauses 1-3, wherein the power control circuit also includes a signal summation unit, and wherein the power control circuit is further configured to: cause the signal summation unit to receive a first signal summation input based on a power signal from a current sensor; cause the signal summation unit to receive a second signal summation input based on a control signal from an input connection; use the signal summation unit to generate a signal summation output based on the first signal summation input and the second signal summation input, wherein the signal summation output includes the sum of the first signal summation input and the second signal summation input; and generate an output signal based on the signal summation output.

[0080] Item 5: A power control circuit according to Item 4, wherein the power control circuit also includes a signal ramp unit, and wherein the power control circuit is further configured to generate a second signal sum input based on a control signal from an input connection using the signal ramp unit, wherein the second signal sum input includes a ramp signal pulse sequence corresponding to a control signal pulse sequence occurring at a control signal frequency.

[0081] Clause 6: A power control circuit according to any one of clauses 1-5, wherein the power control circuit also includes a comparator, and wherein in order to generate an output signal, the power control circuit is configured to: cause the comparator to receive a first comparator input based on a control signal from the controller and a power signal from the current sensor; cause the comparator to receive a second comparator input based on the control signal from the controller; and use the comparator to generate a comparator output based on the first comparator input and the second comparator input, wherein the comparator output includes an output signal delivered to a gate driver circuit.

[0082] Item 7: A power control circuit according to Item 6, wherein the power control circuit further includes a first signal ramp unit and a second signal ramp unit, wherein in order for the comparator to receive a first comparator input based on a control signal from a controller and a power signal from a current sensor, the power control circuit is configured to: generate a first ramp signal pulse sequence corresponding to a control signal pulse sequence appearing at a control signal frequency using the first signal ramp unit; and generate a first comparator input based on the first ramp signal pulse sequence and the power signal from the current sensor, and wherein in order for the comparator to receive a second comparator input based on a control signal from the controller, the power control circuit is configured to generate a second comparator input using the second signal ramp unit to include a second ramp signal pulse sequence corresponding to a control signal pulse sequence appearing at a control signal frequency.

[0083] Clause 8: A power control circuit according to any of clauses 1-7, wherein the control signal includes an analog control signal, wherein the power control circuit is configured such that the controller receives the analog feedback signal by delivering the output signal to the gate driver circuit to control the power signal delivered from the power source to the load, wherein the analog feedback signal indicates one or more parameters of the power signal delivered from the power source to the load, and wherein the analog control signal is based on the analog feedback signal.

[0084] Clause 9: The power control circuit of any of clauses 1-8, wherein the control signal comprises a modulated digital signal.

[0085] Clause 10: The power control circuit of any of clauses 1-9, wherein to deliver the output signal to control the gate driver circuit to manage the power signal, the power control circuit is configured to deliver the output signal to the gate driver circuit.

[0086] Clause 11: The power control circuit of any of clauses 1-10, wherein to deliver the output signal to control the gate driver circuit to manage the power signal, the power control circuit is configured to deliver the output signal to the controller so that the controller controls the gate driver circuit to manage the power signal.

[0087] Clause 12: The power control circuit of any of clauses 1-11, wherein the current sensor comprises a Hall effect sensor configured to sense a magnetic field corresponding to the current of the power signal.

[0088] Clause 13: A method includes: generating, by a current sensor of a power control circuit, a power signal corresponding to an electrical signal delivered from a power source to a load; and receiving, by the power control circuit, a control signal from a controller via an input connection of the power control circuit, the control signal including a control signal pulse train occurring at a control signal frequency. The method also includes: generating, by the power control circuit, an output signal based on the power signal, the control signal pulse train, and the control signal frequency; and delivering, by the power control circuit, the output signal via an output connection to control a gate driver circuit to manage the power signal delivered from the power source to the load.

[0089] Item 14: A method according to item 13, wherein generating an output signal comprises: generating the output signal by a power control circuit to include a gate control pulse sequence, wherein each gate control pulse in the gate control pulse sequence is configured to cause the power transistor to turn on and off according to a power transistor switching cycle, and wherein delivering the output signal comprises: delivering the output signal by the power control circuit to a gate driver circuit such that the gate driver circuit controls a gate terminal of the power transistor such that the power transistor is turned off and on according to the gate control pulse sequence.

[0090] Item 15: A method according to Item 14, wherein the power transistor is connected to a node located between a power source and a load, so that when a power control circuit delivers an output signal to a gate driver circuit to control the power transistor, the method includes: in response to the power transistor being turned on, the power control circuit causes at least a portion of the power signal to flow through the power transistor; and in response to the power transistor being turned off, the power control circuit causes the power signal to flow from the power source to the load without flowing through the power transistor.

[0091] Clause 16: A method according to any one of clauses 13-15, wherein the power control circuit further includes a signal summation unit, and wherein the method further includes: the power control circuit causes the signal summation unit to receive a first signal summation input based on a power signal from a current sensor; the power control circuit causes the signal summation unit to receive a second signal summation input based on a control signal from an input connection; the power control circuit uses the signal summation unit to generate a signal summation output based on the first signal summation input and the second signal summation input, wherein the signal summation output includes the sum of the first signal summation input and the second signal summation input; and the power control circuit generates an output signal based on the signal summation output.

[0092] Item 17: A method according to Item 16, wherein the power control circuit further comprises a signal ramp unit, and wherein the method further comprises: the power control circuit uses the signal ramp unit to generate a second signal sum input based on a control signal from an input connection, wherein the second signal sum input comprises a ramp signal pulse sequence corresponding to a control signal pulse sequence occurring at a control signal frequency.

[0093] Clause 18: A method according to any one of clauses 13-17, wherein the power control circuit further includes a comparator, and wherein generating an output signal includes: the power control circuit causes the comparator to receive a first comparator input based on a control signal from a controller and a power signal from a current sensor; the power control circuit causes the comparator to receive a second comparator input based on the control signal from the controller; and the power control circuit uses the comparator to generate a comparator output based on the first comparator input and the second comparator input, wherein the comparator output includes an output signal delivered to a gate driver circuit.

[0094] Item 19: A method according to Item 18, wherein the power control circuit further includes a first signal ramp unit and a second signal ramp unit, wherein causing the comparator to receive a first comparator input based on a control signal from a controller and a power signal from a current sensor comprises: the power control circuit uses the first signal ramp unit to generate a first ramp signal pulse sequence corresponding to a control signal pulse sequence occurring at a control signal frequency; and the power control circuit generates the first comparator input based on the first ramp signal pulse sequence and the power signal from the current sensor, and wherein causing the comparator to receive a second comparator input based on the control signal from the controller comprises: the power control circuit uses the second signal ramp unit to generate a second comparator input to include a second ramp signal pulse sequence corresponding to a control signal pulse sequence occurring at a control signal frequency.

[0095] Clause 20: A system includes a controller, a gate driver circuit, and a power control circuit. The power control circuit includes an input connection, an output connection, and a current sensor configured to generate a power signal corresponding to an electrical signal delivered from a power source to a load. The power control circuit is configured to: receive a control signal from the controller via the input connection, the control signal including a control signal pulse train occurring at a control signal frequency; generate an output signal based on the power signal, the control signal pulse train, and the control signal frequency; and deliver the output signal via the output connection to control the gate driver circuit to manage the power signal delivered from the power source to the load.

[0096] The techniques described in the present disclosure may be implemented, at least in part, in hardware, software, firmware, or any combination thereof. For example, various aspects of the described techniques may be implemented within one or more processors, including one or more microprocessors, DSPs, ASICs, FPGAs, or any other equivalent integrated or discrete logic circuit devices, as well as any combination of these components. The term "processor" or "processing circuit device" generally refers to any of the aforementioned logic circuit devices (alone or in combination with other logic circuit devices) or any other equivalent circuit device. A control unit including hardware may also perform one or more techniques of the present disclosure.

[0097] Such hardware, software, and firmware may be implemented in the same device or in separate devices to support the various operations and functions described in this disclosure. In addition, any of the described units, modules, or components may be implemented together, or individually as discrete but interoperable logic devices. Depicting different features as modules or units is intended to highlight different functional aspects, and does not necessarily imply that such modules or units must be implemented by separate hardware or software components. On the contrary, the functions associated with one or more modules or units may be performed by separate hardware or software components, or integrated in common or separate hardware or software components.

[0098] The techniques described in the present disclosure may also be implemented or encoded in a computer-readable medium containing instructions, such as a computer-readable storage medium. The instructions embedded or encoded in the computer-readable storage medium may cause a programmable processor or other processor, for example, to perform the method when the instructions are executed. The computer-readable storage medium may include RAM, ROM, programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), EEPROM, flash memory, hard disk, compact disk read-only memory (CD-ROM), floppy disk, cassette, magnetic media, optical media, or other computer-readable media.

[0099] Various examples have been described. These and other examples are within the scope of the following claims.

Claims

1. A power control circuit, comprising: Input connection; Output connections; as well as a current sensor configured to generate a power signal corresponding to an electrical signal delivered from a power source to a load, The power control circuit is configured as follows: receiving a control signal from a controller via the input connection, the control signal comprising a train of control signal pulses occurring at a control signal frequency; generating an output signal based on the power signal, the control signal pulse sequence, and the control signal frequency; and The output signal is delivered via the output connection to control a gate driver circuit to manage the power signal delivered from the power source to the load.

2. The power control circuit according to claim 1, wherein in order to generate the output signal, the power control circuit is configured to generate the output signal to include a gate control pulse sequence, wherein each gate control pulse in the gate control pulse sequence is configured to cause the power transistor to turn on and off according to a power transistor switching cycle, and Wherein, in order to deliver the output signal, the power control circuit is configured to deliver the output signal to the gate driver circuit so that the gate driver circuit controls the gate terminal of the power transistor so that the power transistor is turned off and on according to the gate control pulse sequence.

3. The power control circuit of claim 2, wherein the power transistor is connected to a node between the power source and the load, such that when the power control circuit delivers the output signal to the gate driver circuit to control the power transistor, the power control circuit is configured to: In response to the power transistor being turned on, causing at least a portion of the power signal to flow through the power transistor; and In response to the power transistor being turned off, the power signal is caused to flow from the power source to the load without flowing through the power transistor.

4. The power control circuit according to claim 1, wherein the power control circuit further comprises a signal summation unit, and wherein the power control circuit is further configured to: causing the signal summing unit to receive a first signal summing input based on the power signal from the current sensor; causing the signal summation unit to receive a second signal summation input based on the control signal from the input connection; generating, using the signal summation unit, a signal summation output based on the first signal summation input and the second signal summation input, wherein the signal summation output comprises a sum of the first signal summation input and the second signal summation input; and The output signal is generated based on the signal sum output.

5. A power control circuit according to claim 4, wherein the power control circuit also includes a signal ramp unit, and wherein the power control circuit is further configured to: use the signal ramp unit to generate the second signal sum input based on the control signal from the input connection, wherein the second signal sum input includes a ramp signal pulse sequence corresponding to the control signal pulse sequence occurring at the control signal frequency.

6. The power control circuit according to claim 1, wherein the power control circuit further comprises a comparator, and wherein in order to generate the output signal, the power control circuit is configured to: causing the comparator to receive a first comparator input based on the control signal from the controller and the power signal from the current sensor; causing the comparator to receive a second comparator input based on the control signal from the controller; and Using the comparator, a comparator output is generated based on the first comparator input and the second comparator input, wherein the comparator output comprises the output signal delivered to the gate driver circuit.

7. The power control circuit according to claim 6, wherein the power control circuit further comprises a first signal ramp unit and a second signal ramp unit, Wherein, in order for the comparator to receive the first comparator input based on the control signal from the controller and the power signal from the current sensor, the power control circuit is configured as follows: generating, using the first signal ramp unit, a first ramp signal pulse train corresponding to the control signal pulse train occurring at the control signal frequency; and generating the first comparator input based on the first ramp signal pulse train and the power signal from the current sensor, and Wherein, in order to enable the comparator to receive the second comparator input based on the control signal from the controller, the power control circuit is configured to generate the second comparator input using the second signal ramp unit to include a second ramp signal pulse sequence corresponding to the control signal pulse sequence occurring at the control signal frequency.

8. The power control circuit according to claim 1, wherein the control signal comprises an analog control signal, wherein the power control circuit is configured such that the controller receives an analog feedback signal by delivering the output signal to the gate driver circuit to control the power signal delivered from the power source to the load, wherein the analog feedback signal is indicative of one or more parameters of the power signal delivered from the power source to the load, and Wherein the analog control signal is based on the analog feedback signal.

9. The power control circuit of claim 1, wherein the control signal comprises a modulated digital signal. 10 . The power control circuit of claim 1 , wherein to deliver the output signal to control the gate driver circuit to manage the power signal, the power control circuit is configured to deliver the output signal to the gate driver circuit.

11. The power control circuit of claim 1 , wherein in order to deliver the output signal to control the gate driver circuit to manage the power signal, the power control circuit is configured to deliver the output signal to the controller so that the controller controls the gate driver circuit to manage the power signal.

12. The power control circuit of claim 1, wherein the current sensor comprises a Hall effect sensor configured to sense a magnetic field corresponding to the current of the power signal.

13. A method comprising: generating, by a current sensor of the power control circuit, a power signal corresponding to the electrical signal delivered from the power source to the load; receiving, by the power control circuit from a controller via an input connection of the power control circuit, a control signal comprising a train of control signal pulses occurring at a control signal frequency; generating, by the power control circuit, an output signal based on the power signal, the control signal pulse sequence, and the control signal frequency; as well as The output signal is delivered by the power control circuit via an output connection to control a gate driver circuit to manage the power signal delivered from the power source to the load.

14. The method according to claim 13, Wherein generating the output signal comprises: generating the output signal by the power control circuit to include a sequence of gate control pulses, wherein each gate control pulse in the sequence of gate control pulses is configured to cause the power transistor to turn on and off according to a power transistor switching cycle, and The delivering of the output signal comprises: the power control circuit delivering the output signal to the gate driver circuit so that the gate driver circuit controls the gate terminal of the power transistor so that the power transistor is turned off and on according to the gate control pulse sequence.

15. The method of claim 14, wherein the power transistor is connected to a node between the power source and the load such that when the power control circuit delivers the output signal to the gate driver circuit to control the power transistor, the method comprises: In response to the power transistor being turned on, causing at least a portion of the power signal to flow through the power transistor by the power control circuit; as well as In response to the power transistor being turned off, the power control circuit causes the power signal to flow from the power source to the load without flowing through the power transistor.

16. The method of claim 13, wherein the power control circuit further comprises a signal summing unit, and wherein the method further comprises: The power control circuit enables the signal summing unit to receive a first signal summing input based on the power signal from the current sensor; causing the signal summing unit to receive, by the power control circuit, a second signal summing input based on the control signal from the input connection; generating, by the power control circuit, a signal sum output based on the first signal sum input and the second signal sum input using the signal sum unit, wherein the signal sum output comprises a sum of the first signal sum input and the second signal sum input; as well as The output signal is generated by the power control circuit based on the signal sum output.

17. The method of claim 16, wherein the power control circuit further comprises a signal ramp unit, and wherein the method further comprises: The second signal sum input is generated by the power control circuit using the signal ramp unit based on the control signal from the input connection, wherein the second signal sum input includes a ramped signal pulse train corresponding to the control signal pulse train occurring at the control signal frequency.

18. The method of claim 13, wherein the power control circuit further comprises a comparator, and wherein generating the output signal comprises: causing the comparator to receive, by the power control circuit, a first comparator input based on the control signal from the controller and the power signal from the current sensor; causing the comparator to receive a second comparator input based on the control signal from the controller by the power control circuit; as well as A comparator output is generated by the power control circuit using the comparator based on the first comparator input and the second comparator input, wherein the comparator output comprises the output signal delivered to the gate driver circuit.

19. The method according to claim 18, wherein the power control circuit further comprises a first signal ramp unit and a second signal ramp unit, Wherein causing the comparator to receive the first comparator input based on the control signal from the controller and the power signal from the current sensor comprises: generating, by the power control circuit, a first ramp signal pulse sequence corresponding to the control signal pulse sequence occurring at the control signal frequency using the first signal ramp unit; as well as generating the first comparator input by the power control circuit based on the first ramp signal pulse train and the power signal from the current sensor, and Wherein causing the comparator to receive the second comparator input based on the control signal from the controller includes: generating the second comparator input by the power control circuit using the second signal ramp unit to include a second ramp signal pulse sequence corresponding to the control signal pulse sequence occurring at the control signal frequency.

20. A system comprising: Controller; Gate driver circuit; as well as A power control circuit comprising: Input connection; output connections; and a current sensor configured to generate a power signal corresponding to an electrical signal delivered from a power source to a load, The power control circuit is configured as follows: receiving a control signal from the controller via the input connection, the control signal comprising a train of control signal pulses occurring at a control signal frequency; generating an output signal based on the power signal, the control signal pulse sequence, and the control signal frequency; and The output signal is delivered via the output connection to control the gate driver circuit to manage the power signal delivered from the power source to the load.

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