Dynamic power management system for low power and high performance radar applications

Abstract

A radar device includes a radar function, a driver configured to control a path device, and a radar controller. The radar function is configured to generate radar frames in a first mode for generating high isolation frames and a second mode for generating low isolation frames. The radar function has a supply voltage input and is configured to operate with the supply voltage input at a radar supply voltage level. The radar controller configures the driver to control the pass device to regulate a voltage provided to the supply voltage input of the radar function to the radar supply voltage level with a high power supply rejection ratio to minimize a ripple voltage when the radar function is in the first mode, and the driver is configured to force the pass device into a bypass mode to reduce power dissipation when the radar function is in the second mode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Indian Application No. 202341067043 filed on October 6, 2023, the contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates generally to radar sensors and, more particularly, to a dynamic power management system for low power high performance radar applications. Background Art

[0004] A radar sensor is an electromagnetic device used to detect the characteristics (e.g., position, distance, size, identification, etc.) of an external object or "target" at a variable distance. A radar sensor transmits electromagnetic energy in the environment and receives a portion of the reflected energy in the form of an echo. A highly integrated modern radar sensor may consist of a power management integrated circuit (PMIC) and a radar IC configured as a system on a chip (SoC). Although some radar functions, such as a radar digital core or other radar digital signal processing (DSP) functions, may be directly powered by a PMIC rail using a buck converter, etc., other key radar functions such as transmit (TX), receiver (RX) functions, analog / digital conversion (ADC) functions, etc. should be isolated from the PMIC ripple by at least one isolation barrier. Such isolation is expected to avoid spurious signals in the intermediate frequency (IF) spectrum that may appear as false targets. Low-end radar sensors typically require a low-cost housing (e.g., a plastic package, etc.), which requires minimal sensor power dissipation.

[0005] The disadvantages of conventional radar configurations include the high power dissipation of the radar sensor and its cost, as well as the impact of the PMIC ripple on the radar sensor signal integrity in terms of undesirable spurious signals, etc. Due to the DC-DC buck converter activity in the form of ripple voltage, low-cost PMICs present high spurious signal levels around the IF spectrum, so that additional barriers may be added between the PMIC and the radar IC. The additional barriers may reduce the overall power efficiency of the radar sensor. Using a PMIC with very low ripple is a conventional option, but this increases the overall radar sensor cost. Summary of the invention

[0006] According to an embodiment, a radar device includes:

[0007] a radar function having a supply voltage input and being configured to operate at said supply voltage input at a radar supply voltage level and having a first mode for generating a high isolation frame and a second mode for generating a low isolation frame;

[0008] a driver configured to control the access device; and

[0009] a radar controller that configures the driver to control the access device to adjust the voltage provided to the supply voltage input of the radar function to the radar supply voltage level when in the first mode, and configures the driver to force the access device into a bypass mode when in the second mode.

[0010] Illustratively, the driver is configured to control the channel device to regulate the supply voltage provided to the radar function with a high power supply rejection ratio in the first mode, and wherein the driver is configured to force the channel device to have zero voltage drop in the second mode.

[0011] Exemplarily, the radar controller is configured to instruct an external voltage converter to output a voltage at the radar supply voltage level to the path device in the second mode, or to output a voltage at an upper voltage level greater than the radar supply voltage level to the path device in the first mode.

[0012] Illustratively, the driver includes a low dropout regulator controller configured to regulate voltage in the first mode and to force the pass device in the second mode.

[0013] Illustratively, the driver is configured to control a bipolar junction transistor as the pass device.

[0014] Illustratively, the radar function operates according to the received radar profile to generate a total number of radar frames including at least one frame set, wherein each frame set includes a first number of high isolation frames followed by a second number of low isolation radar frames.

[0015] Illustratively, the total number as well as the first number and the second number are determined according to a use case.

[0016] Illustratively, the result received for the high isolation frame is used as reference information for the result received for the low isolation frame.

[0017] For example, the driver includes:

[0018] an operational amplifier having a first input receiving a reference voltage, a second input coupled to a control node, and an output for coupling to a control terminal of the pass device;

[0019] a first resistor having a first end coupled to the supply voltage input of the radar function and having a second end coupled to the control node;

[0020] a second resistor having a first end coupled to the control node and having a second end coupled to a power reference node; and

[0021] A switch controlled by the radar controller for selectively coupling the output of the operational amplifier to the power supply reference node.

[0022] According to an embodiment, a radar sensor includes:

[0023] a radar device configured to generate radar frames, wherein the radar device has a first mode for generating high isolation frames and has a second mode for generating low isolation frames, and wherein the radar device comprises a radar function having a supply voltage input and is configured to operate at the supply voltage input at a radar supply voltage level;

[0024] a converter having a programmable voltage output, wherein the converter is directed to output a voltage at the radar supply voltage level or at an upper voltage level greater than the radar supply voltage level;

[0025] a voltage control system comprising a driver coupled to a pass device, wherein the pass device comprises a current terminal coupled between the voltage output of the converter and the supply voltage input of the radar function, and wherein the driver has a control output coupled to a control terminal of the pass device; and

[0026] a radar controller that instructs the converter to output a voltage at the upper voltage level and configures the driver to control the access device to adjust the voltage of the supply voltage input provided to the radar function to the radar supply voltage level to configure the radar device in the first mode, and instructs the converter to output a voltage at the radar supply voltage level and configures the driver to force the access device to be in a bypass mode to configure the radar device in the second mode.

[0027] Illustratively, the driver of the voltage control system controls the pass device in the first mode to regulate the supply voltage provided to the radar function with a power supply rejection ratio sufficient to minimize a ripple voltage at the voltage output of the converter, and wherein the driver forces the pass device to have zero voltage drop between the pass device current terminals in the second mode.

[0028] Illustratively, the converter comprises a DC-DC buck converter outputting a voltage having a ripple voltage indicative of DC-DC switching.

[0029] Illustratively, the driver comprises a low dropout regulator controller, and wherein the pass device comprises a bipolar junction transistor.

[0030] Illustratively, the radar apparatus operates according to the received radar profile to generate a plurality of radar frames including at least one frame set, wherein each frame set includes a first number of high isolation frames followed by a second number of low isolation radar frames.

[0031] According to an embodiment, a method for generating a radar frame includes:

[0032] Configure the radar sensor to generate high isolation frames, including:

[0033] instructing to provide a supply voltage at an upper voltage level greater than a radar supply voltage level suitable for a radar function of the radar sensor; and

[0034] driving a pass-through device receiving the supply voltage to regulate the supply voltage input of the radar function to the radar supply voltage level; and

[0035] Configuring the radar sensor to generate a low isolation frame includes:

[0036] instructing to provide a supply voltage at the radar supply voltage level; and

[0037] The pass-through device is forced into a bypass mode to pass the supply voltage to the supply voltage input of the radar function.

[0038] Illustratively, the driving the path means comprises: for the high isolation frame, driving the path means to regulate the voltage at the supply voltage input of the radar function with a power supply rejection ratio sufficient to minimize a ripple voltage of the supply voltage.

[0039] Illustratively, the forcing the pass device comprises: forcing the pass device to have a zero voltage drop for the low isolation frame.

[0040] For example, the method further includes:

[0041] receiving a profile indicating a total number of radar frames to be generated for a radar session, a first number of high isolation frames per frame set for the radar session, and a second number of low isolation frames per frame set;

[0042] configuring the radar sensor to generate high isolation frames for a first time and generating the first number of high isolation frames;

[0043] configuring the radar sensor a second time to generate low isolation frames and generating the second number of low isolation frames; and

[0044] The first configuration and the second configuration and generation are repeated until the total number of radar frames have been generated.

[0045] Illustratively, the method further comprises determining the total number, the first number and the second number according to a use case.

[0046] Illustratively, the method further comprises using the result received from the high isolation frame as reference information for the result received from the low isolation frame. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Embodiments of the present invention are illustrated by way of example and are not limited by the accompanying drawings. Similar reference numerals in the drawings may indicate similar elements. For simplicity and clarity, the elements in the drawings are illustrated and are not necessarily drawn to scale.

[0048] Figure 1 is a simplified block diagram of a radar sensor implemented according to one embodiment.

[0049] Figure 2 is a simplified block diagram illustrating high isolation (HI) radar frames generated in mode M1 and low isolation (LI) radar frames generated in mode M2 ​​according to one embodiment.

[0050] Figure 3 is a simplified block diagram illustrating an exemplary set of frames according to one embodiment.

[0051] Figure 4 is a simplified block diagram illustrating an exemplary radar session including a total number K of radar frames, according to one embodiment.

[0052] Figure 5 is a diagram showing an implementation according to an embodiment Figure 4 Radar Conversation Figure 1 Flowchart of the operation of a radar sensor.

[0053] Figure 6 is a schematic diagram of an exemplary LDO regulator according to one embodiment, the exemplary LDO regulator including an exemplary driver coupled to a corresponding exemplary pass device to implement Figure 1 Either or both of a driver of an LDO regulator and a corresponding pass device. DETAILED DESCRIPTION

[0054] The isolation barrier between the power management integrated circuit (PMIC) ripple and the radar device configured as a radar integrated circuit (IC) improves signal integrity at the expense of increased power dissipation, making a good compromise between power dissipation and received signal integrity favorable. The specific compromise may depend on the use case of a given radar session. As used herein, "use case" refers to a set of parameters or variables that define the radar application, the environment being scanned or monitored, or the desired resolution required for a given radar session. The isolation barrier between the PMIC and the radar device can be built internally (LDO regulator, including a controller and a pass device configured inside the radar IC), built externally (through an LDO on the board), or built in a hybrid manner, such as providing a pass device on the board, where the control circuit system is within the radar IC. The hybrid solution generally achieves a good compromise between dissipation, isolation, area and cost at the IC level.

[0055] The radar device can control a low-cost PMIC with a programmable buck converter that produces different output voltage levels according to the use case. It should be noted that in other embodiments, the PMIC can be controlled by another controller device (not shown), depending on the components in the radar sensor and the functions and roles of the components in the entire radar system. Another controller device can be configured as a microcontroller (MCU) or a processor, such as a digital signal processor (DSP), etc. Each of the different output voltages presents a relatively high level of ripple. A controlled channel device is provided as a barrier between the PMIC output and the radar IC power input. In the first mode for generating a high-isolation radar frame, the PMIC is programmed to output an upper voltage level, and the channel device is controlled to reduce the voltage to the regulated supply voltage level required by the radar IC, while also minimizing the ripple of the upper voltage level at the regulated supply voltage output. In the first mode, the radar IC generates one or more radar range and Doppler data graphs representing the distance and speed of the radar target, respectively, while the spurious signal energy that may have been caused by the ripple voltage present in the supply voltage at the upper voltage level is minimized. The high isolation mode achieves more accurate results at the expense of additional power dissipation.

[0056] In the second low power mode for generating low isolation radar frames, the PMIC is programmed to output a lower voltage level that is substantially at the supply voltage level required by the radar functional circuit system of the radar IC, and the access device is controlled to operate as a low resistance switch with substantially zero voltage drop. When the access device operates in this way without regulation, the ripple voltage present in the supply voltage at the lower voltage level is passed to the radar IC. Therefore, in this low isolation mode, the radar sensor operates at reduced power at the expense of increased spurious noise in the radar range and Doppler data map. However, in continuous radar frames, one or more high isolation low noise frames may be interleaved with low isolation high noise frames to establish a suitable compromise between performance and power dissipation. Comparisons can be made between low noise and corresponding high noise range and Doppler data maps to identify and filter out spurious noise using digital processing techniques.

[0057] Figure 1 1 is a simplified block diagram of a radar sensor 100 implemented according to one embodiment. The radar sensor 100 includes a power management integrated circuit (PMIC) 102, a radar device in the form of a radar integrated circuit (IC) 104, one or more access devices 106, and a power source 108. In various embodiments, the power source 108 may be a battery (not shown), such as a car battery, or may be another PMIC coupled to the battery. The radar IC 104 is a radar device configured to generate a radar frame using one or more radar functions 110. As used herein, the term "radar function" is defined as a radar circuit system of the radar IC 104, which is configured to perform one or more radar functions performed by the radar IC 104 when operating as part of a radar sensor. In the illustrated configuration, the radar IC 104 incorporates two radar functions 110, respectively labeled RF1 and RF2, wherein one or both of RF1 and RF2 may be used when generating a radar frame. In one embodiment, for example, RF1 may include circuitry forming a receiver, clock generator, radar chirp generator, bias generator, built-in self-test (BIST) functionality, etc., while RF2 may include one or more radar transmitter circuits.

[0058] The pass devices 106, labeled P1 and P2, respectively, are used by a low voltage drop (LDO) controller 114 of the radar IC 104 to control the supply voltage provided to the radar functions RF1 and RF2, respectively. RF1 and RF2 are shown as being in separate voltage source domains, but the RF1 and RF2 may be included in the same voltage source domain in an alternative configuration. In some configurations, the power domain of the radar transmitter may be separated from other radar functions to avoid any interference issues, or to allow transmitter power domain flexibility in order to control output power transmission. The radar IC 104 may be configured as a system on a chip (SoC), and may also include a radar controller 112, an LDO controller 114, and a control interface (I / F) 116. The LDO controller 114 and the pass device 106 are collectively configured as an LDO regulator 115, which operates as a voltage control system that forms an isolation barrier between the PMIC 102 and the radar function 110, as further described herein.

[0059] The PMIC 102 includes a control I / F 118, a power controller 120, and one or more DC-DC buck converters, which are shown as N buck converters 121, and are individually shown as BUCK1 122, BUCK2 123, ..., BUCKN 124. N is any suitable integer greater than zero, and includes the case of N=1, when only one buck converter 121 is provided. In general, the power supply 108 provides a supply voltage to the voltage source input of the PMIC 102, and the PMIC 102 provides the DC-DC converted supply voltage to the various components of the radar IC 104. The radar IC 104 may include additional circuitry (not shown), and the PMIC 102 may include additional voltage converters or regulators of the same or different types for providing supply voltages to the additional circuitry of the radar IC 104. In one embodiment, buck converter 121 is a relatively low-cost converter that performs DC-DC switching at an intermediate frequency (IF) spectrum with significant ripple voltage that may otherwise interfere with the operation of radar IC 104 when generating radar frames, as further described herein.

[0060] In the configuration shown, BUCK1 122 outputs a first supply voltage VP1 to a pass device P1, and BUCK2 123 outputs a second supply voltage VP2 to a pass device P2. Additional buck converters may be provided for additional pass devices and corresponding radar functions of the radar IC 104 or for other elements (not shown) in the radar sensor 100, such as memory devices, controllers, drivers, other radar ICs for cascaded systems, etc. The last BUCK2 124 outputs an Nth supply voltage VPN that is provided to the power input of the radar controller 112. Pass device P1 receives VP1 and provides a first supply voltage VS1 to the supply voltage input of the radar function RF1, and pass device P2 receives VP2 and provides a second supply voltage VS2 to the supply voltage input of the radar function RF2. The LDO controller 114 provides a first control voltage VC1 to the control terminal of the pass device P1, and a second control voltage VC2 to the control terminal of the pass device P2. Selected ones of the supply voltages VP (e.g., VP1 and VP2) are at an upper voltage level (UVL) or a lower voltage level (LVL). As further described herein, BUCK1 122 is instructed to provide VP1 at an upper voltage level UVL1 or a lower voltage level LVL1, where LVL1 has a radar supply voltage level suitable for operating a first radar function RF1. Similarly, BUCK2 123 is instructed to provide VP2 at an upper voltage level UVL2 or a lower voltage level LVL2, where LVL2 has a radar supply voltage level suitable for operating a second radar function RF2.

[0061] It should be noted that if RF1 and RF2 are configured to operate with substantially the same supply voltage, or VS1=VS2, then UVL1=UVL2 and LVL1=LVL2. In this case, a single buck converter 121 may be provided to generate a single supply voltage VP provided to both of the pass devices P1 and P2. In addition, although two radar functions RF1 and RF2 are shown for the radar IC 104, in an alternative configuration, any suitable number of radar functions 110 may be provided, including a single radar function. A plurality of different radar functions 110 may be included, each operating at a different supply voltage such that LVL1 and LVL2 are different. In general, separate buck converters 121 and pass devices may be provided to generate different UVLi and LVLi voltages, where "i" is an index value from 1 to N. When only one radar function 110 is included, only one buck converter 121 and one pass device 106 may be required. Pass device 106 is shown as being external, but in an alternative embodiment, may instead be incorporated into radar IC 104.

[0062] A communication bus 126 links the radar controller 112 with the control interface 116 in a communication manner, another communication bus 128 links the control interfaces 116 and 118 together in a communication manner, and another communication bus 130 links the control interface 118 with the power controller 120 in a communication manner. Each of the buses 126, 128, and 130 may include one or more conductors and corresponding control signals. In one embodiment suitable for automotive applications, etc., the control interfaces 116 and 118 are configured as a controller area network (CAN) or serial peripheral interface (SPI) interface for enabling automotive circuit system modules to communicate with each other. The power controller 120 communicates with each of the buck converters 121 via another communication bus 132 having one or more conductors and corresponding control signals. In this way, the radar controller 112 communicates with the power controller 120 to instruct each buck converter 121 to provide the voltage level at its corresponding VPi output to the configured voltage, as further described herein.

[0063] The LDO controller 114 includes a separate driver circuit system for each access device 106, including a driver DRV1 for access device P1 and a driver DRV2 for access device P2. Drivers DRV1 and DRV2 are controlled by the radar controller 112 via corresponding control signals of the control bus 136. The radar controller 112 controls each of the drivers DRV1 and DRV2 via the control bus 136 to select a driver mode or a forced mode to generate a corresponding VC control signal (VC1 or VC2) provided to the corresponding access device 106 according to the selected operating mode. In the driver mode, one or more drivers in the drivers DRVi are configured to control the corresponding access device Pi to use the corresponding power supply voltage VPi provided at the corresponding upper voltage level UPLi to adjust the corresponding supply voltage VSi provided to the corresponding radar function RFi. In the forced mode, one or more drivers in the drivers DRVi are configured to force the corresponding access device Pi into a bypass mode to operate as a switch with zero voltage drop, thereby passing the corresponding power supply voltage VPi provided at the lower voltage level LPLi as the corresponding supply voltage VSi provided to the corresponding radar function RFi.

[0064] The radar IC 104 is configured to generate radar frames in the form of high isolation (HI) frames in a first mode (M1) or in the form of low isolation (LI) frames in a second mode (M2). In the first mode M1 for generating HI frames, the driver DRVi and the corresponding pass device Pi operate in a driver mode to act as a barrier to prevent the ripple voltage from the corresponding buck converter (e.g., BUCK1 or BUCK2) from affecting the HI radar frame generated by the radar IC 104 using the corresponding radar function RFi. In this way, when the corresponding supply voltage VSi is provided to the corresponding radar function 110, the ripple voltage on the supply voltage VPi at UPLi provided by the corresponding buck converter 121 is substantially suppressed, filtered or otherwise blocked by the LDO regulator 115. As further described herein, each driver (e.g., DRV1 or DRV2) and corresponding pass device (e.g., P1 or P2) and other supporting circuitry form an LDO having a regulation loop with a power supply rejection ratio (PSRR) sufficient to output a supply voltage (e.g., VS1 or VS2) while rejecting supply variations in the form of ripple voltage. The first mode M1 enables the radar IC 104 to generate a HI radar frame that is isolated from the buck converter ripple voltage and is therefore free from interference, such as spurious signals in the IF spectrum that might otherwise appear as false targets.

[0065] In the second mode M2 ​​for generating the L1 radar frame, the driver DRVi and the corresponding path device Pi operate in a forced mode, wherein the radar function RFi is subjected to the ripple voltage from the corresponding buck converter (e.g., BUCK1 or BUCK2). In this way, when the corresponding radar function RFi is provided with the corresponding supply voltage VSi, the ripple voltage on the supply voltage VPi at LPLi provided by the corresponding buck converter 121 is not blocked by the LDO regulator 115. The second mode M2 ​​enables the radar IC 104 to generate a L1 frame that is not isolated from the buck converter ripple voltage and is therefore not immune to stray interference in the IF spectrum. The second mode M2 ​​enables the generation of the L1 frame with reduced power dissipation of the radar sensor 100, because the power dissipated in the corresponding path device (e.g., P1 or P2) due to the step-down of the input voltage is zero (VP1=VS1 or VP2=VS2). The L1 frame is not immune to interference caused by the buck converter ripple voltage and is therefore impaired in integrity.

[0066] The power dissipation (Pdiss) in the pass device Pi is determined as Pdiss_Pi=(VPi-VSi)*Iloadi, where Iloadi is the current flowing into the corresponding RFi function through the pass device Pi. In the second mode M2 ​​for generating the LI frame, the radar controller 112 communicates with the power controller 120 to instruct the buck converter BUCKi to set its output voltage VPi to the lower voltage level LPLi. In order to minimize the power dissipation, the lower voltage level LPLi is substantially equal to the corresponding supply voltage VSi required by the corresponding radar function RFi, or Make In addition, the radar controller 112 controls the corresponding driver DRVi to operate in the forced mode to force the corresponding channel device Pi to enter the bypass mode so that there is almost zero voltage drop between VPi and VSi. In this way, the power dissipation of the channel device Pi in the second mode M2 ​​is actually zero (or negligible in other ways). However, in this case, the PSRR of the LDO regulator 115 is also very low, so that the ripple voltage on LPLi is effectively transferred to RFi without hindrance.

[0067] In the first mode M1 for generating the HI radar frame, the radar controller 112 communicates with the power controller 120 to instruct the buck converter BUCKi to set its output voltage VPi to the upper voltage level UPLi. The upper voltage level UPLi is greater than the corresponding supply voltage VSi required by the corresponding radar function RFi, or UPLi>VSi. In addition, the radar controller 112 controls the corresponding driver DRVi to operate in the driver mode to drive the corresponding channel device Pi to adjust VSi with minimal voltage ripple. The voltage difference between UPLi and VSi is selected so that the corresponding driver DRVi can use the source voltage UPLi to adjust VSi with a sufficiently high PSRR to reduce or effectively minimize the ripple voltage of UPLi to VSi. In this way, UPLi is selected to enable the LDO regulator 115 to adjust VSi without ripple, so that the radar IC 104 can operate with minimal spurious signal energy at the expense of increased power dissipation. In this case, the power dissipated by the channel device Pi is Pdiss_Pi=(UPLi-VSi)*Iloadi.

[0068] In one embodiment, each of the pass devices 106 is a bipolar junction transistor (BJT), etc., which may be an N-type device (e.g., NPN) or a P-type device (e.g., PNP) depending on the driver configuration. Alternative pass devices are contemplated, such as other types of transistors, including field effect transistors (FETs), junction FETs (JFETs), or metal oxide semiconductors FEFs (MOSFETs), etc., including N-channel or P-channel FETs, JFETs, or MOSFETs. In general, each pass device 106 has a control terminal (e.g., a base terminal or a gate terminal, etc.) that receives a corresponding control signal VC from the LDO controller 114, and has a current terminal (e.g., a collector terminal and an emitter terminal, or a drain terminal and a source terminal, etc.) coupled between the VP output of the corresponding buck converter 121 and the supply voltage VS input of the corresponding radar function 110. Such BJTs or FETs or MOS-type transistors, etc. are driven to a saturation mode by the corresponding driver DRVi in a driver mode to regulate the voltage to minimize the ripple voltage. In addition, such BJT or FET or MOS type transistor etc. is forced into bypass mode by the corresponding driver DRVi in the forced mode to operate as a zero voltage switch to minimize power dissipation.

[0069] Figure 2 2 is a simplified block diagram illustrating a HI radar frame generated in mode M1 and a LI radar frame generated in mode M2 ​​according to one embodiment. In the illustrated embodiment, a HI frame 202 is generated in mode M1 and a LI frame 204 is generated in mode M2. The HI frame 202 includes a series of a sequential number A "chirps" sent during a chirp period, followed by a silent period. Similarly, the LI frame 204 includes a series of a sequential number B chirps sent during a chirp period, followed by a silent period. Each chirp is a single frequency tone with a frequency that varies with time. In a linear frequency modulated continuous wave (FMCW) radar, each chirp has a frequency that varies linearly with time within a predetermined chirp period. The duty cycle of each radar frame is the ratio between the chirp period (the period during which the chirp is sent) and the duration of the silent period. Ideally, each radar frame would have a 100% duty cycle with chirp periods and no silent periods. However, the radar sensor 100 consumes a lot of power during the chirp periods, creating heat dissipation and power dissipation issues. In this way, a 50% duty cycle is often a suitable compromise between target detection and power dissipation per radar frame.

[0070] During the chirp period, the radar IC 104 operates in both a transmit (TX) mode for transmitting chirps and a receive (RX) mode for receiving and detecting responses from the environment, which can be evaluated to identify any targets of interest. During the silent period, the radar IC 104 operates without transmitting or receiving, but remains ready for the next frame. The A and B values ​​that define the number of chirps transmitted for the respective HI and LI frames during the chirp period can be fixed values ​​or programmable values, which can be the same (i.e., A=B) or different depending on the use case.

[0071] Figure 3 3 is a simplified block diagram illustrating an exemplary frame set 302 according to one embodiment. Frame set 302 is a programmable number X of HI frames (HI1, ..., HIX) transmitted followed by another programmable number Y of LI frames (LI1, ..., LIY). The values ​​X and Y determine a set ratio X:Y provided by a radar profile loaded prior to executing a radar session by radar IC 104. X is an integer of 0 or greater and is typically at least 1 for each set. Y is also an integer of 0 or greater, where Y can be 1 or greater to reduce power dissipation, but can also be 0 when the interleaved mode is not used for a given use case. HI frames are free of ripple voltage interference and can be used as reference radar frames for one or more subsequent LI frames in a given set. LI frames are radar frames that may be contaminated by ripple voltage, which causes spurious signals that may otherwise cause false targets. Each frame set uses at least one HI reference frame to establish a clean radar scene that can be used as a reference for spurious signal mitigation techniques applied to one or more LI frames.

[0072] A typical interleaved frame set includes a HI radar frame followed by one or more LI radar frames. The HI frame provides a clear radar scene that can be used to mitigate spurious signals generated in subsequent LI frames of the same frame set. Although any number of LI frames may be included, the later LI frames are spaced apart from the reference HI frame by a greater amount of time, making the mitigation techniques less useful for subsequent LI frames. Frame sets with only LI frames can be used to reduce power dissipation while collecting a limited amount of information contaminated by spurious signal energy. Non-interleaved frame sets with only HI frames provide the highest quality information at the expense of higher power dissipation. A possible variation is to include multiple HI frames and one or more LI frames in each frame set for a given use case to reduce power dissipation compared to a non-interleaved radar session.

[0073] Figure 44 is a simplified block diagram illustrating an exemplary radar session 402 including a total number K of radar frames according to one embodiment. K is an integer that can be at least X+Y (e.g., the total number of radar frames per frame set) and is typically a multiple M of X+Y, or K=M*(X+Y), where the asterisk "*" represents multiplication. As shown, radar session 402 includes a series of sequential P frame sets S1, S2, ..., SP, where each frame set S1-SP includes X HI frames followed by Y LI frames, such as shown in frame set 302. The radar profile of radar session 402 specifies X, Y, and K. It should be noted that K can be specified independently of X and Y, so that radar session 402 can terminate when K frames are sent, even in the middle of frame set S1-SP.

[0074] Figure 5 4 is a flow chart illustrating the operation of the radar sensor 100 in executing the radar session 402 according to one embodiment. At a first block 502, the radar IC 104 is powered up from a standby mode or from a power down state (or off state). At a next block 504, a radar profile for the radar session 402 is loaded by the radar controller 112 according to the applicable use case. The radar profile may include a large amount of information about the radar session, including, for example, chirp information (e.g., start / stop frequency, chip bandwidth, etc.), receiver information (e.g., gain settings, filter settings, etc.), transmitter information (e.g., power level, phase information, etc.), analog / digital converter (ADC) information (e.g., sampling rate), etc. However, for the purposes of this disclosure, the radar profile also includes an interleaving value INLV, a K value for determining the aggregate ratio X:Y and the total number of frames to be executed in the radar session 402, and an A value and a B value for determining the number of chirps for HI frames and LI frames, respectively. INLV is a Boolean value that determines whether radar session 402 includes any LI frames interleaved with HI frames or whether radar session 402 is operating in a non-interleaved mode in which the radar session includes only HI frames. For a radar session of a given implementation of radar sensor 100, the A value and the B value may be predetermined.

[0075] At the next block 506, the INLV value is queried to determine whether the radar session 402 includes interleaved HI and LI frames. When INLV is true, the operation proceeds to block 508, where the radar sensor 100 is configured by the radar controller 112 to operate in the first mode M1 to generate one or more HI frames of the current frame set. This includes instructing the applicable buck converter 121 to generate a corresponding supply voltage VPi at its corresponding upper voltage level UVLi, thereby configuring the applicable driver DRVi of the LDO regulator 115 to operate the corresponding pass device Pi in the driver mode to regulate the supply voltage VSi to significantly reduce or minimize the ripple voltage from VPi, thereby eliminating spurious signal energy in the HI frame at the expense of increased power dissipation. The operation then proceeds to block 510, where the radar IC 104 transmits A chirps of the first HI frame or the next HI frame, while operating in the RX mode to receive reflection information for processing, wherein the chirp period is followed by a silent period. At the next block 512, it is queried whether X HI frames have been generated. If not, operation loops back to block 510, which is repeated for the next HI frame of the current frame set.

[0076] When X HI frames are completed as determined at block 512, operation proceeds to block 514, where radar sensor 100 is configured by radar controller 112 to operate in a second mode M2 ​​to generate one or more LI frames of the current frame set. This includes instructing the applicable buck converter 121 to generate a corresponding supply voltage VPi at its corresponding lower voltage level LVLi, thereby configuring the applicable driver DRVi of LDO regulator 115 to force the corresponding pass device Pi into bypass mode so that the ripple voltage from VPi is passed to VSi, thereby reducing power dissipation at the expense of the presence of stray signal energy in the LI frame. Operation then proceeds to block 516, where radar IC 104 transmits B chirps of the first LI frame or the next LI frame, while operating in RX mode to receive reflection information for processing, wherein the chirp period is followed by a silent period. At the next block 518, it is queried whether Y LI frames have been generated. If not, operation loops back to block 516, which is repeated for the next LI frame of the current frame set. When the current set of Y LI frames is complete as determined at block 518, operation proceeds to block 520 to determine whether a total number of frames, K, has been generated.

[0077] At block 520, if K frames have not been completed, the operation loops back to block 508, where the radar sensor 100 is again reconfigured to operate in the first mode M1 to start the next frame set. The operation repeats, where the operation loops between blocks 508 to 520 until K frames are completed. Typically, K frames include multiple frame sets, where each set includes X HI frames followed by Y LI frames, such as Figure 4As shown. It should be noted that the K parameter may instead be implemented as a running count, where the radar session 402 is complete when a total of K frames have been generated, regardless of whether the last set of frames has been completed. After completing K frames as determined at block 520, operation proceeds to block 522, where the radar IC 104 is placed in a standby mode (or another low power mode), and the current radar session 402 ends.

[0078] Referring back to block 506, if INLV is false, then operation instead proceeds to block 524, where the radar sensor 100 is configured by the radar controller 112 to operate in a first mode M1 for one or more HI frames up to a total of K HI frames. Likewise, the HI mode includes configuring either or both of the drivers DRV1 and DRV2 of the LDO regulator 115 to operate in a driver mode to regulate the supply voltages VS1 and VS2 to significantly reduce or minimize the ripple voltage from VP1 and VP2, thereby eliminating spurious signal energy in the HI frames at the expense of increased power dissipation. For use cases where it is desirable to minimize spurious signal energy to obtain more accurate results, a non-interleaved operating mode may be advantageous. Operation then proceeds to block 526, where the radar sensor transmits A chirps for the first HI frame or the next HI frame while operating in an RX mode to receive reflection information for processing, followed by a silent period. At the next block 528, it is queried whether the K HI frames are complete, and if not, the operation loops back to block 526, which is repeated until the K HI frames are complete. When the K HI frames are complete, the operation proceeds to block 522, where the radar IC 104 is placed in a standby mode (or another low power mode), and the current radar session 402 ends.

[0079] Figure 66 is a schematic diagram of an exemplary LDO regulator 600 according to one embodiment, the exemplary LDO regulator 600 including an exemplary driver DRVi 602 coupled to a corresponding exemplary pass device Pi to implement either or both of the drivers DRV1 and DRV2 of the LDO regulator 115 and the corresponding pass devices P1 and P2. DRVi 602 includes an operational amplifier (OPAMP) 604, a switch SW, resistors R1 and R2, and a capacitor C. One or more of the components may be provided externally, such as the capacitor C. OPAMP 604 has a negative (or inverting) input that receives a reference voltage VREF, which is a DC voltage signal that may be generated on the radar IC 104. OPAMP 604 has an output that provides a corresponding control signal VCI, which is provided to a control terminal of the pass device Pi. In the illustrated embodiment, Pi is configured as a PNP (or P-type) BJT having a base terminal (control terminal) and a pair of current terminals including a collector terminal and an emitter terminal. The emitter terminal of Pi is coupled to receive a supply voltage VPi (generated by a corresponding buck converter BUCKi) from the PMIC 102, and the collector terminal of Pi provides a corresponding supply voltage VSi (provided to a supply voltage input of a corresponding radar function RFi).

[0080] The collector terminal of Pi is additionally coupled to one end of resistor R1 and one end of capacitor C. The other end of R1 is coupled to a control node 606, which is additionally coupled to one end of R2 and coupled to the positive (or non-inverting) input of OPAMP 604. The other end of C and the other end of R2 are coupled to a power supply reference voltage, which can be any suitable reference node, such as ground (GND). Switch SW is shown as being configured as a normally open single-pole single-throw (SPST) switch having a pair of controlled terminals and a control terminal. The output of OPAMP 604 is coupled to one controlled terminal of SW, the other controlled terminal of SW is coupled to GND (or other voltage level, depending on the type of access device), and the control terminal of SW receives at least one of the one or more control signals Ci from radar controller 112 via control bus 136. R1 is shown as a programmable or adjustable resistor that can be adjusted to set the voltage level of VSi. In the configuration shown, OPAMP 604 has a supply voltage input (referenced to GND) that receives VPi. The same or another one of the control signals Ci from the radar controller 112 is provided to an enable (En) input of the OPAMP 604 .

[0081] In the operation of DRVi 602 and access device Pi, radar controller 112 places DRVi 602 in driver mode by enabling OPAMP 604 and by opening switch SW (or by keeping switch SW open). Remember, radar controller 112 also controls PMIC 102 to set VPi at the upper voltage level UVLi. In driver mode, OPAMP 604 uses VPi to drive Pi via VCi to maintain the voltage of control node 606 at VREF to adjust the voltage level of VSi. The voltage level of VSi is determined by the voltage level of VREF and by the setting of adjustable resistor R1. In this way, the regulation loop between DRVi 602 and Pi has a high PSRR for significantly reducing or effectively eliminating any ripple voltage on VPi, so that VSi is adjusted to its nominal target level with almost no ripple voltage. Therefore, radar IC 104 can generate a clean HI frame using the corresponding radar function RFi.

[0082] The radar controller 112 places the DRVi 602 in a forced mode by disabling the OPAMP 604 and by closing the switch SW. Remember that the radar controller 112 also controls the PMIC 102 to set VPi at a lower voltage level LVLi, which is substantially equal to the established regulated voltage level of VSi. In the forced mode, the base terminal of Pi is grounded, so that Pi is effectively placed in a bypass mode that passes VPi directly to VSi with almost zero voltage drop. In this way, any ripple voltage on VPi is passed to VSi and therefore to the corresponding radar function RFi that the radar IC 104 uses when generating the LI frame.

[0083] For DRVi and Pi, alternative configurations may be used. For example, Pi may be implemented by an NPN (or N-type) BJT, with DRVi being reconfigured accordingly, such as being powered by a separate higher voltage power supply from another buck converter of the PMIC 102, etc. In addition, Pi may be implemented as a transistor of P-type or N-type MOS or FET or MOSFET type, with DRVi being reconfigured accordingly.

[0084] Although the present invention has been described in conjunction with several embodiments, the present invention is not intended to be limited to the specific forms set forth herein. Rather, it is desired to cover such alternatives, modifications, and equivalents as may reasonably be included within the scope of the present invention as defined by the appended claims. For example, in various embodiments in which the present invention is not limited by a particular circuit polarity, device type, or voltage or error level, variations of positive circuitry or negative circuitry may be used. For example, circuitry states such as circuitry low and circuitry high may be reversed depending on whether a pin or signal is implemented in a positive circuitry or negative circuitry, etc. In some cases, the circuitry state may be programmable, wherein the circuitry state may be reversed for a given circuitry function.

[0085] As used herein, the term "a" is defined as one or more than one. In addition, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be understood to imply that another claim element introduced by the indefinite article "a" will limit any particular claim containing the claim element so introduced to an invention containing only one such element, even when the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a". The above also applies to the use of definite articles. Unless otherwise stated, terms such as "first" and "second" are used to arbitrarily distinguish the elements described by such terms. Therefore, these terms are not necessarily intended to indicate the time or other priority ordering of such elements.

Claims

1. A radar device, characterized in that: include: a radar function having a supply voltage input and being configured to operate at said supply voltage input at a radar supply voltage level and having a first mode for generating a high isolation frame and a second mode for generating a low isolation frame; a driver configured to control the access device; as well as a radar controller that configures the driver to control the access device to adjust the voltage provided to the supply voltage input of the radar function to the radar supply voltage level when in the first mode, and configures the driver to force the access device into a bypass mode when in the second mode.

2. The radar device according to claim 1, characterized in that The driver is configured to control the channel device to regulate a supply voltage provided to the radar function with a high power supply rejection ratio in the first mode, and wherein the driver is configured to force the channel device to have zero voltage drop in the second mode.

3. The radar device according to claim 1, characterized in that The radar controller is configured to instruct an external voltage converter to output a voltage at the radar supply voltage level to the pathway device in the second mode, or to output a voltage at an upper voltage level greater than the radar supply voltage level to the pathway device in the first mode.

4. The radar device according to claim 1, characterized in that The driver includes a low dropout regulator controller configured to regulate voltage in the first mode and to force the pass device in the second mode.

5. The radar device according to claim 1, characterized in that The driver comprises: an operational amplifier having a first input receiving a reference voltage, a second input coupled to a control node, and an output for coupling to a control terminal of the pass device; a first resistor having a first end coupled to the supply voltage input of the radar function and having a second end coupled to the control node; a second resistor having a first end coupled to the control node and having a second end coupled to a power reference node; and A switch controlled by the radar controller for selectively coupling the output of the operational amplifier to the power supply reference node.

6. A radar sensor, characterized in that: include: a radar device configured to generate radar frames, wherein the radar device has a first mode for generating high isolation frames and has a second mode for generating low isolation frames, and wherein the radar device comprises a radar function having a supply voltage input and is configured to operate at the supply voltage input at a radar supply voltage level; a converter having a programmable voltage output, wherein the converter is directed to output a voltage at the radar supply voltage level or at an upper voltage level greater than the radar supply voltage level; a voltage control system including a driver coupled to a pass device, wherein the pass device includes a current terminal coupled between the voltage output of the converter and the supply voltage input of the radar function, and wherein the driver has a control output coupled to a control terminal of the pass device; as well as a radar controller that instructs the converter to output a voltage at the upper voltage level and configures the driver to control the access device to adjust the voltage of the supply voltage input provided to the radar function to the radar supply voltage level to configure the radar device in the first mode, and instructs the converter to output a voltage at the radar supply voltage level and configures the driver to force the access device to be in a bypass mode to configure the radar device in the second mode.

7. The radar sensor according to claim 6, characterized in that: The driver of the voltage control system controls the pass device in the first mode to regulate a supply voltage provided to the radar function with a power supply rejection ratio sufficient to minimize a ripple voltage at the voltage output of the converter, and wherein the driver forces the pass device to have a zero voltage drop between the pass device current terminals in the second mode.

8. A method for generating a radar frame, characterized in that: The method comprises: Configure the radar sensor to generate high isolation frames, including: instructing to provide a supply voltage at an upper voltage level greater than a radar supply voltage level suitable for a radar function of the radar sensor; and driving a pass-through device receiving the supply voltage to regulate the supply voltage input of the radar function to the radar supply voltage level; and Configuring the radar sensor to generate a low isolation frame includes: instructing to provide a supply voltage at the radar supply voltage level; and The pass-through device is forced into a bypass mode to pass the supply voltage to the supply voltage input of the radar function.

9. The method according to claim 8, characterized in that The driving pathway means includes, for the high isolation frame, regulating a voltage at the supply voltage input of the radar function with a power supply rejection ratio sufficient to minimize a ripple voltage of the supply voltage.

10. The method according to claim 8, characterized in that Also includes: receiving a profile indicating a total number of radar frames to be generated for a radar session, a first number of high isolation frames per frame set for the radar session, and a second number of low isolation frames per frame set; configuring the radar sensor to generate high isolation frames for a first time and generating the first number of high isolation frames; configuring the radar sensor to generate low isolation frames a second time and generating the second number of low isolation frames; as well as The first configuration and the second configuration and generation are repeated until the total number of radar frames have been generated.

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