A buck converter in COT mode

Abstract

The present invention provides a buck converter in COT mode, including a main comparator, a conduction time generation module, and a PWM generation module. The main comparator is used to compare the feedback voltage and the reference voltage. The conduction time generation module is used to provide a conduction time signal in COT mode. The PWM generation module is configured to: when the conduction time signal changes from 0 to 1, determine whether the feedback voltage is less than the reference voltage; if the feedback voltage is less than the reference voltage, skip the off time, so that the high-side power transistor continues to conduct until the feedback voltage is greater than or equal to the reference voltage, and then turn off the high-side power transistor of the buck converter. The buck converter in COT mode of the present invention uses the output voltage of the main comparator as a judgment criterion to determine whether to reduce or skip the off time, so as to extend the conduction time of the high-side power transistor, enabling the output voltage to obtain more power, which is more beneficial to scenarios that require more power.

Description

Technical Field

[0001] The present invention relates to a buck converter, and more particularly to a buck converter in COT mode. The buck converter in COT mode can be a traditional buck converter in COT mode or other types of buck converters in COT mode, such as a buck converter in ACOT (Adaptive Constant On-Time) mode. Background Art

[0002] Figure 1 Shows the most basic example of a buck converter in ACOT (Adaptive Constant On-Time) mode. The buck converter in ACOT mode includes a main comparator Cp1, a conduction time generation module T1, a PWM generation module P1 connected to the output terminals of both of them, and a driver D1 connected to the output terminal of the PWM generation module P1.

[0003] In the buck converter in ACOT mode, the output terminal of the driver D1 is connected to the gates of the high-side power transistor HS and the low-side power transistor LS of the Buck circuit (i.e., the buck converter), so that the PWM generation module P1 uses the driver D1 to amplify the PWM signal to drive a large MOSFET. One input terminal of the main comparator Cp1 is connected to the feedback signal FB of the buck converter, and the other input terminal is connected to the reference voltage V ref connection. The gates of the high-side power transistor HS, the gates of the low-side power transistor LS, and an inductor are commonly connected to a switching node SW, and the other end of the inductor is the voltage output terminal of the buck converter. Therefore, a part of the inductor current IL serves as the capacitive current i out flowing through the equivalent series resistance ESR and the output capacitor C of the buck converter C , and another part serves as the output current I O of the buck converter (i.e., the load current ILOAD).

[0004] As Figure 2 shown, the feedback voltage FB can be divided into the voltage ripple of the equivalent series resistance ESR and the voltage ripple of the capacitor voltage. The product of the capacitive current i C and the equivalent series resistance ESR is the voltage across the equivalent series resistance ESR. Therefore, the change in the voltage across the equivalent series resistance ESR is caused by the change in the capacitive current i C . The peak value of the voltage ripple of the ESR is the product of the difference between the maximum value and the minimum value of the capacitive current i C and the equivalent series resistance ESR. The capacitor voltage ripple is the voltage ripple generated by the change of the internal charge of the capacitor, and it is caused by the change of the capacitive current i C .

[0005] The main comparator Cp1 compares the feedback voltage FB with the reference voltage V ref When the feedback voltage FB drops below the reference voltage V ref The output voltage Vea of the main comparator Cp1 will become high. Since the output terminal of the main comparator Cp1 is connected to the set terminal Set of the PWM generation module P1, the high level of the output voltage Vea of the main comparator Cp1 causes a conduction pulse to appear in the high-side power transistor conduction signal HSON generated by the PWM generation module P1 (i.e., HSON = 1). This conduction pulse is used to drive the high-side power transistor HS to conduct through the driver D1. The high-side power transistor conduction signal HSON is proportional to the switch node voltage VSW.

[0006] At the same time, since the PWM generation module generates a PWM signal and sends it to the driver D1, and the PWM generation module is connected to a voltage-controlled on-time generation module T1 to receive the on-time signal Ton, and the on-time signal Ton becomes high at the end of the on-time, the conduction pulse (i.e., HSON = 1) drives the high-side power transistor HS to conduct through the driver D1 until the on-time generation module T1 sends a high-level on-time signal Ton to reset the high-side power transistor conduction signal HSON, and the high-side power transistor conduction signal HSON becomes 0, causing the high-side power transistor HS to turn off and the low-side power transistor to turn off.

[0007] Among them, the on-time generation module T1 needs to be connected to the voltage input terminal of the buck converter to detect the input voltage VIN, so as to achieve a constant switching frequency by making the on-time proportional to the input voltage VIN when the input voltage VIN changes. Similarly, the on-time generation module T1 needs to be connected to the voltage output terminal of the buck converter to detect the output voltage VOUT (also denoted as Vout) of the buck converter, and then, when the output voltage VOUT reaches different voltage values, achieve a constant switching frequency by making the on-time proportional to the output voltage VOUT.

[0008] As Figure 2 shown, when the feedback voltage FB just drops below the reference voltage V ref the high-side power transistor will immediately conduct, causing the ESR ripple and the capacitor ripple to rise again. Soon, the feedback voltage FB will be higher than the reference voltage V ref again, causing the output voltage Vea of the main comparator Cp1 to immediately become low. Therefore, from the analysis of the existing buck converter in the ACOT mode, when operating conventionally in the COT mode, the duty cycle of the output voltage Vea of the main comparator Cp1 is very small, and its pulse shape is a slender waveform. In fact, when all buck converters in the COT mode are operating normally, the waveform output by the error amplifier Vea is relatively slender.

[0009] Figure 3 and Figure 4 show two operating scenarios where the step-down converter in the existing ACOT mode has limited operation, Figure 3 shows the waveform of the high-side power transistor conduction signal HSON when the load steps up, Figure 4 shows the waveform of the maximum duty cycle of the high-side power transistor conduction signal HSON when the input voltage VIN steps down below the output voltage regulation point. Here, the output voltage regulation point refers to the DC value of the output voltage VOUT corresponding to the feedback voltage FB when the valley value of the feedback voltage FB is equal to the reference voltage Vref. And in fact, the average value VFB_average of the feedback voltage FB is equal to the sum of the reference voltage Vref and 1 / 2 of the feedback voltage ripple.

[0010] In Figure 3 the shown operating scenario, since the load current ILOAD steps up and is higher than the average value of the inductor current IL, this causes the output voltage VOUT to drop below the output voltage regulation point, and the feedback voltage FB is lower than the reference voltage Vref. Subsequently, the output voltage Vea of the main comparator Cp1 remains at 1 for a relatively long time until the average value of the inductor current IL is higher than the load current ILOAD, at which time the ripple of the feedback voltage FB is higher than the reference voltage Vref again.

[0011] In Figure 4 the shown operating scenario, since the input voltage VIN is lower than the output voltage regulation point, therefore, the maximum output voltage VOUT that can be obtained is equal to the input voltage VIN × the maximum duty cycle of the high-side power transistor conduction signal HSON. Thus, the maximum output voltage VOUT is also much lower than the output voltage regulation point, and then the feedback voltage FB will always be lower than Vref. In this case, the output voltage Vea of the main comparator Cp1 is always equal to 1.

[0012] Although the above two situations are different, there is a common point: "the output voltage Vea of the main comparator Cp1 is equal to 1 for a long time (temporarily or permanently)". Therefore, the waveform of Vea is not a conventional slender waveform. Moreover, the output voltage Vea of the main comparator Cp1 is still equal to 1 even at the end of the conduction duration of the high-side power transistor conduction signal HSON, and the end of the conduction duration of the power transistor conduction signal HSON is achieved by the conduction time generation module T1 sending out the conduction signal Ton.

[0013] As Figure 3 shown, once the load changes from a light load to a heavy load, the load current ILOAD steps up, causing the output voltage VOUT to drop. The step-down converter in the existing ACOT mode will attempt to reach the current load level by turning on the high-side field-effect transistor to make the inductor current reach the current load level.

[0014] However, if the step change of the load is fast and large, the existing buck converters in ACOT mode or COT mode may require multiple COT (fixed on-time) cycles to increase the inductor current. Each COT cycle is separated by at least a minimum off-time.

[0015] Obviously, a longer minimum off-time will have an adverse effect on the COT load step response. To obtain a better load step response, it is necessary to reduce the minimum off-time or skip the off-time temporarily according to certain criteria. Summary of the Invention

[0016] The object of the present invention is to provide a buck converter in COT mode to increase the maximum duty cycle of the high-side power transistor conduction signal by extending the on-time and improve the fast load step response.

[0017] To achieve the above object, the present invention provides a buck converter in COT mode, including a main comparator, an on-time generation module, and a PWM generation module. The main comparator is used to compare the feedback voltage and the reference voltage. The on-time generation module is used to provide an on-time signal in COT mode. The PWM generation module is configured to: when the on-time signal changes from 0 to 1, determine whether the feedback voltage is less than the reference voltage; if the feedback voltage is less than the reference voltage, skip the off-time, so that the high-side power transistor continues to conduct until the feedback voltage is greater than or equal to the reference voltage, and then turn off the high-side power transistor of the buck converter.

[0018] The PWM generation module is further configured to: turn off the high-side power transistor when the timing time starting from the conduction of the high-side power transistor reaches the maximum on-time.

[0019] The PWM generation module receives the extended on-time signal processed by the on-time signal and the output voltage of the main comparator, and uses it as the reset signal of the high-side power transistor conduction signal. When the high-side power transistor conduction signal is reset, the high-side power transistor is turned off.

[0020] The buck converter in COT mode includes a delay module connected to the on-time signal, an on-time extension ability detection module connected to both the on-time signal and the output voltage of the main comparator, and an AND gate. The two input terminals of the AND gate are respectively connected to the on-time delay signal output by the delay module and the on-time extension detection signal output by the on-time extension ability detection module. The AND gate is used to output the extended on-time signal.

[0021] The delay module is configured to perform a fixed delay on the on-time signal to obtain the on-time delay signal.

[0022] The fixed delay is 3ns - 7ns.

[0023] The on - time extension ability detection module is a D - flip - flop. Its clock terminal is connected to the on - time signal, the data port is connected to a high level, the reset terminal is connected to the output voltage of the main comparator, and the inverted output terminal outputs an on - time extension detection signal.

[0024] The reset terminal of the on - time extension ability detection module is connected to the output signal of an OR - NOT gate to connect, through the OR - NOT gate, to the inverted signal of the output voltage of the main comparator and one of the high - side power transistor maximum current indication signal and the maximum on - time signal.

[0025] The high - side power transistor maximum current indication signal changes from 0 to 1 when the current of the high - side power transistor reaches the maximum protection current; the maximum on - time signal changes from 0 to 1 when the timing time from the conduction of the high - side power transistor reaches the maximum on - time; the output voltage of the main comparator changes from 1 to 0 when the feedback voltage is greater than the reference voltage; the on - time extension ability detection module is reset when the output signal of the OR - NOT gate is equal to 0, making the on - time extension detection signal become 1, and then turning off the high - side power transistor of the buck converter.

[0026] The PWM generation module is also set as follows: If, under continuous preset times, the feedback voltage is less than the reference voltage when reaching the maximum on - time, the buck converter enters the 100% duty - cycle mode, where the high - side power transistor can conduct forever and is only turned off when the feedback voltage is greater than or equal to the reference voltage or when the current of the high - side power transistor reaches the maximum protection current.

[0027] The buck converter in the COT mode of the present invention uses the output voltage of the main comparator as a judgment criterion to determine whether to reduce or skip the turn - off time to extend the conduction time of the high - side power transistor, so that the output voltage obtains more power, which is more beneficial to scenarios that require more power. Brief Description of the Drawings

[0028] Figure 1 is the most basic example diagram of an existing buck converter in the ACOT (Adaptive Constant On - Time) mode.

[0029] Figure 2 is the waveform diagram of an existing buck converter in the ACOT mode during operation.

[0030] Figure 3 and Figure 4 are the waveform diagrams of an existing buck converter in the ACOT mode under two operating scenarios, Figure 3 showing the waveform of the high - side power transistor conduction signal when the load steps up, Figure 4The waveform of the maximum duty cycle of the high-side power transistor conduction signal when the input voltage steps down below the output voltage regulation point is shown.

[0031] Figure 5 、 Figure 6A and Figure 6B show a comparison diagram of the waveforms of an existing buck converter and the waveforms of the buck converter of the present invention that uses the output voltage of the main comparator at the end of the conduction time of the high-side power transistor as the criterion for skipping the off time. Among them, Figure 5 shows the waveform when the load steps up, Figure 6A shows the waveform of the maximum duty cycle when the input voltage steps down below the output voltage regulation point, Figure 6B shows the waveform of the maximum duty cycle of the high-side power transistor conduction signal when the input voltage steps down above the output voltage regulation point.

[0032] Figure 7 is a specific structural diagram of a buck converter in COT mode according to an embodiment of the present invention.

[0033] Figure 8 is a circuit diagram of the improved part of a buck converter in COT mode according to an embodiment of the present invention.

[0034] Figure 9 is the schematic diagram of the generation of the second charging current.

[0035] Figure 10 is a typical waveform diagram of the buck converter of the present invention in COT mode.

[0036] Figure 11 is a waveform diagram of an existing buck converter in ACOT mode in an analog scenario, and the analog scenario corresponds to the situation of a rapid load jump.

[0037] Figure 12 is a waveform diagram of the buck converter of the present invention in ACOT mode in an analog scenario, and the analog scenario corresponds to the situation of a rapid load jump.

[0038] Figure 13 is a waveform comparison diagram of an existing and the buck converter of the present invention in ACOT mode in an analog scenario, and the analog scenario corresponds to the maximum duty cycle limit.

[0039] Figure 14 shows Figure 13 a partial enlarged view of the waveforms of an existing and the buck converter of the present invention in ACOT mode in the analog scenario of the maximum duty cycle limit shown.

[0040] Figure 15It is the actual load step response diagram of the buck converter in the ACOT mode of the present invention.

[0041] Figures 16A to 16D It shows the oscilloscope waveform diagram of the buck converter in the ACOT mode of the present invention under the scenario of the maximum duty cycle. Detailed implementation manner

[0042] The buck converter in the COT mode of the present invention is mainly based on the following principle:

[0043] A relatively long minimum off-time will cause the output voltage to be insufficient in power in some scenarios, which will in turn have an adverse effect on the COT load step response. When the output voltage requires more power, the key idea is to extend the conduction time of the high-side power transistor HS. To obtain a better load step response, the minimum off-time can be reduced, or the off-time can be skipped temporarily according to certain criteria, and the duty cycle of the high-side power transistor conduction signal HSON can be further increased to enable the output voltage to obtain more power.

[0044] In the present invention, the output voltage Vea of the main comparator CP1 is used as the judgment criterion to determine whether to reduce or skip the off-time, so as to extend the conduction time of the high-side power transistor and enable the output voltage to obtain more power.

[0045] Specifically as described above, during normal operation, the output voltage Vea of the main comparator CP1 has a slender waveform and is equal to 1 only for a very short time at the rising edge of the switch node SW. Therefore, the present invention can add a logic to detect the state of the output voltage Vea of the main comparator CP1 when the conduction time of the high-side power transistor HS is about to end. If the output voltage Vea of the main comparator CP1 is still equal to 1 when the conduction time of the high-side power transistor HS ends (that is, the conduction time signal Ton changes from 0 to 1), it indicates that the integrated circuit is in an abnormal state. In this case, the buck converter obviously requires more power. Therefore, in this case, the off-time will be skipped and the conduction time will continue until the output voltage Vea of the main comparator CP1 is zero or the timing time starting from the conduction of the high-side power transistor (that is, HSON changes to 1) reaches the maximum conduction time (that is, the maximum conduction time signal TON_MAX changes from 0 to 1).

[0046] Figure 5 、 Figure 6A and Figure 6B It shows a comparison diagram of the waveforms of the existing buck converter and the buck converter of the present invention using the output voltage Vea of the main comparator CP1 at the end of the conduction time of the high-side power transistor HS as the judgment criterion for skipping the off-time. Among them, Figure 5 It shows the waveform when the load step rises, Figure 6AShows the waveform of the maximum duty cycle when the input voltage VIN steps down below the output voltage regulation point. Figure 6B Shows the waveform of the maximum duty cycle of the high-side power transistor conduction signal HSON when the input voltage VIN steps down above the output voltage regulation point. In Figure 5 , Figure 6A and Figure 6B , in this embodiment, the buck converter in COT mode specifically adopts the buck converter in ACOT mode. The waveforms of the new buck converter are orange, and the waveforms of the new buck converter further increase the duty cycle of the high-side power transistor conduction signal HSON.

[0047] As Figure 5 shown, in the case of a load step-up, if the output voltage Vea of the main comparator CP1 is still equal to 1 when the conduction time of the high-side power transistor HS ends (i.e., the conduction time signal Ton = 1), the turn-off time is skipped, as shown by the blue circle in Figure 5 .

[0048] The change in the limit of the maximum duty cycle of the buck converter before and after improvement can be described in combination with Figure 6A and Figure 6B .

[0049] As Figure 6A shown, when the input voltage VIN drops below the output voltage regulation point, the output voltage VOUT corresponding to the input voltage VIN is lower than the target output voltage VOUT_SETTING. Therefore, the output voltage VOUT is always lower than the output voltage regulation point. In this case, the situation of the duty cycle is discussed. At this time, the output voltage Vea of the main comparator is always at a high level.

[0050] Actually, the average value of the output voltage VOUT can only reach:

[0051] VIN × max_duty = VIN × (T - min_off_time) / T,

[0052] where VIN is the input voltage, max_duty is the maximum duty cycle of the high-side power transistor conduction signal, and T is the switching period.

[0053] For example, in an existing buck converter, if the minimum off-time min_off_time = 150 ns and the switching frequency is 600 kHz (i.e., the switching period T = 1.667 μs), and the input voltage VIN = the target output voltage VOUT_SETTING = 5 V, the maximum output voltage VOUT is equal to:

[0054] 5 × (1.667 - 0.15) / 1.667 = 4.55 V.

[0055] Therefore, in Figure 6A , in order to increase the output voltage, the existing buck converters face the same situation as the load step-up shown in Figure 5 . It is necessary to reduce the minimum off-time min_off_time or increase the on-time On-time to increase the duty cycle. However, the existing buck converters in ACOT mode do not support these two methods.

[0056] In this embodiment, the buck converter in ACOT mode is set to execute the following logic:

[0057] When the on-time of the high-side power transistor HS ends (i.e., the on-time signal Ton changes from 0 to 1), it is judged whether the output voltage Vea of the main comparator CP1 is 1; if the output voltage Vea of the main comparator is equal to 1 (i.e., the feedback voltage FB < the reference voltage Vref), the off-time will be skipped, so that the high-side power transistor HS continues to conduct until the output voltage Vea of the main comparator is zero or the timing time starting from the conduction of the high-side power transistor (i.e., HSON becomes 1) reaches the maximum on-time, and at this time the high-side power transistor HS is turned off.

[0058] The same logic can also be applied to the buck converter in the ordinary COT mode to improve the maximum duty cycle limit of the on-signal HSON of the high-side power transistor of the existing buck converter.

[0059] In other embodiments, the maximum on-time is not set. In the case where the buck converter executes the above logic and the value of the input voltage VIN is not sufficient to make VOUT reach the target output voltage VOUT_SETTING, if the maximum on-time is not set, the buck converter will keep the high-side power transistor HS conducting forever. This is the working condition of the buck converter in the mode of continuous conduction with a 100% duty cycle.

[0060] Although the mode of continuous conduction with a 100% duty cycle is feasible, it is often necessary to set other charge pump circuits or periodically turn on the low-side power transistor LS briefly to charge the bootstrap capacitor, or set the high-side power transistor HS as a PMOS transistor to support the continuous conduction of the high-side power transistor HS.

[0061] In this embodiment, the present invention uses an NMOS transistor as the high-side power transistor. To drive this NMOS transistor, a voltage 5V higher than the voltage of the switching node SW is required. A common way to achieve this is to add an additional circuit called a bootstrap capacitor. Simply put, a bootstrap capacitor is a capacitor. One terminal of the capacitor is connected to the driving circuit and is powered by a 5V voltage source through a diode, and the other terminal is connected to the switching node SW. When the low-side power transistor LS is turned on, the 5V voltage source charges the bootstrap capacitor. The buck converter of the present invention will utilize the energy stored in the bootstrap capacitor to drive the high-side power transistor HS.

[0062] However, in the 100% duty cycle mode, since the low-side power transistor LS is not turned on, there is no time to recover the energy for the bootstrap capacitor. The bootstrap capacitor will gradually lose energy over time, so we need other circuits such as a charge pump circuit to supplement this part of the lost energy of the bootstrap capacitor. Therefore, if it is desired that the buck converter of the present invention can operate in a mode of continuous conduction with a 100% duty cycle when using an NMOS transistor as the high-side power transistor HS, then a charge pump circuit needs to be provided at the power supply terminal of the capacitor to supplement the energy lost by the bootstrap capacitor.

[0063] In other embodiments, if the high-side power transistor HS is a PMOS transistor, then the present invention does not require a new charge pump to support the continuous conduction of the high-side power transistor HS with a 100% duty cycle. Additionally, if the present invention allows the low-side power transistor LS to be turned on simultaneously within the maximum on-time TON_MAX after the high-side power transistor HS is turned on, then a new charge pump is also not required. Because as mentioned before, after the low-side power transistor LS is turned on, the energy in the bootstrap capacitor will be recovered.

[0064] In this embodiment, the maximum on-time = 30 μs. Since the maximum on-time is only 30 μs, the energy lost by the bootstrap capacitor during this period is actually negligible, so a good output voltage can be maintained, thereby extending the battery life. Moreover, each time the low-end FET is turned on, the energy will be updated. Therefore, in this embodiment, a new charge pump circuit is not required. At the same time, the 30 μs maximum on-time ensures that the switching frequency does not generate audible noise.

[0065] In this embodiment, the maximum conduction time = 30 μs, and the minimum off - time min_off_time = 150 ns. When the conduction signal of the high - side power transistor reaches the maximum duty cycle, the switching period T is the sum of the maximum conduction time and the minimum off - time min_off_time. Therefore, the duty cycle is 99.5%. Based on a duty cycle of 99.5% and an input voltage of 5V, the output voltage can reach 4.975V. Compared with the calculated result of the output voltage of 4.55V of the existing buck converter, the output voltage of the buck converter of the present invention has been significantly improved.

[0066] As Figure 6B shown, when the input voltage VIN drops but is still above the output voltage regulation point, the maximum value of the output voltage VOUT corresponding to the input voltage VIN is still slightly higher than the target output voltage VOUT_SETTING. However, due to the limitations of the COT mode, the average output voltage VOUT cannot reach the target output voltage VOUT_SETTING. In this case, the duty cycle is discussed.

[0067] For example, in an existing buck converter operating in the COT mode, when the input voltage VIN = 5.2V, the switching frequency is 600 kHz (i.e., the switching period T = 1.667 μs), and the minimum off - time min_off_time is 150 ns, the maximum output voltage VOUT is only equal to:

[0068] VOUT=(1.667 - 0.15) / 1.667×5.2 = 4.73V

[0069] Obviously, for the existing buck converter operating in the COT mode, an input voltage VIN of 5.2V cannot support a 5V output either.

[0070] However, in this embodiment, the buck converter operating in the COT mode is set to execute the following logic:

[0071] When the conduction time of the high - side power transistor HS ends (i.e., the conduction - time signal TON = 1), it is judged whether the output voltage Vea of the main comparator CP1 is 1; if the output voltage Vea of the main comparator is equal to 1, the off - time will be skipped, causing the high - side power transistor HS to continue conducting until the output voltage Vea of the main comparator is zero or the timing time starting from the conduction of the high - side power transistor (i.e., HSON becomes 1) reaches the maximum conduction time. At this time, the high - side power transistor HS is turned off.

[0072] Therefore, in this embodiment, the conduction time is extended to VOUT / (VIN - VOUT) × min_off_time = 3.75 μs, but it has not reached the maximum conduction time (30 μs). Therefore, theoretically, the buck converter in the COT mode of the present invention can support a 5V output with a 5.2V input.

[0073] In this embodiment, since the input voltage VIN is still high enough, the buck converter in the COT mode of the present invention can pull up the feedback voltage FB above the reference voltage Vref. Then, the high-side power transistor conduction signal HSON is reset when the output voltage Vea of the main comparator CP1 is 0. The conduction time of the high-side power transistor HS depends on the duration of the output voltage Vea = 1 of the main comparator CP1.

[0074] Therefore, in fact, in Figure 6B In this case as shown, the buck converter in the COT mode of the present invention will operate in a mode with a fixed off-time (i.e., off-time = minimum off-time min_off-time) and a variable conduction time. By executing the above logic, the buck converter of the present invention changes from a constant conduction time mode to a constant off-time mode.

[0075] Next, in combination with Figure 7 and Figure 8 illustrate the specific structure of the buck converter in the COT mode according to an embodiment of the present invention. In Figure 7 and Figure 8 In the shown embodiment, the buck converter in the COT mode is a buck converter in the ACOT mode.

[0076] As Figure 7 and Figure 8 shown, the buck converter in the COT mode of the present invention includes a main comparator Cp1, a conduction time generation module T1, a PWM generation module P1, and a driver D1 connected to the output terminal of the PWM generation module P1.

[0077] The main comparator is used to compare the feedback voltage FB and the reference voltage Vref, and makes the output voltage Vea of the main comparator become high level (Vea = 1) when the feedback voltage FB is less than the reference voltage Vref. The conduction time generation module is used to provide a conduction time signal TON in the COT mode.

[0078] The PWM generation module P1 is connected to the output voltage Vea of the main comparator Cp1 to use it as the set signal of the high-side power transistor conduction signal HSON. The high level of the output voltage Vea of the main comparator Cp1 makes the high-side power transistor conduction signal HSON generated by the PWM generation module P1 become high level.

[0079] Moreover, the PWM generation module is configured to: when the on-time signal Ton of the high-side power transistor HS changes from 0 to 1, determine whether the feedback voltage FB is less than the reference voltage Vref; if the feedback voltage FB is less than the reference voltage Vref, skip the off-time, so that the high-side power transistor HS continues to conduct until the feedback voltage FB is greater than or equal to the reference voltage Vref, and then turn off the high-side power transistor HS. Specifically, the PWM generation module P1 is connected to the extended on-time signal TON_EXT processed by the on-time signal of the on-time generation module T1 and the output voltage Vea of the main comparator Cp1 to use it as the reset signal of the high-side power transistor on-signal HSON, thereby implementing the above function.

[0080] Thus, the extended on-time signal TON_EXT replaces the existing on-time signal TON that is the reset signal of the high-side power transistor on-signal HSON. When the extended on-time signal TON_EXT is at a high level (i.e., TON_EXT = 1), the reset of the high-side power transistor on-signal HSON is achieved to turn off the high-side power transistor HS.

[0081] One input terminal of the main comparator Cp1 is connected to the feedback signal FB of the buck converter, and the other input terminal is connected to the reference voltage V ref and the output terminal is used to output the output voltage Vea of the main comparator CP1.

[0082] Since in this embodiment, the buck converter in COT mode adopts the buck converter in ACOT mode, and the on-time it provides varies with the input voltage and the output voltage, therefore, the on-time generation module T1 includes a second comparator Cp2. The inverting input terminal of the second comparator Cp2 is connected to the voltage output terminal of the buck converter to receive the output voltage VOUT. The non-inverting input terminal of the second comparator Cp2 is simultaneously connected to the first timing capacitor Cton grounded, the first grounding switch transistor NM3 grounded, and the first charging current Iton. The output terminal of the second comparator Cp2 is the output terminal of the on-time generation module T1 and is used for the on-time signal TON. When the on-time signal TON is 1, it indicates the end of the on-time of the high-side power transistor HS, thereby being able to provide the on-time.

[0083] The source of the first grounding switch transistor NM3 is grounded, the drain is connected to the non-inverting input terminal of the second comparator Cp2, and the gate is connected to the high-side power transistor conduction signal HSON output by the PWM generation module P1 through the NOT gate NOT1, which is used to turn on the first grounding switch transistor NM3 when the high-side power transistor conduction signal HSON = 0 output by the PWM generation module P1, thereby causing the first timing capacitor Cton to be unable to charge, so that the conduction time generation module T1 starts timing when the high-side power transistor conduction signal HSON = 1. Therefore, the conduction time signal TON becomes 1 when the timing time from the conduction of the high-side power transistor (i.e., HSON becomes 1) reaches the conduction time.

[0084] Since the inverting input terminal of the second comparator Cp2 is connected to the voltage output terminal of the buck converter to receive the output voltage VOUT, therefore, when the output voltage reaches different voltage values, a constant switching frequency is achieved by making the conduction time proportional to the output voltage VOUT.

[0085] The first current source is used to provide a first charging current Iton proportional to the input voltage VIN. In this embodiment, the first current source is the current output terminal of the first current mirror, wherein the sources of all the switching transistors of the first current mirror are connected to the voltage input terminal of the buck converter to receive the input voltage VIN, and the current output terminal of the first current mirror is connected to the non-inverting input terminal of the second comparator Cp2, which means that the current flowing into the first timing capacitor Cton is proportional to the input voltage VIN. Therefore, the current flowing into the first timing capacitor Cton of the current source is proportional to the input voltage VIN, and a constant switching frequency is achieved by making the conduction time proportional to the input voltage VIN when the input voltage VIN changes.

[0086] In this embodiment, the first current mirror is a PMOS current mirror, which includes a first current mirror switching transistor PM1 and a second current mirror switching transistor PM2 whose gates are connected to each other, and the sources of both are connected to the input voltage VIN. The drain of the first current mirror switching transistor PM1 is connected to the gate, and the drain is grounded through a current mirror resistor Rvin and connected to the current output terminal of the second current mirror. Thus, the current mirror resistor Rvin can set the output current of the first current mirror, and the set output current is proportional to the input voltage VIN. The drain of the second current mirror switching transistor PM2 is the current output terminal of the first current mirror, which is used to provide the first charging current Iton.

[0087] The second current mirror is an NMOS current mirror, which includes a third current mirror switching transistor NM1 and a fourth current mirror switching transistor NM2 with their gates connected to each other. The drain of the third current mirror switching transistor NM1 is connected to its gate and connected to the input voltage VIN through a first resistor R1. The source of the third current mirror switching transistor NM1 is grounded through a current mirror grounding transistor PM3 in diode-connected form. The drain of the fourth current mirror switching transistor NM2 is the current output terminal of the second current mirror, and the source is grounded through a second current mirror resistor Rvin2, and the resistance value of the second current mirror resistor Rvin2 is the same as that of the current mirror resistor Rvin.

[0088] In this embodiment, since the ratio of the first current mirror is 1x / 1x, the first charging current Iton is the current flowing through the second current mirror switching transistor PM2, which is equal to the current flowing through the first current mirror switching transistor PM1.

[0089] And the current flowing through the first current mirror switching transistor PM1 is equal to the sum of the currents flowing into the current mirror resistor Rvin and the second current mirror resistor Rvin2.

[0090] The current flowing through the second current mirror resistor Rvin2 = the voltage threshold of the current mirror grounding transistor PM3 / the second current mirror resistor Rvin2 = VT_PM3 / Rvin,

[0091] The current flowing through the current mirror resistor Rvin = (input voltage VIN - the voltage threshold of the first current mirror switching transistor PM1) / the current mirror resistor Rvin = (VIN - VT_PM1) / Rvin,

[0092] Therefore, the first charging current Iton is:

[0093] Iton = (VIN - VT_PM1) / Rvin + VT_PM3 / Rvin,

[0094] Because the first current mirror switching transistor PM1 and the current mirror grounding transistor PM3 are in the same process and are similar to each other, the voltage threshold VT_PM1 of the first current mirror switching transistor is approximately equal to the voltage threshold VT_PM3 of the current mirror grounding transistor.

[0095] The first charging current Iton is:

[0096] Iton = (VIN - VT_PM1) / Rvin + VT_PM3 / Rvin = VIN / Rvin + (VT_PM3 - VT_PM2) / Rvin = VIN / Rvin

[0097] Therefore, the first charging current Iton provided by the first current source is proportional to the input voltage VIN. The actual circuit for implementing the first charging current Iton (i.e., the bias current proportional to the input voltage VIN) may be more complex.

[0098] The above structures of the present invention are all consistent with the specific structures of the existing buck converters in the ACOT mode. Therefore, in the ACOT mode, the on-time generation module T1 sets the high-side power transistor conduction signal HSON to 1 according to the rising edge of the output signal Vea of the comparator, so that the high-side power transistor HS starts to conduct; and resets the high-side power transistor conduction signal HSON according to the rising edge of the on-time signal TON to turn off the high-side power transistor HS.

[0099] The on-time (as shown in the red box in Figure 8 ) generated by the on-time generation module T1 is the time when the voltage in the first timing capacitor Cton reaches or exceeds the voltage at the inverting input terminal of the second comparator Cp2 (i.e., the output voltage VOUT). According to the basic equation for the charge stored in a capacitor: Q = V×C = I×t, the turn-on time Ton of the buck converter can be obtained as:

[0100] Ton = V×C / I = VOUT×Cton / Iton,

[0101] The above pre-calculated first charging current Iton is equal to VIN / Rvin. Therefore, the turn-on time Ton of the buck converter is obtained as:

[0102] Ton = VOUT×Cton / (VIN / Rvin) = (VOUT / VIN)×(Cton×Rvin)

[0103] Therefore, in the ACOT mode, the on-time set by the on-time signal TON is proportional to both the output voltage VOUT and the input voltage VIN.

[0104] For a buck converter, when we know its on-time, it is also easy to calculate its switching period or switching frequency.

[0105] T (buck converter) = Ton / D, where the duty cycle D = VOUT / VIN

[0106] ->T (buck converter) = Ton / (VOUT / VIN) = (VIN / VOUT)×Ton

[0107] Substituting the on-time calculated in the above ACOT mode into the equation, the switching period T(ACOT) of the buck converter under ACOT will be obtained:

[0108] T(ACOT) = (VIN / VOUT) × Ton = (VIN / VOUT) × (VOUT / VIN) × (Cton × Rvin) = Cton × Rvin,

[0109] The final result of the switching period here does not include VIN and VOUT. It only depends on the preselected first timing capacitor Cton and the current mirror resistor Rvin. Therefore, we can say that in ACOT mode, the switching frequency is constant and independent of the values of the input voltage VIN and the output voltage VOUT. This is the meaning of the letter "A" (Adaptive) in the buck converter in ACOT mode.

[0110] As Figure 8 shown, the buck converter in COT mode of the present invention adds the following modules on the basis of the existing buck converter in COT mode: a delay module DL1, a conduction time extension ability detection module DET1, and an AND gate AND1 whose two input terminals are respectively connected to the conduction time delay signal TON_DL of the delay module DL1 and the conduction time extension detection signal nExt_TON of the conduction time extension ability detection module DET1. Among them, the extended conduction time signal TON_EXT output by the AND gate AND1 serves as the reset signal of the high-side power tube conduction signal HSON. The extended conduction time signal TON_EXT replaces the existing conduction time signal TON as the reset signal of the high-side power tube conduction signal HSON. When the extended conduction time signal TON_EXT is at a high level (i.e., TON_EXT = 1), the reset of the high-side power tube conduction signal HSON is realized to turn off the high-side power tube HS.

[0111] The delay module DL1 is an RC delay timer. The delay module DL1 is set to perform a fixed delay of 5 ns on the conduction time signal TON to obtain the conduction time delay signal TON_DL, so as to leave room for the operation of the detection circuit DET1. In fact, the increased delay will make the conduction time slightly exceed the ratio of the output voltage VOUT / the input voltage VIN. However, this effect is too small to be negligible.

[0112] The time range of the fixed delay of the delay module DL1 is equal to 5 ns (±40%). This means that the delay time range of the delay module DL1 will be between 3 ns and 7 ns.

[0113] The conduction time extension ability detection module DET1 is a D flip-flop. Its clock terminal CLK is connected to the conduction time signal TON. The data port D is connected to a high level (5V). The reset terminal R is connected to the output signal nEXT_RS of a NOR gate, and is connected to the high-side power transistor maximum current indication signal IMAX, the maximum conduction time signal TON_MAX, and the inverted signal of the output voltage Vea of the main comparator through the NOR gate. The inverted output terminal QB of the conduction time extension ability detection module DET1 outputs a conduction time extension detection signal nExt_TON.

[0114] In some other embodiments, the high-side power transistor maximum current indication signal IMAX and the maximum conduction time signal TON_MAX can be omitted. Therefore, the reset terminal R can be directly connected to the output voltage Vea of the main comparator. Alternatively, one of the high-side power transistor maximum current indication signal IMAX and the maximum conduction time signal TON_MAX can be omitted, such that the reset terminal R is connected to the inverted signal of the output voltage Vea of the main comparator and one of the high-side power transistor maximum current indication signal IMAX and the maximum conduction time signal TON_MAX through the NOR gate.

[0115] The conduction time extension ability detection module DET1 is a traditional D flip-flop. The output of the positive output terminal Q of the D flip-flop will be equal to the input of its data port D at the rising edge of the signal at the clock terminal CLK, and will be reset to the default state when the signal at the reset terminal R is 0, that is, the output of the positive output terminal Q becomes 0 and the output of the inverted output terminal QB becomes 1. In this circuit, the conduction time signal TON is the input clock of the conduction time extension ability detection module DET1.

[0116] Since the output signal nEXT_RS of the NOR gate is connected to the reset terminal R of the conduction time extension ability detection module DET1, when the output signal nEXT_RS of the NOR gate received by the reset terminal R of the conduction time extension ability detection module DET1 is equal to 0, the conduction time extension ability detection module DET1 will be reset to the default state, and the conduction time extension detection signal nExt_TON output by its inverted output terminal becomes 1.

[0117] In this embodiment, the three input terminals of the NOR gate are respectively connected to the high-side power transistor maximum current indication signal IMAX, the maximum conduction time signal TON_MAX, and the inverted signal of the output voltage Vea of the main comparator.

[0118] Among them, the maximum current indication signal IMAX of the high-side power transistor changes from 0 to 1 when the current of the high-side power transistor reaches the maximum protection current. The maximum conduction time signal TON_MAX changes from 0 to 1 when the timing time starting from the conduction of the high-side power transistor (i.e., HSON changes to 1) reaches the maximum conduction time. The output voltage Vea of the main comparator changes from 1 to 0 when the feedback voltage FB is greater than the reference voltage Vref.

[0119] Thus, the conduction time extension ability detection module DET1 is reset when the output signal nEXT_RS of the NOR gate is equal to 0 (i.e., the output voltage Vea of the comparator = 0 or TON_MAX = 1 or IMAX = 1), so that the conduction time extension detection signal nExt_TON output from its inverted output terminal becomes 1, turning off the high-side power transistor HS of the buck converter. If none of the above three situations exist, the conduction time extension ability detection module DET1 will latch the high-level result at the rising edge of the conduction time signal TON, so that the conduction time extension detection signal nExt_TON output from its inverted output terminal becomes 0 (i.e., 0V) within less than 1 ns after the conduction time signal TON = 1. During the period when the change of the conduction time extension detection signal nExt_TON is not completed, the conduction time delay signal TON_DL is still equal to 0 because the delay time of the conduction time delay signal TON_DL relative to the conduction time signal TON is 5 ns longer.

[0120] Therefore, at the rising edge of the conduction time signal TON, if the output voltage Vea of the main comparator = 1 (at this time, the high-side power transistor HS has just conducted, and it must satisfy TON_MAX = 0 and IMAX = 0), the conduction time extension detection signal nExt_TON = 0, blocking the output of the conduction time delay signal TON_DL and keeping the extended conduction time signal TON_EXT equal to zero (0V), so that the high-side power transistor HS continues to be turned on; until one of the following three situations occurs (Vea = 0, TON_MAX = 1, IMAX = 1), the extended conduction time signal TON_EXT becomes 1, turning off the high-side power transistor HS.

[0121] Therefore, through the simple circuit composed of the above-mentioned delay module DL1, conduction time extension ability detection module DET1, and AND gate AND1, the present invention successfully converts the constant conduction time mode into the constant off time mode.

[0122] The maximum current indication signal IMAX of the high-side power transistor is the output of the high-side power transistor maximum current protection circuit. When the high-side power transistor HS is turned on, the current sensing circuit senses the current passing through the high-side power transistor HS and makes the maximum current indication signal IMAX of the high-side power transistor change from 0 to 1 when the current reaches the maximum protection current, so as to turn off the high-side power transistor HS. This is to ensure that the high-side power transistor HS operates within the current safe operating area.

[0123] The maximum time generation module is a timer. The maximum time generation module is used to generate a maximum on-time signal TON_MAX, and the maximum on-time signal TON_MAX changes from 0 to 1 when the timing time starting from the turn-on of the high-side power transistor (i.e., HSON becomes 1) reaches the maximum on-time.

[0124] The maximum time generation module includes a third comparator Cp3. The inverting input terminal of the third comparator Cp3 is connected to the third comparator reference voltage (1.2V), and the non-inverting input terminal is simultaneously connected to a second timing capacitor Ctmax grounded, a second grounded switch transistor NM4 grounded, and a second charging current Itmax. Therefore, the maximum on-time provided by the maximum on-time signal TON_MAX is the time when the second charging current Itmax is charged into the second timing capacitor Ctmax until the voltage of the second timing capacitor Ctmax reaches the third comparator reference voltage (1.2V), and the maximum on-time is very accurate.

[0125] The maximum on-time is in the range of 30 μs (±15%), which means it will be in the range of 25.5 μs to 34.5 μs. The second charging current Itmax is a constant current and is generated by a simple bias current circuit. Specifically, as Figure 9 shown, the second charging current Itmax is the mirror current of the base bias current. The base bias circuit includes a buffer B1 for generating the base bias current and a third current mirror with the current input terminal connected to the base bias current. The output terminal of the third current mirror is used to output the second charging current Itmax. The non-inverting input terminal of the buffer B1 is connected to the buffer input voltage (1.2V), the inverting input terminal of the buffer B1 is connected to the third current mirror resistor R3 and the source of the fifth switch transistor NM5, the output terminal of the buffer B1 is connected to the gate of the fifth switch transistor NM5, and the source of the fifth switch transistor NM5 is connected to the current input terminal of the third current mirror and generates the base bias current. Therefore, the base bias current generated by the buffer B1 is equal to 1.2V / R3. The third current mirror resistor R3 has a trimming network to perform trimming operations on the maximum time generation module during mass production.

[0126] The typical waveforms of the buck converter in the COT mode of the present invention are as Figure 10 shown. InFigure 10 In [the circuit], the input voltage VIN is approximately 5.75V, which is quite low for a target output voltage of 5.5V. At the rising edge of the on-time signal TON, we can see that the output voltage of the main comparator Vea = 1 (i.e., the feedback voltage FB < the reference voltage Vref). Therefore, the on-time extension ability detection module DET1 will detect the state of Vea and set the on-time extension detection signal nExt_TON = 0 within approximately 1ns.

[0127] The on-time delay signal TON_DL represents a signal that is delayed by 5.5ns from the on-time signal TON. The extended on-time signal TON_EXT is the AND function of the on-time delay signal TON_DL and the on-time extension detection signal nExt_TON. The extended on-time signal TON_EXT remains 0 until the feedback voltage FB is higher than VREF (i.e., the output voltage of the main comparator Vea = 0), to reset the on-time extension ability detection module DET1 and reset the high-side power transistor on signal HSON. The on-time is extended from 1.3565μs to 5.064μs to increase the maximum duty cycle.

[0128] Figure 11 and Figure 12 shows the waveform diagrams of an existing and the present invention's buck converter in ACOT mode in an analog scenario, where the analog scenario corresponds to the situation of a rapid load jump (the load current changes from 0 -> 8A in 1μs).

[0129] Figure 11 shows that for VIN = 12V, VOUT = 5.5V, the load current steps from 0 -> 8A in 1μs, and the output voltage undershoot of the existing buck converter in ACOT mode is 344.5mV.

[0130] Figure 12 shows that for VIN = 12V, VOUT = 5.5V, the load steps from 0 -> 8A in 1μs, and after using the buck converter of the present invention in ACOT mode, the output voltage undershoot drops to 283mV.

[0131] Figure 13 shows a waveform comparison diagram of an existing and the present invention's buck converter in ACOT mode in an analog scenario, where the analog scenario corresponds to the maximum duty cycle limit.

[0132] Figure 13 shows a comparison of the simulation results of the maximum duty cycle of an existing buck converter in the ACOT mode of the present invention. Among them, the output voltage VOUT = 5.54V, the load current ILOAD = 2A, and the input voltage VIN drops from 6.25V to 5.5V.

[0133] The blue waveform is the waveform of the buck converter (output voltage VOUT, switch node voltage VSW, inductor current IL) in the ACOT mode of the present invention. The pink waveform is the waveform of an existing buck converter (output voltage VOUT, switch node voltage VSW, inductor current IL) in the ACOT mode. In the simulation, the output voltage VOUT of the existing circuit starts to drop when the input voltage VIN = 6V. In the circuit of the present invention, when VIN = 5.48V, since the conduction time of the switch node SW is extensible, the output voltage VOUT is still close to 5.42V (maximum duty cycle ~ 99%).

[0134] Figure 14 shows Figure 13 A partial enlarged view of the waveforms of an existing and the buck converter of the present invention in the ACOT mode under the simulated scenario of the maximum duty cycle limit shown. Figure 14 Shows two periods during which the maximum duty cycle of the circuit of the present invention is extended relative to the existing circuit. In period 1, VIN is still high enough to support the output, and the conduction time of the integrated circuit is determined by the output voltage Vea of the main comparator. In period 2, the input voltage VIN is at a low level. If the maximum conduction time is set, the conduction time of the entire circuit of the present invention is limited by the maximum conduction time signal TON_MAX.

[0135] Among them, the blue waveform is the waveform of the buck converter in the COT mode of the present invention (1 - output voltage VOUT, 3 - switch node voltage VSW, 4 - inductor current IL). The pink waveform is the waveform of the existing COT mode circuit (2 - output voltage VOUT, 5 - inductor current IL, 6 - switch node voltage VSW). It can be easily seen from the partial enlarged view that in the circuit of the present invention, the conduction time continuously extends within "Period 1", while the input voltage VIN is decreasing. The conduction time will only be reset when the output voltage Vea of the main comparator is zero or the conduction time reaches the maximum conduction time. In "Period 2", the conduction time of the integrated circuit is limited by the maximum conduction time. As mentioned above, if the maximum conduction time is not set (the maximum conduction time is infinite), the circuit of the present invention can enter the working mode with a 100% duty cycle, making the simulation result only depend on the relationship between the input voltage VIN, the output voltage VOUT and the load. However, if the conduction time is too long, other charge pump circuits are needed to maintain the power supply of the high-side power transistor HS. In addition, another purpose of setting the maximum conduction time is not to allow the integrated circuit to switch at audible frequencies. If a 100% duty cycle is required, other logics can be added to make the circuit of the present invention jump to the 100% duty cycle mode. For example, the PWM generation module can be set as follows: if the feedback voltage FB is less than the reference voltage Vref (i.e., the output voltage Vea of the main comparator = 1) when reaching the maximum conduction time for a continuous preset number of times (such as 8 times), the buck converter in the COT mode of the present invention can be made to jump to the 100% duty cycle mode, where the high-side power transistor can conduct forever and only turn off when the feedback voltage (FB) is greater than or equal to the reference voltage (Vref) or when the current of the high-side power transistor reaches the maximum protection current, rather than turning off the high-side power transistor according to the maximum conduction time.

[0136] Figure 15 Shows the experimental results of the silicon wafer, that is, the actual load step response diagram of the buck converter in the ACOT mode of the present invention on the silicon wafer. As Figure 15 shown, the conduction time of the high-side power transistor expands as expected. In the figure, blue represents the input voltage VIN, and the yellow signal represents the switch node voltage SW (whose waveform is consistent with the conduction signal HSON of the high-side power transistor) respectively, and the red signal represents the load current ILOAD.

[0137] Figures 16A to 16D Shows the oscilloscope waveform diagram of the buck converter in the ACOT mode of the present invention under the scenario of the maximum duty cycle, where the input voltage VIN starts to scan upward from 20V and the output voltage VOUT is set = 20V. When the input voltage VIN is relatively low, the conduction time represented by the switch node SW extends.

[0138] The above are only the preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Various changes can be made to the above embodiments of the present invention. Any simple, equivalent changes and modifications made in accordance with the claims and the content of the specification of the present invention application shall fall within the scope of protection of the claims of the present invention patent. Those not described in detail in the present invention are all conventional technical contents.

Claims

1. A buck converter in COT mode, characterized in that: It includes a main comparator (Cp1), an on-time generation module for providing an on-time signal (TON) of a COT mode, a delay module (DL1), an on-time extension capability detection module (DET1), an AND gate (AND1), and a PWM generation module (P1), wherein the main comparator (Cp1) is used to compare a feedback voltage (FB) and a reference voltage (Vref); two input terminals of the AND gate (AND1) are respectively connected to an on-time delay signal (TON_DL) and an on-time extension detection signal (nExt_TON), and the AND gate (AND1) outputs an extended on-time signal (TON_EXT); The delay module (DL1) performs a fixed delay on the on-time signal (TON) to obtain the on-time delay signal (TON_DL); the on-time extension capability detection module (DET1) is a D flip-flop, whose clock terminal (CLK) is connected to the on-time signal (TON), the data port (D) is connected to a high level, the reset terminal (R) is connected to the output voltage (Vea) of the main comparator, and the inverting output terminal (QB) outputs the on-time extension detection signal (nExt_TON); The PWM generation module (P1) is configured to: receive an extended on-time signal (TON_EXT) to use it as a signal to turn off the high-side power tube (HS); When the on-time signal (TON) changes from 0 to 1, it is determined whether the feedback voltage (FB) is less than the reference voltage (Vref); if the feedback voltage (FB) is less than the reference voltage (Vref), the off-time will be skipped so that the high-side power tube (HS) continues to be turned on until the feedback voltage (FB) is greater than or equal to the reference voltage (Vref), at which time the high-side power tube (HS) of the buck converter is turned off.

2. The buck converter in COT mode according to claim 1, characterized in that: The PWM generation module (P1) is also configured to: turn off the high-side power tube (HS) when the timing time from the start of the high-side power tube being turned on reaches the maximum on-time.

3. The buck converter in COT mode according to claim 1, characterized in that: The fixed delay is 3ns-7ns.

4. The buck converter in COT mode according to claim 1, characterized in that: The output voltage (Vea) of the main comparator changes from 1 to 0 when the feedback voltage (FB) is greater than the reference voltage (Vref).

5. The buck converter in COT mode according to claim 2, characterized in that: The PWM generation module (P1) is further configured to: if the feedback voltage (FB) is less than the reference voltage (Vref) when the maximum on-time is reached for a continuous preset number of times, the buck converter enters a 100% duty cycle mode, wherein the high-side power tube can be turned on forever and is only turned off when the feedback voltage (FB) is greater than or equal to the reference voltage (Vref) or when the current of the high-side power tube reaches the maximum protection current.

6. A buck converter in COT mode, characterized in that: It includes a main comparator (Cp1), an on-time generation module for providing an on-time signal (TON) of a COT mode, a delay module (DL1), an on-time extension capability detection module (DET1), an AND gate (AND1), and a PWM generation module (P1), the main comparator (Cp1) is used to compare a feedback voltage (FB) and a reference voltage (Vref), two input ends of the AND gate (AND1) are respectively connected to an on-time delay signal (TON_DL) and an on-time extension detection signal (nExt_TON), and the AND gate (AND1) outputs an extended on-time signal (TON_EXT); The delay module (DL1) performs a fixed delay on the on-time signal (TON) to obtain the on-time delay signal (TON_DL); the on-time extension capability detection module (DET1) is a D flip-flop, whose clock terminal (CLK) is connected to the on-time signal (TON), the data port (D) is connected to a high level, the inverting output terminal (QB) outputs the on-time extension detection signal (nExt_TON), and the reset terminal (R) is connected to the output signal (nEXT_RS) of a NOR gate (NOR) to connect the inverted signal of the output voltage (Vea) of the main comparator, as well as the maximum current indication signal (IMAX) and the maximum on-time signal (TON_MAX) of the high-side power tube through the NOR gate (NOR); The PWM generation module (P1) is configured to: receive an extended on-time signal (TON_EXT) to use it as a signal to turn off the high-side power tube (HS); When the on-time signal (TON) changes from 0 to 1, it is determined whether the feedback voltage (FB) is less than the reference voltage (Vref); if the feedback voltage (FB) is less than the reference voltage (Vref), the off-time will be skipped so that the high-side power tube (HS) continues to be turned on until the feedback voltage (FB) is greater than or equal to the reference voltage (Vref), at which time the high-side power tube (HS) of the buck converter is turned off.

7. The buck converter in COT mode according to claim 6, characterized in that: The high-side power tube maximum current indication signal (IMAX) changes from 0 to 1 when the current of the high-side power tube reaches the maximum protection current; the maximum on-time signal (TON_MAX) changes from 0 to 1 when the timing time from the start of the high-side power tube conduction reaches the maximum on-time; the output voltage (Vea) of the main comparator changes from 1 to 0 when the feedback voltage (FB) is greater than the reference voltage (Vref); The on-time extension capability detection module (DET1) is reset when the output signal (nEXT_RS) of the NOR gate (NOR) is equal to 0, so that the on-time extension detection signal (nExt_TON) becomes 1, thereby turning off the high-side power tube (HS) of the buck converter.

8. The buck converter in COT mode according to claim 6, characterized in that: The PWM generation module (P1) is also configured to: turn off the high-side power tube (HS) when the timing time from the start of the high-side power tube being turned on reaches the maximum on-time.

9. The buck converter in COT mode according to claim 8, characterized in that: The PWM generation module (P1) is further configured to: if the feedback voltage (FB) is less than the reference voltage (Vref) when the maximum on-time is reached for a continuous preset number of times, the buck converter enters a 100% duty cycle mode, wherein the high-side power tube can be turned on forever and is only turned off when the feedback voltage (FB) is greater than or equal to the reference voltage (Vref) or when the current of the high-side power tube reaches the maximum protection current.

10. The buck converter in COT mode according to claim 6, characterized in that: The fixed delay is 3ns-7ns.

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