Self-adaptive synchronous rectification control method suitable for CLLLC resonant converter

Abstract

The invention discloses a self-adaptive synchronous rectification control method suitable for a CLLLC resonant converter, solves the problem that the calculation process of a theoretical calculation method for synchronous rectification of the CLLLC resonant converter is relatively complex, and belongs to the field of CLLLC resonant converter control. Based on the circuit characteristics and the working process of the CLLLC converter, the influence of a converter synchronous rectification driving signal on the output frequency when the converter stably outputs a signal is analyzed, and a relation equation of the change of the synchronous rectification signal and the change of the working frequency near an ideal synchronous rectification signal is deduced; and the synchronous rectification function of the CLLLC converter is realized by using the rule of the equation. In rectification control, a certain disturbance signal is given to a synchronous rectification signal, and then the synchronous rectification signal of the converter gradually approaches to an ideal synchronous rectification state according to the change of the working frequency before and after the converter reaches a stable output signal. Additional sensors are not needed, and meanwhile complex theoretical calculation is avoided.

Description

Technical Field

[0001] The invention relates to an adaptive synchronous rectification control method suitable for a CLLLC resonant converter, and belongs to the field of CLLLC resonant converter control. Background Art

[0002] The CLLLC resonant converter has a wider input voltage range and better soft switching characteristics by adding LLC resonant cavity structures on the primary and secondary sides of the transformer. It can achieve the natural soft switching characteristics of the converter without the need for other auxiliary circuits. It has been widely used in the fields of aerospace energy, electric vehicles, distributed energy storage, etc. However, the input and output of the converter are both full-bridge structures. Compared with the reverse conduction characteristics of the switch tube, the synchronous rectification method can further improve the working efficiency of the converter.

[0003] The existing synchronous rectification methods mainly include voltage detection method, current detection method and theoretical calculation method. Among them, the voltage detection method is a typical principle of detecting the voltage between the source and drain of the device. When the device is reversely conducted, the voltage between the drains will be a positive voltage, and synchronous rectification will be turned on at this time; the current detection method uses a current sensor to detect the current flowing through the diode on the rectifier side, and determines the synchronous rectification signal according to its polarity. The theoretical calculation method establishes a mathematical model of the CLLLC resonant converter, and uses mathematical calculations to obtain the phase and duty cycle of the rectifier side current under different working conditions, and uses this as the basis for synchronous rectification. At present, the commonly used CLLLC resonant converter modeling method is the fundamental wave analysis method, through which the phase difference between the rectifier side current and the drive side voltage can be approximately obtained, and then the synchronous rectification signal on the rectifier side can be obtained. However, this method has a large deviation in the under-resonance working mode, so that a more accurate synchronous rectification signal cannot be obtained. Although the extended harmonic analysis method is more accurate than the fundamental wave analysis method, it still cannot solve the problem of discontinuous resonant current in the under-resonance working mode. Compared with the frequency domain model, the time domain model can solve this problem well, but the CLLLC resonant converter has 5 resonant elements, and its solution process is more complicated.

[0004] By comparing the above three methods, it can be seen that the theoretical calculation method does not require the addition of any additional sensors. It can determine the synchronous rectification signal based on the switching frequency, output voltage and current and other state information, which can effectively improve the working efficiency and power density of the converter, but its calculation process is relatively complicated. Summary of the invention

[0005] In view of the problem that the calculation process of the theoretical calculation method of the synchronous rectification of the CLLLC resonant converter is relatively complicated, the present invention provides an adaptive synchronous rectification control method applicable to the CLLLC resonant converter without changing the circuit structure.

[0006] An adaptive synchronous rectification control method applicable to a CLLLC resonant converter of the present invention comprises:

[0007] The output voltage V of the CLLLC resonant converter o Perform real-time acquisition and output the real-time acquired output voltage output signal V o With a given voltage V ref Comparison is performed, and the compared error signal is sent to the loop controller to stabilize the output voltage of the CLLLC resonant converter;

[0008] When the output voltage of the CLLLC resonant converter is stable and the CLLLC resonant converter operates in the under-resonance mode, the synchronous rectification optimization is performed:

[0009] S1, giving the converter the initial synchronous rectification signal conduction time T SR,k-1 After the output voltage of the CLLLC resonant converter is stable, record the operating frequency f at this time s,k-1 ;The initial value of k is 1;

[0010] S2, giving the converter a fixed disturbance ΔT on the synchronous rectification signal SR , let the synchronous rectification signal conduction time T SR,k =T SR,k-1 +ΔT SR After the output voltage of the CLLLC resonant converter is stable, the operating frequency at this time is recorded as f s,k , and obtain a reference value of frequency change Δf ref =|f s,k -f s,k-1 |; The time interval between two disturbances satisfies the time required for the output voltage to adjust to the reference value;

[0011] S3, giving the converter synchronous rectification signal a fixed disturbance ΔT SR , let the conduction time of the synchronous rectification signal be T SR,k+1 =T SR,k +ΔT SR After the output voltage of the CLLLC resonant converter is stable, record the operating frequency f at this time s,k+1 , we get a frequency change Δf=|f s,k+1 -f s,k |;

[0012] S4. If Δf≥AΔf ref , let T SR,k+1 =T SR,k -ΔT SR , the on-time of the ideal synchronous rectification in under-resonance mode is determined to be T SR,k+1 , end, if Δf<AΔf ref, then update Δf ref The value is Δf, k=k+1, go to S3, A is 1.5.

[0013] When the output voltage of the CLLLC resonant converter is stable and the CLLLC resonant converter operates in over-resonance mode, synchronous rectification optimization is performed:

[0014] S1, synchronous rectification signal lag time of converter After that, the initial synchronous rectification signal conduction time T SR,k-1 After the output voltage of the CLLLC resonant converter is stable, record the operating frequency f at this time s,k-1 ;The initial value of k is 1; Satisfy the maximum hysteresis time of the converter under all working conditions;

[0015] S2, synchronous rectification signal hysteresis time After that, a fixed disturbance ΔT is given to the synchronous rectification signal of the converter. SR , let the synchronous rectification signal conduction time T SR,k =T SR,k-1 +ΔT SR After the output voltage of the CLLLC resonant converter is stable, the operating frequency at this time is recorded as f s,k , and obtain a reference value of frequency change Δf ref =|f s,k -f s,k-1 |;

[0016] S3, synchronous rectification signal hysteresis time After that, a fixed disturbance ΔT is given to the synchronous rectification signal of the converter. SR , let the conduction time of the synchronous rectification signal be T SR,k+1 =T SR,k +ΔT SR After the output voltage of the CLLLC resonant converter is stable, record the operating frequency f at this time s,k+1 , we get a frequency change Δf=|f s,k+1 -f s,k |; The time interval between two disturbances satisfies the time required for the output voltage to adjust to the reference value;

[0017] S4. If Δf≥AΔf ref , let T SR,k+1 =T SR,k -ΔT SR , Determine the ideal synchronous rectification signal hysteresis time in over-resonance state And the conduction time is T SR,k+1 , end, if Δf<AΔf ref , then update Δf refThe value is Δf, k=k+1, go to S3, A is 1.5.

[0018] The beneficial effect of the present invention is that the present invention gives a certain disturbance signal to the synchronous rectification signal, and then makes the synchronous rectification signal of the converter gradually approach the ideal synchronous rectification state according to the change of the working frequency before and after the converter reaches a stable output signal. The advantages of the present invention are mainly manifested in: since the CLLLC resonant converter already has an output voltage detection unit that can detect the output voltage, the switching frequency under variable frequency control can be directly obtained by the microcontroller, so this method can achieve ideal synchronous rectification without additional sensors, while avoiding complex theoretical calculations. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is the principle diagram of the control method of the present invention;

[0020] Figure 2 A flow chart for optimizing the present invention;

[0021] Figure 3 For the definition of different rectification states;

[0022] Figure 4 Different working modes of CLLLC resonant converter in time domain model;

[0023] Figure 5 is the working waveform of the converter when it is in a synchronous rectification distortion state in the under-resonance working mode;

[0024] Figure 6 T is the sub-resonant working mode SR With load R o and operating frequency f s The relationship curve diagram of

[0025] Figure 7 When the input voltage is 400V and the output voltage is 1000W, the stable output voltage is 54V. SR With the operating frequency f s The relationship curve of

[0026] Figure 8 When the input voltage is 400V and the output voltage is 1000W, the stable output voltage is 54V. SR With f s Dynamic adjustment process;

[0027] Fig. 9 This is the working waveform when the input is 400V and the output is stable at 54V under 1000W working condition;

[0028] Fig.10 is the working waveform of the converter in the over-resonance working mode;

[0029] Fig.11 is the phase angle of lag in over-resonance operation mode With load R o and operating frequency f s The relationship curve diagram of

[0030] Fig.12 When the input voltage is 420V and the output voltage is 1000W, the stable output voltage is 48V. SR With the operating frequency f s The relationship curve of

[0031] Fig.13 When the input voltage is 420V and the output voltage is 1000W, the stable output voltage is 48V. SR With f s Dynamic adjustment process;

[0032] Fig.14 This is the working waveform when the input is 420V and the output is stable at 48V under 1000W working conditions. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0035] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0036] The adaptive synchronous rectification control method for the CLLLC resonant converter of this embodiment is based on the circuit characteristics and working process of the CLLLC converter, analyzes the influence of the converter synchronous rectification drive signal on the output frequency of the converter when the converter stabilizes the output signal, derives the relationship equation between the change of the synchronous rectification signal and the change of the operating frequency near the ideal synchronous rectification signal, and uses the law of the equation to realize the synchronous rectification function of the CLLLC converter.

[0037] The CLLLC converter can work in both directions and can work in different modes due to different working frequencies. The following specifically describes the CLLLC converter working in under-resonance and over-resonance modes when working in the forward direction.

[0038] Example 1: Taking the converter working in the under-resonance mode as an example, when the converter works in the under-resonance mode, it is considered to be in an ideal synchronous rectification state. According to the time domain analysis method, it works in the P mode and the O mode, such as Figure 4 shown.

[0039] According to Kirchhoff's voltage law and current law, the expressions of the resonant current, resonant capacitor voltage and excitation current of mode P and mode O can be obtained.

[0040]

[0041] in

[0042]

[0043] In order to obtain the unknowns in the above formula, certain constraints need to be considered:

[0044] ① The inductor current and capacitor voltage will not change suddenly. Therefore, when two adjacent modes are switched, the values ​​of the inductor current and capacitor voltage should be equal.

[0045]

[0046] ② Because the converter adopts variable frequency modulation strategy, the waveform satisfies half-cycle symmetry when working in steady state, that is, the value of the state variable at the starting time of a cycle and the value at the half-cycle time are opposite to each other;

[0047]

[0048] ③Since the analysis is of an ideal model, the influence of loss is not considered, that is, the input and output power of the converter are equal.

[0049]

[0050] After iterative calculation by MATLAB, the relationship curve between the driving time of the synchronous rectification signal, the operating frequency and the output power of the converter in the under-resonance working mode is obtained as follows: Figure 6 As shown in the figure, in the under-resonance working mode, the minimum time of the synchronous rectification drive signal is about T r =π / ω a1 .

[0051] Based on the above calculation, taking the design parameters of this implementation as an example, L r =57.068μH, C r =44.386nF, L m=285.341μH, n = 8. Let the converter input voltage be 400V, the output voltage be 54V, and under the full load of 1kW, the time domain model is calculated to obtain the operating frequency of the converter to be 87kHz when the loss is ignored.

[0052] At this time, the voltage and current coefficients of the converter in P mode and O mode are P a1 =-155.4738, P a2 =-72.1478, P a3 =-422.5267, P a4 =-239.2876, t1 = 5.088e-6, O1 = -278.3431, O2 = 311.0252. Considering the rectifier diode conduction voltage drop V f =The loss caused by 0.3V.

[0053]

[0054] The change in output voltage can be expressed as

[0055]

[0056] If the converter output is still maintained at 54V, the coefficient of the converter operating in the 87kHz time domain model is used as a reference, and the time relationship diagram of the converter operating frequency and the synchronous rectification drive signal can be obtained as follows: Figure 7 If the on-time of the synchronous rectifier is further increased, the converter will have two additional operating modes, and the operating waveforms are as follows: Figure 5 As shown. In [t1,t 1_mi ] period, the inductance L r1 With capacitor C r1 Resonance still occurs and the circuit continues to work in P mode. At this time, the current is reversed, so the secondary side transfers energy to the primary side.

[0057] In [t 1_mi During the time period t2], due to the existence of inductance, the current cannot change suddenly. Since the switch tube is turned off, the current will be conducted by the parasitic diode of another switch tube in the bridge arm. At this time, the converter works in N mode.

[0058] The time domain expression in N mode is similar to that in P mode. It only needs to change V'2 to -V'2, that is,

[0059]

[0060] The final value of the P mode is the initial value of the N mode. Substituting the final value of the P mode into the initial value of the N mode, the energy transferred from the secondary side to the primary side of the converter can be obtained.

[0061]

[0062] The change in output voltage can be expressed as

[0063]

[0064] Since the synchronous rectification driving time is performed with a small disturbance, the time domain parameters at 87kHz are still used, and |Δf can be obtained s |With T SR The relationship curve is as follows Figure 7 As shown in (b). Figure 7 From (b), we can see that when T SR If you still want to maintain a certain input voltage after exceeding the ideal synchronous rectification signal, the operating frequency of the converter will change significantly. Therefore, you can gradually increase T SR The conduction time of the converter can be determined by judging the relative change of the operating frequency to determine whether the converter is in an ideal synchronous rectification state.

[0065] Based on the above analysis, an adaptive synchronous rectification control method suitable for CLLLC resonant converter is obtained, as shown in Figure 2 As shown in (a) and (b) in the figure. First, based on the collected voltage and current, it is determined that the working state of the converter will not change. At the same time, the output signal V o Real-time sampling is performed and compared with the given value V ref The error signal is sent to the loop controller. When the output is stable, the working state of the converter is obtained. The CLLLC resonant converter works in the under-resonance mode and performs synchronous rectification optimization:

[0066] Step 1: Give the converter an initial synchronous rectification signal conduction time T SR,k-1 After the output voltage of the CLLLC resonant converter is stable, record the operating frequency f at this time s,k-1 ; The initial value of k is 1; In this embodiment, T SR,0 =0.48T r1 , T r1 is the resonant period;

[0067] Step 2: As the loss of the converter synchronous rectifier tube is reduced, the converter operating frequency needs to be further adjusted to stabilize the output voltage. When the converter output is stable, a fixed disturbance ΔT is given to the converter synchronous rectifier signal. SR , let the synchronous rectification signal conduction time T SR,k =T SR,k-1 +ΔT SR After the output voltage of the CLLLC resonant converter is stable, the operating frequency at this time is recorded as f s,k , and obtain a reference value of frequency change Δfref =|f s,k -f s,k-1 |.

[0068] Step 3: Give the converter synchronous rectification signal a fixed disturbance ΔT SR , let the conduction time of the synchronous rectification signal be T SR,k+1 =T SR,k +ΔT SR After the output voltage of the CLLLC resonant converter is stable, record the operating frequency f at this time s,k+1 , we get a frequency change Δf=|f s,k+1 -f s,k |; In this embodiment, T SR,0 =0.48T r1 , T r1 is the resonant period;

[0069] Step 4: If Δf<AΔf ref , then let Δf ref =Δf, go to step 3; if Δf≥AΔf ref , the converter is considered to be in a synchronous rectification error state. At this time, the synchronous rectification drive signal needs to return to the previous state. The ideal synchronous rectification conduction time in the under-resonance mode is determined to be T SR,k+1 In this example, A = 1.5, ΔT SR The change amount changes in 1% steps; at the same time, the time interval between two disturbances meets the time required for the output voltage to adjust to the reference value. In order to allow the output to have enough time to stabilize after the disturbance is added, the time of each superimposed disturbance is set to 1ms.

[0070] According to the constructed model, the optimization process of the synchronous rectification drive signal is as follows: Figure 8 The adjusted experimental results are shown in Fig. 9 shown.

[0071] Example 2: Taking the converter working in the over-resonance mode as an example, when the converter works in the over-resonance working mode, it is considered to be in an ideal synchronous rectification state. According to the time domain analysis method, it works in the N mode and the P mode, and the working waveform is as follows: Fig.10 shown.

[0072] According to Kirchhoff's voltage law and current law, the expressions of the resonant current, resonant capacitor voltage and excitation current of mode N and mode P can be obtained.

[0073]

[0074] In the case of over-resonance, the circuit is inductive and the load current lags behind the primary drive for a certain period of time. Using the boundary conditions, we can get that in the over-resonance mode, taking the secondary current zero crossing point t0 as the reference, T SR With the operating frequency f s and load R o The relationship curve is as follows Fig.11 shown. It is used to set the initial turn-on time of the secondary-side rectifier tube. When the synchronous rectification method proposed in this embodiment is used later, no calculation is required. Just set a larger time. The subsequent turn-on time can be corrected by the optimization algorithm.

[0075] Also based on the above calculation, let the converter input voltage be 420V, the output voltage be 48V, and under the full load of 1kW, the time domain model is calculated to obtain that the operating frequency of the converter is 115kHz when the loss is ignored.

[0076] At this time, the voltage and current coefficients of the converter in N mode and P mode are N b1 =-521.7242, N b2 =-120.017, N b3 =-14.8509, N b4 =-167.1706, P b1 =-149.0349, P b2 =-50.4038, P b3 =-405.4478, P b4 =-167.1706. Considering the conduction voltage drop V of the rectifier diode f =The loss caused by 0.3V.

[0077]

[0078] The change in output voltage can be expressed as

[0079]

[0080] If the converter output is still maintained at 48V, the coefficient of the converter working in the 115kHz time domain model can be used as a reference, and the time relationship diagram of the converter operating frequency and the synchronous rectification drive signal can be obtained with the secondary side current zero crossing point as the reference. Fig.12 As shown in (a).

[0081] Under the above working conditions, after iterative calculation, it can be known that the lag time of the synchronous rectification signal is 0.21μs. Under the over-resonant operation state, the initial value of the synchronous rectification signal lag needs to meet the maximum lag time under all working conditions, so as to achieve the driving signal lag time. As an example, the current flowing through the secondary side is continuous when the converter is in over-resonance. If the conduction time T of the synchronous rectification is further increased at this time, SR , since the converter has a large margin at the initial moment of synchronous rectification, the converter will reach a new equilibrium state again, and the time t1 can be calculated as a known quantity. At this time, the converter is also combined in N mode and P mode.

[0082] After iterative calculation, in this working mode, if the output voltage is to be maintained at 48V, the working frequency needs to be adjusted to 122.8kHz. Then, the waveform of the transition from the incomplete synchronous rectification state to the ideal synchronous rectification state can be obtained as follows: Fig.12 As shown in (b).

[0083] Therefore, in the over-resonance mode, the initial value can lag behind the primary side drive signal for a long time, which can be measured in practice and leave a certain margin. After finding the ideal turn-off time of the synchronous rectifier tube through the same optimization algorithm as the under-resonance, its turn-on time can be found by setting the turn-on time to the general switching frequency. When the CLLLC resonant converter works in the over-resonance mode, the process of optimizing the synchronous rectification includes:

[0084] Step 1: Synchronous rectification signal lag time of converter After that, the initial synchronous rectification signal conduction time T SR,k-1 After the output voltage of the CLLLC resonant converter is stable, record the operating frequency f at this time s,k-1 ; To meet the maximum hysteresis time of the converter under all working conditions, this embodiment T S represents the switching cycle; the initial value of k is 1,

[0085] Step 2: Synchronous rectification signal hysteresis time After that, a fixed disturbance ΔT is given to the synchronous rectification signal of the converter. SR , let the synchronous rectification signal conduction time T SR,k =T SR,k-1 +ΔT SR After the output voltage of the CLLLC resonant converter is stable, the operating frequency at this time is recorded as f s,k , and obtain a reference value of frequency change Δf ref =|f s,k -f s,k-1 |; In this embodiment, ΔT SR =0.01T S , T S represents the switching cycle;

[0086] Step 3: Synchronous rectification signal hysteresis time After that, a fixed disturbance ΔT is given to the synchronous rectification signal of the converter. SR , let the conduction time of the synchronous rectification signal be T SR,k+1 =T SR,k +ΔT SR After the output voltage of the CLLLC resonant converter is stable, record the operating frequency f at this time s,k+1 , we get a frequency change Δf=|f s,k+1 -f s,k |;

[0087] Step 4: If Δf ≥ AΔf ref , let T SR,k+1 =T SR,k -ΔT SR , Determine the ideal synchronous rectification signal hysteresis time in over-resonance state And the conduction time is T SR,k+1 , end, if Δf<AΔf ref , then update Δf ref The value of is Δf, k=k+1, go to step 3, in this example A=1.5, ΔT SR The change amount changes in 1% steps; at the same time, the time interval between two disturbances meets the time required for the output voltage to adjust to the reference value. In order to allow the output to have enough time to stabilize after the disturbance is added, the time of each superimposed disturbance is set to 1ms.

[0088] According to the constructed model, the optimization process of the synchronous rectification drive signal is as follows: Fig.13 The adjusted experimental results are shown in Fig.14 shown.

[0089] Although the present invention is described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the present invention. It should therefore be understood that many modifications may be made to the exemplary embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that the various dependent claims and features described herein may be combined in a manner different from that described in the original claims. It should also be understood that features described in conjunction with individual embodiments may be used in other described embodiments.

Claims

1. An adaptive synchronous rectification control method for a CLLLC resonant converter, characterized in that: include: The output voltage V of the CLLLC resonant converter o Perform real-time acquisition and output the real-time acquired output voltage output signal V o With a given voltage V ref Comparison is performed, and the compared error signal is sent to the loop controller to stabilize the output voltage of the CLLLC resonant converter; When the output voltage of the CLLLC resonant converter is stable and the CLLLC resonant converter operates in the under-resonance mode, the synchronous rectification optimization is performed: S1, giving the converter the initial synchronous rectification signal conduction time T SR,k-1 After the output voltage of the CLLLC resonant converter is stable, record the operating frequency f at this time s,k-1 ;The initial value of k is 1; S2, giving the converter a fixed disturbance ΔT on the synchronous rectification signal SR , let the synchronous rectification signal conduction time T SR,k =T SR,k-1 +ΔT SR After the output voltage of the CLLLC resonant converter is stable, the operating frequency at this time is recorded as f s,k , and obtain a reference value of frequency change Δf ref =|f s,k -f s,k-1 |; The time interval between two disturbances satisfies the time required for the output voltage to adjust to the reference value; S3, giving the converter synchronous rectification signal a fixed disturbance ΔT SR , let the conduction time of the synchronous rectification signal be T SR,k+1 =T SR,k +ΔT SR After the output voltage of the CLLLC resonant converter is stable, record the operating frequency f at this time s,k+1 , we get a frequency change Δf=|f s,k+1 -f s,k |; S4. If Δf≥AΔf ref , let T SR,k+1 =T SR,k -ΔT SR , the on-time of the ideal synchronous rectification in under-resonance mode is determined to be T SR,k+1 , end, if Δf<AΔf ref , then update Δf ref The value is Δf, k=k+1, go to S3, A is 1.

5.

2. The adaptive synchronous rectification control method for CLLLC resonant converter according to claim 1, characterized in that: T SR,0 =0.48T r1 , T r1 is the resonance period.

3. The adaptive synchronous rectification control method for CLLLC resonant converter according to claim 1, characterized in that: ΔT SR =0.01T r1 。 4. The adaptive synchronous rectification control method for CLLLC resonant converter according to claim 1, characterized in that: The time interval between two disturbances is 1ms.

5. An adaptive synchronous rectification control method for a CLLLC resonant converter, characterized in that: include: The output voltage V of the CLLLC resonant converter o Perform real-time acquisition and output the real-time acquired output voltage output signal V o With a given voltage V ref Comparison is performed, and the compared error signal is sent to the loop controller to stabilize the output voltage of the CLLLC resonant converter; When the output voltage of the CLLLC resonant converter is stable and the CLLLC resonant converter operates in over-resonance mode, synchronous rectification optimization is performed: S1, synchronous rectification signal lag time of converter After that, the initial synchronous rectification signal conduction time T SR,k-1 After the output voltage of the CLLLC resonant converter is stable, record the operating frequency f at this time s,k-1 ;The initial value of k is 1; Satisfy the maximum hysteresis time of the converter under all working conditions; S2, synchronous rectification signal hysteresis time After that, a fixed disturbance ΔT is given to the synchronous rectification signal of the converter. SR , let the synchronous rectification signal conduction time T SR,k =T SR,k-1 +ΔT SR After the output voltage of the CLLLC resonant converter is stable, the operating frequency at this time is recorded as f s,k , and obtain a reference value of frequency change Δf ref =\f s,k -f s,k-1 \; S3, synchronous rectification signal hysteresis time After that, a fixed disturbance ΔT is given to the synchronous rectification signal of the converter. SR , let the conduction time of the synchronous rectification signal be T SR,k+1 =T SR,k +ΔT SR After the output voltage of the CLLLC resonant converter is stable, record the operating frequency f at this time s,k+1 , we get a frequency change Δf=|f s,k+1 -f s,k |; The time interval between two disturbances satisfies the time required for the output voltage to adjust to the reference value; S4. If Δf≥AΔf ref , let T SR,k+1 =T SR,k -ΔT SR , Determine the ideal synchronous rectification signal hysteresis time in over-resonance state And the conduction time is T SR,k+1 , end, if Δf<AΔf ref , then update Δf ref The value is Δf, k=k+1, go to S3, A is 1.

5.

6. The adaptive synchronous rectification control method for CLLLC resonant converter according to claim 5, characterized in that: T S Represents the switching cycle.

7. The adaptive synchronous rectification control method for CLLLC resonant converter according to claim 5, characterized in that: T S Represents the switching cycle.

8. The adaptive synchronous rectification control method for CLLLC resonant converter according to claim 5, characterized in that: ΔT SR =0.01T S , T S Represents the switching cycle.

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