Multi-level inverter and pre-charge and discharge control method thereof

Abstract

The present invention discloses a multi-level inverter and a control method for pre-charging and discharging thereof. The multi-level inverter includes an inverter circuit, at least one flying capacitor branch and a charging and discharging unit; the charging and discharging unit is connected to an input power supply terminal, the inverter circuit is connected to the charging and discharging unit, and at least one flying capacitor branch is connected in series with the inverter circuit; in an abnormal stage of the multi-level inverter, the charging and discharging unit is used to select the charging and discharging branch according to the flying capacitor voltage in the flying capacitor branch, and the inverter circuit and the flying capacitor branch are used to provide a charging and discharging circuit according to the flying capacitor voltage. The phenomenon of voltage stress increase of controllable semiconductor devices can be improved, and at the same time, the voltage stability of the flying capacitor is improved through the discharge circuit of the flying capacitor, thereby improving the stability of the multi-level inverter.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of voltage conversion, and in particular to a multi-level inverter and a pre-charge and discharge control method thereof. Background Art

[0002] Before the flying capacitor type multi-level inverter operates normally, the flying capacitor needs to be pre-charged to avoid the problem of excessive voltage stress of the controllable semiconductor device at startup. In the prior art, there are few control methods for pre-charging a flying capacitor with multiple flying capacitor branches, and the flying capacitor voltage cannot be discharged when it is greater than the set voltage after the inverter fails, which reduces the stability of the flying capacitor voltage. Summary of the invention

[0003] The present invention provides a multi-level inverter and a pre-charge and discharge control method thereof, so as to improve the problem of excessive voltage stress of a controllable semiconductor device during the pre-charge process and improve the stability of the multi-level inverter.

[0004] In a first aspect, an embodiment of the present invention provides a multi-level inverter, comprising an inverter circuit, at least one flying capacitor branch and a charge-discharge unit;

[0005] The charge and discharge unit is connected to the input power supply end, the inverter circuit is connected to the charge and discharge unit, and at least one of the flying capacitor branches is connected in series with the inverter circuit; in the abnormal stage of the multi-level inverter, the charge and discharge unit is used to select the charge and discharge branch according to the flying capacitor voltage in the flying capacitor branch, and the inverter circuit and the flying capacitor branch are used to provide a charge and discharge circuit according to the flying capacitor voltage.

[0006] In a second aspect, an embodiment of the present invention further provides a method for controlling pre-charging and discharging of a multi-level inverter, which is performed by the multi-level inverter according to the first aspect, and the method includes:

[0007] Obtaining a flying capacitor voltage in a flying capacitor branch;

[0008] When the flying capacitor voltage is greater than a preset capacitor voltage, the charging and discharging unit is controlled to select a discharge branch, and the inverter circuit and the flying capacitor branch provide a discharge circuit;

[0009] When the flying capacitor voltage is less than or equal to a preset capacitor voltage, the charging and discharging unit is controlled to switch on the charging branch, and the inverter circuit and the flying capacitor branch provide a charging loop.

[0010] The technical solution of the embodiment of the present invention is to set a charge-discharge unit connected between the input power supply end and the inverter circuit. In the abnormal stage of the multi-level inverter, the charge-discharge unit can select the charge-discharge branch according to the flying capacitor voltage in the flying capacitor branch. When the flying capacitor voltage in the flying capacitor branch is less than the preset capacitor voltage, the charge-discharge unit can be controlled to select the charging branch, and the inverter circuit provides a charging circuit, so that the input power supply end charges the flying capacitor of at least one flying capacitor branch through the charging branch of the charge-discharge unit and the charging circuit provided by the inverter circuit. At the same time, the charge-discharge unit can disconnect the connection relationship between the input power supply end and the controllable semiconductor device in the inverter circuit, so that the voltage stress increase phenomenon of the controllable semiconductor device can be improved during the charging process of the multi-level inverter, and the life of the controllable semiconductor device is increased, thereby increasing the life of the multi-level inverter. When the flying capacitor voltage in the flying capacitor branch is greater than the preset capacitor voltage, the charging and discharging unit can be controlled to select the discharge branch, and the inverter circuit provides a discharge loop at the same time, so that the flying capacitor in the flying capacitor branch is discharged through the inverter circuit and the discharge branch, so that the flying capacitor voltage drops to the preset capacitor voltage, avoiding the flying capacitor voltage exceeding the system safety voltage level, improving the voltage stability of the flying capacitor, and thus improving the stability of the multi-level inverter. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A schematic diagram of the structure of a multi-level inverter provided by an embodiment of the present invention;

[0012] Figure 2 A schematic diagram of the structure of another multi-level inverter provided by an embodiment of the present invention;

[0013] Figure 3 A schematic diagram of an equivalent structure of a charging circuit of a multi-level inverter provided in an embodiment of the present invention;

[0014] Figure 4 for Figure 3 A state diagram of a charging current of a multi-level inverter in a charging stage is provided;

[0015] Figure 5 for Figure 3 Another schematic diagram of the state of charging current of a multi-level inverter in the charging stage is provided;

[0016] Figure 6 for Figure 3 A state diagram of a discharge current of a multi-level inverter in a discharge phase is provided;

[0017] Figure 7 for Figure 3 Another state diagram of the discharge current of a multi-level inverter in the discharge phase is provided;

[0018] Figure 8 A schematic diagram of the structure of another multi-level inverter provided by an embodiment of the present invention;

[0019] Fig. 9 A schematic diagram of an equivalent structure of a charging circuit of another multi-level inverter provided in an embodiment of the present invention;

[0020] Fig.10 for Fig. 9 A state diagram of a charging current of a multi-level inverter in a charging phase is provided;

[0021] Fig.11 for Fig. 9 Another schematic diagram of the state of charging current of a multi-level inverter in the charging stage is provided;

[0022] Fig.12 for Fig. 9 A schematic diagram of a simulation curve of charging of a flying capacitor in a multi-level inverter is provided;

[0023] Fig.13 for Fig. 9 A state diagram of a discharge current of a multi-level inverter in a discharge phase is provided;

[0024] Fig.14 for Fig. 9 Another state diagram of the discharge current of a multi-level inverter in the discharge phase is provided;

[0025] Fig.15 for Fig. 9 A schematic diagram of a simulation curve of a flying capacitor discharge in a multi-level inverter is provided;

[0026] Fig.16 for Fig. 9 Provided is a schematic diagram of an equivalent circuit of a flying capacitor of a multi-level inverter during a charging process;

[0027] Fig.17 for Figure 3 Provided is a schematic diagram of an equivalent circuit of a flying capacitor of a multi-level inverter during a charging process;

[0028] Fig.18 for Fig.16 A schematic diagram of voltage variation of bus capacitors before and after the flying capacitor charging process of a multi-level inverter is provided;

[0029] Fig.19 A schematic diagram of a flow chart of charging and discharging interruption of a flying capacitor provided by an embodiment of the present invention;

[0030] Fig. 20 for Fig. 9A schematic diagram of voltage variation of a bus capacitor when a flying capacitor of a multi-level inverter is interrupted multiple times during charging is provided;

[0031] Fig.21 for Fig. 9 Another schematic diagram of a simulation curve of flying capacitor charging in a multi-level inverter is provided;

[0032] Fig. 22 for Fig. 9 A schematic diagram of a simulation curve of flying capacitor discharge in another multi-level inverter is provided;

[0033] Fig.23 A schematic flow chart of a method for controlling pre-charging and discharging of a multi-level inverter provided in an embodiment of the present invention;

[0034] Fig.24 for Fig. 9 A schematic flow chart of another method for controlling pre-charging and discharging of a multi-level inverter is provided. DETAILED DESCRIPTION

[0035] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0036] Figure 1 A schematic diagram of the structure of a multi-level inverter provided by an embodiment of the present invention. Figure 1 As shown, the multi-level inverter includes an inverter circuit 110, at least one flying capacitor branch 120 and a charge and discharge unit 130; the charge and discharge unit 130 is connected to the input power supply terminal, the inverter circuit 110 is connected to the charge and discharge unit 130, and at least one flying capacitor branch 120 is connected in series with the inverter circuit 110; in an abnormal stage of the multi-level inverter, the charge and discharge unit 130 is used to select the charge and discharge branch according to the flying capacitor voltage in the flying capacitor branch 120, and the inverter circuit 110 and the flying capacitor branch 120 are used to provide a charge and discharge loop according to the flying capacitor voltage.

[0037] Specifically, the input power supply end is used to provide direct current. The charge and discharge unit 130 has a normal working branch and a charge and discharge branch. During the normal working process of the multi-level inverter, the charge and discharge unit 130 can connect the input power supply end and the inverter circuit 110 through the normal working branch, and the flying capacitor branch 120 is connected in series with the inverter circuit 110, so that the multi-level inverter can perform multi-level inverter conversion through the inverter circuit 110 and the flying capacitor branch 120. In the abnormal stage of the multi-level inverter, the charge and discharge unit 130 can select the charge and discharge branch, and the inverter circuit 110 can provide a charge and discharge loop, so that the input power supply end charges and discharges the flying capacitor in the flying capacitor branch 120 through the charge and discharge branch. When the multi-level inverter includes a plurality of flying capacitor branches 120, the plurality of flying capacitor branches 120 are connected in series with the inverter circuit 110 in sequence. When the charge-discharge unit 130 and the inverter circuit 110 provide a charge-discharge circuit for the flying capacitor branch 120, a charge-discharge circuit can be provided for multiple flying capacitor branches 120 at the same time, so that multiple flying capacitor branches 120 can be charged and discharged, which increases the use range of the multi-level inverter. Among them, the abnormal stage of the multi-level inverter can include a startup stage before the normal operation of the multi-level inverter, and the flying capacitor voltage in the flying capacitor branch 120 is less than the preset capacitor voltage. At this time, the charge-discharge unit 130 can be controlled to select the charging branch, and the inverter circuit 110 provides a charging circuit, so that the input power supply end charges the flying capacitor of the flying capacitor branch 120 through the charging branch of the charge-discharge unit 130 and the charging circuit provided by the inverter circuit 110. At the same time, the charge-discharge unit 130 can disconnect the connection relationship between the input power supply end and the controllable semiconductor device in the inverter circuit 110, so that the voltage stress of the controllable semiconductor device can be improved during the charging process of the multi-level inverter, and the life of the controllable semiconductor device is improved, thereby improving the life of the multi-level inverter. Moreover, the abnormal stage of the multi-level inverter can also include a stage in which the multi-level inverter is repeatedly powered on or powered on again in a short time after a fault, and the flying capacitor voltage in the flying capacitor branch 120 is greater than the preset capacitor voltage. At this time, the charging and discharging unit 130 can be controlled to select the discharge branch, and the inverter circuit 110 provides a discharge circuit, so that the flying capacitor in the flying capacitor branch 120 is discharged through the inverter circuit 110 and the discharge branch, so that the flying capacitor voltage drops to the preset capacitor voltage, avoiding the flying capacitor voltage exceeding the system safety voltage level, improving the voltage stability of the flying capacitor, and thus improving the stability of the multi-level inverter. Moreover, the multi-level inverter has a charging and discharging circuit of the flying capacitor at the same time, which can realize the voltage stability of the flying capacitor voltage in multi-modes, and ensure the safety and stability of the flying capacitor voltage in different working modes.

[0038] The technical solution of this embodiment is to set a charge-discharge unit connected between the input power supply end and the inverter circuit. In the abnormal stage of the multi-level inverter, the charge-discharge unit can select the charge-discharge branch according to the flying capacitor voltage in the flying capacitor branch. When the flying capacitor voltage in the flying capacitor branch is less than the preset capacitor voltage, the charge-discharge unit can be controlled to select the charging branch, and the inverter circuit provides a charging circuit, so that the input power supply end charges the flying capacitor of at least one flying capacitor branch through the charging branch of the charge-discharge unit and the charging circuit provided by the inverter circuit. At the same time, the charge-discharge unit can disconnect the connection relationship between the input power supply end and the controllable semiconductor device in the inverter circuit, so that the voltage stress increase phenomenon of the controllable semiconductor device can be improved during the charging process of the multi-level inverter, and the life of the controllable semiconductor device is increased, thereby increasing the life of the multi-level inverter. When the flying capacitor voltage in the flying capacitor branch is greater than the preset capacitor voltage, the charging and discharging unit can be controlled to select the discharge branch, and the inverter circuit provides a discharge loop at the same time, so that the flying capacitor in the flying capacitor branch is discharged through the inverter circuit and the discharge branch, so that the flying capacitor voltage drops to the preset capacitor voltage, avoiding the flying capacitor voltage exceeding the system safety voltage level, improving the voltage stability of the flying capacitor, and thus improving the stability of the multi-level inverter.

[0039] Figure 2 FIG. 1 is a schematic diagram of another structure of a multi-level inverter provided by an embodiment of the present invention. Figure 2 As shown, the charge and discharge unit 130 includes a first gating module 131 and a second gating module 132, the inverter circuit 110 includes a first half-bridge 111 and a second half-bridge 112, the first end of the first gating module 131 is connected to the first input power supply terminal V+, the second end of the first gating module 131 is connected to the first end of the first half-bridge 111, the second end of the first half-bridge 111, the third end of the first gating module 131 and the first end of the second half-bridge 112 are connected to the neutral input power supply terminal V0; the second gating module 132 includes a normal working branch 1321 and a charging branch 1322, the second end of the second half-bridge 112 is connected to the second end of the normal working branch 1321 and the charging branch 1322 The first end of the normal working branch 1321 and the charging branch 1322 are connected to the second input power supply terminal V-; the third end of the first half bridge 111 is connected to the first end of the flying capacitor branch 120, and the third end of the second half bridge 112 is connected to the second end of the flying capacitor branch 120, and at least one flying capacitor branch 120 is connected in series; the first gating module 131 is used to select the first end and the second end of the first gating module 131 in the normal stage of the multi-level inverter, and to select the second end and the third end in the discharge stage of the abnormal stage; the second gating module 132 is used to select the normal working branch 1321 in the normal stage, and to select the charging branch 1322 in the charging stage of the abnormal stage.

[0040] Specifically, Figure 2 exemplarily shows that the multi-level inverter also includes a first bus capacitor C1 and a second bus capacitor C2. The first bus capacitor C1 is connected between the first input power terminal V+ and the neutral input power terminal V0, and the second bus capacitor C2 is connected between the second input power terminal V- and the neutral input power terminal V0, and is used to stabilize and filter the DC power provided by the input power terminal. The capacitance values ​​of the first bus capacitor C1 and the second bus capacitor C2 can be equal, so that the potential of the neutral input power terminal V0 is U dc / 2. In the normal working stage of the multi-level inverter, the first gating module 131 selects the first end and the second end, so that the first input power supply terminal V+ is connected to the first end of the first half bridge 111, and the second gating module 132 selects the normal working branch 1321, so that the second input power supply terminal V- is connected to the second end of the second half bridge 112, and at the same time, the second end of the first half bridge 111 and the first end of the second half bridge 112 are connected to the neutral input power supply terminal V0, so that the multi-level inverter conversion can be realized through the inverter circuit 110 and the flying capacitor branch 120.

[0041] In the abnormal stage of the multi-level inverter, when the flying capacitor voltage is less than the preset capacitor voltage, the first gating module 131 simultaneously turns off the first end and the second end, as well as the second end and the third end, and the first gating module 131 does not provide a current loop. At the same time, the second gating module 132 selects the charging branch 1322, the first half bridge 111 selects the second end and the third end, and the second half bridge 112 selects the second end and the third end. The second input power supply terminal V- and the neutral input power supply terminal V0 provide a discharge loop through the charging branch 1322, the first half bridge 111 and the second half bridge 112, so as to charge the flying capacitor on the flying capacitor branch 120. When the flying capacitor voltage is greater than the preset capacitor voltage, the first selection module 131 selects the second end and the third end, the second selection module 132 disconnects the normal working branch 1321 and the charging branch 1322, and at the same time, the first half bridge 111 selects the first end and the third end, and the second half bridge 112 selects the first end and the third end, so that the flying capacitor voltage on the flying capacitor branch 120 is discharged in sequence through the third end and the second end of the first half bridge 111, the second end and the third end of the first selection module 131, and the second end and the third end of the second half bridge 112, so that the flying capacitor voltage drops to the preset capacitor voltage, thereby improving the voltage stability of the flying capacitor and thus improving the stability of the multi-level inverter.

[0042] Continue to refer Figure 2 The first gating module 131 includes a first switch device K1, a second switch device K2 and a first pre-charging resistor R DC1 The first end of the first switch device K1 is used as the first end of the first gating module 131, and the second end of the first switch device K1 is connected to the first pre-charging resistor RDC1 The first end of the first pre-charging resistor R DC1 The second end of is connected to the second end of the second switch device K2, and the first end of the second switch device K2 serves as the third end of the first gating module 131.

[0043] Specifically, the first switch device K1 and the second switch device K2 may be normally open contacts or normally closed contacts of a relay. DC1 It is connected in series to the discharge branch of the first gating module 131 to limit the discharge current. In the normal working stage of the multi-level inverter, the first switch device K1 can be controlled to be in a closed state and the second switch device K2 can be controlled to be in an open state, so that the first input power supply terminal V+ is connected to the first end of the first half-bridge 111. In the abnormal stage of the multi-level inverter, when the flying capacitor voltage is less than the preset capacitor voltage, the first switch device K1 can be controlled to be in an open state and the second switch device K2 can be controlled to be in an open state. At this time, a discharge circuit is provided for the flying capacitor branch 120 through the second gating module 132. When the flying capacitor voltage is greater than the preset capacitor voltage, the first switch device K1 can be controlled to be in an open state and the second switch device K2 can be controlled to be in a closed state, so that the flying capacitor voltage on the flying capacitor branch 120 passes through the third end and the second end of the first half-bridge 111, the second switch device K2 and the first pre-charging resistor R DC1 , and the second end and the third end of the second half bridge 112 are discharged.

[0044] Continue to refer Figure 2 The normal working branch 1321 includes a third switch device K3, and the charging branch 1322 includes a fourth switch device K4 and a second pre-charging resistor R DC2 The first end of the third switch device K3 serves as the first end of the normal working branch 1321, and the second end of the third switch device K3 serves as the second end of the normal working branch 1321; the first end of the fourth switch device K4 serves as the first end of the charging branch 1322, and the second end of the fourth switch device K4 is connected to the second pre-charging resistor R DC2 The first end is connected to the second pre-charge resistor R DC2 The second end of is used as the second end of the charging branch 1322.

[0045] Specifically, Figure 2 As shown, the normal working branch 1321 and the charging branch 1322 are connected in parallel between the second input power source V- and the second end of the second half bridge 112. The third switch device K3 and the fourth switch device K4 can be normally open contacts or normally closed contacts of a relay. The second pre-charging resistor R DC2It is connected in series to the charging branch 1322 of the second gating module 132, and is used to limit the charging current. In the normal working stage of the multi-level inverter, the third switch device K3 can be controlled to be in a closed state, and the fourth switch device K4 can be in an open state, so that the second input power terminal V- is connected to the second end of the second half-bridge 112. In the abnormal stage of the multi-level inverter, when the flying capacitor voltage is less than the preset capacitor voltage, the third switch device K3 can be controlled to be in an open state, and the fourth switch device K4 can be in a closed state, at this time, the second input power terminal V- and the neutral input power terminal V0 are connected through the fourth switch device K4 and the second pre-charging resistor R DC2 , the second end and the third end of the first half bridge 111, and the second end and the third end of the second half bridge 112 charge the flying capacitor on the flying capacitor branch 120. When the flying capacitor voltage is greater than the preset capacitor voltage, the third switch device K3 is in an open state, and the fourth switch device K4 is in an open state. At the same time, the first switch device K1 is in an open state, and the second switch device K2 is in a closed state, so that the flying capacitor voltage on the flying capacitor branch 120 passes through the third end and the second end of the first half bridge 111, the second switch device K2 and the first pre-charging resistor R in sequence. DC1 , and the second end and the third end of the second half bridge 112 are discharged.

[0046] Continue to refer Figure 2 , the first half bridge 111 comprises a first transistor S x1 , a first diode D1, a second transistor S x2 and a second diode D2. The second half bridge 112 includes a third transistor S x3 , a third diode D3, a fourth transistor S x4 and a fourth diode D4; a first transistor S x1 The first electrode of the first diode D1 is connected to the cathode of the first diode D1 and serves as the first end of the first half bridge 111. The first transistor S x1 The second electrode of the first diode D1, the anode of the second transistor S x2 The first electrode of the second diode D2 is connected to the cathode of the second diode D2 and serves as the third end of the first half bridge 111. The second transistor S x2 The second electrode of the third transistor S is connected to the anode of the second diode D2 and serves as the second end of the first half bridge 111; x3 The first electrode of the third transistor S is connected to the cathode of the third diode D3 and serves as the first end of the second half bridge 112. x3 The second electrode of the third diode D3, the anode of the fourth transistor S x4 The first electrode of the fourth transistor S is connected to the cathode of the fourth diode D4 and serves as the third end of the second half bridge 112. x4The second electrode of is connected to the anode of the fourth diode D4 and serves as the second end of the second half bridge 112.

[0047] Specific, exemplary, such as Figure 2 As shown, the first transistor S x1 and the second transistor S x2 The third transistor S is turned on in time. x3 and the fourth transistor S x4 Time-sharing conduction. In the abnormal stage of the multi-level inverter, when the flying capacitor voltage is less than the preset capacitor voltage, the first switch device K1 is in the open state, the second switch device K2 is in the open state, the third switch device K3 is in the open state, and the fourth switch device K4 is in the closed state. At the same time, the second transistor S x2 and the fourth transistor S x4 The first transistor S is turned on. x1 and the third transistor S x3 At this time, the current provided by the neutral input power supply terminal V0 passes through the second transistor S x2 , flying capacitor branch 120, fourth transistor S x4 and the fourth switch device K4 to the second input power supply terminal V-, forming a charging loop. When the flying capacitor voltage is greater than the preset capacitor voltage, the first switch device K1 is in an open state, the second switch device K2 is in a closed state, the third switch device K3 is in an open state, and the fourth switch device K4 is in an open state. At the same time, the second transistor S x2 and the fourth transistor S x4 Turn off, the first transistor S x1 and the third transistor S x3 At this time, the flying capacitor voltage of the flying capacitor branch 120 is turned on through the first transistor S x1 , the second switch device K2, the first pre-charging resistor R DC1 and the third transistor S x3 Discharge to form a discharge circuit.

[0048] Continue to refer Figure 2 The flying capacitor branch 120 includes a fifth transistor S x5 , the fifth diode D5, the sixth transistor S x6 , the sixth diode D6 and the flying capacitor C fx ; The fifth transistor S x5 The first electrode of the fifth transistor S is connected to the cathode of the fifth diode D5 and serves as the first end of the flying capacitor branch 120. x5 The second electrode and the anode of the fifth diode D5 are connected to the flying capacitor C fx The first electrode is connected to the flying capacitor C fx The second electrode and the sixth transistor S x6The first electrode of the sixth transistor S is connected to the cathode of the sixth diode D6. x6 The second electrode of is connected to the anode of the sixth diode D6 and serves as the second end of the flying capacitor branch 120.

[0049] Specifically, the multi-level inverter further includes an output half-bridge connected in series to a side of the flying capacitor branch 120 away from the inverter circuit 110. Figure 2 As shown, the output half bridge includes a seventh transistor S x7 , the seventh diode D7, the eighth transistor S x8 and the eighth diode D8. The seventh transistor S x7 After the first electrode of the seventh transistor S is connected to the cathode of the seventh diode D7, it is connected to the first end of the last flying capacitor branch 120. x7 After the second electrode of the seventh diode D7 is connected to the anode of the eighth transistor S x8 The first electrode of the eighth transistor S is connected to the cathode of the eighth diode D8 as the output terminal VOUT of the multi-level inverter. x8 After the second electrode of is connected to the anode of the eighth diode D8 , it is connected to the second end of the last flying capacitor branch 120 . Figure 2 exemplarily shows that the multi-level inverter includes a flying capacitor branch 120. In this case, the inverter circuit 110, the flying capacitor branch 120 and the output half bridge are combined to form a five-level inverter. fx The preset capacitor voltage can be U dc / 4. Among them, U dc is the voltage between the first input power supply terminal V+ and the second input power supply terminal V-. fx The voltage of the first switch device K1 to the fourth switch device K4 and the first transistor S x1 To the sixth transistor S x6 The switching state of the flying capacitor C fx Charge and discharge control.

[0050] For example, Figure 3 The equivalent structure diagram of a charging circuit of a multi-level inverter provided by an embodiment of the present invention is shown in FIG. Figure 3 As shown, the multi-level inverter includes two flying capacitor branches 120. In this case, the multi-level inverter is a seven-level inverter. The flying capacitor C in the flying capacitor branch 120 directly connected to the inverter circuit 110 is fx is the first flying capacitor C fx1 , the flying capacitor C in the other flying capacitor branch 120 fx is the second flying capacitor C fx2 The first flying capacitor Cfx1 The corresponding preset capacitor voltage can be U dc / 4, the second flying capacitor C fx2 The corresponding preset capacitor voltage can be U dc / 8. Figure 4 for Figure 3 A schematic diagram of the charging current state of a multi-level inverter in the charging stage is provided. Figure 4 As shown, at the start of the seven-level inverter, the flying capacitor C fx The voltage on the first switch device K1 is 0, and the second switch device K2 is in an open state, the third switch device K3 is in an open state, and the fourth switch device K4 is in a closed state. x2 and the fourth transistor S x4 The first transistor S is turned on. x1 and the third transistor S x3 At this time, the fifth transistor S on the two flying capacitor branches 120 can be controlled x5 and the sixth transistor S x6 are both turned on, so that the current provided by the neutral input power supply terminal V0 passes through the second transistor S x2 , two flying capacitor branches 120, a fourth transistor S x4 and the fourth switch device K4 to the second input power supply terminal V-, forming a charging loop. Thus, the two flying capacitors C fx Charging at the same time. Figure 5 for Figure 3 Another schematic diagram of the charging current state of a multi-level inverter in the charging stage is provided. Figure 5 As shown, when the second flying capacitor C fx2 Charge to the corresponding preset capacitor voltage, i.e. U dc / 8, the fifth transistor S in the second flying capacitor branch 120 is controlled x5 and the sixth transistor S x6 The current provided by the neutral input power supply terminal V0 passes through the second transistor S x2 , the first flying capacitor branch 120, the fourth transistor S x4 and the fourth switch device K4 to the second input power supply terminal V-, forming a charging loop. fx1 Charge to the corresponding preset capacitor voltage, i.e. U dc / 4. Then all transistors in the inverter circuit 110 and the flying capacitor branch 120 are turned off simultaneously, completing the flying capacitor C of the multi-level inverter. fx pre-charge process.

[0051] Figure 6 for Figure 3A state diagram of the discharge current of a multi-level inverter in the discharge phase is provided. Figure 6 As shown, during the stage of repeated power-on or power-on again in a short time after a multi-level fault, the first flying capacitor C fx1 The voltage on the capacitor is greater than the corresponding preset capacitor voltage, that is, U dc / 4, the second flying capacitor C fx2 The voltage on the capacitor is greater than the corresponding preset capacitor voltage, that is, U dc / 8, the first switch device K1 is controlled to be in an open state, the second switch device K2 is controlled to be in a closed state, the third switch device K3 is controlled to be in an open state, and the fourth switch device K4 is controlled to be in an open state. x2 and the fourth transistor S x4 Turn off, the first transistor S x1 and the third transistor S x3 At the same time, the fifth transistor S in the first flying capacitor branch 120 is turned on. x5 and the sixth transistor S x6 The fifth transistor S in the second flying capacitor branch 120 is turned on. x5 and the sixth transistor S x6 Turn off, at this time the first flying capacitor C fx1 Through the first transistor S x1 , the second switch device K2, the first pre-charging resistor R DC1 and the third transistor S x3 Discharge. Figure 7 for Figure 3 Another state diagram of the discharge current of a multi-level inverter in the discharge phase is provided. Figure 7 As shown, when the first flying capacitor C fx1 Discharge to the second flying capacitor C fx2 When the voltage is greater than 100, the fifth transistor S in the second flying capacitor branch 120 is controlled. x5 and the sixth transistor S x6 The second flying capacitor C fx2 By passing through the fifth transistor S in the first flying capacitor branch 120 x5 and the sixth transistor S x6 , and the first transistor S x1 , the second switch device K2, the first pre-charging resistor R DC1 and the third transistor S x3 Discharge until the second flying capacitor C fx2 Discharge to the corresponding preset capacitor voltage, i.e., U dc / 8. Then all transistors in the inverter circuit 110 and the flying capacitor branch 120 are turned off simultaneously, completing the flying capacitor C of the multi-level inverter. fx pre-discharge process.

[0052] In some embodiments, Figure 8 FIG. 1 is a schematic diagram of another structure of a multi-level inverter provided by an embodiment of the present invention. Figure 8 As shown, the positions of the first gating module 131 and the second gating module 132 can be changed so that the first end and the second end of the first gating module 131 are respectively connected to the second input power supply terminal V- and the second end of the second half bridge 112, and the third end of the first gating module 131 is connected to the neutral input power supply terminal V0. The second gating module 132 is connected between the first input power supply terminal V+ and the first end of the first half bridge 111. At this time, the flying capacitor C can also be controlled by controlling the states of the first gating module 131, the second gating module 132, the inverter circuit 110 and the flying capacitor branch 120. fx Charge and discharge control.

[0053] For example, Fig. 9 FIG. 1 is a schematic diagram of an equivalent structure of a charging circuit of another multi-level inverter provided in an embodiment of the present invention. Fig. 9 As shown, the multi-level inverter includes two flying capacitor branches 120. In this case, the multi-level inverter is a seven-level inverter. The flying capacitor C in the flying capacitor branch 120 directly connected to the inverter circuit 110 is fx is the first flying capacitor C fx1 , the flying capacitor C in the other flying capacitor branch 120 fx is the second flying capacitor C fx2 The first flying capacitor C fx1 The corresponding preset capacitor voltage can be U dc / 4, the second flying capacitor C fx2 The corresponding preset capacitor voltage can be U dc / 8. Fig.10 for Fig. 9 A schematic diagram of the charging current state of a multi-level inverter in the charging stage is provided. Fig.10 As shown, at the start of the seven-level inverter, the flying capacitor C fx The voltage on the first switch device K1 is 0, and the second switch device K2 is in an open state, the third switch device K3 is in an open state, and the fourth switch device K4 is in a closed state. x2 and the fourth transistor S x4 Turn off, the first transistor S x1 and the third transistor S x3 At this time, the fifth transistor S on the two flying capacitor branches 120 can be controlled x5 and the sixth transistor S x6 are all turned on, so that the current provided by the first input power supply terminal V+ passes through the fourth switch device K4 and the first pre-charging resistor R DC1, the first transistor S x1 , two flying capacitor branches 120 and a third transistor S x3 Flows to the neutral input power supply terminal V0 to form a charging loop. fx Charging at the same time. Fig.11 for Fig. 9 Another schematic diagram of the charging current state of a multi-level inverter in the charging stage is provided. Fig.11 As shown, when the second flying capacitor C fx2 Charge to the corresponding preset capacitor voltage, i.e. U dc / 8, the fifth transistor S in the second flying capacitor branch 120 is controlled x5 and the sixth transistor S x6 The first input power supply terminal V+ is turned off, so that the current provided by the first input power supply terminal V+ passes through the fourth switch device K4 and the first pre-charging resistor R DC1 , the first transistor S x1 , the first flying capacitor branch 120 and the third transistor S x3 Flows to the neutral input power supply terminal V0 to form a charging loop. fx1 Charge to the corresponding preset capacitor voltage, i.e. U dc / 4. Then all transistors in the inverter circuit 110 and the flying capacitor branch 120 are turned off simultaneously, completing the flying capacitor C of the multi-level inverter. fx pre-charge process.

[0054] For example, Fig.12 for Fig. 9 A schematic diagram of a simulation curve of flying capacitor charging in a multi-level inverter is provided. Curve 1 is a first flying capacitor C fx1 The charging voltage curve of the second flying capacitor C fx2 The charging voltage curve is shown in Figure 1. The horizontal axis is time and the vertical axis is the flying capacitor voltage. dc When the first flying capacitor C is 2000V, fx1 Can be charged to 500V, that is, U dc / 4. The second flying capacitor C fx2 Can be charged to 250V, that is, U dc / 8.

[0055] Fig.13 for Fig. 9 A state diagram of the discharge current of a multi-level inverter in the discharge phase is provided. Fig.13 As shown in the figure, during the stage of repeated power-on or power-on again in a short time after the multi-level inverter fails, the first flying capacitor C fx1 The voltage on the capacitor is greater than the corresponding preset capacitor voltage, that is, U dc / 4, the second flying capacitor C fx2 The voltage on the capacitor is greater than the corresponding preset capacitor voltage, that is, U dc / 8, the first switch device K1 is controlled to be in an open state, the second switch device K2 is controlled to be in a closed state, the third switch device K3 is controlled to be in an open state, and the fourth switch device K4 is controlled to be in an open state. x2 and the fourth transistor S x4 The first transistor S is turned on. x1 and the third transistor S x3 At the same time, the fifth transistor S in the first flying capacitor branch 120 is turned off. x5 and the sixth transistor S x6 The fifth transistor S in the second flying capacitor branch 120 is turned on. x5 and the sixth transistor S x6 Turn off, at this time the first flying capacitor C fx1 Through the second transistor S x2 , the second switch device K2, the first pre-charging resistor R DC1 and the fourth transistor S x4 Discharge. Fig.14 for Fig. 9 Another state diagram of the discharge current of a multi-level inverter in the discharge phase is provided. Fig.14 As shown, when the first flying capacitor C fx1 Discharge to the second flying capacitor C fx2 When the voltage is greater than 100, the fifth transistor S in the second flying capacitor branch 120 is controlled. x5 and the sixth transistor S x6 The second flying capacitor C fx2 By passing through the fifth transistor S in the first flying capacitor branch 120 x5 and the sixth transistor S x6 , and the second transistor S x2 , the second switch device K2, the first pre-charging resistor R DC1 and the fourth transistor S x4 Discharge until the second flying capacitor C fx2 Discharge to the corresponding preset capacitor voltage, i.e., U dc / 8. Then all transistors in the inverter circuit 110 and the flying capacitor branch 120 are turned off simultaneously, completing the flying capacitor C of the multi-level inverter. fx pre-discharge process.

[0056] For example, Fig.15 for Fig. 9 A schematic diagram of a simulation curve of a flying capacitor discharge in a multi-level inverter is provided. Curve 3 is a first flying capacitor C fx1 The discharge voltage curve of the second flying capacitor Cfx2 The discharge voltage curve is shown in Figure 1. The horizontal axis is time and the vertical axis is the flying capacitor voltage. dc The first flying capacitor C fx1 The initial voltage is 580V, and the second flying capacitor C fx2 When the initial voltage is 280V, the first flying capacitor C fx1 Discharge to 280V, and then charge the first flying capacitor C fx1 and the second flying capacitor C fx2 At the same time, discharge to the second flying capacitor C fx2 The preset capacitor voltage is 250V. Then the first flying capacitor C fx1 Charge to the corresponding preset capacitor voltage of 500V, which is U dc / 4.

[0057] Continue to refer Fig.10 and Fig.11 In the charging process of the multi-level inverter, the first switch device K1 is in the off state, and the second switch device K2 is in the off state, so that the second bus capacitor C2 and the fourth transistor S x4 The fourth transistor S is disconnected to prevent the voltage of the second bus capacitor C2 from rising during the charging process. x4 The excessive voltage stress may lead to the damage of the transistor, thereby improving the phenomenon of the voltage stress increase of the controllable semiconductor device, increasing the life of the controllable semiconductor device, and further increasing the life of the multi-level inverter.

[0058] Continue to refer Figures 1 to 12 The multi-level inverter further includes a first balancing resistor R C1 and the second balancing resistor R C2 ; The first balancing resistor R C1 Connected between the first input power terminal V+ and the neutral input power terminal V0, the second balancing resistor R C2 Connected between the second input power terminal V- and the neutral input power terminal V0.

[0059] Specifically, the first balancing resistor R C1 and the second balancing resistor R C2 The resistance values ​​of the neutral input power supply terminal V0 can be equal, so that the potential of the neutral input power supply terminal V0 is stable at U during normal operation of the multilevel inverter. dc / 2. In the flying capacitor C fx During the charging and discharging process, the voltages of the first bus capacitor C1 and the second bus capacitor C2 are not equal, causing the potential of the neutral input power supply terminal V0 to shift. At this time, the first balancing resistor R C1 and the second balancing resistor RC2 Detect the potential offset value of the neutral input power supply terminal V0. When the potential offset value exceeds the preset offset threshold range, the flying capacitor C can be interrupted. fx During the charge and discharge process, the first balancing resistor R C1 and the second balancing resistor R C2 It can automatically balance the potential of the neutral input power supply terminal V0 to U dc / 2. Then continue to start the flying capacitor C fx The charging and discharging process until the flying capacitor C fx The charge and discharge are completed, ensuring that the potential of the neutral input power supply terminal V0 will not deviate too much, and can automatically balance the potential to U after the charge and discharge are completed. dc / 2, to avoid the influence of voltage stress on transistors. For example, Fig.16 for Fig. 9 The equivalent circuit diagram of a flying capacitor of a multi-level inverter during the charging process is provided. Fig.17 for Figure 3 The equivalent circuit diagram of a flying capacitor of a multi-level inverter during the charging process is provided. Fig.16 As shown, the flying capacitor C fx In the charging circuit, the voltage of the first bus capacitor C1 decreases, and the potential of the neutral input power supply terminal V0 is increased. Fig.17 As shown, the flying capacitor C fx In the charging circuit, the second bus capacitance C2 is reduced, and the potential of the neutral input power supply terminal V0 is reduced. At this time, the flying capacitor C fx During the charge and discharge process, the first balancing resistor R C1 and the second balancing resistor R C2 It can automatically balance the potential of the neutral input power supply terminal V0 to U dc / 2. Fig.18 for Fig.16 A schematic diagram of the voltage change of the bus capacitor before and after the flying capacitor charging process of a multi-level inverter is provided. The horizontal axis is time, the vertical axis is the potential of the neutral input power supply end, curve 5 is the voltage change curve of the first bus capacitor C1, and curve 6 is the voltage change curve of the second bus capacitor C2. Fig.18 As shown, in the charging stage of the flying capacitor (before the dotted line), the potential offset value of the neutral input power supply terminal V0 can be continuously charged when it is within the preset offset threshold range, the voltage of the first bus capacitor C1 decreases, and the voltage of the second bus capacitor C2 increases. After the charging stage of the flying capacitor ends (after the dotted line), the voltages of the first bus capacitor C1 and the second bus capacitor C2 automatically balance to U dc / 2.

[0060] In some embodiments, during the charging process, when the potential offset value of the neutral input power supply terminal V0 exceeds the preset offset threshold range, it is necessary to interrupt the flying capacitor C fx During the charge and discharge process, the first balancing resistor R C1 and the second balancing resistor R C2 It can automatically balance the potential of the neutral input power supply terminal V0 to U dc / 2. Then continue to start the flying capacitor C fx The charging and discharging process until the flying capacitor C fx The charge and discharge are completed. Fig.19 A schematic diagram of a process flow of interrupting the charging and discharging of a flying capacitor provided by an embodiment of the present invention. Fig.19 As shown, when the voltage U of the first bus capacitor C1 dc1 The voltage U of the second bus capacitor C2 dc2 The absolute value of the difference is greater than the maximum preset offset threshold ΔU within the preset offset threshold range. dcmax When the voltage U dc1 The voltage U of the second bus capacitor C2 dc2 The absolute value of the difference is less than or equal to the maximum preset offset threshold ΔU dcmax When the voltage U of the first bus capacitor C1 is determined dc1 The voltage U of the second bus capacitor C2 dc2 Is the absolute value of the difference less than the minimum preset offset threshold ΔU within the preset offset threshold range? dcmin When the voltage U of the first bus capacitor C1 dc1 The voltage U of the second bus capacitor C2 dc2 The absolute value of the difference is less than the minimum preset offset threshold ΔU within the preset offset threshold range. dcmin When the interruption program ends, the flying capacitor C fx The charging and discharging process. When the voltage U dc1 The voltage U of the second bus capacitor C2 dc2 The absolute value of the difference is not less than the minimum preset offset threshold ΔU within the preset offset threshold range. dcmin When all transistors are turned off, the voltage U of the first bus capacitor C1 is determined. dc1 The voltage U of the second bus capacitor C2 dc2 Is the absolute value of the difference less than the minimum preset offset threshold ΔU within the preset offset threshold range? dcmin , until the interrupt program ends.

[0061] Fig. 20 for Fig. 9A schematic diagram of voltage variation of bus capacitors when a flying capacitor of a multi-level inverter is interrupted multiple times during charging is provided, wherein the abscissa is time, the ordinate is the potential of the neutral input power supply terminal, curve 7 is the voltage variation curve of the first bus capacitor C1, and curve 8 is the voltage variation curve of the second bus capacitor C2. Fig.21 for Fig. 9 Another schematic diagram of a simulation curve of flying capacitor charging in a multi-level inverter is provided. Curve 9 is a first flying capacitor C fx1 The charging voltage curve of the second flying capacitor C fx2 The charging voltage curve is shown in Figure 1, where the horizontal axis is time and the vertical axis is the flying capacitor voltage. During the charging process, the voltage of the first bus capacitor C1 decreases and the voltage of the second bus capacitor C2 increases. When the potential offset value of the neutral input power supply terminal V0 exceeds the preset offset threshold range, the flying capacitor C is interrupted. fx The charging process is to turn off all transistors so that the potential of the neutral input power supply terminal V0 automatically balances to the value U dc / 2. Then return to the node to continue flying capacitor C fx Charging, repeat the above process until the flying capacitor C fx When charging is finished, all transistors are turned off, and the potential of the neutral input power supply terminal V0 automatically balances to the value U dc / 2.

[0062] It should be noted that the flying capacitor C fx During the discharge process, when the potential offset value of the neutral input power supply terminal V0 exceeds the preset offset threshold range, the flying capacitor C can also be interrupted. fx The discharge process. For example, Fig. 22 for Fig. 9 Another schematic diagram of a simulation curve of the discharge of a flying capacitor in a multi-level inverter is provided. Curve 11 is a curve of the discharge of the first flying capacitor C fx1 The discharge voltage curve of the second flying capacitor C fx2 The discharge voltage curve is shown in Figure 1, where the horizontal axis is time and the vertical axis is the flying capacitor voltage. During the discharge process, the voltage of the first bus capacitor C1 increases and the voltage of the second bus capacitor C2 decreases. When the potential offset value of the neutral input power supply terminal V0 is greater than the preset offset threshold, the flying capacitor C is interrupted. fx The discharge process, that is, turning off all transistors, makes the potential of the neutral input power supply terminal V0 automatically balance the value U dc / 2. Then return to the node to continue flying capacitor C fx Discharge, repeat the above process until the flying capacitor C fx At the end of discharge, all transistors are turned off, and the potential of the neutral input power supply terminal V0 automatically balances to the value U dc / 2.

[0063] An embodiment of the present invention further provides a method for controlling pre-charging and discharging of a multi-level inverter, which is executed by the multi-level inverter provided by any embodiment of the present invention. Fig.23 The present invention provides a flow chart of a method for controlling pre-charging and discharging of a multi-level inverter. Fig.23 As shown, the method includes:

[0064] S110, obtaining a flying capacitor voltage in a flying capacitor branch;

[0065] S120, when the flying capacitor voltage is greater than the preset capacitor voltage, controlling the charge and discharge unit to select the discharge branch, and the inverter circuit and the flying capacitor branch provide a discharge loop;

[0066] S130, when the flying capacitor voltage is less than or equal to the preset capacitor voltage, the charging and discharging unit is controlled to select the charging branch, and the inverter circuit and the flying capacitor branch provide a charging circuit.

[0067] The technical solution of this embodiment, by obtaining the flying capacitor voltage in the flying capacitor branch, when the flying capacitor voltage is greater than the preset capacitor voltage, the charging and discharging unit can be controlled to select the discharge branch, and the inverter circuit provides a discharge circuit, so that the flying capacitor in the flying capacitor branch is discharged through the inverter circuit and the discharge branch, so that the flying capacitor voltage drops to the preset capacitor voltage, and the voltage stability of the flying capacitor is improved, thereby improving the stability of the multi-level inverter. When the flying capacitor voltage is less than or equal to the preset capacitor voltage, the charging branch can be controlled to select the charging branch, and the inverter circuit provides a charging circuit, so that the input power supply end charges the flying capacitor of at least one flying capacitor branch through the charging branch of the charging and discharging unit and the charging circuit provided by the inverter circuit. At the same time, the charging and discharging unit can disconnect the connection relationship between the input power supply end and the controllable semiconductor device in the inverter circuit, so that the phenomenon of voltage stress increase of the controllable semiconductor device can be improved during the charging process of the multi-level inverter, and the life of the controllable semiconductor device is improved, thereby improving the life of the multi-level inverter.

[0068] In some embodiments, the multilevel inverter includes n flying capacitor branches, which are sequentially connected in series and then connected in series with the inverter circuit; the flying capacitor branch directly connected to the inverter circuit is the first flying capacitor branch, and the flying capacitor branch with the farthest connection line to the inverter circuit is the nth flying capacitor branch; wherein n is an integer greater than 1; when the flying capacitor voltage is greater than the preset capacitor voltage, the charge and discharge unit is controlled to select the discharge branch, and the inverter circuit and the flying capacitor branch provide a discharge circuit, including:

[0069] When the flying capacitor voltage of the ath flying capacitor branch is greater than the corresponding preset capacitor voltage, the charge and discharge unit is controlled to select the discharge branch, the inverter circuit provides a discharge loop, and the first flying capacitor branch provides a discharge loop.

[0070] Specifically, from the first flying capacitor branch to the direction of the a-th flying capacitor branch, the preset capacitor voltage corresponding to the previous flying capacitor branch is twice the preset capacitor voltage corresponding to the next flying capacitor branch. When the flying capacitor voltage of the a-th flying capacitor branch is greater than the corresponding preset capacitor voltage, the charge and discharge unit can be controlled to select the discharge branch, the inverter circuit provides a discharge circuit, and the first flying capacitor branch provides a discharge circuit, so that the multi-level inverter provides a discharge circuit for the first flying capacitor branch and starts to discharge the first flying capacitor branch.

[0071] When the flying capacitor voltage of the mth flying capacitor branch is discharged to the flying capacitor voltage of the m+1th flying capacitor branch, the first flying capacitor branch to the m+1th flying capacitor branch are controlled to provide a discharge circuit until the flying capacitor voltage of the ath flying capacitor branch is discharged to the corresponding preset capacitor voltage; wherein m is an integer greater than or equal to 1 and less than a, and a is an integer greater than 1 and less than or equal to n.

[0072] Specifically, when the flying capacitor voltage of the first flying capacitor branch is discharged to the flying capacitor voltage of the second flying capacitor branch, the second flying capacitor branch is controlled to provide a discharge circuit so that the second flying capacitor branch starts to discharge. Similarly, the first a-1 flying capacitor branches are discharged in sequence until the flying capacitor voltage of the first a-1 flying capacitor branch is discharged to the flying capacitor voltage of the a-th flying capacitor branch, so that when the flying capacitor of the a-th flying capacitor branch is discharged, the first a-1 flying capacitor branches can provide a discharge circuit for the flying capacitor of the a-th flying capacitor branch, thereby realizing the sequential discharge of at least one flying capacitor branch.

[0073] It should be noted that after multiple flying capacitor branches are discharged, the first a-1 flying capacitor branches can be charged, so that the first a-1 flying capacitor branches are charged to the corresponding preset capacitor voltage in sequence from the a-1th flying capacitor branch to the first flying capacitor branch.

[0074] In some embodiments, the multilevel inverter includes n flying capacitor branches, which are sequentially connected in series and then connected in series with the inverter circuit; the flying capacitor branch directly connected to the inverter circuit is the first flying capacitor branch, and the flying capacitor branch with the farthest connection line to the inverter circuit is the nth flying capacitor branch; wherein n is an integer greater than 1; when the flying capacitor voltage is less than or equal to the preset capacitor voltage, the charging and discharging unit is controlled to select the charging branch, and the inverter circuit and the flying capacitor branch provide a charging circuit, including:

[0075] When the flying capacitance of the bth flying capacitor branch is less than or equal to the corresponding preset capacitance voltage, the charging and discharging unit is controlled to select the charging branch, the inverter circuit provides a charging circuit, and the first to bth flying capacitor branches provide a charging circuit; wherein b is an integer greater than or equal to 1 and less than or equal to n;

[0076] Specifically, when the flying capacitance of the bth flying capacitor branch is less than or equal to the corresponding preset capacitance voltage, the charging and discharging unit can be controlled to select the charging branch, the inverter circuit provides a charging circuit, and the first to bth flying capacitor branches provide a charging circuit at the same time, so that the multi-level inverter charges the first to bth flying capacitor branches at the same time.

[0077] When the flying capacitor voltage of the bth flying capacitor branch is charged to the corresponding preset capacitor voltage, the first to b-1th flying capacitor branches are controlled to provide a charging loop until the flying capacitor voltage of each flying capacitor branch is charged to the corresponding preset capacitor voltage.

[0078] Specifically, from the direction of the first flying capacitor branch to the b-th flying capacitor branch, the preset capacitor voltage corresponding to the previous flying capacitor branch is twice the preset capacitor voltage corresponding to the next flying capacitor branch. When the flying capacitor voltage of the b-th flying capacitor branch is charged to the corresponding preset capacitor voltage, the b-th flying capacitor branch can be controlled to disconnect the charging circuit, and then charge the first b-1 flying capacitor branches. And so on, until the first flying capacitor branch is charged to the corresponding preset capacitor voltage, so that all flying capacitor branches can be charged in sequence.

[0079] For example, Fig.24 for Fig. 9 Another flow chart of a method for controlling pre-charge and discharge of a multi-level inverter is provided. Fig.24 As shown, when the multi-level inverter includes two flying capacitor branches 120, the second flying capacitor C fx2 The flying capacitor voltage U fx2 Is it greater than the corresponding preset capacitor voltage U fx2ref When the second flying capacitor C fx2 The flying capacitor voltage U fx2Greater than the corresponding preset capacitor voltage U fx2ref When Fig.13 As shown, the first flying capacitor C fx1 Through the second transistor S x2 , the second switch device K2, the first pre-charging resistor R DC1 and the fourth transistor S x4 Discharge. At the first flying capacitor C fx1 The flying capacitor voltage U fx1 Discharge to the second flying capacitor C fx2 The flying capacitor voltage U fx2 When Fig.14 As shown, the fifth transistor S in the second flying capacitor branch 120 is controlled. x5 and the sixth transistor S x6 The second flying capacitor C fx2 By passing through the fifth transistor S in the first flying capacitor branch 120 x5 and the sixth transistor S x6 , and the second transistor S x2 , the second switch device K2, the first pre-charging resistor R DC1 and the fourth transistor S x4 Discharge until the second flying capacitor C fx2 The flying capacitor voltage U fx2 Equal to the corresponding preset capacitor voltage U fx2ref Then the multilevel inverter is controlled to be in the charging state, such as Fig.11 As shown, the first switch device K1 is controlled to be in an open state, the second switch device K2 is controlled to be in an open state, the third switch device K3 is controlled to be in an open state, the fourth switch device K4 is controlled to be in a closed state, and the second transistor S x2 and the fourth transistor S x4 Turn off, the first transistor S x1 and the third transistor S x3 The fifth transistor S in the first flying capacitor branch 120 is turned on. x5 and the sixth transistor S x6 The fifth transistor S in the second flying capacitor branch 120 is turned on. x5 and the sixth transistor S x6 The first input power supply terminal V+ is turned off, so that the current provided by the first input power supply terminal V+ passes through the fourth switch device K4 and the first pre-charging resistor R DC1 , the first transistor S x1 , the first flying capacitor branch 120 and the third transistor S x3 Flows to the neutral input power supply terminal V0 to form a charging loop. fx1 Charge to the corresponding preset capacitor voltage U fx1ref , that is Udc / 4, ending the charging and discharging process of the multi-level inverter.

[0080] When the second flying capacitor C fx2 The flying capacitor voltage U fx2 Less than or equal to the corresponding preset capacitor voltage U fx2ref When comparing the first flying capacitor C fx1 The flying capacitor voltage U fx1 And the corresponding preset capacitor voltage U fx1ref When the first flying capacitor C fx1 The flying capacitor voltage U fx1 Greater than the corresponding preset capacitor voltage U fx1ref When the first flying capacitor C fx1 Through the second transistor S x2 , the second switch device K2, the first pre-charging resistor R DC1 and the fourth transistor S x4 Discharge. At the first flying capacitor C fx1 The flying capacitor voltage U fx1 Discharge to the second flying capacitor C fx2 The flying capacitor voltage U fx2 When the multilevel inverter is in charging state, Fig.10 As shown, the fifth transistor S on the two flying capacitor branches 120 is controlled. x5 and the sixth transistor S x6 are all turned on, so that the current provided by the first input power supply terminal V+ passes through the fourth switch device K4 and the first pre-charging resistor R DC1 , the first transistor S x1 , two flying capacitor branches 120 and a third transistor S x3 Flows to the neutral input power supply terminal V0 to form a charging loop. fx When the second flying capacitor C fx2 Charge to the corresponding preset capacitor voltage U fx2ref When Fig.11 As shown, the fifth transistor S in the second flying capacitor branch 120 is controlled. x5 and the sixth transistor S x6 The first input power supply terminal V+ is turned off, so that the current provided by the first input power supply terminal V+ passes through the fourth switch device K4 and the first pre-charging resistor R DC1 , the first transistor S x1 , the first flying capacitor branch 120 and the third transistor S x3 Flows to the neutral input power supply terminal V0 to form a charging loop. fx1 Charge to the corresponding preset capacitor voltage U fx1ref , that is U dc / 4, ending the charging and discharging process of the multi-level inverter.

[0081] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A multi-level inverter, characterized in that: It includes an inverter circuit, at least one flying capacitor branch and a charging and discharging unit; The charge and discharge unit is connected to the input power supply end, the inverter circuit is connected to the charge and discharge unit, and at least one of the flying capacitor branches is connected in series with the inverter circuit; in the abnormal stage of the multi-level inverter, the charge and discharge unit is used to select the charge and discharge branch according to the flying capacitor voltage in the flying capacitor branch, and the inverter circuit and the flying capacitor branch are used to provide a charge and discharge circuit according to the flying capacitor voltage.

2. The multilevel inverter according to claim 1, characterized in that: The charge and discharge unit comprises a first gating module and a second gating module, the inverter circuit comprises a first half-bridge and a second half-bridge, the first end of the first gating module is connected to the first input power supply end, the second end of the first gating module is connected to the first end of the first half-bridge, the second end of the first half-bridge, the third end of the first gating module and the first end of the second half-bridge are connected to the neutral input power supply end; the second gating module comprises a normal working branch and a charging branch, the second end of the second half-bridge is connected to the second end of the normal working branch and the charging branch, and the first end of the normal working branch and the charging branch is connected to the second input power supply end; the third end of the first half-bridge is connected to the first end of the flying capacitor branch, the third end of the second half-bridge is connected to the second end of the flying capacitor branch, and at least one of the flying capacitor branches is connected in series; the first gating module is used to select the first end and the second end of the first gating module in the normal stage of the multi-level inverter, and select the second end and the third end in the discharge stage of the abnormal stage; the second gating module is used to select the normal working branch in the normal stage, and select the charging branch in the charging stage of the abnormal stage.

3. The multilevel inverter according to claim 2, characterized in that: The first gating module includes a first switching device, a second switching device and a first pre-charging resistor; The first end of the first switching device serves as the first end of the first enabling module, the second end of the first switching device is connected to the first end of the first pre-charging resistor and serves as the second end of the first enabling module, the second end of the first pre-charging resistor is connected to the second end of the second switching device, and the first end of the second switching device serves as the third end of the first enabling module.

4. The multilevel inverter according to claim 2, characterized in that: The normal working branch includes a third switch device, and the charging branch includes a fourth switch device and a second pre-charging resistor; The first end of the third switching device serves as the first end of the normal working branch, and the second end of the third switching device serves as the second end of the normal working branch; the first end of the fourth switching device serves as the first end of the charging branch, the second end of the fourth switching device is connected to the first end of the second pre-charging resistor, and the second end of the second pre-charging resistor serves as the second end of the charging branch.

5. The multilevel inverter according to any one of claims 2 to 4, characterized in that: The first half-bridge includes a first transistor, a first diode, a second transistor and a second diode, and the second half-bridge includes a third transistor, a third diode, a fourth transistor and a fourth diode; The first electrode of the first transistor is connected to the cathode of the first diode and serves as the first end of the first half bridge; the second electrode of the first transistor, the anode of the first diode, the first electrode of the second transistor and the cathode of the second diode are connected and serve as the third end of the first half bridge; the second electrode of the second transistor is connected to the anode of the second diode and serves as the second end of the first half bridge; The first electrode of the third transistor is connected to the cathode of the third diode and serves as the first end of the second half bridge. The second electrode of the third transistor, the anode of the third diode, the first electrode of the fourth transistor and the cathode of the fourth diode are connected and serve as the third end of the second half bridge. The second electrode of the fourth transistor is connected to the anode of the fourth diode and serves as the second end of the second half bridge.

6. The multilevel inverter according to claim 1, characterized in that: The flying capacitor branch includes a fifth transistor, a fifth diode, a sixth transistor, a sixth diode and a flying capacitor; The first electrode of the fifth transistor is connected to the cathode of the fifth diode and serves as the first end of the flying capacitor branch. The second electrode of the fifth transistor and the anode of the fifth diode are connected to the first electrode of the flying capacitor. The second electrode of the flying capacitor is connected to the first electrode of the sixth transistor and the cathode of the sixth diode. The second electrode of the sixth transistor is connected to the anode of the sixth diode and serves as the second end of the flying capacitor branch.

7. The multilevel inverter according to claim 2, characterized in that: Also includes a first balancing resistor and a second balancing resistor; The first balancing resistor is connected between the first input power terminal and the neutral input power terminal, and the second balancing resistor is connected between the second input power terminal and the neutral input power terminal.

8. A method for controlling pre-charge and discharge of a multi-level inverter, performed by the multi-level inverter according to any one of claims 1 to 7, characterized in that: The method comprises: Obtaining a flying capacitor voltage in a flying capacitor branch; When the flying capacitor voltage is greater than a preset capacitor voltage, the charging and discharging unit is controlled to select a discharge branch, and the inverter circuit and the flying capacitor branch provide a discharge circuit; When the flying capacitor voltage is less than or equal to a preset capacitor voltage, the charging and discharging unit is controlled to switch on the charging branch, and the inverter circuit and the flying capacitor branch provide a charging loop.

9. The method for controlling pre-charge and discharge of a multi-level inverter according to claim 8, characterized in that: The multi-level inverter comprises n flying capacitor branches, which are sequentially connected in series and then connected in series with the inverter circuit; the flying capacitor branch directly connected to the inverter circuit is the first flying capacitor branch, and the flying capacitor branch farthest from the inverter circuit is the nth flying capacitor branch; wherein n is an integer greater than 1; when the flying capacitor voltage is greater than a preset capacitor voltage, the charging and discharging unit is controlled to select the discharge branch, and the inverter circuit and the flying capacitor branch provide a discharge circuit, comprising: When the flying capacitor voltage of the ath flying capacitor branch is greater than the corresponding preset capacitor voltage, the charging and discharging unit is controlled to select the discharge branch, the inverter circuit provides a discharge loop, and the first flying capacitor branch provides a discharge loop; When the flying capacitor voltage of the mth flying capacitor branch is discharged to the flying capacitor voltage of the m+1th flying capacitor branch, the first flying capacitor branch to the m+1th flying capacitor branch are controlled to provide a discharge circuit until the flying capacitor voltage of the ath flying capacitor branch is discharged to the corresponding preset capacitor voltage; wherein m is an integer greater than or equal to 1 and less than a, and a is an integer greater than 1 and less than or equal to n.

10. The method for controlling pre-charge and discharge of a multi-level inverter according to claim 8, characterized in that: The multi-level inverter comprises n flying capacitor branches, which are sequentially connected in series and then connected in series with the inverter circuit; the flying capacitor branch directly connected to the inverter circuit is the first flying capacitor branch, and the flying capacitor branch farthest from the inverter circuit is the nth flying capacitor branch; wherein n is an integer greater than 1; when the flying capacitor voltage is less than or equal to a preset capacitor voltage, the charging and discharging unit is controlled to select the charging branch, and the inverter circuit and the flying capacitor branch provide a charging circuit, comprising: When the flying capacitance of the bth flying capacitor branch is less than or equal to the corresponding preset capacitance voltage, the charging and discharging unit is controlled to select the charging branch, the inverter circuit provides a charging circuit, and the first to bth flying capacitor branches provide a charging circuit; wherein b is an integer greater than or equal to 1 and less than or equal to n; When the flying capacitor voltage of the bth flying capacitor branch is charged to the corresponding preset capacitor voltage, the first to b-1th flying capacitor branches are controlled to provide a charging circuit until the flying capacitor voltage of each flying capacitor branch is charged to the corresponding preset capacitor voltage.

Images