A power amplifier power-on protection circuit and control system

Abstract

The present invention relates to the field of power-on control technology, and specifically to a power-on protection circuit and control system for a power amplifier, wherein the protection circuit is arranged between a controller and a power amplifier, and if the protection circuit receives a power-on signal only through a control signal T1 pin, a power-on signal is sent through a control signal T2 pin; if the protection circuit receives a power-on signal only through a control signal R1 pin, a power-on signal is sent through a control signal R2 pin; if the protection circuit receives a power-on signal through both a control signal T1 pin and a control signal R1 pin at the same time, both the control signal T2 pin and the control signal R2 pin are powered off. It can be understood that the technical solution can avoid the problem that the controller sends two power-on signals at the same time due to malfunction, resulting in damage to the product, and the circuit is simple, the cost is low, and the reliability is high.

Description

Technical Field

[0001] The present invention relates to the technical field of power-on control, and in particular to a power-on protection circuit and a control system for a power amplifier. Background Art

[0002] In the field of phased array antennas, there are strict power-on requirements for the power-on control of RF power amplifiers. Most products can only power on the power amplifier in the transmit mode or receive mode within a certain period of time. It is strictly forbidden to power on the RF power amplifier to transmit and receive at the same time. If the RF power amplifier is powered on to transmit and receive at the same time due to misoperation, the product will be damaged.

[0003] At present, the control signal for powering on the RF power amplifier comes from software control. When debugging the software or when there is a bug in the software, there may be a malfunction, resulting in powering on the transmit mode or the receive mode of the power amplifier at the same time, causing damage to the product. Summary of the invention

[0004] In view of this, an object of the present invention is to provide a power amplifier power-on protection circuit and control system to solve the problem in the prior art that the power-on control signal of the RF power amplifier may malfunction and cause damage to the product.

[0005] According to a first aspect of an embodiment of the present invention, there is provided a power amplifier power-on protection circuit, comprising: The protection circuit is connected to the controller through the control signal T1 pin and the control signal R1 pin; the protection circuit is connected to the power amplifier transmission mode control port through the control signal T2 pin; the protection circuit is connected to the power amplifier reception mode control port through the control signal R2 pin; If the protection circuit receives the power-on signal only through the control signal T1 pin, it sends the power-on signal through the control signal T2 pin; If the protection circuit receives the power-on signal only through the control signal R1 pin, it sends the power-on signal through the control signal R2 pin; If the protection circuit receives a power-on signal through the control signal pin T1 and the control signal pin R1 at the same time, the control signal pin T2 and the control signal pin R2 are both powered off.

[0006] Preferably, the protection circuit includes a first NOT gate, a second NOT gate, a first AND gate and a second AND gate; The input end of the first NOT gate is connected to the control signal R1 pin; the output end of the first NOT gate is connected to the second input end of the first AND gate; the first input end of the first AND gate is connected to the control signal T1 pin; the output end of the first AND gate is connected to the control signal T2 pin; The input end of the second NOT gate is connected to the control signal T1 pin; the output end of the second NOT gate is connected to the first input end of the second AND gate; the second input end of the second AND gate is connected to the control signal R1 pin; the output end of the second AND gate is connected to the control signal R2 pin.

[0007] According to a second aspect of an embodiment of the present invention, a power amplifier power-on control system is provided, comprising: A controller, a power amplifier and a power amplifier power-on protection circuit as described in any one of the above; The controller is connected to the control signal T1 pin and the control signal R1 pin of the power amplifier power-on protection circuit; the transmission mode control port of the power amplifier is connected to the control signal T2 pin of the power amplifier power-on protection circuit; the reception mode control port of the power amplifier is connected to the control signal R2 pin of the power amplifier power-on protection circuit; If the controller sends a power-on signal to the control signal T1 pin, the transmit mode control port of the power amplifier is powered on; If the controller sends a power-on signal to the control signal R1 pin, the receiving mode control port of the power amplifier is powered on; If the controller sends a power-on signal to the control signal T1 pin and the control signal R1 pin at the same time, the transmission mode control port and the reception mode control port of the power amplifier are both powered off.

[0008] Preferably, the controller is FPGA, CPLD or ARM.

[0009] The technical solution provided by the embodiments of the present invention may have the following beneficial effects: It can be understood that the present invention shows a power amplifier power-on protection circuit, which is arranged between the controller and the power amplifier. If the protection circuit receives a power-on signal only through the control signal T1 pin, it sends a power-on signal through the control signal T2 pin; if the protection circuit receives a power-on signal only through the control signal R1 pin, it sends a power-on signal through the control signal R2 pin; if the protection circuit receives a power-on signal through the control signal T1 pin and the control signal R1 pin at the same time, the control signal T2 pin and the control signal R2 pin are both powered off. It can be understood that the technical solution can avoid the problem of the controller sending two power-on signals at the same time due to malfunction, resulting in damage to the product, and the circuit is simple, low cost and high reliability.

[0010] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0012] Figure 1 is a schematic block diagram of a power amplifier power-on protection circuit according to an exemplary embodiment; Figure 2 is a specific schematic block diagram of a power amplifier power-on protection circuit according to an exemplary embodiment; Figure 3 The figure is a schematic diagram showing a conventional controller controlling a power amplifier according to an exemplary embodiment. DETAILED DESCRIPTION

[0013] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Instead, they are merely examples of devices and methods consistent with some aspects of the present invention as detailed in the appended claims.

[0014] In one embodiment, Figure 1 is a schematic block diagram of a power amplifier power-on protection circuit according to an exemplary embodiment. Figure 1 In the figure, T1 is the control signal T1 pin, which is the pin that the controller sends the "control signal T1" to the protection circuit. If this pin is powered on, it means that the controller wants to power on the power amplifier transmit mode; R1 is the control signal R1 pin, which is the pin that the controller sends the "control signal R1" to the protection circuit. If this pin is powered on, it means that the controller wants to power on the power amplifier receive mode; T2 is the control signal T2 pin, which is the pin that the protection circuit sends the "control signal T2" to the power amplifier transmit mode control port; R2 is the control signal R2 pin, which is the pin that the protection circuit sends the "control signal R2" to the power amplifier receive mode control port. See Figure 1 , a power amplifier power-on protection circuit is provided, comprising: The protection circuit is connected to the controller through the control signal T1 pin and the control signal R1 pin; the protection circuit is connected to the power amplifier transmission mode control port through the control signal T2 pin; the protection circuit is connected to the power amplifier reception mode control port through the control signal R2 pin; If the protection circuit receives the power-on signal only through the control signal T1 pin, it sends the power-on signal through the control signal T2 pin; If the protection circuit receives the power-on signal only through the control signal R1 pin, it sends the power-on signal through the control signal R2 pin; If the protection circuit receives a power-on signal through the control signal pin T1 and the control signal pin R1 at the same time, the control signal pin T2 and the control signal pin R2 are both powered off.

[0015] It can be understood that the present invention shows a power amplifier power-on protection circuit, which is arranged between the controller and the power amplifier. If the protection circuit receives a power-on signal only through the control signal T1 pin, it sends a power-on signal through the control signal T2 pin; if the protection circuit receives a power-on signal only through the control signal R1 pin, it sends a power-on signal through the control signal R2 pin; if the protection circuit receives a power-on signal through the control signal T1 pin and the control signal R1 pin at the same time, the control signal T2 pin and the control signal R2 pin are both powered off. It can be understood that the technical solution can avoid the problem of the controller sending two power-on signals at the same time due to malfunction, resulting in damage to the product, and the circuit is simple, low cost and high reliability.

[0016] It should be noted that see Figure 2 , T1 is the control signal T1 pin, R1 is the control signal R1 pin, T2 is the control signal T2 pin, R2 is the control signal R2 pin, 11 is the first NOT gate, 12 is the second NOT gate, 21 is the first AND gate, and 22 is the second AND gate.

[0017] exist Figure 2 In the embodiment, the protection circuit includes a first NOT gate, a second NOT gate, a first AND gate and a second AND gate; The input end of the first NOT gate is connected to the control signal R1 pin; the output end of the first NOT gate is connected to the second input end of the first AND gate; the first input end of the first AND gate is connected to the control signal T1 pin; the output end of the first AND gate is connected to the control signal T2 pin; The input end of the second NOT gate is connected to the control signal T1 pin; the output end of the second NOT gate is connected to the first input end of the second AND gate; the second input end of the second AND gate is connected to the control signal R1 pin; the output end of the second AND gate is connected to the control signal R2 pin.

[0018] In specific practice, if the "control signal T1" is "1", it means that the control signal T1 pin is powered on, and if the "control signal T1" is "0", it means that the control signal T1 pin is powered off, and so on, as follows: Existing technical solutions such as Figure 3As shown, there may be malfunctions during software debugging or when there are bugs in the software, that is, "control signal T1" and "control signal R1" output logic 1 at the same time, and the power amplifier's transmission or reception is powered on at the same time. This operation usually damages the product and is not allowed. Of course, "control signal T1" and "control signal R1" can output logic 0 at the same time, indicating that the power amplifier transmission and the power amplifier reception are not powered on.

[0019] The technical solution shown in this embodiment implements power-on protection of the power amplifier through NOT gate and AND gate logic circuits. During software debugging or when there is a bug in the software, even if a malfunction occurs and causes the "control signal T1" and "control signal R1" to output logic 1 at the same time, the "control signal T2" and "control signal R2" received by the power amplifier will be logic 0.

[0020] The working logic of the protection circuit is as follows: 1. When the “control signal T1” outputs logic 1 and the “control signal R1” outputs logic 0, the “control signal T2” outputs logic 1 and the “control signal R2” outputs logic 0.

[0021] 2. When “control signal T1” outputs logic 0 and “control signal R1” outputs logic 1, “control signal T2” outputs logic 0 and “control signal R2” outputs logic 1.

[0022] 3. When “control signal T1” outputs logic 1, “control signal R1” outputs logic 1, “control signal T2” outputs logic 0, and “control signal R2” outputs logic 0.

[0023] 4. When "control signal T1" outputs logic 0, "control signal R1" outputs logic 0, "control signal T2" outputs logic 0, and "control signal R2" outputs logic 0. The input and output logic truth table is shown in Table 1.

[0024] Table 1

[0025] Therefore, no matter what logic signals the input signals "control signal T1" and "control signal R1" are, they can avoid the situation of outputting logic 1 at the same time after passing through the protection circuit, and can ensure the use of normal logic control function.

[0026] It can be understood that the technical solution shown in this embodiment solves the problem that the power amplifier transmitter and the power amplifier receiver are powered on at the same time even if a malfunction occurs during software debugging or when there is a bug in the software, thereby avoiding product damage. The circuit is simple, low cost, and highly reliable, and can be implemented using only two NOT gates and two two-input AND gate logic devices.

[0027] In another embodiment, a power amplifier power-on control system is provided, comprising: A controller, a power amplifier and a power amplifier power-on protection circuit as described in any one of the above; The controller is connected to the control signal T1 pin and the control signal R1 pin of the power amplifier power-on protection circuit; the transmission mode control port of the power amplifier is connected to the control signal T2 pin of the power amplifier power-on protection circuit; the reception mode control port of the power amplifier is connected to the control signal R2 pin of the power amplifier power-on protection circuit; If the controller sends a power-on signal to the control signal T1 pin, the transmit mode control port of the power amplifier is powered on; If the controller sends a power-on signal to the control signal R1 pin, the receiving mode control port of the power amplifier is powered on; If the controller sends a power-on signal to the control signal T1 pin and the control signal R1 pin at the same time, the transmission mode control port and the reception mode control port of the power amplifier are both powered off.

[0028] Preferably, the controller is FPGA, CPLD or ARM. Specifically, the controller can be other microcontroller chips.

[0029] “Control signal T1” and “Control signal R1” are two GPIO output interfaces of the microcontroller chip.

[0030] It can be understood that the same or similar parts of the above embodiments can be referenced to each other, and the contents not described in detail in some embodiments can refer to the same or similar contents in other embodiments.

[0031] It should be noted that, in the description of the present invention, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, the meaning of "plurality" refers to at least two.

[0032] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present invention includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present invention belong.

[0033] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0034] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0035] In addition, each functional unit in each embodiment of the present invention may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0036] The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0037] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0038] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A power amplifier power-on protection circuit, characterized in that: include: The protection circuit is connected to the controller through the control signal T1 pin and the control signal R1 pin; the protection circuit is connected to the power amplifier transmission mode control port through the control signal T2 pin; the protection circuit is connected to the power amplifier reception mode control port through the control signal R2 pin; If the protection circuit receives the power-on signal only through the control signal T1 pin, it sends the power-on signal through the control signal T2 pin; If the protection circuit receives the power-on signal only through the control signal R1 pin, it sends the power-on signal through the control signal R2 pin; If the protection circuit receives a power-on signal through the control signal pin T1 and the control signal pin R1 at the same time, the control signal pin T2 and the control signal pin R2 are both powered off.

2. The power amplifier power-on protection circuit according to claim 1, characterized in that: The protection circuit includes a first NOT gate, a second NOT gate, a first AND gate and a second AND gate; The input end of the first NOT gate is connected to the control signal R1 pin; the output end of the first NOT gate is connected to the second input end of the first AND gate; the first input end of the first AND gate is connected to the control signal T1 pin; the output end of the first AND gate is connected to the control signal T2 pin; The input end of the second NOT gate is connected to the control signal T1 pin; the output end of the second NOT gate is connected to the first input end of the second AND gate; the second input end of the second AND gate is connected to the control signal R1 pin; the output end of the second AND gate is connected to the control signal R2 pin.

3. A power amplifier power-on control system, comprising the power amplifier power-on protection circuit according to any one of claims 1 to 2, characterized in that: Also includes: controllers and power amplifiers; The controller is connected to the control signal T1 pin and the control signal R1 pin of the power amplifier power-on protection circuit; the transmission mode control port of the power amplifier is connected to the control signal T2 pin of the power amplifier power-on protection circuit; the reception mode control port of the power amplifier is connected to the control signal R2 pin of the power amplifier power-on protection circuit; If the controller sends a power-on signal to the control signal T1 pin, the transmit mode control port of the power amplifier is powered on; If the controller sends a power-on signal to the control signal R1 pin, the receiving mode control port of the power amplifier is powered on; If the controller sends a power-on signal to the control signal T1 pin and the control signal R1 pin at the same time, the transmission mode control port and the reception mode control port of the power amplifier are both powered off.

4. The power amplifier power-on control system according to claim 3, characterized in that: The controller is FPGA, CPLD or ARM.

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