A K-band high linearity MMIC power amplifier

Abstract

The present invention provides a K-band high linearity MMIC power amplifier, which includes: a power distribution unit, a power synthesis unit and two power amplification units; the power amplification unit is connected to the power distribution unit, and the power amplification unit is connected to the power synthesis unit; the power amplification unit includes a first-stage amplification circuit, a second-stage amplification circuit and a third-stage amplification circuit, and a gradual impedance transformation structure is connected between the first-stage amplification circuit and the second-stage amplification circuit, and between the second-stage amplification circuit and the third-stage amplification circuit; the third-stage amplification circuit includes a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor, and the drains of the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor are connected to nF multilayer capacitors; the sources of the fourth transistor and the fifth transistor are connected to the ground in parallel, and the sources of the sixth transistor and the seventh transistor are connected to the ground in parallel. The present invention can improve linearity.

Description

Technical Field

[0001] The present invention relates to the technical field of power amplifiers, and in particular to a K-band high-linearity MMIC power amplifier. Background Art

[0002] In modern communication systems, whether strategic or tactical, satellite communications with large capacity and high quality have become one of the most important means of communication. The communication field has a great demand for microwave and millimeter wave components and circuits, and has its own special requirements. Since there are extremely strict restrictions on the size and weight of the system in mobile communications, airborne communications, health communications and other communication systems, GaN MMIC is the most suitable candidate for applications in military and civilian communications.

[0003] The research and application of the third generation broadband semiconductor materials represented by GaN is the forefront and hot spot of global semiconductor research. GaN has the advantages of high electron mobility and electron saturation drift velocity, high breakdown field strength, good heat dissipation performance, stable chemical properties, and resistance to electron irradiation, making GaN-based materials very ideal semiconductor materials for the development of high-frequency, broadband, high-efficiency, and high-power electronic devices. GaN MMIC with GaN as the substrate has the advantages of high output power and high working efficiency. MMIC has a high degree of integration and can meet the needs of miniaturization. It is of great significance to develop a small single-chip output amplifier with sufficient power. GaN MMIC has a very wide range of applications in radar, communications, electronic warfare and other fields.

[0004] The power amplifier is one of the core components in the communication field. The performance of the power amplifier directly affects the performance of the communication system and plays a decisive role in the communication system. Usually, the power amplifier is at the end of the transmitter of the entire communication system. After the signal passes through the modem, mixer and filter, it is finally amplified to a certain power by the power amplifier and then transmitted through the antenna. Therefore, the output power, working bandwidth and other performance indicators of the power amplifier directly affect the performance of the entire transmitter. In order to meet the requirements for bandwidth and rate in the communication system, it is necessary to continuously optimize the linear performance of the power amplifier. Summary of the invention

[0005] The embodiment of the present invention provides a K-band high-linearity MMIC power amplifier to improve the linearity of the MMIC power amplifier.

[0006] An embodiment of the present invention provides a K-band high linearity MMIC power amplifier, including: A power distribution unit, a power synthesis unit and two symmetrically arranged power amplification units; The two power amplifying units are arranged in parallel, the input ends of the two power amplifying units are respectively connected to the power distribution unit, and the output ends of the two power amplifying units are respectively connected to the power synthesis unit; The two power amplification units each include a first-stage amplification circuit, a second-stage amplification circuit and a third-stage amplification circuit, and a gradient impedance conversion structure is connected between the first-stage amplification circuit and the second-stage amplification circuit, and between the second-stage amplification circuit and the third-stage amplification circuit respectively; The first-stage amplifier circuit includes a first transistor, the second-stage amplifier circuit includes a second transistor and a third transistor, the second transistor and the third transistor are arranged in parallel, the third-stage amplifier circuit includes a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor, the fourth transistor and the fifth transistor are arranged in parallel, and the sixth transistor and the seventh transistor are arranged in parallel; The drains of the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor are connected with nF-level multilayer capacitors; Sources of the fourth transistor and the fifth transistor are connected in parallel to the ground, and sources of the sixth transistor and the seventh transistor are connected in parallel to the ground.

[0007] In a possible implementation, the gate of the first transistor is connected to the power distribution unit, the source of the first transistor is grounded, the drain of the first transistor is connected to the first capacitor, the first capacitor is grounded, and the drain of the first transistor is connected to the gradient impedance transformation structure; The gate of the second transistor is connected to the output end of the gradient impedance conversion structure connected to the first transistor, the source of the second transistor is grounded, the drain of the second transistor is connected to the second capacitor, the second capacitor is grounded, and the drain of the second transistor is connected to the gradient impedance conversion structure; The fourth transistor and the fifth transistor are arranged in parallel, the gate of the fourth transistor is connected to the output end of the gradient impedance transformation structure connected to the second transistor, the drain of the fourth transistor is connected to the third capacitor, and the third capacitor is grounded; The gate of the fifth transistor is connected to the output end of the gradient impedance transformation structure connected to the second transistor, the drain of the fifth transistor is connected to the fourth capacitor, and the fourth capacitor is grounded; The third transistor, the sixth transistor and the seventh transistor are symmetrically arranged with the second transistor, the fourth transistor and the fifth transistor, respectively.

[0008] In a possible implementation, the gradient impedance transformation structure includes a first impedance transformation structure and a second impedance transformation structure, and the first impedance transformation structure and the second impedance transformation structure are connected in series; The drain of the first transistor is connected to one of the first impedance transformation structures, and the second impedance transformation structure corresponding to the first impedance transformation structure connected to the drain of the first transistor is respectively connected to the gate of the second transistor and the gate of the third transistor; The drain of the second transistor is connected to another first impedance transformation structure, and the second impedance transformation structure corresponding to the first impedance transformation structure connected to the drain of the second transistor is respectively connected to the gate of the fourth transistor and the gate of the fifth transistor; The drain of the third transistor is connected to the third first impedance transformation structure, and the second impedance transformation structure corresponding to the first impedance transformation structure connected to the drain of the third transistor is respectively connected to the gate of the sixth transistor and the gate of the seventh transistor.

[0009] In one possible implementation, a balancing resistor is connected between the gate of the second transistor and the gate of the third transistor, a balancing resistor is connected between the drain of the second transistor and the drain of the third transistor, a balancing resistor is connected between the gate of the fourth transistor and the gate of the fifth transistor, a balancing resistor is connected between the drain of the fourth transistor and the drain of the fifth transistor, a balancing resistor is connected between the gate of the sixth transistor and the gate of the seventh transistor, and a balancing resistor is connected between the drain of the sixth transistor and the drain of the seventh transistor.

[0010] In a possible implementation, bias circuits are provided before gates of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor, respectively, and the bias circuits include a first branch and a second branch connected in parallel.

[0011] In a possible implementation, the first branch includes a fifth capacitor, and the fifth capacitor is grounded; The second branch includes a resistor and a sixth capacitor connected in series, and the resistor is grounded.

[0012] In one possible implementation, the K-band high linearity MMIC power amplifier operates in the range of 17-22 GHz.

[0013] In a possible implementation, the power distribution unit and the power synthesis unit both include a 3 dB high power Lange coupler.

[0014] In a possible implementation, two 100Ω resistors are connected in parallel to the isolation port of the Lange coupler of the power synthesis unit.

[0015] In a possible implementation, a 7 mm×7 mm surface mount leadless ceramic tube package is used, and the dust and water resistance level of the package is greater than or equal to IP66.

[0016] The embodiment of the present invention provides a K-band high linearity MMIC power amplifier. By connecting a gradient impedance transformation structure between the first-stage amplifier circuit and the second-stage amplifier circuit, and between the second-stage amplifier circuit and the third-stage amplifier circuit, a multi-stage gradient impedance transformation structure is used for inter-stage matching. The impedance matching is first matched to the intermediate impedance point, and then matched to the final required impedance point. Finally, the impedance matching can be completed in a smaller equal Q value circle, and the linearity of the power amplifier is improved while extending the bandwidth, thereby improving the performance of the power amplifier in the broadband. The linearity of the MMIC power amplifier is improved by connecting two nF multilayer capacitors in parallel to the drains of the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor. By connecting the sources of the fourth transistor and the fifth transistor in parallel to the ground, and the sources of the sixth transistor and the seventh transistor in parallel to the ground, the parasitic effects when multiple transistors are connected in parallel can be reduced, the performance of the transistors at high frequencies can be improved, and the area is reduced, the cost is reduced, and the linearity of the power amplifier is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0018] Figure 1 It is a schematic diagram of the structure of the overall circuit of the K-band high linearity MMIC power amplifier provided by an embodiment of the present invention; Figure 2 is a schematic structural diagram of a circuit of a single power amplification unit provided by an embodiment of the present invention; Figure 3 is a schematic diagram of an external capacitor provided by an embodiment of the present invention; Figure 4 The IMD3 with and without nF capacitors provided in the embodiments of the present invention; Figure 5 It is a schematic diagram of a gradually changing impedance transformation structure provided by an embodiment of the present invention; Figure 6 It is a direct match to the Smith chart; Figure 7 is a Smith chart of gradual matching provided by an embodiment of the present invention; Figure 8 is a schematic diagram of a balancing resistor provided by an embodiment of the present invention; Fig. 9 is a schematic structural diagram of a 3dB Lange coupler A1 provided in an embodiment of the present invention; Fig.10is a schematic structural diagram of a 3dB Lange coupler A2 provided in an embodiment of the present invention; Fig.11 is a three-temperature test curve of the measured small signal gain provided by an embodiment of the present invention; Fig.12 It is a three-temperature test curve of the input return loss measured in an embodiment of the present invention; Fig.13 It is a three-temperature test curve of the saturated output power P5 measured in an embodiment of the present invention; Fig.14 It is a three-temperature test curve of the measured output IP3 provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0019] In order to enable people in the technical field to better understand the present solution, the technical solution in the embodiment of the present solution will be clearly described below in conjunction with the drawings in the embodiment of the present solution. Obviously, the described embodiment is an embodiment of a part of the present solution, not all of the embodiments. Based on the embodiments in the present solution, all other embodiments obtained by ordinary technicians in the field without creative work should fall within the scope of protection of the present solution.

[0020] The term "including" and any other variations in the specification and claims of this solution and the above drawings mean "including but not limited to", and is intended to cover non-exclusive inclusions and is not limited to the examples listed in the text. In addition, the terms "first" and "second" are used to distinguish different objects, not to describe a specific order.

[0021] The following is a detailed description of the implementation of the present invention in conjunction with the specific drawings: Figure 1 A schematic diagram of a circuit structure of a K-band high linearity MMIC power amplifier provided by an embodiment of the present invention includes: A power distribution unit, a power synthesis unit and two symmetrically arranged power amplification units; The two power amplifying units are arranged in parallel, the input ends of the two power amplifying units are respectively connected to the power distribution unit, and the output ends of the two power amplifying units are respectively connected to the power synthesis unit; The two power amplification units each include a first-stage amplification circuit, a second-stage amplification circuit and a third-stage amplification circuit, and a gradient impedance conversion structure is connected between the first-stage amplification circuit and the second-stage amplification circuit, and between the second-stage amplification circuit and the third-stage amplification circuit respectively; The first-stage amplifier circuit includes a first transistor, the second-stage amplifier circuit includes a second transistor and a third transistor, the second transistor and the third transistor are arranged in parallel, the third-stage amplifier circuit includes a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor, the fourth transistor and the fifth transistor are arranged in parallel, and the sixth transistor and the seventh transistor are arranged in parallel; The drains of the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor are connected with nF-level multilayer capacitors; Sources of the fourth transistor and the fifth transistor are connected in parallel to the ground, and sources of the sixth transistor and the seventh transistor are connected in parallel to the ground.

[0022] In this embodiment, the RF signal is divided into two paths after being equally divided by the power distribution unit. The two paths are amplified by two power amplifier units respectively, and then the power is combined by the power combination unit before being output as RF. Figure 2 shown.

[0023] In this embodiment, the main factors affecting the device video bandwidth are the parasitic capacitance inside the transistor and the inductance on the power supply arm. The video bandwidth VBW can be expressed by the following formula.

[0024]

[0025] Better video bandwidth performance means better wideband linear performance of the device.

[0026] In this embodiment, when designing the drain power supply circuit, a vertically symmetrical circuit structure is used, and this symmetrical structure can reduce the equivalent inductance of the circuit power supply part. The reduction of the equivalent inductance can improve the video bandwidth performance of the circuit.

[0027] In this embodiment, the fourth transistor and the fifth transistor, the sixth transistor and the seventh transistor are connected in parallel with a common source ground hole. This connection method can reduce the parasitic effects when multiple transistors are connected in parallel, improve the performance of the transistors at high frequencies, and make the overall layout more compact, reduce the area, and reduce the cost.

[0028] Specifically, when packaging the circuit, two nF-level multilayer capacitors are placed outside the amplifier chip and in the drain power supply part of the third-stage amplifier circuit, such as Figure 3 As shown, C1 and C2 are external capacitors. The two nF capacitors are connected to the drain power PAD of the first-stage amplifier circuit, the second-stage amplifier circuit, and the third-stage amplifier circuit through a gold wire with a diameter of 25um. The two nF capacitors can not only filter out the ripple signal brought by the power supply, but also reduce the additional inductance introduced by the circuit package, and improve the linearity level of the overall packaged device. Figure 4Shown, the circuit design scheme provided by the present embodiment is within the scope of double-tone interval 400MHz-800MHz, and linearity index is obviously better than the power amplifier that is not equipped with nF level capacitor.The design method adopted in the present embodiment is not introduced extra components and parts, and the physical size of components and parts is not obviously increased, and this design method is generally used with the design of K-band amplifier circuit.Confirmed by final test result, this example circuit can reach excellent linearity performance within the scope of double-tone interval of 800MHz.

[0029] In the embodiment of the present invention, a gradual impedance transformation structure is connected between the first-stage amplifier circuit and the second-stage amplifier circuit, and between the second-stage amplifier circuit and the third-stage amplifier circuit, and a multi-stage gradual impedance transformation structure is used for inter-stage matching, first matching to the intermediate impedance point, and then matching to the final required impedance point, so that impedance matching can be completed in a smaller equal Q value circle, while extending the bandwidth and improving the linearity of the power amplifier, thereby improving the performance of the power amplifier in the broadband. By connecting two nF-level multilayer capacitors in parallel to the drains of the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor, the linearity of the MMIC power amplifier is improved. By connecting the sources of the fourth transistor and the fifth transistor in parallel to the ground, and the sources of the sixth transistor and the seventh transistor in parallel to the ground, the parasitic effects when multiple transistors are connected in parallel can be reduced, the performance of the transistors at high frequencies can be improved, and the area can be reduced, and the cost can be reduced, thereby improving the linearity of the power amplifier.

[0030] The K-band high linear MMIC power amplifier of the present invention has an operating frequency band range of 17-22 GHz, a saturated output power of 40 dBm, a gain of 26 dB, a third-order intermodulation output power of 43 dBm, and an input / output return loss greater than 10 dB under a 20 V operating voltage.

[0031] The present invention adopts a three-stage cascade amplifier structure, uses source pull and load pull technology to obtain the impedance of transistors under different gate widths to design an impedance matching network, and uses a power synthesis network and an impedance matching network to synthesize the output final stage, effectively reducing the area and manufacturing cost. The present invention can achieve high linearity, high power and small volume of the power amplifier in the K band.

[0032] In a possible implementation, the gate of the first transistor is connected to the power distribution unit, the source of the first transistor is grounded, the drain of the first transistor is connected to the first capacitor, the first capacitor is grounded, and the drain of the first transistor is connected to the gradient impedance transformation structure; The gate of the second transistor is connected to the output end of the gradient impedance conversion structure connected to the first transistor, the source of the second transistor is grounded, the drain of the second transistor is connected to the second capacitor, the second capacitor is grounded, and the drain of the second transistor is connected to the gradient impedance conversion structure; The fourth transistor and the fifth transistor are arranged in parallel, the gate of the fourth transistor is connected to the output end of the gradient impedance transformation structure connected to the second transistor, the drain of the fourth transistor is connected to the third capacitor, and the third capacitor is grounded; The gate of the fifth transistor is connected to the output end of the gradient impedance transformation structure connected to the second transistor, the drain of the fifth transistor is connected to the fourth capacitor, and the fourth capacitor is grounded; The third transistor, the sixth transistor and the seventh transistor are symmetrically arranged with the second transistor, the fourth transistor and the fifth transistor, respectively.

[0033] In this embodiment, a gradual impedance transformation structure is used to ensure impedance matching when signals are transmitted between transistors, reduce signal reflection, and improve signal transmission efficiency. The symmetrical arrangement of the third transistor, the sixth transistor, and the seventh transistor with the second transistor, the fourth transistor, and the fifth transistor helps to balance the performance of the circuit and improve the linearity and stability of the amplifier. All transistors operate in a high linearity operating state, and the size of the first transistor Q1 is smaller than that of the second transistor Q2, the third transistor Q3, the fourth transistor Q4, the fifth transistor Q5, the sixth transistor Q6, and the seventh transistor Q7, such as the channel length (L) and channel width (W) of the transistor. These dimensions determine the electrical characteristics of the transistor, such as current driving capability, transconductance, threshold voltage, etc. The fourth transistor Q4-the seventh transistor Q7 ensures the overall output power of the circuit.

[0034] In a possible implementation, the drain of the first transistor Q1 is connected to a DC blocking capacitor and then to a gradual impedance transformation structure, and the drain of the second transistor Q2 is connected to a DC blocking capacitor and then to the gradual impedance transformation structure.

[0035] In this embodiment, the DC isolation capacitor between each stage of the amplifier circuit is used to isolate the DC signal from the RF signal. Figure 1 shown.

[0036] In a possible implementation, the gradient impedance transformation structure includes a first impedance transformation structure and a second impedance transformation structure, and the first impedance transformation structure and the second impedance transformation structure are connected in series. Figure 5 As shown, Z1 is the characteristic impedance corresponding to the first impedance transformation structure, and Z2 is the characteristic impedance corresponding to the second impedance transformation structure.

[0037] The drain of the first transistor is connected to one of the first impedance transformation structures, and the second impedance transformation structure corresponding to the first impedance transformation structure connected to the drain of the first transistor is respectively connected to the gate of the second transistor and the gate of the third transistor; The drain of the second transistor is connected to another first impedance transformation structure, and the second impedance transformation structure corresponding to the first impedance transformation structure connected to the drain of the second transistor is respectively connected to the gate of the fourth transistor and the gate of the fifth transistor; The drain of the third transistor is connected to the third first impedance transformation structure, and the second impedance transformation structure corresponding to the first impedance transformation structure connected to the drain of the third transistor is respectively connected to the gate of the sixth transistor and the gate of the seventh transistor.

[0038] In this embodiment, a gradual impedance matching method is used for inter-stage matching. That is, when performing inter-stage matching, first match to the intermediate impedance point, and then match to the final desired impedance point. Finally, the impedance matching can be completed in a smaller equal Q value circle. By using this design method, the bandwidth of the device can be effectively improved, and the performance of the device in the broadband can be ensured.

[0039] Specifically, through the load-pull and source-pull techniques, it can be known that when performing the final stage matching, the process used in this embodiment is in the frequency band of 17-22 GHz, and the matching circuit needs to match the impedance from 7-8.3*jΩ to 50Ω. If the matching circuit is directly matched, as shown in Figure 6. The Q value of the matching circuit is 1.3, and the impedance matching can only be completed near the center frequency. When the present invention adopts the gradient impedance matching, such as Figure 7 , first match the impedance to the middle impedance in the operating frequency band as a buffer, and then finally match it to the target impedance of 50 ohms. After using the gradient impedance matching, the Q of the matching circuit becomes 0.7. Compared with the direct matching, the bandwidth of the matching circuit has been significantly improved. Finally, in the final stage matching of this embodiment, the impedance is matched to 12+2*jΩ, 40+10*jΩ, and finally to 50Ω.

[0040] In one possible implementation, a balancing resistor is connected between the gate of the second transistor and the gate of the third transistor, a balancing resistor is connected between the drain of the second transistor and the drain of the third transistor, a balancing resistor is connected between the gate of the fourth transistor and the gate of the fifth transistor, a balancing resistor is connected between the drain of the fourth transistor and the drain of the fifth transistor, a balancing resistor is connected between the gate of the sixth transistor and the gate of the seventh transistor, and a balancing resistor is connected between the drain of the sixth transistor and the drain of the seventh transistor.

[0041] In this embodiment, a balancing resistor is used between the two transistors to balance the phase imbalance that occurs during power synthesis and improve stability. Figure 8 As shown, R3 and R4 are balancing resistors.

[0042] In a possible implementation, bias circuits are provided before gates of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor, respectively, and the bias circuits include a first branch and a second branch connected in parallel.

[0043] In a possible implementation, the first branch includes a fifth capacitor, and the fifth capacitor is grounded; The second branch includes a resistor and a sixth capacitor connected in series, and the resistor is grounded.

[0044] In this embodiment, the first branch and the second branch are used to absorb the ripple introduced by the power supply during actual use, thereby improving the stability of the overall circuit.

[0045] In one possible implementation, the K-band high linearity MMIC power amplifier operates in the range of 17-22 GHz.

[0046] In this embodiment, the K-band high linearity MMIC power amplifier is commonly used in satellite communications, radar systems, and other wireless communication applications requiring high frequencies.

[0047] In a possible implementation, the power distribution unit and the power synthesis unit both include a 3 dB high power Lange coupler.

[0048] In this embodiment, two 3dB high-power Lange couplers are used to respectively realize the functions of power distribution and synthesis. Fig. 9 As shown, the input signal enters from port ① of Lange coupler A1, and is output from ports ② and ③. The output signal has a phase difference of 90 degrees. The two output signals pass through Figure 2 The power amplifier unit shown is synthesized by a high power Lange coupler A2, such as Fig.10 As shown, the power is synthesized through port ④ and port ⑤, and then output through port ⑥. The Lange coupler A1 and Lange coupler A2 have an isolation greater than 35 dB, which improves the port anti-mismatch capability of this implementation case, reduces the influence of the peripheral circuit on the amplifier circuit, and enhances the robustness of the circuit.

[0049] In a possible implementation, two 100Ω resistors are connected in parallel to the isolation port of the Lange coupler of the power synthesis unit.

[0050] In this embodiment, the isolation port of the Lange coupler is connected in parallel with two 100Ω resistors to improve the power handling capability of the unit circuit. Fig.10 R2 in FIG. 1 is a 100Ω resistor in this embodiment.

[0051] In a possible implementation, a 7 mm×7 mm surface mount leadless ceramic tube package is used, and the dust and water resistance level of the package is greater than or equal to IP66.

[0052] In this embodiment, a 7 mm×7 mm surface mount leadless ceramic tube package is used to achieve airtight level packaging.

[0053] Specifically, in this embodiment, the key technology is studied as follows: according to the key indicators of the embodiment, the appropriate process is selected, and the schematic diagram and layout simulation are carried out according to the specific requirements of this embodiment, so as to achieve small signal gain, saturation power, linearity and other indicators that are better than other products and are at the leading level at home and abroad.

[0054] The power amplifier provided in this embodiment has an operating frequency of 17GHz-22GHz, a bias condition of Vdd=+20V, a static operating current Idq=700mA, and a small signal gain of 26dB under a continuous wave and +20V operating voltage, a saturated output power Psat=40dBm, and a third-order intermodulation output power of 43dBm. The input return loss of the power amplifier provided in this embodiment is above 10dB, and the input and output impedance is 50Ω.

[0055] Specifically, parameters of a K-band high linearity MMIC power amplifier in this embodiment are shown in Table 1: Table 1

[0056] Through post-tapeout assembly test, we get Figure 11-Figure 14 The package test curves are shown. Fig.11 It can be seen that the small signal gain of this embodiment meets the design requirements. Fig.12 It can be seen that this embodiment has good input return loss. Fig.13 It can be seen that the saturated output power of this embodiment meets the design requirements. Fig.14 It can be seen that the output IP3 meets the design requirements.

[0057] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A K-band high linearity MMIC power amplifier, characterized in that: include: A power distribution unit, a power synthesis unit and two symmetrically arranged power amplification units; The two power amplifying units are arranged in parallel, the input ends of the two power amplifying units are respectively connected to the power distribution unit, and the output ends of the two power amplifying units are respectively connected to the power synthesis unit; The two power amplification units each include a first-stage amplification circuit, a second-stage amplification circuit and a third-stage amplification circuit, and a gradient impedance transformation structure is connected between the first-stage amplification circuit and the second-stage amplification circuit, and between the second-stage amplification circuit and the third-stage amplification circuit respectively; The first-stage amplifier circuit includes a first transistor, the second-stage amplifier circuit includes a second transistor and a third transistor, the second transistor and the third transistor are arranged in parallel, the third-stage amplifier circuit includes a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor, the fourth transistor and the fifth transistor are arranged in parallel, and the sixth transistor and the seventh transistor are arranged in parallel; The drains of the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor are connected with nF-level multilayer capacitors; Sources of the fourth transistor and the fifth transistor are connected to the ground in parallel, and sources of the sixth transistor and the seventh transistor are connected to the ground in parallel.

2. The K-band high linearity MMIC power amplifier according to claim 1, characterized in that: The gate of the first transistor is connected to the power distribution unit, the source of the first transistor is grounded, the drain of the first transistor is connected to the first capacitor, the first capacitor is grounded, and the drain of the first transistor is connected to the gradient impedance transformation structure; The gate of the second transistor is connected to the output end of the gradient impedance transformation structure connected to the first transistor, the source of the second transistor is grounded, the drain of the second transistor is connected to the second capacitor, the second capacitor is grounded, and the drain of the second transistor is connected to the gradient impedance transformation structure; The fourth transistor and the fifth transistor are arranged in parallel, the gate of the fourth transistor is connected to the output end of the gradient impedance transformation structure connected to the second transistor, the drain of the fourth transistor is connected to the third capacitor, and the third capacitor is grounded; The gate of the fifth transistor is connected to the output end of the gradient impedance transformation structure connected to the second transistor, the drain of the fifth transistor is connected to the fourth capacitor, and the fourth capacitor is grounded; The third transistor, the sixth transistor and the seventh transistor are respectively arranged symmetrically with the second transistor, the fourth transistor and the fifth transistor.

3. The K-band high linearity MMIC power amplifier according to claim 2, characterized in that: The gradient impedance transformation structure comprises a first impedance transformation structure and a second impedance transformation structure, wherein the first impedance transformation structure and the second impedance transformation structure are connected in series; The drain of the first transistor is connected to one of the first impedance transformation structures, and the second impedance transformation structure corresponding to the first impedance transformation structure connected to the drain of the first transistor is respectively connected to the gate of the second transistor and the gate of the third transistor; The drain of the second transistor is connected to another of the first impedance transformation structures, and the second impedance transformation structure corresponding to the first impedance transformation structure connected to the drain of the second transistor is respectively connected to the gate of the fourth transistor and the gate of the fifth transistor; The drain of the third transistor is connected to the third of the first impedance transformation structures, and the second impedance transformation structures corresponding to the first impedance transformation structure connected to the drain of the third transistor are respectively connected to the gate of the sixth transistor and the gate of the seventh transistor.

4. The K-band high linearity MMIC power amplifier according to claim 2, characterized in that: A balancing resistor is connected between the gate of the second transistor and the gate of the third transistor, a balancing resistor is connected between the drain of the second transistor and the drain of the third transistor, a balancing resistor is connected between the gate of the fourth transistor and the gate of the fifth transistor, a balancing resistor is connected between the drain of the fourth transistor and the drain of the fifth transistor, a balancing resistor is connected between the gate of the sixth transistor and the gate of the seventh transistor, and a balancing resistor is connected between the drain of the sixth transistor and the drain of the seventh transistor.

5. The K-band high linearity MMIC power amplifier according to claim 2, characterized in that: A bias circuit is provided before the gates of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor, respectively. The bias circuit includes a first branch and a second branch connected in parallel.

6. The K-band high linearity MMIC power amplifier according to claim 5, characterized in that: The first branch includes a fifth capacitor, and the fifth capacitor is grounded; The second branch includes a resistor and a sixth capacitor connected in series, and the resistor is grounded.

7. The K-band high linearity MMIC power amplifier according to claim 1, characterized in that: The operating range of the K-band high linearity MMIC power amplifier is 17-22 GHz.

8. The K-band high linearity MMIC power amplifier according to claim 1, characterized in that: The power distribution unit and the power synthesis unit both include a 3dB high-power Lange coupler.

9. The K-band high linearity MMIC power amplifier according to claim 8, characterized in that: Two 100Ω resistors are connected in parallel to the isolation port of the Lange coupler of the power synthesis unit.

10. The K-band high linearity MMIC power amplifier according to claim 1, characterized in that: It adopts 7mm×7mm surface mount leadless ceramic tube package, and the dust and water resistance level of the package is greater than or equal to IP66.

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