Jitter circuit and active laser rangefinder

Abstract

The present application discloses a jitter circuit, characterized in that it comprises: N phase delay line units, used to output N delayed signals respectively according to a trigger input signal, and the N delayed signals are delayed by 1 to N delay times Td respectively; N phase selection circuits, used to receive the N delayed signals, and select one of the N delayed signals as a trigger output signal according to a phase selection control signal; and an M-bit counter circuit, used to increase a count by one after receiving the trigger output signal each time, and output the phase selection control signal to the N phase selection circuit according to the count, wherein the count reaches 2. M After that, the count is reset and N is 2. M , M is a positive integer greater than one.

Description

Technical Field

[0001] The present application belongs to the technical field of electronic circuits and relates to a dither circuit for reducing distance quantization error during short-range distance measurement in a direct time of flight (DTOF) system. Background Art

[0002] Direct time of flight (DTOF) is a technology that determines the distance of an object by directly calculating the time it takes for a modulated laser pulse signal of a specific wavelength to be reflected from the surface of the object. When using a single photon collapse diode (spad) as a short-range ranging detector, due to the pile up effect, the higher the laser signal intensity, the narrower the width. Therefore, in a fixed time bin, the signal may be so narrow that there is only one photon count in a time bin, which will cause a large quantization error when the system resolves the distance.

[0003] In order to correct the error caused by the pulse effect during close-range distance measurement, it is necessary to obtain the difference between the measured distance and the actual distance at different distances and use this to correct the error. To obtain higher accuracy, more sampling points are required, so the test target needs to be moved more times. The above approach will undoubtedly consume more calibration time and affect production efficiency.

[0004] Therefore, there is an urgent need for a test target that does not need to be moved a large number of times, so as to reduce the distance quantization error caused by the pile-up effect when providing close-range distance measurement. Summary of the invention

[0005] The present application is to provide a jitter circuit and an active laser rangefinder to solve the deficiencies in the prior art, and the purpose is to reduce the quantization error of the direct time-of-flight sensor when measuring the distance at close range.

[0006] In order to achieve the above purpose, this application adopts the following technical solutions:

[0007] According to an embodiment of the present application, a jitter circuit is provided, characterized in that it includes: N phase delay line units, used to output N delayed signals according to a trigger input signal, respectively, and the N delayed signals are delayed by 1 to N delay times Td respectively; N phase selection circuits, used to receive the N delayed signals, and select one of the N delayed signals as a trigger output signal according to a phase selection control signal; and an M-bit counter circuit, used to increase a count by one after each reception of the trigger output signal, and output the phase selection control signal to the N phase selection circuit according to the count, wherein the count reaches 2 M After that, the count is reset and N is 2. M , M is a positive integer greater than one.

[0008] Preferably, in order to implement the N-phase delay line unit, it is characterized in that the N-phase delay line unit includes N buffer circuits connected in series with each other, the first buffer circuit of the N buffer circuits is used to receive the trigger input signal, and the i-th buffer circuit of the N buffer circuits is used to output the i-th delayed signal of the N delayed signals, wherein the i-th delayed signal is delayed by i times the delay time Td of the trigger input signal, and i is a positive integer between 1 and N.

[0009] Preferably, in order to set the delay time Td, the N buffer circuits adjust the delay time Td according to a delay adjustment signal load_adj.

[0010] Preferably, in order to allow the feedback count to have an appropriate delay, the invention further comprises a delay circuit for receiving the trigger output signal from the N-phase selection circuit and outputting the trigger output signal to the M-bit counter circuit after delay.

[0011] Preferably, in order to allow the feedback count to have an appropriate delay, the delay circuit delays the trigger output signal for a time greater than the delay time Td.

[0012] Preferably, in order to allow the M-bit counter circuit to cycle with a smaller count, the M-bit counter circuit receives a count of 2. m Enable signal, so that the count reaches 2 m The count is then reset, where m is a positive integer greater than one and less than M.

[0013] Preferably, in order to allow the jitter circuit to switch in turn in different counting modes, it is characterized in that the M-bit counter circuit is set in turn in 2 m Counting mode with 2 M Counting mode.

[0014] Preferably, in order to allow the dithering circuit to operate in a non-dithering mode, it is characterized in that it further includes a dithering mode selection circuit, which includes a selection circuit for receiving the trigger input signal and another input signal. When the selection circuit receives an enable signal trim_en indicating that the trigger input signal is selected, the selection circuit outputs the trigger input signal to the N-phase delay line unit. When the selection circuit receives an enable signal trim_en indicating that a signal other than the trigger input signal is selected, the selection circuit outputs the other input signal to the N-phase delay line unit.

[0015] Preferably, in order to allow the jitter circuit to operate in the ring oscillation mode, it is characterized in that the jitter mode selection circuit further includes an AND logic gate for receiving one of the N delayed signals output from the N phase selection circuit and an oscillation enable signal osc_en, and the output of the AND logic gate is the other input signal of the selection circuit.

[0016] According to an embodiment of the present application, an active laser rangefinder is provided, characterized by comprising: the jitter circuit as described above; and a direct time-of-flight sensor for performing measurement according to the trigger output signal.

[0017] Due to the adoption of the above scheme, the beneficial effects of the present application are as follows: the present invention provides a method for reducing the ranging quantization error, a fixed delay is added to the signal transmitting end of the optical ranging instrument, and the distribution of the counting points of the time to digital converter (TDC) is changed after the signal is transmitted to the receiving end, so that the counting points are evenly distributed on the time bin, which can improve the ranging quantization error affected by the pile-up effect during close-range ranging. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 FIG. 1 is a block diagram of a dithering circuit 100 according to an embodiment of the present application, which is used to reduce a ranging quantization error in a direct flight system.

[0019] Figure 2 FIG. 1 is a circuit diagram of an N-phase delay line circuit unit 120 according to an embodiment of the present application.

[0020] Figure 3 FIG. 1 is a circuit diagram of a dithering mode selection circuit 110 according to an embodiment of the present application.

[0021] Figure 4 FIG. 1 is a circuit diagram of an N-phase selection circuit 130 according to an embodiment of the present application.

[0022] Figure 5 FIG. 4 is a frequency diagram of a trigger input signal trigger_in and a trigger output signal trigger_out according to an embodiment of the present application.

[0023] Figure 6 FIG. 4 is a frequency diagram of laser cycles in a non-dithering mode and a dithering mode according to an embodiment of the present application.

[0024] Figure 7 Based on Figure 6 The delays shown are based on a statistical plot of the delays for consecutive laser cycles.

[0025] Fig. 8A This is the histogram in non-dithering mode.

[0026] Figure 8B This is the histogram in dithering mode.

[0027] Fig. 9A Schematic diagram of the direct arrival time and centroid average time of the reference signal in non-jitter mode.

[0028] Fig. 9B Schematic diagram of the direct arrival time and centroid average time of the reference signal in the jitter mode. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other implementation methods obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0030] The terms "first", "second", "third", etc. (if any) in the specification and claims of this application and the drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the objects described in these descriptions can be interchanged where appropriate. In the description of this application, "plurality" means two or more, unless otherwise clearly and specifically defined. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or in one or more hardware circuits or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0031] In the description of the present application, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0032] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two components or the interaction relationship between two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0033] In order to make the purpose, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with drawings and specific implementation methods.

[0034] The present invention provides a method for reducing the ranging quantization error. A fixed delay is added to the signal transmitting end of an optical ranging instrument. After the signal is transmitted to the receiving end, the counting point distribution of a time to digital converter (TDC) is changed, so that the counting points are evenly distributed on the time bin. The ranging quantization error caused by the pile-up effect during short-distance ranging can be improved.

[0035] Please refer to Figure 1 As shown, it is a block diagram of a dither circuit 100 according to an embodiment of the present application, which is used to reduce the ranging quantization error in a direct flight system. The dither circuit 100 can be applied to an optical ranging instrument of a direct flight system. The dither circuit 100 can include a dither mode selection circuit 110, an N-phase delay line circuit unit 120, an N-phase selection circuit 130, a delay circuit 140 and an M-bit counter circuit 150, where N can be a positive integer 2 M , where M is a positive integer greater than 1. Figure 1 In the embodiment shown, M is 4 and N is 16. Therefore, the N-phase delay line circuit unit 120 has 16 phase delay circuits. The N-phase selection circuit 130 has 16 input ports for receiving the 16 phase delay signals output by the N-phase delay line circuit unit 120.

[0036] The M-bit counter circuit 150 has M bits. Figure 1 In the illustrated embodiment, the M-bit counter circuit 150 has 4 bits and can output a 4-bit phase selection control signal phase_ctrl<3:0> to the N-phase selection circuit 130 to select one of the N phases for output.

[0037] In one embodiment, the phase selection control signal output by the M-bit counter circuit 150 has M bits, and the values ​​of the phase selection control signals output in turn are from 1 to 2. M , that is, from 1 to N.

[0038] Those skilled in the art will appreciate that, although the present application is described in an example where N is 16 and M is 4, it can be applied to other embodiments. For example, it can be applied to an embodiment where N is 8 and M is 3, or it can be applied to an embodiment where N is 32 and M is 5.

[0039] The M-bit counter circuit 150 may also have more than one count conversion input signal. Figure 1 The 4-bit counter circuit 150 shown may have a count 4 enable input signal cnt4_en and a count 8 enable input signal cnt8_en. For example, when receiving the count 4 enable input signal cnt4_en, the M-bit counter circuit 150 sequentially outputs a phase selection control signal whose value is from 1 to 4. When receiving the count 8 enable input signal cnt8_en, the M-bit counter circuit 150 sequentially outputs a phase selection control signal whose value is from 1 to 8.

[0040] Generally speaking, the M-bit counter circuit 150 can have more than one count m conversion input signal, where m is a positive integer greater than 1 and less than M. When the M-bit counter circuit 150 receives the count m enable input signal, the M-bit counter circuit 150 will be converted into an m-bit counter circuit 150. In other words, the values ​​of the phase selection control signals outputted in turn are from 1 to 2. m When the m-bit counter circuit 150 does not receive any count m enable input signal, it can be restored to the M-bit counter circuit 150 .

[0041] In one embodiment, the M-bit counter circuit 150 can be set in a 2-bit to M-bit mode in turn. For example, Figure 1 The 4-bit counter circuit 150 shown can be set in a counting mode of 4, a counting mode of 8 and a counting mode of 16 in turn. When in the counting mode of 4, the 4-bit counter circuit 150 will sequentially and alternately output the phase selection control signal with a value of 0 to 3 to the N phase selection circuit 130. When in the counting mode of 8, the 4-bit counter circuit 150 will sequentially and alternately output the phase selection control signal with a value of 0 to 7 to the N phase selection circuit 130. When in the counting mode of 16, the 4-bit counter circuit 150 will sequentially and alternately output the phase selection control signal with a value of 0 to 15 to the N phase selection circuit 130. Accordingly, the N phase selection circuit 130 can alternately and cyclically output the trigger output signal trigger_out with 1 to 4, 1 to 8 and 1 to 16 phase delays.

[0042] The trigger output signal trigger_out outputted by the N-phase selection circuit 130 is inputted into the delay circuit 140. The delay circuit 140 delays the trigger output signal by a fixed period of time and then transmits the delayed trigger output signal to the M-bit counter circuit 150 for counting.

[0043] Please refer to Figure 2 , which is a circuit diagram of an N-phase delay line circuit unit 120 according to an embodiment of the present application. The N-phase delay line circuit unit 120 may include N buffer circuits 210-1 to 210-N connected in series in sequence. The delay Td of each buffer circuit 210 may be fixed and consistent.

[0044] like Figure 2 As shown, when N is 16, the N-phase delay line circuit unit 120 includes 16 buffer circuits 210-1 to 210-16 connected in series. The output signal of the i-th buffer circuit 210 is the Ph i signal, where i is a positive integer between 1 and N. Except for the last buffer circuit 210-N, the output signal Ph of each buffer circuit 210-i is i The N output signals of the N buffer circuits 210 are respectively output to the N phase selection circuits 130. For example, Ph i With Ph j The delay time of the output signal can be expressed as:

[0045] Ph j -Ph i =(ji)×T d (1≤i <j≤N)

[0046] exist Figure 1 and Figure 2 In the embodiment shown, the delay time Td of the buffer circuit 210 can be adjustable. The delay time Td of each buffer circuit 210 can be set by the delay adjustment signal load_adj. However, regardless of whether it is adjusted, the delay time Td of each buffer circuit 210 can be consistent. Figure 1 and Figure 2 The delay adjustment signal load_adj in the illustrated embodiment is three bits, but a person skilled in the art will appreciate that it is not necessarily three bits, and may be a delay adjustment signal of other lengths. Each buffer circuit 210 may have a default delay time Td. When no valid delay adjustment signal load_adj is received, each buffer circuit 210 delays the input signal by the default delay time Td.

[0047] The trigger output signal trigger_out output by the N phase selection circuit 130 generates a phase selection control signal and returns to the N phase selection circuit 130 through the operation of the delay circuit 140 and the M-bit counter 150. This delay time should correspond to the delay time Td of each buffer circuit 210. For example, when the M-bit counter circuit adopts a falling edge or a negative edge trigger counting, this delay time can be slightly greater than the delay time Td of each buffer circuit 210.

[0048] Please refer to Figure 3 As shown, it is a circuit diagram of a jitter mode selection circuit 110 according to an embodiment of the present application. The jitter mode selection circuit 110 is an optional module. In one embodiment, the jitter circuit 100 may not need the jitter mode selection circuit 110, but directly connect the trigger input signal to the N-phase delay line circuit unit 120. Figure 3 In the illustrated embodiment, the operation mode of the dithering mode selection circuit 110 can be adjusted by an enable signal trim_en.

[0049] The jitter mode selection circuit 110 includes a selection circuit 310, a first input terminal of the two inputs of the selection circuit 310 is a trigger input signal, and a second input terminal is an output signal from an AND logic gate 320. When the enable signal trim_en selects the trigger input signal, for example, when the logic bit of the enable signal trim_en is 0, the selection circuit 310 outputs the trigger input signal trigger_in from the first input terminal to the N-phase delay line circuit unit 120. In other words, the input of the jitter circuit 100 is the trigger input signal trigger_in, and the jitter circuit 100 is in the jitter mode.

[0050] The first input signal of the AND logic gate 320 comes from the last output signal of the N-phase delay line circuit unit 120, and the second input signal comes from the oscillation enable signal osc_en. The oscillation enable signal osc_en can come from the output of an oscillator or an oscillation circuit, or from a frequency signal. When the last output signal of the N-phase delay line circuit unit 120 and the oscillation enable signal osc_en are both high voltage or logic bit 1, the AND logic gate 320 will output a high voltage or logic bit 1 to the second input terminal of the selection circuit 310. Otherwise, the AND logic gate 320 will output a low voltage or logic bit 0 to the second input terminal of the selection circuit 310.

[0051] When the enable signal trim_en selects the output end of the AND logic gate 320, for example, when the logic bit of the enable signal trim_en is 1, the selection circuit 310 outputs the signal of the AND logic gate 320 from the second input end to the N-phase delay line circuit unit 120. In this case, the jitter circuit 100 is in the ring oscillation mode and can be used to test the delay time. By using the enable signal trim_en, it can be selected whether the jitter circuit 100 is in the jitter mode or the ring oscillation mode.

[0052] Please refer to Figure 4 As shown, it is a circuit diagram of the N phase selection circuit 130 according to an embodiment of the present application. Those skilled in the art can understand that in some embodiments, when N is 2 M When , the N phase selection circuit 130 can have M stages, and each stage is composed of a selection circuit that selects one of two. The control of the selection circuit of each stage is a signal corresponding to one bit of the above-mentioned phase selection control signal phase_ctrl. Figure 4 In the embodiment shown, when the first stage is composed of four-selection selection circuits 411 to 414, the control of the first stage selection circuits 411 to 414 is based on the signal corresponding to the lowest two bits of the above-mentioned phase selection control signal phase_ctrl, that is, phase_ctrl <1> and phase_ctrl <0> .

[0053] exist Figure 4 When the second stage shown is composed of two-choice selection circuits 421 and 422, the selection control of these two selection circuits 421 and 422 corresponds to the above-mentioned phase selection control signal phase_ctrl <2> .exist Figure 4 In the third stage, only one selector circuit 431 remains, and its selection control corresponds to the phase selection control signal phase_ctrl <3> The output of the last-stage selection circuit 431 is the trigger output signal trigger_out.

[0054] Specifically, when N is 16 and the M-bit counter circuit 150 outputs the phase selection control signal phase_ctrl<3:0>=b0000, the N-phase selection circuit 130 selects the Ph1 output signal as the trigger output signal trigger_out. After the trigger output signal trigger_out sequentially enters the delay circuit 140 and the M-bit counter circuit 150, the M-bit counter circuit 150 outputs the phase selection control signal phase_ctrl<3:0>=b0001, and the N-phase selection circuit 130 selects the Ph2 output signal as the trigger output signal trigger_out. And so on, until the M-bit counter circuit 150 outputs the phase selection control signal phase_ctrl<3:0>=b1111, completing the cycle of M being 4 or N being 16. Afterwards, the M-bit counter circuit 150 will output the phase selection control signal phase_ctrl<3:0>=b0000 when receiving the trigger output signal trigger_out next time.

[0055] Please refer to Figure 5 As shown, it is a frequency diagram of the trigger input signal trigger_in and the trigger output signal trigger_out according to an embodiment of the present application. When the trigger input signal trigger_in does not add any delay time Td, the rising edge of its trigger output signal trigger_out and the trigger input signal trigger_out will differ by a basic delay time Tori. When the trigger input signal trigger_in adds a delay time Td, the rising edge of its trigger output signal trigger_out and the trigger input signal will differ by Tori+Td. And so on.

[0056] Please refer to Figure 6 As shown, it is a frequency diagram of the laser cycle in the non-dithering mode and the dithering mode according to an embodiment of the present application. Figure 6 The above is the non-jitter mode, and the laser cycle corresponding to the trigger input signal trigger_in corresponds to the aforementioned basic delay time Tori. When the trigger input signal trigger_in is received at T0, the trigger output signal trigger_out is received at the next laser cycle T1. When the trigger input signal trigger_in is received at T1, the trigger output signal trigger_out is received at the next laser cycle T2. And so on.

[0057] exist Figure 6The one below is the jitter mode. After receiving the trigger input signal trigger_in at T0, the trigger output signal trigger_out will be received at time Tori+Td after the next laser cycle T1. When the trigger input signal trigger_in is received at T1, the trigger output signal trigger_out will be received at time Tori+2Td after the next laser cycle T2. And so on.

[0058] When the trigger input signal trigger_in is received at T16 or T0 of the next N cycles, the trigger output signal trigger_out is received at time Tori+Td after the next laser cycle T17 or T1 of the next N cycles. Figure 6 It mainly shows the different delay effects of non-dither mode and dither mode on the trigger input signal trigger_in.

[0059] Please refer to Figure 7 As shown, it is based on Figure 6 The delays shown are statistical plots of the delays for successive laser cycles. Figure 7 Therein, the effect of the delay loop can be seen when the M-bit counter circuit 150 is in 4-count, 8-count, and 16-count modes, respectively.

[0060] Please refer to Fig. 8A As shown in FIG. 1 , it is a histogram in non-jitter mode. When the time-to-digital converter TDC counts, due to the use of the trigger input signal trigger_in in non-jitter mode, its corresponding trigger output signal trigger_out makes the lighting time all in the same time bin. As a result, the histogram statistics during distance measurement are all distributed in the same time bin.

[0061] Please refer to Fig. 9A As shown in FIG. 1 , it is a schematic diagram of the direct arrival time and the centroid average time of the reference signal in the non-jitter mode. Fig. 9A Among them, since the centroid distribution shows a gradient, its quantization error is relatively large.

[0062] Please refer to Figure 8B As shown in FIG. 1 , it is a histogram in the dither mode. When the time-to-digital converter TDC counts, due to the use of the dither mode trigger input signal trigger_in, its corresponding trigger output signal trigger_out will have multiple different delay times, so that the lighting time is in multiple time bins. Therefore, the histogram statistics during distance measurement will be distributed in different adjacent time bins. Therefore, using multiple time bins to solve the distance will obtain a better quantization error.

[0063] For example, in Figure 8B In the embodiment of , the histogram spans five time bins. Then the leftmost and rightmost time bins can be ignored, and the distance can be estimated by counting the three middle time bins, which will get a better quantization error.

[0064] Please refer to Fig. 9B As shown in FIG. 1 , it is a schematic diagram of the direct arrival time and the centroid average time of the reference signal in the jitter mode. Fig. 9B Among them, since the centroid distribution is linear, its quantization error is small.

[0065] According to an embodiment of the present application, a jitter circuit is provided, characterized in that it includes: N phase delay line units, used to output N delayed signals according to a trigger input signal, respectively, and the N delayed signals are delayed by 1 to N delay times Td respectively; N phase selection circuits, used to receive the N delayed signals, and select one of the N delayed signals as a trigger output signal according to a phase selection control signal; and an M-bit counter circuit, used to increase a count by one after each reception of the trigger output signal, and output the phase selection control signal to the N phase selection circuit according to the count, wherein the count reaches 2 M After that, the count is reset and N is 2. M , M is a positive integer greater than one.

[0066] Preferably, in order to implement the N-phase delay line unit, it is characterized in that the N-phase delay line unit includes N buffer circuits connected in series with each other, the first buffer circuit of the N buffer circuits is used to receive the trigger input signal, and the i-th buffer circuit of the N buffer circuits is used to output the i-th delayed signal of the N delayed signals, wherein the i-th delayed signal is delayed by i times the delay time Td of the trigger input signal, and i is a positive integer between 1 and N.

[0067] Preferably, in order to set the delay time Td, the N buffer circuits adjust the delay time Td according to a delay adjustment signal load_adj.

[0068] Preferably, in order to allow the feedback count to have an appropriate delay, the invention further comprises a delay circuit for receiving the trigger output signal from the N-phase selection circuit and outputting the trigger output signal to the M-bit counter circuit after delay.

[0069] Preferably, in order to allow the feedback count to have an appropriate delay, the delay circuit delays the trigger output signal for a time greater than the delay time Td.

[0070] Preferably, in order to allow the M-bit counter circuit to cycle with a smaller count, the M-bit counter circuit receives a count of 2.m Enable signal, so that the count reaches 2 m The count is then reset, where m is a positive integer greater than one and less than M.

[0071] Preferably, in order to allow the jitter circuit to switch in turn in different counting modes, it is characterized in that the M-bit counter circuit is set in turn in 2 m Counting mode with 2 M Counting mode.

[0072] Preferably, in order to allow the dithering circuit to operate in a non-dithering mode, it is characterized in that it further includes a dithering mode selection circuit, which includes a selection circuit for receiving the trigger input signal and another input signal. When the selection circuit receives an enable signal trim_en indicating that the trigger input signal is selected, the selection circuit outputs the trigger input signal to the N-phase delay line unit. When the selection circuit receives an enable signal trim_en indicating that a signal other than the trigger input signal is selected, the selection circuit outputs the other input signal to the N-phase delay line unit.

[0073] Preferably, in order to allow the jitter circuit to operate in the ring oscillation mode, it is characterized in that the jitter mode selection circuit further includes an AND logic gate for receiving one of the N delayed signals output from the N phase selection circuit and an oscillation enable signal osc_en, and the output of the AND logic gate is the other input signal of the selection circuit.

[0074] According to an embodiment of the present application, an active laser rangefinder is provided, characterized by comprising: the jitter circuit as described above; and a direct time-of-flight sensor for performing measurement according to the trigger output signal.

[0075] The jitter circuit and active laser rangefinder provided by the present application can reduce the quantization error of the distance measurement by the direct time-of-flight sensor when measuring the distance at close range. The present invention provides a method for reducing the quantization error of the distance measurement, adding a fixed delay to the signal transmitting end of the optical distance measuring instrument, and changing the distribution of the count points of the time to digital converter (TDC) after transmission to the receiving end, so that the count points are evenly distributed on the time bin, which can improve the distance measurement quantization error affected by the pile-up effect when measuring the distance at close range.

[0076] The above is only a preferred specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can make equivalent substitutions or changes within the technical scope disclosed in the present application according to the technical solution and application concept of the present application, which should be covered by the protection scope of the present application.

Claims

1. A jitter circuit, characterized in that: Include: N phase delay line units, used to output N delayed signals according to the trigger input signal, and the N delayed signals are delayed by 1 to N delay times Td respectively; N phase selection circuits, used for receiving the N delayed signals and selecting one of the N delayed signals as a trigger output signal according to a phase selection control signal; as well as The M-bit counter circuit is used to increase a count by one each time after receiving the trigger output signal, and output the phase selection control signal to the N-phase selection circuit according to the count, wherein the count reaches 2 M After that, the count is reset and N is 2. M , M is a positive integer greater than one.

2. The jitter circuit according to claim 1, characterized in that: The N-phase delay line unit includes N buffer circuits connected in series, the first buffer circuit of the N buffer circuits is used to receive the trigger input signal, and the i-th buffer circuit of the N buffer circuits is used to output the i-th delayed signal of the N delayed signals, wherein the i-th delayed signal is delayed by i times the delay time Td of the trigger input signal, and i is a positive integer between 1 and N.

3. The jitter circuit according to claim 2, characterized in that: The N buffer circuits adjust the delay time Td according to a delay adjustment signal load_adj.

4. The jitter circuit according to claim 1, characterized in that: It further comprises a delay circuit for receiving the trigger output signal from the N-phase selection circuit and outputting the trigger output signal to the M-bit counter circuit after delay.

5. The jitter circuit according to claim 1, wherein: The delay circuit delays the trigger output signal for a time greater than the delay time Td.

6. The jitter circuit according to claim 1, characterized in that: The M-bit counter circuit receives the count 2 m Enable signal, so that the count reaches 2 m The count is then reset, where m is a positive integer greater than one and less than M.

7. The jitter circuit according to claim 6, characterized in that: The M-bit counter circuit is set in turn at 2 m Counting mode with 2 M Counting mode.

8. The jitter circuit according to claim 1, characterized in that: It further includes a jitter mode selection circuit, which includes a selection circuit for receiving the trigger input signal and another input signal. When the selection circuit receives an enable signal trim_en indicating that the trigger input signal is selected, the selection circuit outputs the trigger input signal to the N-phase delay line unit. When the selection circuit receives an enable signal trim_en indicating that a signal other than the trigger input signal is selected, the selection circuit outputs the other input signal to the N-phase delay line unit.

9. The jitter circuit according to claim 8, characterized in that: The jitter mode selection circuit further includes an AND logic gate for receiving one of the N delayed signals output from the N phase selection circuit and an oscillation enable signal osc_en, and the output of the AND logic gate is the other input signal of the selection circuit.

10. An active laser rangefinder, characterized in that: It comprises: a jitter circuit as claimed in any one of claims 1 to 9; and a direct time-of-flight sensor for measuring according to the trigger output signal.

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