Radio frequency switching circuit and method of operating radio frequency switching circuit
By designing multiple switches and switch control circuits in the RF switch circuit, the RSE problem caused by the deterioration of isolation characteristics between antennas in multi-mode, multi-band wireless communication systems is solved, and efficient signal isolation and low power consumption are achieved.
Patent Information
- Application Number
- CN202410646675.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-10-06
- Filing Date
- 2024-05-23
- Publication Date
- 2025-04-08
AI Technical Summary
In a multi-mode and multi-band wireless communication system, when multiple front-end modules share one antenna, the isolation characteristics between the antennas deteriorate, resulting in the problem that signals are transmitted to adjacent antennas and radiated spurious emissions (RSEs).
A radio frequency (RF) switching circuit is designed, including four switches and switch control circuits. In low power mode, the switch control circuit disconnects the first switch, the second switch and the third switch and turns on the fourth switch to reduce current consumption. In isolation mode, turn on the third switch and turn off the other switches to improve signal isolation.
Through this design, the occurrence of RSE is reduced, the isolation characteristics between antennas are improved, current consumption is reduced, and the current specifications of low power mode are met.
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Figure CN119788046A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to radio frequency (RF) switching circuits and methods of operating RF switching circuits. Background Art
[0002] In wireless communication systems, an RF switch within a front end module (FEM) may be located at an end of the FEM and may be placed close to an antenna.
[0003] In a wireless communication system supporting multi-mode and multi-band, multiple FEMs may share one antenna, and as the integration level increases, the isolation characteristics between antennas deteriorate, so that signals are transmitted to adjacent antennas and radiated spurious emissions (RSE) may be generated from the RF switches connected to the adjacent antennas or the RF switches within the FEM.
[0004] The above information is presented as background information only to assist in understanding the present disclosure. No determination has been made, and no assertion is made, as to whether any of the above may be applicable as prior art with respect to the present disclosure. Summary of the invention
[0005] This Summary is provided to introduce a selection of concepts in a simplified form that are further described in the Detailed Description below. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
[0006] In one general aspect, a radio frequency (RF) switching circuit includes: a first switch connected between a first port and an antenna port; a second switch connected between the second port and the antenna port; a third switch connected between the antenna port and ground; a fourth switch connected between the antenna port and ground; and a switch control circuit configured to control the first switch, the second switch, and the third switch to be disconnected and the fourth switch to be turned on in a low power mode.
[0007] The switch control circuit may be configured to turn on the third switch and turn off the first switch, the second switch, and the fourth switch in the isolation mode.
[0008] The switch control circuit may include: a first driver, configured to select one of a first voltage and a second voltage generated from a first power supply according to a first control signal, and output the selected voltage to the first switch; a second driver, configured to select one of the first voltage and the second voltage according to the first control signal, and output the selected voltage to the second switch; a third driver, configured to select one of the first voltage and the second voltage according to the first control signal, and output the selected voltage to the third switch; and a fourth driver, configured to output one of a third voltage generated from a second power supply different from the first power supply and a fourth voltage generated from the first power supply to the fourth switch according to the second control signal.
[0009] The second control signal may include a first voltage, and the first voltage may be set to 0V in the low power mode.
[0010] The switch control circuit may further include: a low dropout (LDO) circuit configured to generate a first voltage from a first power source; and a charge pump circuit configured to generate a second voltage lower than the first voltage from the first voltage.
[0011] The third voltage may be lower than the first voltage, and the second power supply may be a continuous power supply.
[0012] The fourth driver may include: a first transistor, configured to provide a third voltage as a turn-on voltage to the fourth switch through an output terminal, wherein the first transistor may have a control terminal for receiving a second control signal; and a second transistor, configured to provide a fourth voltage as a turn-off voltage to the fourth switch through the output terminal, wherein the second transistor may have a control terminal connected to ground.
[0013] The fourth driver may also include: a third transistor connected between the first transistor and the output terminal, wherein the third transistor may have a control terminal connected to ground and may be configured to be turned on when the first transistor is turned on; and a fourth transistor connected between the second transistor and the output terminal, wherein the fourth transistor may have a control terminal connected to ground and may be configured to be turned on when the second transistor is turned on.
[0014] The switch control circuit may be configured to turn on the first switch and turn off the second, third, and fourth switches in a reception mode, and turn on the second switch and turn off the first, third, and fourth switches in a transmission mode.
[0015] In another general aspect, a method of operating a radio frequency (RF) switching circuit includes: in a receiving mode, turning on a first switch connected between a first port and an antenna port to receive a signal from the antenna port; in a transmitting mode, turning off the first switch and turning on a second switch connected between a second port and the antenna port to transmit a signal to the antenna port; in an isolation mode, turning off the first switch and the second switch and turning on a third switch connected between the antenna port and ground to terminate the antenna port; and in a low power mode, turning off the first switch, the second switch, and the third switch and turning on a fourth switch connected between the antenna port and ground to terminate the antenna port.
[0016] The method may further include opening the fourth switch in the isolation mode.
[0017] The method may also include: according to the first control signal, respectively turning on or off the first switch, the second switch and the third switch by providing one of a first voltage and a second voltage generated from a first power supply to the first switch, the second switch and the third switch; and according to the second control signal, turning on or off the fourth switch by providing one of a third voltage generated from a second power supply different from the first power supply and a fourth voltage generated from the first power supply.
[0018] The second control signal may include a first voltage, and the first voltage may be set to 0V in the low power mode.
[0019] The third voltage may be lower than the first voltage.
[0020] In another general aspect, a radio frequency (RF) switching circuit includes: a first switch connected between a first port and an antenna port; a second switch connected between the second port and the antenna port; a third switch connected between the antenna port and ground; a fourth switch connected between the antenna port and ground; and a switch control circuit configured to control the first switch, the second switch, and the third switch to be disconnected using a first power supply in a low power mode, and to control the fourth switch to be turned on using a second power supply different from the first power supply.
[0021] The switch control circuit may be configured to turn off the first switch, the second switch, and the fourth switch and turn on the third switch using the first power source in the isolation mode.
[0022] The switch control circuit may be configured to turn on the first switch using the first power source and turn off the second switch, the third switch, and the fourth switch in the reception mode.
[0023] The switch control circuit may be configured to turn on the second switch using the first power source and turn off the first switch, the third switch, and the fourth switch in the transmission mode.
[0024] The switch control circuit may include: a first driver, configured to select one of a first voltage and a second voltage generated from a first power supply according to a first control signal, and output the selected voltage to the first switch; a second driver, configured to select one of the first voltage and the second voltage according to the first control signal, and output the selected voltage to the second switch; a third driver, configured to select one of the first voltage and the second voltage according to the first control signal, and output the selected voltage to the third switch; and a fourth driver, configured to output one of a third voltage generated from the second power supply and a fourth voltage generated from the first power supply to the fourth switch according to the second control signal.
[0025] Other features and aspects will be apparent from the following detailed description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 and Figure 2 is a diagram showing an example of an RF switch used in a wireless communication system.
[0027] Figure 3 It is shown Figure 1 or Figure 2 An example of a FEM is shown in the figure.
[0028] Figure 4 is a diagram showing an example of an RF switch circuit according to an embodiment.
[0029] Figure 5 It is shown in Figure 4 The state of each switch during the operating mode of the RF switch circuit is shown in the diagram.
[0030] Figure 6 It is shown Figure 4 An example of a switch control circuit is shown in FIG.
[0031] Figure 7 It shows that according to Figure 4 The operation modes of the RF switch circuit are shown in the diagram of the control signals of the driver 117 and the operation states of the charge pump circuit.
[0032] Figure 8 It is shown Figure 4 An example of a switch control circuit is shown in FIG.
[0033] Fig. 9 yes Figure 6 A circuit diagram of the driver 115 is shown in FIG.
[0034] Fig.10 is a diagram showing an example of an RF switch circuit according to another embodiment.
[0035] Fig.11 It shows that according to Fig.10 2 is a diagram of an example of an operation mode of the RF switch circuit, a control signal of the driver 115 and an operation state of the charge pump circuit shown in FIG.
[0036] Fig.12 It is shown in Fig.10 The state of each switch during the operating mode of the RF switch circuit is shown in the diagram.
[0037] Fig.13 yes Figure 6 A circuit diagram of the driver 117 is shown in FIG.
[0038] Throughout the drawings and detailed description, unless otherwise described, the same reference numerals refer to the same elements. For clarity, illustration, and convenience, the drawings may not be drawn to scale, and the relative sizes, proportions, and descriptions of the elements in the drawings may be exaggerated. DETAILED DESCRIPTION
[0039] Hereinafter, although examples of the present disclosure will be described in detail with reference to the accompanying drawings, it should be noted that the examples are not limited thereto.
[0040] The following specific embodiments are provided to help the reader gain a comprehensive understanding of the methods, devices, and / or systems described herein. However, various changes, modifications, and equivalents of the methods, devices, and / or systems described herein will be apparent after understanding the present disclosure. For example, the order of operations described herein is merely an example and is not limited to the order set forth herein, but may be changed as will be apparent after understanding the present disclosure, except for operations that must occur in a certain order. In addition, descriptions of features known in the art may be omitted for clarity and brevity.
[0041] The features described herein may be implemented in different forms and are not to be construed as being limited to the examples described herein. Rather, the examples described herein are provided only to illustrate some of the many possible ways to implement the methods, devices, and / or systems described herein that will be apparent after understanding the present disclosure.
[0042] Throughout the specification, when an element (such as a layer, a region, or a substrate) is described as being “on”, “connected to”, or “coupled to” another element, it may be directly “on”, directly “connected to”, or directly “coupled to” the other element, or one or more other elements may be present between them. Conversely, when an element is described as being “directly” “on”, “directly connected to”, or “directly coupled to” another element, there are no other elements present between them.
[0043] As used herein, the term "and / or" includes any one of the associated listed items and any combination of any two or more of the associated listed items; similarly, "at least one of..." includes any one of the associated listed items and any combination of any two or more of the associated listed items.
[0044] Although terms such as "first", "second", and "third" may be used herein to describe various members, components, regions, layers, or portions, these members, components, regions, layers, or portions are not limited by these terms. Instead, these terms are only used to distinguish one member, component, region, layer, or portion from another member, component, region, layer, or portion. Therefore, the first member, first component, first region, first layer, or first portion mentioned in the examples described herein may also be referred to as the second member, second component, second region, second layer, or second portion without departing from the teachings of the examples.
[0045] For ease of description, spatially relative terms such as "above", "upper", "below", "lower", etc. may be used herein to describe the relationship of one element to another element as shown in the drawings. In addition to the orientation depicted in the drawings, such spatially relative terms are intended to also include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, an element described as being "above" or "upper" relative to another element will then be "below" or "lower" relative to the other element. Therefore, the term "above" includes both the orientation of the above and below, depending on the spatial orientation of the device. The device may also be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative terms used herein will be interpreted accordingly.
[0046] The terms used herein are only used to describe various examples and are not used to limit the present disclosure. The words "a", "an" and "the" are intended to include plural forms as well, unless the context clearly indicates otherwise. The terms "include", "comprises" and "have" specify the presence of stated features, quantities, operations, components, elements and / or combinations thereof, but do not exclude the presence or addition of one or more other features, quantities, operations, components, elements and / or combinations thereof.
[0047] Due to manufacturing techniques and / or tolerances, the shapes shown in the drawings may vary. Therefore, the examples described herein are not limited to the specific shapes shown in the drawings but include shape variations that occur during manufacturing.
[0048] Herein, it is noted that the use of the term “may” with respect to an example, such as with respect to what an example may include or implement, means that there is at least one example that includes or implements this feature, and all examples are not limited thereto.
[0049] As will be apparent after understanding the present disclosure, the features of the examples described herein may be combined in various ways. In addition, although the examples described herein have multiple configurations, other configurations are also possible, as will be apparent after understanding the present disclosure.
[0050] Throughout the specification, RF signals include Wi-Fi (IEEE 802.11 series, etc.), WiMAX (IEEE 802.16 series, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed Packet Access + (HSPA+), High Speed Downlink Packet Access + (HSDPA+), High Speed Uplink Packet Access + (HSUPA+), Enhanced Data GSM Evolution (EDGE), Global System for Mobile Communications (GSM), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, third generation (3G), fourth generation (4G), fifth generation (5G), and any other wireless and wired protocols specified hereafter, but are not limited to these.
[0051] One or more of the embodiments may provide an RF switching circuit and method of operating an RF switching circuit that may reduce radiated spurious emissions (RSE).
[0052] Figure 1 and Figure 2 is a diagram showing an example of an RF switch used in a wireless communication system.
[0053] Reference Figure 1 , in a wireless communication system, a plurality of front end modules (FEMs) 10 and 20 may be connected to one antenna 30 .
[0054] The RF switch 40 may connect one FEM among the plurality of FEMs 10 and 20 to the antenna 30 .
[0055] and Figure 1 Different, refer to Figure 2 , the plurality of FEMs 50 and 60 may be connected to the plurality of antennas 70 and 80, respectively.
[0056] Figure 3 It is shown Figure 1 or Figure 2 An example of a FEM is shown in FIG. Figure 3 It is shown in Figure 1 The FEM10 shown in Figure 1 FEM 20 or Figure 2 The FEM 50 and 60 shown in FIG. can also be used with Figure 3The FEM 10 shown in FIG. 1 is configured identically or similarly to that shown in FIG.
[0057] Reference Figure 3 , the FEM 10 may include a power amplifier (PA) 12 , a low noise amplifier (LNA) 14 , and an RF switch 16 .
[0058] The RF switch 16 can selectively connect to the PA 12 or the LNA 14 .
[0059] In a wireless communication system supporting multi-mode and multi-band, some of the multiple FEMs may share one antenna, such as Figure 1 As shown in , some of the multiple FEMs can be connected to different antennas respectively. Since multiple FEMs and multiple antennas having these connection structures are integrated, a signal transmitted from any one antenna may be transmitted to an adjacent antenna, and radiated spurious emissions (RSE) may be induced in an RF switch connected to an adjacent antenna or in an RF switch within the FEM and transmitted. Therefore, the antenna port connected to the RF switch can be designed to maintain 50 ohms in all cases.
[0060] Figure 4 is a diagram showing an example of an RF switch circuit according to an embodiment.
[0061] Reference Figure 4 , the RF switch circuit 100 may include a port P1_R, a port P2_T, a port P3, a switch S1, a switch S2, a switch S3, a switch S4, a switch S5, and a switch S6. The RF switch circuit 100 may also include a resistor R1 and a resistor R2. The RF switch circuit 100 may also include a switch control circuit 110.
[0062] Port P1_R may be a receiving port. Port P2_T may be a transmitting port. The path between port P3 and port P1_R may be a receiving path. The path between port P3 and port P2_T may be a transmitting path. Port P3 may be an output port or an antenna port for connecting to an antenna.
[0063] The switch S1 may be connected between the port P1_R and the port P3. The switch S3 may be connected between the port P1_R and the ground. The switch S1 and the switch S3 may operate complementarily. When the switch S1 is turned on, the switch S3 may be turned off, and when the switch S1 is turned off, the switch S3 may be turned on.
[0064] The switch S2 may be connected between the port P2_T and the port P3. The switch S4 may be connected between the port P2_T and the ground. The switch S2 and the switch S4 may operate complementarily. When the switch S2 is turned on, the switch S4 may be turned off, and when the switch S2 is turned off, the switch S4 may be turned on.
[0065] The switch S5 may be connected between the port P3 and the ground. The resistor R1 may be connected between the switch S5 and the ground.
[0066] The switch S6 may be connected between the port P3 and the ground. The resistor R2 may be connected between the switch S6 and the ground.
[0067] In low power mode, switches S1 to S5 may be turned off, and switch S6 may be turned on. In low power mode, the RF switch circuit 100 may minimize current consumption by disabling almost all internal circuit elements. However, only switch S6 may be turned on, and port P3 may be terminated at 50 ohms.
[0068] The switch S1 , the switch S2 , the switch S3 , the switch S4 , the switch S5 , and the switch S6 may be turned on or off according to a control signal output from the switch control circuit 110 .
[0069] The switch control circuit 110 may control the switching on and off of the switches S1 , S2 , S3 , S4 , S5 , and S6 according to an operation mode of the RF switch circuit 100 .
[0070] Figure 5 It is shown in Figure 4 The state of each switch during the operating mode of the RF switch circuit is shown in the diagram.
[0071] Reference Figure 5 , the operation modes of the RF switch circuit 100 may include an active mode and a low power mode.
[0072] The valid modes may include a reception mode RX, a transmission mode TX, and an isolation mode ISO.
[0073] In the receiving mode RX, the switch S1 and the switch S4 may be turned on, and the switch S2, the switch S3, the switch S5, and the switch S6 may be turned off. Therefore, the signal received through the port P3 may be output through the port P1_R.
[0074] In the transmission mode TX, the switch S2 and the switch S3 may be turned on, and the switch S1, the switch S4, the switch S5, and the switch S6 may be turned off. Therefore, a signal input through the port P2_T may be output to the port P3.
[0075] In the isolation mode ISO, the switches S3, S4, and S5 may be turned on, and the switches S1, S2, and S6 may be turned off. Therefore, when no signal is transmitted or received, the isolation between the transmission path and the reception path may be increased.
[0076] In low power mode, switches S1 to S5 may be opened, and switch S6 may be closed. Thus, port P3 may be terminated at 50 ohms in low power mode.
[0077] Figure 6 It is shown Figure 4 An example of a switch control circuit is shown in FIG.
[0078] Reference Figure 6 , the switch control circuit 110 can control Figure 4 Switches S1 to S6 are shown in FIG.
[0079] The switch control circuit 110 may include a low dropout (LDO) circuit 111 , a charge pump circuit 113 , a plurality of drivers 115 that control switches S1 to S5 , and a driver 117 that controls the switch S6 .
[0080] The LDO circuit 111 may generate a positive voltage VLDO lower than the battery voltage VBAT according to the battery voltage VBAT supplied from the battery power source, and may provide the positive voltage VLDO to the plurality of drivers 115 and the driver 117. In addition, the LDO circuit 111 may provide the positive voltage VLDO to the charge pump circuit 113. The positive voltage VLDO may be a voltage higher than a turn-on voltage of the switches S1 to S5.
[0081] The charge pump circuit 113 may generate a negative voltage VNEG1 by charge pumping the positive voltage VLDO according to the input clock signal CLK, and may provide the negative voltage VNEG1 to the plurality of drivers 115 and 117 .
[0082] The plurality of drivers 115 may generate control signals having a positive voltage VLDO or a negative voltage VNEG1 according to a control signal VC input from the outside, and may provide the control signals to the switches S1 to S5 , respectively.
[0083] The driver 117 may receive the positive voltage VLDO provided from the LDO circuit 111 as a control signal, may generate a control signal having a positive voltage VIO or a negative voltage VNEG1, and may provide it to the switch S6. The driver 117 may generate a control signal that turns on the switch S6 when the switches S1 to S5 are disconnected in the low power mode. The driver 117 may generate a control signal that turns on the switch S6 when the voltage VLDO becomes 0V. Here, the positive voltage VIO is a voltage provided from a continuous power supply different from the battery voltage VBAT, and may be lower than the voltage VLDO. Since the current consumption must be minimized in the low power mode, the driver 117 may control the switch S6 using the positive voltage VIO.
[0084] According to an embodiment, switch S6 can be turned on at a voltage lower than the voltage applied to switches S1 to S5. Switch S6 can be turned on by a positive voltage VIO to reduce current consumption. For example, the turn-on voltage of switches S1 to S5 can be 2.5V, while the turn-on voltage of switch S6 can be 1.8V, which is lower than 2.5V. At the same time, if a low turn-on voltage can be used, the turn-on resistance of the corresponding switch S6 can be increased. Therefore, the resistance value of the resistor R2 connected to switch S6 can be set according to the turn-on resistance of switch S6. According to an embodiment, the resistance value of resistor R2 can be set to a value that optimizes the performance of RSE reduction when switch S6 is turned on.
[0085] Figure 7 It shows that according to Figure 4 The operation mode of the RF switch circuit is shown in the diagram of the control signal of the driver 117 and the operation state of the charge pump circuit. Figure 7 , the sixth driver may represent driver 117 .
[0086] Reference Figure 7 , the charge pump circuit 113 may be set to an on state in the active mode, and may be set to an off state in the low power mode.
[0087] In the receiving mode RX in the active mode, the driver 117 may output the negative voltage VNEG1 as a control signal to turn off the switch S6 .
[0088] In the transmission mode TX in the active mode, the driver 117 may output the negative voltage VNEG1 as a control signal to turn off the switch S6 .
[0089] In the isolation mode ISO in the active mode, the driver 117 may output a negative voltage VNEG1 as a control signal to turn off the switch S6. Meanwhile, in the isolation mode ISO in the active mode, the switch S5 is turned on, so the signal input through the port P3 may be terminated at the ground through the switch S5.
[0090] In the low power mode, the driver 117 may output a positive voltage VIO as a control signal to turn on the switch S6. At this time, the switches S1 to S5 may be turned off.
[0091] Figure 8 It is shown Figure 4 An example of a switch control circuit is shown in FIG.
[0092] like Figure 8 As shown in , the off voltage of the switch S6 may be different from the off voltages of the switches S1 to S5. For example, the off voltage of the switch S6 may be a negative voltage VNEG2, while the off voltages of the switches S1 to S5 may be a negative voltage VNEG1.
[0093] In this case, with Figure 6 Differently, the switch control circuit 110 a may include a charge pump circuit 113 a generating a negative voltage VNEG1 and a charge pump circuit 113 b generating a negative voltage VNEG2 .
[0094] The charge pump circuit 113 a may generate a negative voltage VNEG1 by charge pumping a positive voltage VLDO generated by the LDO circuit 111 a according to the clock signal CLK1 , and may provide the negative voltage VNEG1 to a plurality of drivers 115 a that provide control signals to switches S1 to S5 .
[0095] The charge pump circuit 113b may generate a negative voltage VNEG2 by charge pumping the positive voltage VLDO according to the clock signal CLK2, and may provide the negative voltage VNEG2 to the driver 117a. The clock signal CLK2 may be the same as or different from the clock signal CLK1.
[0096] The plurality of drivers 115 a may each generate a control signal having a positive voltage VLDO or a negative voltage VNEG1 according to a control signal VC input from the outside, and may provide the generated control signal to the switches S1 to S5 .
[0097] The driver 117a may generate a control signal having a positive voltage VIO or a negative voltage VNEG2 according to a control signal VC_LPM input from the outside, and may provide the generated control signal to the switch S6. The control signal VC may be a control signal indicating one of a reception mode RX, a transmission mode TX, and an isolation mode ISO in an effective mode. The control signal VC_LPM may be a control signal indicating a low power mode.
[0098] Fig. 9 yes Figure 6 1 is a circuit diagram of one driver 115 among the multiple drivers 115 shown in FIG.
[0099] Reference Fig. 9 , the driver 115 may include a transistor F1 , a transistor F2 , a transistor F3 , a transistor F4 , an inverter 1151 , an inverter 1152 , and a capacitor C1 .
[0100] Transistor F1 may be a P-type FET, and transistor F2 may be an N-type FET. Transistor F3 may be the same type of FET as transistor F1, and transistor F4 may be the same type of FET as transistor F2.
[0101] The positive voltage VLDO may be applied from the LDO circuit 111 to the source terminal of the transistor F1 , the drain terminal of the transistor F1 may be connected to the source terminal of the transistor F3 , and the drain terminal of the transistor F3 may be connected to the node N1 .
[0102] Negative voltage VNEG1 may be applied to the source terminal of transistor F2, the drain terminal of transistor F2 may be connected to the source terminal of transistor F4, and the drain terminal of transistor F4 may be connected to node N1. The gate terminal (also referred to as the control terminal) of transistor F3 and the gate terminal of transistor F4 may be grounded. Node N1 may be an output terminal of driver 115.
[0103] The inverter 1151 may include an input terminal and an output terminal. The control signal VC may be input to the input terminal of the inverter 1151, and the output terminal of the inverter 1151 may be connected to the gate terminal of the transistor F1. The inverter 1151 may output a positive voltage VLDO or 0V through the output terminal according to the control signal VC.
[0104] The inverter 1152 may include an input terminal and an output terminal. The control signal VC may be input to the input terminal of the inverter 1152, and the output terminal of the inverter 1152 may be connected to the gate terminal of the transistor F2. The inverter 1152 may output 0V or a negative voltage VNEG1 through the output terminal according to the control signal VC.
[0105] When the control signal VC is at a high level (e.g., a positive voltage), the transistor F1 may be turned on, and the transistor F2 may be turned off. When the transistor F1 is turned on, the voltage difference between the gate terminal and the source terminal of the transistor F3 becomes a negative voltage, so the P-type transistor F3 may be turned on, and the positive voltage VLDO may be output as the control signal VS. The switches S1 to S5 may be turned on in response to the control signal VS having the positive voltage VLDO.
[0106] On the other hand, when the control signal VC is at a low level (e.g., 0V), the transistor F1 may be turned off, and the transistor F2 may be turned on. When the transistor F2 is turned on, the voltage difference between the gate terminal and the source terminal of the transistor F4 becomes a positive voltage, so the N-type transistor F4 may be turned on, and the negative voltage VNEG1 may be output as the control signal VS. The switches S1 to S5 may be turned off in response to the control signal VS having the negative voltage VNEG1.
[0107] The capacitor C1 may be connected between the node N1 and the ground, and may be used to stabilize the voltage of the node N1 .
[0108] According to an embodiment, the switch S5 may be connected between the port P3 and the ground, and the switch S6 may also be connected between the port P3 and the ground. Fig.10 As shown in , if only switch S5 exists among switches S5 and S6, then Fig.12 As shown in , a control signal of the driver 115 that controls the switch S5 according to the operation mode of the RF switch circuit can be output.
[0109] Fig.10 is a diagram showing an example of an RF switch circuit according to another embodiment, and Fig.12 It is shown in Fig.10 The state of each switch during the operating mode of the RF switch circuit is shown in the diagram.
[0110] like Fig.10 As shown in FIG. 1 , the RF switch circuit 100 a may have a structure without the switch S6 . That is, only the switch S5 may be connected between the port P3 and the ground.
[0111] like Fig.12 As shown in FIG. 1 , in the receiving mode RX, the RF switch circuit 100a may turn on switches S1 and S4 and may turn off switches S2, S3, and S5. Therefore, the signal received through the port P3 may be output through the port P1_R.
[0112] In the transmission mode TX, the RF switch circuit 100a may turn on the switches S2 and S3 and turn off the switches S1, S4, and S5. Therefore, a signal input through the port P2_T may be output to the port P3.
[0113] In the isolation mode ISO, the RF switch circuit 100a can turn on the switches S3, S4, and S5, and turn off the switches S1 and S2. Therefore, when no signal is transmitted or received, the isolation between the transmission path and the reception path can be increased.
[0114] In the low power mode, the RF switch circuit 100a may open switches S1 to S4 and close switch S5. Therefore, in the low power mode, the port P3 may be terminated at 50 ohms.
[0115] Fig.11 It shows that according to Fig.10 2 is a diagram of an example of an operation mode of the RF switch circuit, a control signal of the driver 115 and an operation state of the charge pump circuit shown in FIG.
[0116] Reference Fig.12Since the switch S5 is turned on in the isolation mode ISO in the low power mode as well as in the active mode, the driver 115 controlling the switch S5 can output the positive voltage VLDO as a control signal to turn on the switch S5 in the isolation mode ISO in the active mode, and can output the positive voltage VLDO as a control signal to turn on the switch S5 even in the low power mode. Fig.11 In FIG. 1 , the fifth driver may represent the driver 115 controlling the switch S5 .
[0117] In the low power mode, the charge pump circuit 113 has a disconnected state, so the voltage of the source terminal of the transistor F2 has an undefined voltage value instead of the negative voltage VNEG1. For example, if the voltage of the source terminal of the transistor F2 is higher than 0V in the low power mode, leakage current may flow to the ground of the inverter 1152. This makes it impossible to meet the current specification of the low power mode.
[0118] Therefore, according to this embodiment, in order to prevent the leakage current of the inverter 1152 in the low power mode, the RF switch circuit 100 may further include a switch S6 connected between the port P3 and the ground, such as Figure 4 as shown in .
[0119] As also described above, the switch S6 may be turned on with a lower positive voltage VIO than the positive voltage VLDO to minimize current consumption in the low power mode.
[0120] Fig.13 yes Figure 6 A circuit diagram of the driver 117 is shown in FIG.
[0121] Reference Fig.13 , the driver 117 may include a transistor F5, a transistor F6, a transistor F7, a transistor F8, an inverter 1171, an inverter 1172, and a capacitor C2.
[0122] Transistor F5 may be a P-type FET, and transistor F6 may be an N-type FET. Transistor F7 may be the same type of FET as transistor F5, and transistor F8 may be the same type of FET as transistor F6.
[0123] A positive voltage VIO as a continuous power source may be applied to a source terminal of transistor F5, a drain terminal of transistor F5 may be connected to a source terminal of transistor F7, and a drain terminal of transistor F7 may be connected to node N2.
[0124] Negative voltage VNEG1 may be applied to the source terminal of transistor F6, the drain terminal of transistor F6 may be connected to the source terminal of transistor F8, and the drain terminal of transistor F8 may be connected to node N2. The gate terminal of transistor F7 and the gate terminal of transistor F8 may be grounded. Node N2 may be an output terminal of driver 117.
[0125] The inverter 1171 may include an input terminal and an output terminal.
[0126] The inverter 1172 may include an input terminal and an output terminal.
[0127] The positive voltage VLDO may be input as a control signal to the input terminal of the inverter 1171, and the output terminal of the inverter 1171 may be connected to the input terminal of the inverter 1172. The output terminal of the inverter 1172 may be connected to the gate terminal of the transistor F5. The inverters 1171 and 1172 may output the positive voltage VIO or 0V through the output terminal according to the signal input to the input terminal.
[0128] When the voltage VLDO is 0V, that is, in low power mode, transistor F5 can be turned on. Since the charge pump circuit 113 is disconnected in low power mode, the voltage of the source terminal of transistor F6 has an undefined voltage value instead of the negative voltage VNEG1. Therefore, transistor F6 can be turned off. When transistor F5 is turned on, the voltage difference between the gate terminal and the source terminal of transistor F7 becomes a negative voltage, so the P-type transistor F7 can be turned on, and the positive voltage VIO can be output as the control signal VS. Switch S6 can be turned on in response to the control signal VS having the positive voltage VIO. That is, switch S6 can be turned on in low power mode.
[0129] When the voltage VLDO is greater than 0V, that is, in the active mode, the transistor F5 can be turned off, and the voltage difference between the gate terminal and the source terminal of the transistor F6 becomes a positive voltage, so the N-type transistor F6 can be turned on. When the transistor F6 is turned on, the voltage difference between the gate terminal and the source terminal of the transistor F8 becomes a positive voltage, so the N-type transistor F8 can also be turned on, and the negative voltage VNEG1 can be output as the control signal VS. The switch S6 can be disconnected in response to the control signal VS having the negative voltage VNEG1. That is, in the active mode, the switch S6 can be disconnected.
[0130] The capacitor C2 may be connected between the node N2 and the ground, and may be used to stabilize the voltage of the node N2 .
[0131] According to at least one of the embodiments, by improving the isolation characteristics between antennas in a wireless communication system supporting multi-band multi-mode, RSE caused by a signal being transmitted to an adjacent antenna can be reduced.
[0132] According to at least one of the embodiments, a current specification of a low power mode may be met by preventing a leakage current in a low power mode of an RF switch circuit.
[0133] Although specific examples have been shown and described above, it will be apparent after understanding the present disclosure that various changes in form and detail may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are considered to be illustrative only and not for limiting purposes. The description of the features or aspects in each example is considered to be applicable to similar features or aspects in other examples. Suitable results may also be obtained if the described techniques are performed in a different order, and / or if the components in the described systems, architectures, devices, or circuits are combined in different ways and / or replaced or supplemented by other components or their equivalents. Therefore, the scope of the present disclosure is not limited by specific embodiments, but by the claims and their equivalents, and all changes within the scope of the claims and their equivalents will be interpreted as included in the present disclosure.
Claims
1. A radio frequency (RF) switching circuit, comprising: A first switch connected between the first port and the antenna port; a second switch connected between the second port and the antenna port; a third switch connected between the antenna port and ground; a fourth switch connected between the antenna port and the ground; as well as The switch control circuit is configured to control the first switch, the second switch, and the third switch to be turned off and the fourth switch to be turned on in a low power mode.
2. The RF switch circuit according to claim 1, wherein: The switch control circuit is configured to turn on the third switch and turn off the first switch, the second switch, and the fourth switch in an isolation mode.
3. The RF switch circuit according to claim 2, wherein: The switch control circuit comprises: a first driver configured to select one of a first voltage and a second voltage generated from a first power source according to a first control signal and output the selected voltage to the first switch; a second driver configured to select one of the first voltage and the second voltage according to the first control signal and output the selected voltage to the second switch; a third driver configured to select one of the first voltage and the second voltage according to the first control signal and output the selected voltage to the third switch; and The fourth driver is configured to output one of a third voltage generated from a second power source different from the first power source and a fourth voltage generated from the first power source to the fourth switch according to a second control signal.
4. The RF switch circuit according to claim 3, wherein: The second control signal includes the first voltage, and In the low power mode, the first voltage is set to 0V.
5. The RF switch circuit according to claim 3, wherein: The switch control circuit further includes: a low voltage drop circuit configured to generate the first voltage from the first power supply; and The charge pump circuit is configured to generate the second voltage lower than the first voltage from the first voltage.
6. The RF switch circuit according to claim 3, wherein: The third voltage is lower than the first voltage, and The second power source is a continuous power source.
7. The RF switch circuit according to claim 3, wherein: The fourth driver comprises: a first transistor configured to provide the third voltage as a turn-on voltage to the fourth switch through an output terminal, wherein the first transistor has a control terminal receiving the second control signal; and A second transistor is configured to provide the fourth voltage as an off voltage to the fourth switch through the output terminal, wherein the second transistor has a control terminal connected to the ground.
8. The RF switch circuit according to claim 7, wherein: The fourth driver further includes: a third transistor connected between the first transistor and the output terminal, wherein the third transistor has a control terminal connected to ground and is configured to be turned on when the first transistor is turned on; and a fourth transistor connected between the second transistor and the output terminal, wherein the fourth transistor has a control terminal grounded and is configured to The second transistor is turned on when it is turned on.
9. The RF switch circuit according to claim 1, wherein: The switch control circuit is configured to turn on the first switch and turn off the second, third and fourth switches in a reception mode, and turn on the second switch and turn off the first, third and fourth switches in a transmission mode.
10. A method of operating a radio frequency (RF) switching circuit, the method comprising: In a receiving mode, turning on a first switch connected between the first port and the antenna port to receive a signal from the antenna port; In a transmission mode, the first switch is turned off, and a second switch connected between a second port and the antenna port is turned on to transmit a signal to the antenna port; In an isolation mode, the first switch and the second switch are turned off, and a third switch connected between the antenna port and ground is turned on to terminate the antenna port; as well as In a low power mode, the first switch, the second switch, and the third switch are turned off, and a fourth switch connected between the antenna port and the ground is turned on to terminate the antenna port.
11. The method according to claim 10, further comprising: The fourth switch is opened in the isolation mode.
12. The method according to claim 10, further comprising: According to a first control signal, the first switch, the second switch, and the third switch are respectively turned on or off by providing one of a first voltage and a second voltage generated from a first power supply to the first switch, the second switch, and the third switch respectively; as well as The fourth switch is turned on or off by supplying one of a third voltage generated from a second power source different from the first power source and a fourth voltage generated from the first power source to the fourth switch according to a second control signal.
13. The method according to claim 12, wherein: The second control signal includes the first voltage, and In the low power mode, the first voltage is set to 0V.
14. The method according to claim 12, wherein: The third voltage is lower than the first voltage.
15. A radio frequency (RF) switching circuit, comprising: A first switch connected between the first port and the antenna port; a second switch connected between the second port and the antenna port; a third switch connected between the antenna port and ground; a fourth switch connected between the antenna port and the ground; as well as The switch control circuit is configured to use a first power source to control the first switch, the second switch, and the third switch to be turned off, and use a second power source different from the first power source to control the fourth switch to be turned on in a low power mode.
16. The RF switch circuit of claim 15, wherein: The switch control circuit is configured to turn off the first switch, the second switch, and the fourth switch and turn on the third switch using the first power supply in an isolation mode.
17. The RF switch circuit according to claim 15, wherein: The switch control circuit is configured to turn on the first switch and turn off the second switch, the third switch, and the fourth switch using the first power supply in a reception mode.
18. The RF switch circuit of claim 15, wherein: The switch control circuit is configured to turn on the second switch and turn off the first switch, the third switch, and the fourth switch using the first power source in a transmission mode.
19. The RF switch circuit of claim 15, wherein: The switch control circuit comprises: a first driver configured to select one of a first voltage and a second voltage generated from the first power source according to a first control signal and output the selected voltage to the first switch; a second driver configured to select one of the first voltage and the second voltage according to the first control signal and output the selected voltage to the second switch; a third driver configured to select one of the first voltage and the second voltage according to the first control signal and output the selected voltage to the third switch; and The fourth driver is configured to output one of a third voltage generated from the second power supply and a fourth voltage generated from the first power supply to the fourth switch according to a second control signal.