A level conversion circuit

Abstract

The present invention discloses a level conversion circuit, through a bias voltage V BIAS circuit, and the logic level signals in the low voltage domain are input from the source terminals of NMOS transistors M 21 and M 22 to strengthen the current output capabilities of NMOS transistors M 21 and M 22 and improve the speed of the level conversion circuit, enabling it to operate at a lower supply voltage. When the level conversion circuit is enabled, the bias transistor M BIAS has no body effect, while the NMOS transistors M 21 or M 22 have body effects. By utilizing the threshold voltage difference brought about by the body effect of MOS transistors, the NMOS transistors M 21 or M 22 are turned off, enabling the level conversion circuit to have zero static power consumption; the bias transistor M BIAS and the NMOS transistors M 21 , M 22 are all thick-gate NMOS transistors with good matching properties. Therefore, the speed and static leakage current of the level conversion circuit vary less with the process. When there are a large number of level conversion circuits, the same bias circuit can be shared to reduce the circuit power consumption.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technologies, and particularly to a level conversion circuit. Background Art

[0002] Level conversion circuits are widely used in the field of integrated circuits, such as memories, input / output interface circuits, or analog circuits (power management, charge pumps, analog-to-digital / digital-to-analog converters, etc.). In these integrated circuits, different module circuits may operate in different voltage domains, and the logic signals of these different voltage domains can interact through level conversion circuits. Since level conversion circuits introduce additional delays, high-speed circuits often require level conversion circuits to have small delays, that is, to be fast. In addition, in some integrated circuits, the number of level conversion circuits may be very large, so low power consumption of the level conversion circuit is also required.

[0003] Traditional level conversion circuits, such as Figure 1 shown, are composed of NMOS transistors M 11 and M 12 , PMOS transistors M 13 and M 14 , and an inverter I 10 . The logic signal D and its inverted signal DZ and the inverter I 10 operate in the low voltage domain V DDL . The MOS transistors M 11 , M 12 , M 13 , M 14 operate in the high voltage domain V DDH , so they generally use thick gate transistors.

[0004] When D = 0, that is, when D is the logic low level of the low voltage domain V DDL , DZ = 1, that is, DZ is the logic high level of the low voltage domain V DDL , M 11 turns off, M 12 turns on → OUT = 0, outputting the logic low level of the high voltage domain V DDH , that is, the level conversion circuit converts the logic low level of the low voltage domain into the logic low level of the high voltage domain; in addition, since M 13 turns on, the voltage of OUTN is V DDH , causing M 14 to turn off; since M 11 is in the off state, there is no static leakage current in the entire circuit.

[0005] When D = 1, that is, when D is the logic high level of the low voltage domain V DDL , DZ = 0, that is, DZ is the logic low level of the low voltage domain V DDL , M 11 turns on, M12 Closed → OUTN = 0 → M 14 Open, OUT = 1, output V DDH High - voltage domain logic high level, that is, the level - conversion circuit converts the low - voltage domain logic high level to the high - voltage domain logic high level; in addition, since M 14 is open, the voltage of OUT is V DDH , making M 13 closed; since M 12 is in the closed state, there is no static leakage current in the whole circuit.

[0006] As can be seen from the above, the condition for the correct inversion of the traditional level - conversion circuit is that the current output capabilities of NMOS transistors M 11 and M 12 are stronger than those of PMOS transistors M 13 and M 14 . Assuming that M 11 and M 12 have the same size, M 13 and M 14 have the same size, and the I / V characteristics of MOS transistors conform to the square law, that is

[0007] I(M 11 ) = I(M 12 ) = (1)

[0008] I(M 13 ) = I(M 14 ) = = (2)

[0009] and are the electron and hole mobilities respectively, is the unit capacitance of the gate oxide layer, and are the gate widths of NMOS and PMOS transistors, and are the gate lengths of NMOS and PMOS transistors respectively and are the voltages between the gate and source of NMOS and PMOS transistors respectively and are the threshold voltages of NMOS and PMOS transistors respectively.

[0010] The disadvantage of the traditional level - conversion circuit is that it is greatly affected by V DDL . Assuming V DDL = 1.2V, V DDH = 3.3V, since M 11 and M 12They are all thick-gate transistors with a relatively high threshold voltage. As can be seen from Equations (1) and (2), to ensure the correct flipping of the level conversion circuit, generally, is made larger, while is made smaller. However, when V DDL is slightly higher than , due to the too small driving current, the level conversion speed becomes very slow and cannot meet the requirements of some high-speed integrated circuits. When V DDL <= , the traditional level conversion circuit will not work properly. SUMMARY OF THE INVENTION

[0011] The purpose of the present invention is to provide a level conversion circuit to solve the problems in the background technology.

[0012] To solve the above technical problems, the present invention provides a level conversion circuit, including NMOS transistors M 21 and M 22 , PMOS transistors M 23 and M 24 , inverters I 20 and I 21 , switches SW1 to SW5, a bias transistor M BIAS , and a bias current I BIAS ;

[0013] The bottom end of the substrate of NMOS transistor M 21 and the bottom end of the substrate of NMOS transistor M 22 are both grounded; the input end of inverter I 20 is connected to the logic signal D, and the output end is simultaneously connected to the source end of NMOS transistor M 21 and the input end of inverter I 21 , and the output end of inverter I 21 is connected to the source end of NMOS transistor M 22 ; the gate ends of NMOS transistors M 21 and M 22 are connected; the drain end of NMOS transistor M 21 is simultaneously connected to the drain end of PMOS transistor M 23 and the gate end of PMOS transistor M 24 , and the drain end of NMOS transistor M 22 is simultaneously connected to the drain end of PMOS transistor M 24 and the gate end of PMOS transistor M 23 ; the source ends of PMOS transistors M 23 and M 24 are both connected to the high voltage domain V DDH ;

[0014] The input end of the bias current I BIAS is connected to the high voltage domain V DDH, the output terminal is connected to the drain terminal of the bias transistor M BIAS , the first terminal of the switch SW3, the gate terminal of the NMOS transistor M 21 , and the gate terminal of the NMOS transistor M 22 ; the second terminal of the switch SW3 is grounded; the gate terminal of the bias transistor M BIAS is connected to the first terminal of the switch SW3, the substrate terminal is connected to the first terminals of the switch SW1 and the switch SW2 at the same time, and the second terminal of the switch SW1 and the source terminal of the bias transistor M BIAS are commonly connected to the low voltage domain V DDL ; the second terminal of the switch SW2 is grounded;

[0015] The first terminal of the switch SW5 is connected to the high voltage domain V DDH , and the second terminal is connected to the drain terminal of the NMOS transistor M 22 ; the first terminal of the switch SW4 is connected to the drain terminal of the NMOS transistor M 22 , and the second terminal is grounded.

[0016] In one embodiment, the NMOS transistors M 21 and M 22 , the PMOS transistors M 23 and M 24 and the bias transistor M BIAS are all thick gate devices.

[0017] In one embodiment, the switch SW4 and the switch SW5 are a pull-down switch and a pull-up switch respectively; when the level conversion circuit is not enabled, the switch SW4 is turned on through the PD control signal, so that the output terminal OUT of the level conversion circuit is a fixed low level, or the switch SW5 is turned on through the PU control signal, so that the output terminal OUT of the level conversion circuit is a fixed high level.

[0018] A level conversion circuit provided by the present invention can convert a digital logic level in a low voltage domain such as 1.2V into a digital logic level signal in a high voltage domain such as 3.3V, and has the characteristics of small delay, high speed and low power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a schematic structural diagram of a traditional level conversion circuit.

[0020] Figure 2 is a schematic structural diagram of the level conversion circuit provided by the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0021] The following further describes in detail a level conversion circuit proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the embodiments of the present invention.

[0022] The present invention provides a level conversion circuit, as Figure 2 shown, including NMOS transistors M 21 and M 22 , PMOS transistors M 23 and M 24 , inverters I 20 and I 21 , switches SW1~SW5, bias transistor M BIAS , and bias current I BIAS . Among them, NMOS transistors M 21 and M 22 , PMOS transistors M 23 and M 24 , inverters I 20 and I 21 constitute the core circuit. The substrate terminals of NMOS transistor M 21 and NMOS transistor M 22 are both grounded. The low-voltage domain logic signal DZ is input from the source terminal of NMOS transistor M 21 , and the low-voltage domain logic signal DZZ is input from the source terminal of NMOS transistor M 22 . The bias current I BIAS , bias transistor M BIAS and switches SW1, SW2, and SW3 constitute the bias circuit. EN is the enable signal, and ENB is the inverted signal of the enable signal. When the circuit is enabled, the substrate of bias transistor M BIAS is connected to V DDL through switch SW1. When the circuit cannot be enabled, the substrate of bias transistor M BIAS is connected to ground through switch SW2. NMOS transistors M 21 and M 22 , PMOS transistors M 23 and M 24 and bias transistor M BIAS are all thick-gate devices. Therefore, the characteristics of NMOS transistors M 21 , M 22 and bias transistor M BIAS are relatively matched and change less with the process. Switches SW4 and SW5 are a pull-down switch and a pull-up switch respectively. When the level conversion circuit is not enabled, the output OUT of the level conversion circuit can be made a fixed low level or high level through the PD or PU control signal.

[0023] The working principle is as follows:

[0024] When the level conversion circuit is enabled, i.e., EN = 1, ENB = 0, switch SW1 is turned on, and switches SW2, SW3, SW4, and SW5 are turned off. The source terminal and the substrate terminal of bias transistor M BIAS are both connected to V DDL , and the bias current I BIAS is generally taken as a very small value. Then the bias voltage is:

[0025] V BIAS = V DDL + V GS (M BIAS ) ~ V DDL + V THN0 (3)

[0026] where V THN0 is the threshold voltage of bias transistor M BIAS without the body effect, and V GS (M BIAS ) is the gate-source voltage of bias transistor M BIAS .

[0027] When D = 0, DZ = 1, DZZ = 0, the gate-source voltages of NMOS transistors M 21 and M 22 are respectively:

[0028] V GS (M 21 ) = V BIAS - V DDL = V THN0 (4)

[0029] V GS (M 22 ) = V BIAS - 0 = V DDL + V THN0 (5)

[0030] Since the source-substrate terminal voltage V 21 of NMOS transistor M SB (M 21 ) = V DDL , under the body effect of the threshold voltage, its threshold voltage is:

[0031] V TH (M 21 ) > V GS (M 21 ) = V THN0 , so NMOS transistor M 21 is turned off.

[0032] Since the source-substrate terminal voltage V 22 of NMOS transistor MSB (M 22 ) = 0, there is no body effect, and the threshold voltage V TH (M 22 ) = V THN0 . The NMOS transistor M 22 conducts, and its current output capability is:

[0033] I(M 22 ) = (6)

[0034] The output terminal OUT is driven to the logic low level of the high voltage domain, and the voltage of OUTN is V DDH . Therefore, the PMOS transistor M 24 turns off, and the level conversion core circuit has no static leakage current.

[0035] When D = 1, DZ = 0, DZZ = 1, the gate-source voltages of the NMOS transistors M 21 and M 22 are respectively:

[0036] V GS (M 21 ) = V BIAS - 0 = V DDL + V THN0 (7)

[0037] V GS (M 22 ) = V BIAS - V DDL = V THN0 (8)

[0038] Similarly, due to the source-bulk bottom voltage V 22 of the NMOS transistor M SB (M 22 ) = V DDL , under the body effect of the threshold voltage, its threshold voltage V TH (M 22 ) > V GS (M 22 ) = V THN0 . Therefore, the NMOS transistor M 22 turns off.

[0039] Since the source-bulk bottom voltage V 21 of the NMOS transistor M SB (M 21 ) = 0, there is no body effect, and the threshold voltage V TH (M 21 ) = V THN0 , M 21 conducts, and its current output capability is:

[0040] I(M 21 ) = (9)

[0041] The voltage of OUTN is 0, and PMOS transistor M 24 turns on, and the output terminal OUT is driven to the logic high level of the high voltage domain. Therefore, PMOS transistor M 23 turns off, and the level conversion core circuit has no static leakage current.

[0042] Comparing equations (1), (2), (6), and (9), it can be seen that the level conversion circuit proposed by the present invention has a stronger current output ability than the traditional level conversion circuit. Therefore, it is faster and can operate at a lower supply voltage.

[0043] When the level conversion circuit is not enabled, i.e., EN = 0, ENB = 1, switch SW1 turns off, switches SW2 and SW3 turn on, and the substrate terminal of bias transistor M BIAS is connected to ground, and the bias voltage is 0. Therefore, NMOS transistors M 21 and M 22 turn off. By controlling the PD or PU signal to turn on switch SW4 or SW5, the output terminal OUT of the level conversion circuit can be set to a fixed low level or high level.

[0044] In the present invention, through the bias voltage V BIAS circuit, and the logic level signal of the low voltage domain is input from the source terminals of NMOS transistors M 21 and M 22 , the current output ability of NMOS transistors M 21 and M 22 is enhanced, the speed of the level conversion circuit is increased, and it can operate at a lower supply voltage. When the level conversion circuit is enabled, the bias transistor M BIAS has no body effect, while NMOS transistors M 21 or M 22 have body effects. By using the threshold voltage difference brought by the body effect of the MOS transistor, NMOS transistors M 21 or M 22 turn off, making the level conversion circuit have zero static power consumption.

[0045] Bias transistor M BIAS and NMOS transistors M 21 , M 22 are all thick-gate NMOS transistors, which have good matching. Therefore, the speed and static leakage current of the level conversion circuit vary less with the process. When there are many level conversion circuits, the same bias circuit can be shared, reducing the power consumption of the circuit; when the level conversion circuit is not enabled, through the PD or PU control signal, the output of the level conversion circuit can be set to a fixed low level or high level.

[0046] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A level conversion circuit, characterized in that: Including NMOS tube M 21 and M 22 、PMOS tube M 23 and M 24 、Inverter I 20 and I 21 , switches SW1~SW5, bias tube M BIAS , bias current I BIAS ; NMOS tube M 21 The substrate end and NMOS tube M 22 The substrate ends of the inverter I 20 The input end is connected to the logic signal D, and the output end is connected to the NMOS tube M 21 The source terminal and inverter I 21 The input terminal of the inverter I 21 The output terminal is connected to NMOS tube M 22 The source end of NMOS tube M 21 The gate terminal and NMOS tube M 22 The gate end of NMOS tube M 21 The drain end is connected to the PMOS tube M 23 The drain end and PMOS tube M 24 The gate terminal of NMOS tube M 22 The drain end is connected to the PMOS tube M 24 The drain end and PMOS tube M 23 Gate terminal of PMOS tube M 23 and M 24 The source terminals are connected to the high voltage domain V DDH ; Bias Current I BIAS The input terminal is connected to the high voltage domain V DDH , the output end is connected to the bias tube M BIAS The drain end of the switch SW3, the first end of the NMOS tube M 21 The gate terminal and NMOS tube M 22 The gate terminal of the switch SW3 is connected to the ground; the second terminal of the bias tube M BIAS The gate end is connected to the first end of the switch SW3, the substrate end is connected to the first end of the switch SW1 and the first end of the switch SW2, the second end of the switch SW1 is connected to the bias transistor M BIAS The source terminals are connected to the low voltage domain V DDL , the second end of the switch SW2 is grounded; The first terminal of the switch SW5 is connected to the high voltage domain V DDH The second terminal is connected to NMOS tube M 22 The first terminal of the switch SW4 is connected to the NMOS tube M 22 The drain terminal of the first circuit is connected to the ground; When the level conversion circuit is enabled, the enable signal EN = 1, the inverse signal of the enable signal ENB = 0, the switch SW1 is turned on, the switches SW2, SW3, SW4, and SW5 are turned off, and the bias tube M BIAS The source and substrate terminals are connected to V DDL , The switch SW4 and the switch SW5 are respectively a pull-down switch and a pull-up switch; When the level conversion circuit is not enabled, EN = 0, ENB = 1, switch SW1 is closed, switches SW2 and SW3 are opened, and bias tube M BIAS The substrate end is connected to the ground, the bias voltage is 0, and the NMOS tube M 21 and M 22 Close; open the switch SW4 through the PD control signal to make the output terminal OUT of the level conversion circuit a fixed low level, or open the switch SW5 through the PU control signal to make the output terminal OUT of the level conversion circuit a fixed high level.

2. The level conversion circuit according to claim 1, characterized in that: The NMOS tube M 21 and M 22 、PMOS tube M 23 and M 24 and bias tube M BIAS All are thick-gate devices.

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