A drive circuit with output clamping

Abstract

The present invention provides a driving circuit with output clamping. The driving circuit includes: a first-level level conversion module for converting a low-voltage signal into a floating voltage signal, wherein the upper voltage of the low-voltage signal is a first set voltage, its lower voltage is the ground voltage, the upper voltage of the floating voltage signal is the power supply voltage, and its lower voltage is the difference between the power supply voltage and a second set voltage; a second-level level conversion module connected to the output end of the first-level level conversion module for converting the floating voltage signal into a low-voltage signal; a driving module connected to the output ends of the first and second-level level conversion modules, controlled by the floating voltage signal and the low-voltage signal and generating a driving signal; an output clamping module connected to the output end of the driving module for performing output clamping under the drive of the driving signal. Through the driving circuit provided by the present invention, the problems of high layout cost and system instability existing when an LDO is used to supply power to the driving module in the prior art are solved.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit design, and particularly relates to a driving circuit with output clamping. Background Art

[0002] In analog integrated circuit chips, especially AC / DC chips, a driving circuit with output clamping is often required. In high-voltage chips such as AC / DC, generally, MOS devices with a Vds breakdown voltage of 5V are called low-voltage devices, MOS devices with a Vds breakdown voltage of 30V are called medium-voltage devices, and MOS devices with a Vds breakdown voltage of 500V - 600V are called high-voltage devices; since the layout area of low-voltage devices is much smaller than that of medium-voltage devices, in design, low-voltage devices are used as much as possible to avoid using medium-voltage or high-voltage devices. In a common process, generally, only a Vgs breakdown voltage of more than ten volts is provided, which is called a thin gate oxide process. That is to say, in such a process, the Vgs breakdown voltage of medium-voltage devices is less than the Vds breakdown voltage; if a higher Vgs breakdown voltage is required, more process costs are needed.

[0003] The VCC of many analog integrated circuit chips, especially AC / DC chips, usually has a relatively wide range, possibly from a few volts to dozens of volts. If the driving module is directly powered by the external VCC, then the Vgs voltage of the MOS devices in the driving module will exceed the breakdown voltage; therefore, in existing designs, an intermediate voltage VM of more than ten volts needs to be generated by an LDO (low dropout linear regulator). At this time, the LDO must use medium-voltage devices with a larger layout area, so that the driving module is powered by the intermediate voltage VM of more than ten volts, ensuring that the Vgs and Vds of the MOS devices in the driving module do not exceed the breakdown voltage, but all medium-voltage devices need to be used in the driving module (as Figure 1 shown). Once such a structure is used, the design of the LDO will be an inevitable difficulty: 1. Since the LDO supplies power to the driving module, the dynamic response speed needs to be very fast; 2. The LDO is a negative feedback loop, which will inevitably introduce loop stability problems. Zero-pole compensation is required, and the system stability needs to be ensured when the driving module is working. Usually, capacitors are needed for zero-pole compensation. Since the LDO is a medium-voltage device, a large number of medium-voltage devices are required for the capacitors, which will require a large layout area cost; 3. The LDO will have an output loss on the output power transistor M1. In order to supply power to the driving module, the layout area of the output power transistor M1 will also be quite large. Assuming that the driving requires an instantaneous current of I, then the power loss when the output power transistor M1 is turned on will be P = I 2 *Ron, where Ron is the on-resistance of the output power transistor M1. To reduce the loss, Ron must be as small as possible.

[0004] Figure 2This is an implementation of the prior art. In this implementation, both the driving module and the LDO require the use of intermediate voltage devices. Moreover, the loop compensation M4 in the LDO layout also requires the use of intermediate voltage devices. Generally, the capacitance value of the loop compensation M4 needs to be above 10pF. Therefore, the size of the loop compensation M4 will be very large. At the same time, in order to make the output voltage of the driving as high as possible, the voltage loss of the LDO must be reduced. Therefore, the regulating transistor M1 of the LDO also needs to be very large. It can be seen that in the prior art, both the driving module and the LDO require the use of intermediate voltage devices, which will consume a large amount of layout cost, and due to the use of the LDO, it will bring difficulties in design and system instability. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a driving circuit with output clamping, which is used to solve the problems of high layout cost and system instability when using an LDO to supply power to the driving module in the prior art.

[0006] To achieve the above purpose and other related purposes, the present invention provides a driving circuit with output clamping. The driving circuit includes: a first-level level conversion module, a second-level level conversion module, a driving module, and an output clamping module, all of which are connected between the power supply voltage and the ground;

[0007] The first-level level conversion module is used to convert a low-voltage signal into a floating voltage signal. Among them, the upper voltage of the low-voltage signal is a first set voltage, the lower voltage of the low-voltage signal is the ground voltage, the upper voltage of the floating voltage signal is the power supply voltage, the lower voltage of the floating voltage signal is a clamping voltage, and the clamping voltage is the difference between the power supply voltage and a second set voltage;

[0008] The second-level level conversion module is connected to the output end of the first-level level conversion module and is used to convert the floating voltage signal into the low-voltage signal;

[0009] The driving module is connected to the output end of the first-level level conversion module and the output end of the second-level level conversion module, and is used to generate a driving signal under the control of the floating voltage signal and the low-voltage signal;

[0010] The output clamping module is connected to the output end of the driving module and is used to clamp the output voltage under the drive of the driving signal.

[0011] Optionally, the first-level level conversion module includes: a first-level level conversion unit and a first-level drive enhancement unit,

[0012] The first-level level conversion unit is used to convert the low-voltage signal into an original floating voltage signal;

[0013] The first-stage driving enhancement unit is connected to the output end of the first-stage level conversion unit, and is used for driving and enhancing the original floating voltage signal to generate the floating voltage signal.

[0014] Optionally, the first-stage level conversion unit includes: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor. The source electrodes of the first NMOS transistor and the second NMOS transistor are both grounded. The drain electrode of the first NMOS transistor is connected to the source electrode of the third NMOS transistor. The drain electrode of the second NMOS transistor is connected to the source electrode of the fourth NMOS transistor. The gate electrodes of the first NMOS transistor and the second NMOS transistor are connected to a set of mutually inverted low-voltage signals. The drain electrode of the third NMOS transistor is connected to the drain electrode of the first PMOS transistor. The drain electrode of the fourth NMOS transistor is connected to the drain electrode of the second PMOS transistor. The gate electrodes of the third NMOS transistor and the fourth NMOS transistor are both connected to a first set voltage. The source electrode of the first PMOS transistor is connected to the drain electrode of the third PMOS transistor and the gate electrode of the fourth PMOS transistor. The source electrode of the second PMOS transistor is connected to the gate electrode of the third PMOS transistor and the drain electrode of the fourth PMOS transistor and generates the original floating voltage signal. The gate electrodes of the first PMOS transistor and the second PMOS transistor are both connected to a clamping voltage. The source electrodes of the third PMOS transistor and the fourth PMOS transistor are both connected to a power supply voltage. The first-stage driving enhancement unit includes: a first inverter, a second inverter, and a fifth PMOS transistor. The input end of the first inverter is connected to the original floating voltage signal. The output end of the first inverter is connected to the input end of the second inverter. The output end of the second inverter generates the floating voltage signal. The power supply terminals of the first inverter and the second inverter are both connected to the power supply voltage. The grounding terminals of the first inverter and the second inverter are both connected to the source electrode of the fifth PMOS transistor. The drain electrode of the fifth PMOS transistor is grounded. The gate electrode of the fifth PMOS transistor is connected to the clamping voltage.

[0015] Optionally, the first-stage level conversion module further includes: a clamping voltage generation unit, connected between the power supply voltage and the ground, and used for generating the clamping voltage.

[0016] Optionally, the clamping voltage generating unit includes: at least one first Zener diode and a current source. The cathode of the first Zener diode is connected to the power supply voltage, the anode of the first Zener diode is connected to the input end of the current source and generates the clamping voltage, and the output end of the current source is grounded. When the number of the first Zener diodes is greater than or equal to 2, a plurality of the first Zener diodes are connected in series with each other, the cathode of the first Zener diode string is connected to the power supply voltage, the anode of the first Zener diode string is connected to the input end of the current source and generates the clamping voltage; wherein, the second set voltage is determined by the regulated voltage value and the number of the first Zener diodes.

[0017] Optionally, the second-level level conversion module includes: a second-level level conversion unit and a second-level driving enhancement unit.

[0018] The second-level level conversion unit is connected to the output end of the first-level level conversion module and is configured to convert the floating voltage signal into an original low-voltage signal.

[0019] The second-level driving enhancement unit is connected to the output end of the second-level level conversion unit and is configured to perform driving enhancement on the original low-voltage signal to generate the low-voltage signal.

[0020] Optionally, the second-level level conversion unit includes: a sixth PMOS transistor, a seventh PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor. The sources of the sixth PMOS transistor and the seventh PMOS transistor are both connected to the power supply voltage. The drain of the sixth PMOS transistor is connected to the drain of the fifth NMOS transistor. The drain of the seventh PMOS transistor is connected to the drain of the sixth NMOS transistor. The gates of the sixth PMOS transistor and the seventh PMOS transistor are connected to a set of floating voltage signals that are inverted with each other. The source of the fifth NMOS transistor is connected to the drain of the seventh NMOS transistor and the gate of the eighth NMOS transistor. The source of the sixth NMOS transistor is connected to the gate of the seventh NMOS transistor and the drain of the eighth NMOS transistor and generates the original low-voltage signal. The gates of the fifth NMOS transistor and the sixth NMOS transistor are both connected to the first set voltage. The sources of the seventh NMOS transistor and the eighth NMOS transistor are grounded. The second-level driving enhancement unit includes: a third inverter and a fourth inverter. The input end of the third inverter is connected to the original low-voltage signal. The output end of the third inverter is connected to the input end of the fourth inverter. The output end of the fourth inverter generates the low-voltage signal. The power supply terminals of the third inverter and the fourth inverter are both connected to the first set voltage. The ground terminals of the third inverter and the fourth inverter are both grounded.

[0021] Optionally, the driving module includes: an upper driving transistor and a lower driving transistor. The source of the upper driving transistor is connected to the power supply voltage. The drain of the upper driving transistor is connected to the drain of the lower driving transistor and generates the upper transistor driving signal in the driving signal. The gate of the upper driving transistor is connected to the floating voltage signal. The source of the lower driving transistor is grounded. The gate of the lower driving transistor is connected to the low voltage signal.

[0022] Optionally, the output clamping module includes: an output upper transistor, an output lower transistor and a clamping unit. The drain of the output upper transistor is connected to the power supply voltage. The source of the output upper transistor is connected to the drain of the output lower transistor and generates the output voltage. The gate of the output upper transistor is connected to the upper transistor driving signal in the driving signal. The source of the output lower transistor is grounded. The gate of the output lower transistor is connected to the lower transistor driving signal in the driving signal. The clamping unit is connected between the gate of the output upper transistor and the ground.

[0023] Optionally, the clamping unit includes: at least one second Zener diode. The cathode of the second Zener diode is connected to the gate of the output upper transistor. The anode of the second Zener diode is grounded. When the clamping unit includes two or more second Zener diodes, multiple second Zener diodes are connected in series with each other, and the cathode of the second Zener diode string is connected to the gate of the output upper transistor, and the anode of the second Zener diode string is grounded. The driving circuit further includes: a signal generation module for generating the low voltage signal and the lower transistor driving signal.

[0024] As described above, a driving circuit with output clamping according to the present invention designs a brand-new driving circuit by using level shift and floating voltage technologies. It can be directly powered by an external power supply voltage VCC. Even if the voltage range of VCC exceeds the withstand voltage range of thin gate oxide devices, it is no problem and the LDO is omitted. The present invention only requires fewer intermediate voltage devices, that is, M3-M13 and M16-M19 are intermediate voltage devices and the version areas are not large, so the chip layout cost is reduced, and the clamping driving function of thin gate oxide devices can be realized with the least chip version cost. Moreover, since there is no need for an LDO, there will be no system stability and load response problems. The present invention uses low voltage devices placed in the high voltage well to manufacture inverters, which can further reduce the chip version cost. Description of the Drawings

[0025] Figure 1 It shows a schematic structural diagram of a conventional driving circuit with output clamping.

[0026] Figure 2 It shows a specific circuit diagram of a conventional driving circuit with output clamping.

[0027] Figure 3 It shows a circuit diagram of the driving circuit with output clamping according to the present invention.

[0028] Description of Component Labels

[0029] 100’ Low Dropout Linear Regulator

[0030] 200’ Driver Module

[0031] 10 Driver Circuit

[0032] 100 First-Level Level Conversion Module

[0033] 101 First-Level Level Conversion Unit

[0034] 102 First-Level Drive Enhancement Unit

[0035] 103 Clamping Voltage Generation Unit

[0036] 200 Second-Level Level Conversion Module

[0037] 201 Second-Level Level Conversion Unit

[0038] 202 Second-Level Drive Enhancement Unit

[0039] 300 Driver Module

[0040] 400 Output Clamping Module

[0041] 401 Clamping Unit

[0042] 500 Signal Generation Module Detailed Implementation Manner

[0043] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0044] Please refer to Figure 3 It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Although only the components related to the present invention are shown in the diagrams and are not drawn according to the number, shape, and size of the components during actual implementation, the actual forms, numbers, and proportions of the components during actual implementation can be arbitrarily changed, and the component layout form may also be more complex.

[0045] Such as Figure 3As shown in the figure, this embodiment provides a drive circuit with output clamping. The drive circuit includes: a first-level level conversion module 100, a second-level level conversion module 200, a drive module 300, and an output clamping module 400, all of which are connected between the power supply voltage VCC and the ground.

[0046] The first-level level conversion module 100 is used to convert the low-voltage signal IN into a floating voltage signal FL. Among them, the upper voltage of the low-voltage signal IN is the first set voltage V1, the lower voltage of the low-voltage signal IN is the ground voltage, the upper voltage of the floating voltage signal FL is the power supply voltage VCC, the lower voltage of the floating voltage signal FL is the clamping voltage VCL, and the clamping voltage VCL is the difference between the power supply voltage VCC and the second set voltage V2. It should be noted that here, "the upper voltage of the low-voltage signal IN is the first set voltage V1, and the lower voltage of the low-voltage signal IN is the ground voltage" means that "the low voltage in the low-voltage signal IN is 0 and the high voltage is V1", such as the low-voltage signal IN is a 0-5V signal; "the upper voltage of the floating voltage signal FL is the power supply voltage VCC, and the lower voltage of the floating voltage signal FL is the clamping voltage VCL" means that "the low voltage in the floating voltage signal FL is VCL and the high voltage is VCC", such as the floating voltage signal is a 10-15V signal.

[0047] As an example, as Figure 3 shown, the first-level level conversion module 100 includes: a first-level level conversion unit 101 and a first-level drive enhancement unit 102. The first-level drive enhancement unit 102 is connected to the output end of the first-level level conversion unit 101. The first-level level conversion unit 101 is used to convert the low-voltage signal IN into an original floating voltage signal PFL. The first-level drive enhancement unit 102 is used to drive and enhance the original floating voltage signal PFL to generate the floating voltage signal FL.

[0048] Specifically, the first-level level conversion unit 101 includes: a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M3, a fourth NMOS transistor M4, a first PMOS transistor M5, a second PMOS transistor M6, a third PMOS transistor M7, and a fourth PMOS transistor M8. The sources of the first NMOS transistor M1 and the second NMOS transistor M2 are both grounded. The drain of the first NMOS transistor M1 is connected to the source of the third NMOS transistor M3. The drain of the second NMOS transistor M2 is connected to the source of the fourth NMOS transistor M4. The gates of the first NMOS transistor M1 and the second NMOS transistor M2 are connected to a set of mutually inverted low-voltage signals IN. The drain of the third NMOS transistor M3 is connected to the drain of the first PMOS transistor M5. The drain of the fourth NMOS transistor M4 is connected to the drain of the second PMOS transistor M6. The gates of the third NMOS transistor M3 and the fourth NMOS transistor M4 are both connected to a first set voltage V1. The source of the first PMOS transistor M5 is connected to the drain of the third PMOS transistor M7 and the gate of the fourth PMOS transistor M8. The source of the second PMOS transistor M6 is connected to the gate of the third PMOS transistor M7 and the drain of the fourth PMOS transistor M8 and generates the original floating voltage signal PFL. The gates of the first PMOS transistor M5 and the second PMOS transistor M6 are both connected to the clamping voltage VCL. The sources of the third PMOS transistor M7 and the fourth PMOS transistor M8 are both connected to the power supply voltage VCC (specifically as Figure 3 shown). Among them, the first NMOS transistor M1 and the second NMOS transistor M2 are both low-voltage devices. The third NMOS transistor M3, the fourth NMOS transistor M4, the first PMOS transistor M5, the second PMOS transistor M6, the third PMOS transistor M7, and the fourth PMOS transistor M8 are all medium-voltage devices. In this example, the clamping voltage VCL clamps the source voltage by clamping the gate voltages of the first PMOS transistor M5 and the second PMOS transistor M6, so that the third PMOS transistor M7 and the fourth PMOS transistor M8 will not be broken down because the drain-source voltage Vds exceeds the breakdown voltage. The third NMOS transistor M3 and the fourth NMOS transistor M4 are shielded by medium-voltage transistors, so that the first NMOS transistor M1 and the second NMOS transistor M2 connected to their sources can use low-voltage transistors.

[0049] More specifically, the first-level level conversion unit 101 further includes: an inverter I01. The gate of the first NMOS transistor M1 is connected to the low-voltage signal IN, and the gate of the second NMOS transistor M2 is connected to the low-voltage signal IN through the inverter I01, so that the gates of the first NMOS transistor M1 and the second NMOS transistor M2 are connected to a set of inverted low-voltage signals IN (specifically as Figure 3 shown).

[0050] Specifically, the first-level driving enhancement unit 102 includes: a first inverter I1, a second inverter I2, and a fifth PMOS transistor M9. The input terminal of the first inverter I1 is connected to the original floating voltage signal PFL, the output terminal of the first inverter I1 is connected to the input terminal of the second inverter I2, and the output terminal of the second inverter I2 generates the floating voltage signal FL. The power supply terminals of the first inverter I1 and the second inverter I2 are both connected to the power supply voltage VCC, the ground terminals of the first inverter I1 and the second inverter I2 are both connected to the source of the fifth PMOS transistor M9, the drain of the fifth PMOS transistor M9 is grounded, and the gate of the fifth PMOS transistor M9 is connected to the clamping voltage VCL (specifically as Figure 3 shown). Among them, the first inverter I1 and the second inverter I2 are both low-voltage devices placed in the high-voltage well, and the fifth PMOS transistor M9 is a medium-voltage device. In this example, the clamping voltage VCL clamps the source voltage by clamping the gate voltage of the fifth PMOS transistor M9, so as to provide a relatively low potential (VCL = VCC - V1) as the ground potential for the first inverter I1 and the second inverter I2, that is, the Vds range of the MOS transistors constituting the first inverter I1 and the second inverter I2 is within VCC to VCC - V1. Therefore, the first inverter I1 and the second inverter I2 can adopt low-voltage devices placed in the high-voltage well.

[0051] As an example, as Figure 3 shown, the first-level level conversion module 100 further includes: a clamping voltage generation unit 103, connected between the power supply voltage VCC and the ground, for generating the clamping voltage VCL.

[0052] Specifically, the clamping voltage generating unit 103 includes: at least one first Zener diode D1 and a current source I. The cathode of the first Zener diode D1 is connected to the power supply voltage VCC, the anode of the first Zener diode D1 is connected to the input end of the current source I and generates the clamping voltage VCL, and the output end of the current source I is grounded; when the number of the first Zener diodes D1 is greater than or equal to 2, a plurality of the first Zener diodes D1 are connected in series with each other, and the cathode of the first Zener diode string is connected to the power supply voltage VCC, and the anode of the first Zener diode string is connected to the input end of the current source I and generates the clamping voltage VCL (specifically as Figure 3 shown); wherein, the second set voltage V2 is determined by the regulated voltage value and the number of the first Zener diodes D1. Since the second set voltage V2 is equal to the product of the regulated voltage value of the first Zener diode D1 and the number of the first Zener diodes D1, and the clamping voltage VCL is equal to the difference between the power supply voltage VCC and the second set voltage V2, in specific applications, the number of the first Zener diodes D1 can be set according to actual requirements, so as to set the magnitude of the clamping voltage VCL. Optionally, the voltage value of the clamping voltage VCL is equal to the voltage value of the first set voltage V1.

[0053] The second-level level conversion module 200 is connected to the output end of the first-level level conversion module 100 and is used to convert the floating voltage signal FL into the low-voltage signal IN.

[0054] As an example, as Figure 3 shown, the second-level level conversion module 200 includes: a second-level level conversion unit 201 and a second-level drive enhancement unit 202. The second-level level conversion unit 201 is connected to the output end of the first-level level conversion module 100, and the second-level drive enhancement unit 202 is connected to the output end of the second-level level conversion unit 201. The second-level level conversion unit 201 is used to convert the floating voltage signal FL into the original low-voltage signal PIN, and the second-level drive enhancement unit 202 is used to perform drive enhancement on the original low-voltage signal PIN to generate the low-voltage signal IN.

[0055] Specifically, the second-level level conversion unit 201 includes: a sixth PMOS transistor M10, a seventh PMOS transistor M11, a fifth NMOS transistor M12, a sixth NMOS transistor M13, a seventh NMOS transistor M14, and an eighth NMOS transistor M15. The sources of the sixth PMOS transistor M10 and the seventh PMOS transistor M11 are both connected to the power supply voltage VCC. The drain of the sixth PMOS transistor M10 is connected to the drain of the fifth NMOS transistor M12. The drain of the seventh PMOS transistor M11 is connected to the drain of the sixth NMOS transistor M13. The gates of the sixth PMOS transistor M10 and the seventh PMOS transistor M11 are connected to a set of floating voltage signals FL that are inverted with respect to each other. The source of the fifth NMOS transistor M12 is connected to the drain of the seventh NMOS transistor M14 and the gate of the eighth NMOS transistor M15. The source of the sixth NMOS transistor M13 is connected to the gate of the seventh NMOS transistor M14 and the drain of the eighth NMOS transistor M15 and generates the original low voltage signal PIN. The gates of the fifth NMOS transistor M12 and the sixth NMOS transistor M13 are both connected to the first set voltage V1. The sources of the seventh NMOS transistor M14 and the eighth NMOS transistor M15 are grounded (specifically as Figure 3 shown). Among them, the sixth PMOS transistor M10, the seventh PMOS transistor M11, the fifth NMOS transistor M12, and the sixth NMOS transistor M13 are all medium-voltage devices, and the seventh NMOS transistor M14 and the eighth NMOS transistor M15 are all low-voltage devices.

[0056] More specifically, the second-level level conversion unit 201 further includes: an inverter I02. The gate of the sixth PMOS transistor M10 is connected to the floating voltage signal FL, and the gate of the seventh PMOS transistor M11 is connected to the floating voltage signal FL through the inverter I02, so that the gates of the sixth PMOS transistor M10 and the seventh PMOS transistor M11 are connected to a set of floating voltage signals FL that are inverted with respect to each other. Among them, the power supply terminal of the inverter I02 is connected to the power supply voltage VCC, and the ground terminal of the inverter I02 is connected to the source of the fifth PMOS transistor M9 (specifically as Figure 3 shown). Among them, the inverter I02 is a low-voltage device placed in a high-voltage well. In this example, the clamping voltage VCL clamps the source voltage of the fifth PMOS transistor M9 by clamping the gate voltage thereof, thereby providing a relatively low potential (VCL = VCC - V1) as the ground potential for the inverter I02, that is, the Vds range of the MOS transistors constituting the inverter I02 is within VCC to VCC - V1, so that the inverter I02 can adopt a low-voltage device placed in a high-voltage well.

[0057] Specifically, the second-stage drive enhancement unit 202 includes: a third inverter I3 and a fourth inverter I4. The input terminal of the third inverter I3 is connected to the original low-voltage signal PIN. The output terminal of the third inverter I3 is connected to the input terminal of the fourth inverter I4. The output terminal of the fourth inverter I4 generates the low-voltage signal IN. The power supply terminals of the third inverter I3 and the fourth inverter I4 are both connected to the first set voltage V1. The ground terminals of the third inverter I3 and the fourth inverter I4 are both grounded (specifically as Figure 3 shown). Among them, both the third inverter I3 and the fourth inverter I4 are low-voltage devices.

[0058] The drive module 300 is connected to the output terminals of the first-stage level conversion module 100 and the second-stage level conversion module 200, and is used to generate a drive signal under the control of the floating voltage signal FL and the low-voltage signal IN.

[0059] As an example, as Figure 3 shown, the drive module 300 includes: a drive upper transistor M16 and a drive lower transistor M17. The source electrode of the drive upper transistor M16 is connected to the power supply voltage VCC. The drain electrode of the drive upper transistor M16 is connected to the drain electrode of the drive lower transistor M17 and generates the upper transistor drive signal drvh in the drive signal. The gate electrode of the drive upper transistor drvh is connected to the floating voltage signal FD. The source electrode of the drive lower transistor M17 is grounded. The gate electrode of the drive lower transistor M17 is connected to the low-voltage signal IN. Among them, the drive upper transistor M16 is a PMOS transistor, the drive lower transistor M17 is an NMOS transistor, and both the drive upper transistor M16 and the drive lower transistor M17 are thin gate oxide devices.

[0060] The output clamping module 400 is connected to the output terminal of the drive module 300 and is used to clamp the output voltage OUT under the drive of the drive signal.

[0061] As an example, as Figure 3As shown in the figure, the output clamping module 400 includes: an output upper transistor M18, an output lower transistor M19, and a clamping unit 401. The drain of the output upper transistor M18 is connected to the power supply voltage VCC. The source of the output upper transistor M18 is connected to the drain of the output lower transistor M19 and generates the output voltage OUT. The gate of the output upper transistor M18 is connected to the upper transistor drive signal drvh in the drive signal. The source of the output lower transistor M19 is grounded. The gate of the output lower transistor M19 is connected to the lower transistor drive signal drvl in the drive signal. The clamping unit 401 is connected between the gate of the output upper transistor M18 and the ground. Among them, both the output upper transistor M18 and the output lower transistor M19 are NMOS transistors, and both the output upper transistor M18 and the output lower transistor M19 are thin gate oxide devices.

[0062] Specifically, the clamping unit 401 includes: at least one second Zener diode D2. The cathode of the second Zener diode D2 is connected to the gate of the output upper transistor M18, and the anode of the second Zener diode D2 is grounded; when the clamping unit 401 includes two or more of the second Zener diodes D2, multiple second Zener diodes D2 are connected in series with each other, and the cathode of the second Zener diode string is connected to the gate of the output upper transistor M18, and the anode of the second Zener diode string is grounded (specifically as Figure 3 shown). In specific applications, the number of the second Zener diodes D2 can be set according to the Vds breakdown voltage value of the output upper transistor M18, that is, Vd*N≤V ds_M18 , at this time, the clamping unit 401 clamps the output voltage OUT to N*Vd - V th_M18 ; where Vd is the regulated voltage value of the second Zener diode D2, N is the number of the second Zener diodes D2 in the clamping unit 401, V ds_M18 is the Vds breakdown voltage value of the output upper transistor M18, and V th_M18 is the threshold voltage of the output upper transistor M18.

[0063] As an example, as Figure 3 shown, the drive circuit further includes: a signal generation module 500, which is used to generate the low voltage signal IN and the lower transistor drive signal drvl.

[0064] Specifically, the signal generation module 500 includes: a fifth inverter I5, a sixth inverter I6, a seventh inverter I7, an eighth inverter I8, a ninth inverter I9, a tenth inverter I10, an eleventh inverter I11, a twelfth inverter I12, a thirteenth inverter I13, a NAND gate NAND, and a NOR gate NOR. The input terminal of the fifth inverter I5 is connected to the logic control signal DRV. The output terminal of the fifth inverter I5 is connected to the first input terminal of the NAND gate NAND and the first input terminal of the NOR gate NRO. The second input terminal of the NAND gate NAND is connected to the output terminal of the second-level level conversion module 200 through the sixth inverter I6 and the seventh inverter I7. The output terminal of the NAND gate NAND is connected to the second input terminal of the NOR gate NOR through the eighth inverter I8, the ninth inverter I9, the tenth inverter I10, the eleventh inverter I11, and the twelfth inverter I12. Meanwhile, the output terminal of the tenth inverter I10 generates the lower transistor drive signal drvl. The output terminal of the NOR gate NOR is connected to the input terminal of the thirteenth inverter I13. The output terminal of the thirteenth inverter I13 generates the low voltage signal IN. The power supply terminals of the fifth inverter I5, the sixth inverter I6, the seventh inverter I7, the eighth inverter I8, the ninth inverter I9, the tenth inverter I10, the eleventh inverter I11, the twelfth inverter I12, the thirteenth inverter I13, the NAND gate NAND, and the NOR gate NOR are all connected to the first set voltage V1. The ground terminals of the fifth inverter I5, the sixth inverter I6, the seventh inverter I7, the eighth inverter I8, the ninth inverter I9, the tenth inverter I10, the eleventh inverter I11, the twelfth inverter I12, the thirteenth inverter I13, the NAND gate NAND, and the NOR gate NOR are all grounded (specifically as Figure 3 shown). Among them, the fifth inverter I5, the sixth inverter I6, the seventh inverter I7, the eighth inverter I8, the ninth inverter I9, the tenth inverter I10, the eleventh inverter I11, the twelfth inverter I12, the thirteenth inverter I13, the NAND gate NAND, and the NOR gate NOR are all low-voltage devices.

[0065] Please refer to Figure 3 below to illustrate the working principle of the drive circuit with output clamping according to this embodiment.

[0066] When the logic control signal DRV is at a high level, after logical operation, the low-level signal IN is at a low level and its inverted signal is at a high level; at this time, the first NMOS transistor M1 is turned off, the second NMOS transistor M2 is turned on, the fourth NMOS transistor M4 and the second PMOS transistor M6 are turned on, so that the third PMOS transistor M7 is turned on. At this time, the output is limited by the gate voltage of the second PMOS transistor M6, and thus the output VCL, that is, VCC - V1, is obtained. When the floating voltage signal FL is at a low level, its inverted signal is at a high level; at this time, the sixth PMOS transistor M10 is turned on, the seventh PMOS transistor M11 is turned off, the fifth NMOS transistor M12 and the eighth NMOS transistor M15 are turned on, and the output is 0V at this time. At this time, the driving upper transistor M16 is turned on, the driving lower transistor M17 is turned off, so as to drive the output upper transistor M18 to be turned on and clamp the output voltage OUT for output.

[0067] When the logic control signal DRV is at a low level, after logical operation, the low-level signal IN is at a high level and its inverted signal is at a low level; at this time, the first NMOS transistor M1 is turned on, the second NMOS transistor M2 is turned off, the third NMOS transistor M3 and the first PMOS transistor M5 are turned on, so that the fourth PMOS transistor M8 is turned on, and thus the output VCC is obtained. When the floating voltage signal FL is at a high level, its inverted signal is at a low level; at this time, the sixth PMOS transistor M10 is turned off, the seventh PMOS transistor M11 is turned on, the sixth NMOS transistor M13 and the seventh NMOS transistor M14 are turned on, and the output is limited by the gate voltage of the sixth NMOS transistor M13, and thus the output V1 is obtained. At this time, the driving upper transistor M16 is turned off, the driving lower transistor M17 is turned on, the output upper transistor M18 is turned off, the output lower transistor M19 is turned on, and the output voltage OUT is 0V.

[0068] It can be seen that the driving circuit in this embodiment uses the first-level level conversion module 100 to convert the low-voltage signal of 0 - V1 into a floating voltage signal of VCC - (VCC - V1) to drive the driving upper transistor M16, which ensures that the gate-source voltage Vgs of the driving upper transistor M16 does not exceed the breakdown voltage of its thin gate oxide, and at the same time ensures that the gate-source voltages Vgs of the driving lower transistor M17, the output upper transistor M18 and the output lower transistor M19 also do not exceed the breakdown voltage of their thin gate oxides.

[0069] In summary, a driving circuit with output clamping according to the present invention designs a brand-new driving circuit by using level shifting and floating voltage technologies. It can be directly powered by an external power supply voltage VCC. Even if the voltage range of VCC exceeds the breakdown voltage range of thin gate oxide devices, it is no problem and the LDO can be omitted. The present invention only requires fewer intermediate voltage devices, that is, M3 - M13, M16 - M19 are intermediate voltage devices and the version areas are not very large, so the chip layout cost is reduced, and the clamping driving function of thin gate oxide devices can be realized with the least chip version cost. Moreover, since there is no need for an LDO, there will be no system stability and load response problems. The present invention uses low-voltage devices placed in a high-voltage well to fabricate inverters, which can further reduce the chip version cost. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0070] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A driving circuit with output clamping, characterized in that, The driving circuit includes: a first-level level conversion module, a second-level level conversion module, a driving module, and an output clamping module, all of which are connected between the power supply voltage and the ground; the driving circuit further includes: a signal generation module; The first-level level conversion module is used to convert a low-voltage signal into a floating voltage signal. Among them, the upper voltage of the low-voltage signal is a first set voltage, the lower voltage of the low-voltage signal is the ground voltage, the upper voltage of the floating voltage signal is the power supply voltage, the lower voltage of the floating voltage signal is a clamping voltage, and the clamping voltage is the difference between the power supply voltage and a second set voltage; The second-level level conversion module is connected to the output end of the first-level level conversion module and is used to convert the floating voltage signal into the low-voltage signal; The driving module is connected to the output end of the first-level level conversion module and the output end of the second-level level conversion module and is used to generate a driving signal under the control of the floating voltage signal and the low-voltage signal; among them, the driving module includes: a driving upper transistor and a driving lower transistor. The source of the driving upper transistor is connected to the power supply voltage, the drain of the driving upper transistor is connected to the drain of the driving lower transistor and generates the upper transistor driving signal in the driving signal, the gate of the driving upper transistor is connected to the floating voltage signal, the source of the driving lower transistor is grounded, and the gate of the driving lower transistor is connected to the low-voltage signal; The signal generation module is used to generate the low-voltage signal and the lower transistor driving signal in the driving signal; The output clamping module is connected to the output end of the driving module and the output end of the signal generation module and is used to clamp the output voltage under the drive of the upper transistor driving signal and the lower transistor driving signal.

2. The drive circuit with output clamping according to claim 1, characterized in that, The first-level level conversion module includes: a first-level level conversion unit and a first-level driving enhancement unit, The first-level level conversion unit is used to convert the low-voltage signal into an original floating voltage signal; The first-level driving enhancement unit is connected to the output end of the first-level level conversion unit and is used to perform driving enhancement on the original floating voltage signal to generate the floating voltage signal.

3. The drive circuit with output clamping according to claim 2, characterized in that, The first-level level conversion unit includes: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor. The sources of the first NMOS transistor and the second NMOS transistor are both grounded. The drain of the first NMOS transistor is connected to the source of the third NMOS transistor. The drain of the second NMOS transistor is connected to the source of the fourth NMOS transistor. The gates of the first NMOS transistor and the second NMOS transistor are connected to a set of mutually inverted low-voltage signals. The drain of the third NMOS transistor is connected to the drain of the first PMOS transistor. The drain of the fourth NMOS transistor is connected to the drain of the second PMOS transistor. The gates of the third NMOS transistor and the fourth NMOS transistor are both connected to a first set voltage. The source of the first PMOS transistor is connected to the drain of the third PMOS transistor and the gate of the fourth PMOS transistor. The source of the second PMOS transistor is connected to the gate of the third PMOS transistor and the drain of the fourth PMOS transistor and generates the original floating voltage signal. The gates of the first PMOS transistor and the second PMOS transistor are both connected to a clamping voltage. The sources of the third PMOS transistor and the fourth PMOS transistor are both connected to a power supply voltage. The first-level driving enhancement unit includes: a first inverter, a second inverter, and a fifth PMOS transistor. The input terminal of the first inverter is connected to the original floating voltage signal. The output terminal of the first inverter is connected to the input terminal of the second inverter. The output terminal of the second inverter generates the floating voltage signal. The power supply terminals of the first inverter and the second inverter are both connected to the power supply voltage. The ground terminals of the first inverter and the second inverter are both connected to the source of the fifth PMOS transistor. The drain of the fifth PMOS transistor is grounded. The gate of the fifth PMOS transistor is connected to the clamping voltage.

4. The drive circuit with output clamping according to claim 2 or 3, characterized in that, The first-level level conversion module further includes: a clamping voltage generation unit, connected between the power supply voltage and the ground, for generating the clamping voltage.

5. The drive circuit with output clamping according to claim 4, characterized in that, The clamping voltage generation unit includes: at least one first Zener diode and a current source. The cathode of the first Zener diode is connected to the power supply voltage. The anode of the first Zener diode is connected to the input terminal of the current source and generates the clamping voltage. The output terminal of the current source is grounded. When the number of the first Zener diodes is greater than or equal to 2, multiple first Zener diodes are connected in series with each other, and the cathode of the first Zener diode string is connected to the power supply voltage, and the anode of the first Zener diode string is connected to the input terminal of the current source and generates the clamping voltage. Wherein, the second set voltage is determined by the Zener voltage value and the number of the first Zener diodes.

6. The drive circuit with output clamping according to claim 1, wherein The second-level level conversion module includes: a second-level level conversion unit and a second-level driving enhancement unit. The second-level level conversion unit is connected to the output end of the first-level level conversion module and is used to convert the floating voltage signal into an original low-voltage signal; The second-level driving enhancement unit is connected to the output end of the second-level level conversion unit and is used to enhance the drive of the original low-voltage signal to generate the low-voltage signal.

7. The drive circuit with output clamping according to claim 6, characterized in that, The second-level level conversion unit includes: a sixth PMOS transistor, a seventh PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor. The sources of the sixth PMOS transistor and the seventh PMOS transistor are both connected to the power supply voltage. The drain of the sixth PMOS transistor is connected to the drain of the fifth NMOS transistor. The drain of the seventh PMOS transistor is connected to the drain of the sixth NMOS transistor. The gates of the sixth PMOS transistor and the seventh PMOS transistor are connected to a set of mutually inverted floating voltage signals. The source of the fifth NMOS transistor is connected to the drain of the seventh NMOS transistor and the gate of the eighth NMOS transistor. The source of the sixth NMOS transistor is connected to the gate of the seventh NMOS transistor and the drain of the eighth NMOS transistor and generates the original low-voltage signal. The gates of the fifth NMOS transistor and the sixth NMOS transistor are both connected to a first set voltage. The sources of the seventh NMOS transistor and the eighth NMOS transistor are grounded. The second-level driving enhancement unit includes: a third inverter and a fourth inverter. The input end of the third inverter is connected to the original low-voltage signal. The output end of the third inverter is connected to the input end of the fourth inverter. The output end of the fourth inverter generates the low-voltage signal. The power supply ends of the third inverter and the fourth inverter are both connected to the first set voltage. The grounding ends of the third inverter and the fourth inverter are both grounded.

8. The drive circuit with output clamping according to claim 1, wherein, The output clamping module includes: an output upper transistor, an output lower transistor, and a clamping unit. The drain of the output upper transistor is connected to the power supply voltage. The source of the output upper transistor is connected to the drain of the output lower transistor and generates the output voltage. The gate of the output upper transistor is connected to the upper transistor drive signal in the drive signal. The source of the output lower transistor is grounded. The gate of the output lower transistor is connected to the lower transistor drive signal. The clamping unit is connected between the gate of the output upper transistor and the ground.

9. The drive circuit with output clamping according to claim 8, wherein, The clamping unit includes: at least one second Zener diode. The cathode of the second Zener diode is connected to the gate of the output upper transistor. The anode of the second Zener diode is grounded. When the clamping unit includes two or more second Zener diodes, the multiple second Zener diodes are connected in series with each other, and the cathode of the second Zener diode string is connected to the gate of the output upper transistor, and the anode of the second Zener diode string is grounded.

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