Circuit system of high-voltage signal generator

Abstract

The utility model discloses a circuit system of a high-voltage signal generator. The circuit system comprises a DDS main control circuit, a filter circuit, an operational amplifier circuit, a level conversion circuit, a power supply circuit and a crystal oscillator circuit, the output end of the DDS main control circuit is sequentially connected with the filter circuit and the operational amplifier circuit; the operational amplifier circuit is connected with the power supply circuit and the peripheral port; the DDS main control circuit is also respectively connected with the power supply circuit and the crystal oscillator circuit; the level conversion circuit is connected with the crystal oscillator circuit, the DDS main control circuit and the external power supply circuit; the power supply circuit is connected with an external power supply circuit. According to the scheme, numerous application requirements of high-voltage and high-precision signals can be met.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic systems, and in particular to a high-voltage signal generator circuit system. BACKGROUND

[0002] In recent years, a high-voltage signal generator is a key instrument in the fields of industrial detection, medical equipment, material testing, etc., and its core function is to generate an electric signal with high precision, high amplitude and pure waveform. The traditional high-voltage signal generator is usually based on an analog oscillation circuit or a phase-locked loop (PLL) frequency synthesis technology, and combines a multi-stage discrete component amplifier circuit to realize high-voltage output. However, such a scheme has significant defects, such as limited output swing, limited frequency control precision, limited waveform distortion and noise interference, etc. The temperature drift problem of the analog oscillation circuit and the frequency resolution limitation of the PLL make it difficult to realize wide-range and high-precision frequency adjustment.

[0003] The emerging direct digital frequency synthesis (DDS) technology gradually becomes the preferred scheme for signal source design due to its advantages of high frequency resolution, fast switching and full-digital control. However, most DDS schemes only output low-voltage signals (0-5V), and the bandwidth and slew rate (SR) of their amplifier circuits are insufficient, which easily causes high-frequency signal attenuation or waveform distortion.

[0004] The nonlinear characteristics and insufficient harmonic suppression of the amplifier circuit easily lead to high distortion of the output signal. The nonlinear characteristics of the high-voltage amplifier circuit can introduce high-order harmonics, and the limited stopband attenuation of the conventional low-order filter circuit (such as a second-order Butterworth filter) makes it difficult to meet the high-purity signal requirement.

[0005] The waveform generator instrument equipment on the market, such as SDG2082X (taking the Dingyang 80M signal source instrument as an example), has an output waveform peak value of 20V (±10V), which is the limit. Although it can be matched with a signal power amplifier SPA1010 module to provide only a 10V DC bias for the signal, it cannot meet the requirement of such high-voltage AC signals. CONTENT OF THE INVENTION

[0006] Embodiments of the present application provide a high-voltage signal generator circuit system.

[0007] To achieve the above-mentioned purpose, embodiments of the present application provide a high-voltage signal generator circuit system, which comprises a DDS master control circuit, a filter circuit, an operational amplifier circuit, a level conversion circuit, a power supply circuit and a crystal oscillator circuit.

[0008] The output end of the DDS master control circuit is connected to the filter circuit and the operational amplifier circuit in sequence; the operational amplifier circuit is connected to the power supply circuit and an external port;

[0009] The DDS master control circuit is also connected to the power supply circuit and the crystal oscillator circuit, respectively.

[0010] The level conversion circuit is connected with the crystal circuit, the DDS master circuit and the external power supply circuit.

[0011] The power supply circuit is connected with the external power supply circuit.

[0012] In one of the embodiments, the output signal of the DDS master circuit includes a first current signal and a second current signal which are complementary;

[0013] The filter circuit includes a first filter branch and a second filter branch, the first filter branch is connected with the first current signal, and the second filter branch is connected with the second current signal.

[0014] In one of the embodiments, the first filter branch and the second filter branch both include a seventh-order elliptic filter and an isolation capacitor; the input end of the seventh-order elliptic filter is connected with the output signal of the DDS master circuit, the output end of the seventh-order elliptic filter is connected with one end of the isolation capacitor, and the other end of the isolation capacitor is connected with the operational amplifier circuit.

[0015] In one of the embodiments, the operational amplifier circuit includes a first operational amplifier branch and a second operational amplifier branch, the first operational amplifier branch is connected with the first filter branch, and the second operational amplifier branch is connected with the second filter branch.

[0016] The first operational amplifier branch includes a first operational amplifier chip U6, a first inverting resistor RT4, a first non-inverting resistor RT6, a second non-inverting resistor RT5, a first feedback resistor RTT1, a first compensation capacitor C001, a first isolation resistor RT1, a second feedback resistor RTT2, a second compensation capacitor C002, a first decoupling capacitor C005, a second decoupling capacitor C006, a third decoupling capacitor C007 and a fourth decoupling capacitor C008.

[0017] The second operational amplifier branch includes a second operational amplifier chip U7, a second inverting resistor RT7, a third non-inverting resistor RT9, a fourth non-inverting resistor RT8, a third feedback resistor RTT3, a third compensation capacitor C003, a second isolation resistor RT3, a fourth feedback resistor RTT4, a fourth compensation capacitor C004, a fifth decoupling capacitor C009, a sixth decoupling capacitor C015, a seventh decoupling capacitor C016 and an eighth decoupling capacitor C017.

[0018] In one of the embodiments, the power supply pins of the first operational amplifier chip U6 and the second operational amplifier chip U7 are both connected with the power supply output +V O The pin is connected with the CS pin.

[0019] In one of the embodiments, the power supply circuit comprises: a first pre-filtering capacitor C099, a second pre-filtering capacitor C100, a DC / DC power module U5, a first input capacitor C101, a second input capacitor C102, a filtering inductor L01, a first output capacitor C103, a second output capacitor C104, a third output capacitor C105, and a fourth output capacitor C106;

[0020] The VIN pin and the GND pin of the DC / DC power module U5 are connected with an external power supply circuit;

[0021] The first pre-filtering capacitor C099 and the second pre-filtering capacitor C100 are connected with the filtering inductor L01 and the first input capacitor C101, and the first pre-filtering capacitor C099 and the second pre-filtering capacitor C100 are connected with the EARTH pin;

[0022] The second input capacitor C102 and the filtering inductor L01 are connected with the VIN pin of the DC / DC power module U5, and the first input capacitor C101 and the second input capacitor C102 are connected with the EARTH pin;

[0023] The +VO pin and the 0V pin of the DC / DC power module U5 are connected through one end of the first output capacitor C103 and one end of the second output capacitor C104, and the other end of the first output capacitor C103 and the other end of the second output capacitor C104 are connected with -15V;

[0024] The CS pin and the 0V pin of the DC / DC power module U5 are connected through one end of the third output capacitor C105 and one end of the fourth output capacitor C106, and the other end of the first output capacitor C103 and the other end of the second output capacitor C104 are connected with +15V;

[0025] The CTRL pin and the NC pin of the DC / DC power module U5 are left floating.

[0026] In one of the embodiments, the communication circuit and the MCU circuit are further included;

[0027] The MCU circuit is connected with the DDS master control circuit and the communication circuit respectively.

[0028] In one of the embodiments, the communication circuit comprises a communication chip U9;

[0029] The TX pin and the RX pin of the communication chip U9 are connected with the MCU circuit, the VREF pin of the communication chip U9 is connected with the MCU circuit through the first pull-up resistor R33, the RS pin of the communication chip U9 is connected with GND through the first pull-down resistor R35, the CAN bus differential output CANH pin and the CANL pin of the communication chip U9 are connected through the first impedance resistor R34, and the CANH pin and the CANL pin are respectively connected to the high level line and the low level line of the CAN bus;

[0030] The VCC pin of the communication chip U9 is connected with the MCU circuit through the second pull-up resistor R31 and the third pull-up resistor R32, the VCC pin is connected with the fifth filter capacitor C31 and is pulled down to GND; the TX pin of the communication chip U9 is connected with the CANTX pin of the MCU circuit, and is used for receiving the TTL level data signal sent by the microcontroller; and the RX pin of the communication chip U9 is connected with the CANRX pin of the MCU circuit, and is used for sending the data on the CAN bus to the MCU chip in the form of a TTL level.

[0031] Compared with the prior art, the high-voltage signal generator circuit system has the following beneficial effects: the filter circuit can effectively filter out the noise and high-order harmonics in the signal, so that the output signal is more pure, and in combination with the high-voltage operational amplifier circuit, the low-voltage signal generated by the DDS master control circuit can be amplified to ±24V high-voltage output, so as to meet the application requirements of many high-voltage and high-precision signals. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0033] Figure 1 It is a structural schematic diagram of the high-voltage signal generator circuit system of the embodiment of the present application.

[0034] Figure 2 It is a schematic diagram of the DDS master control circuit in the high-voltage signal generator circuit system of the embodiment of the present application.

[0035] Figure 3 It is a schematic diagram of the crystal oscillator circuit in the high-voltage signal generator circuit system of the embodiment of the present application.

[0036] Figure 4 It is a schematic diagram of the level conversion circuit in the high-voltage signal generator circuit system of the embodiment of the present application.

[0037] Figure 5The schematic diagram of the filter circuit in the high-voltage signal generator circuit system of the embodiment of the present application;

[0038] Figure 6 The schematic diagram of the operational amplifier circuit in the high-voltage signal generator circuit system of the embodiment of the present application;

[0039] Figure 7 The schematic diagram of the power supply circuit in the high-voltage signal generator circuit system of the embodiment of the present application;

[0040] Figure 8 The schematic diagram of the communication circuit in the high-voltage signal generator circuit system of the embodiment of the present application;

[0041] Figure 9 The schematic diagram of the MCU circuit in the high-voltage signal generator circuit system of the embodiment of the present application;

[0042] Figure 10 The schematic diagram of the external power supply circuit in the high-voltage signal generator circuit system of the embodiment of the present application. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0044] In the description of the present application, it should be understood that the terms "center", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only intended to facilitate the description of the present application and simplify the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0045] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connection" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integrally connected, and those of ordinary skill in the art can understand the specific meaning of the above terms in the present application according to the specific circumstances.

[0046] The terms "first", "second", "third", etc. are used only for descriptive purposes and are not to be construed as indicating or implying relative importance or an indicated number of features. Thus, features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise stated.

[0047] Referring to Figure 1 Embodiments of the present application provide a high-voltage signal generator circuit system, comprising:

[0048] DDS master circuit 1, filter circuit 2, operational amplifier circuit 3, level conversion circuit 4, power supply circuit 5 and crystal oscillator circuit 6;

[0049] The output end of the DDS master circuit 1 is connected to the filter circuit 2 and the operational amplifier circuit 3 in turn; the operational amplifier circuit 3 is connected to the power supply circuit 5 and the peripheral port;

[0050] The DDS master circuit 1 is also connected to the power supply circuit 5 and the crystal oscillator circuit 6 respectively;

[0051] The level conversion circuit 4 is connected to the crystal oscillator circuit 6, the DDS master circuit 1 and the external power supply circuit 9;

[0052] The power supply circuit 5 is connected to the external power supply circuit 9.

[0053] Specifically, the output end of the DDS master circuit 1 is connected to the filter circuit 2, for outputting an AC signal to the filter circuit 2 according to an external DDS synthesized signal; the output end of the filter circuit 2 is connected to the operational amplifier circuit 3, for outputting a voltage signal to the operational amplifier circuit 3 according to a filtered signal, wherein the filter circuit 2 can effectively filter out noise and high-order harmonics in the signal, making the output signal more pure; the operational amplifier circuit 3 is connected to the peripheral port, for outputting a high-voltage AC signal amplified by the operational amplifier circuit 3, the operational amplifier circuit amplifying the low-voltage signal adjusted by the filter circuit 2 to high-voltage output; one end of the level conversion circuit 4 is connected to the DDS master circuit 1 and the crystal oscillator circuit 6, for inputting the required 3.3V voltage of the DDS master circuit 1 and the crystal oscillator circuit 6 to the DDS master circuit 1; the crystal oscillator circuit 6 is connected to the DDS master circuit 1, for providing a 75MHz CLOCK signal; the power supply circuit 5 is connected to the operational amplifier circuit 3 and the DDS master circuit 1 circuit, for providing a power supply. The power supply circuit 5 is connected to the external power supply circuit 9.

[0054] The output signal of the DDS master circuit 1 includes two complementary first current signals I OUTB and second current signals I OUT , two I OUT , I OUTBThe current signal can be converted into different types of voltage signals by the configuration of the control register and the design of the external circuit.

[0055] The DDS master circuit 1 uses a fully integrated direct digital frequency synthesis (DDS) chip, which requires a reference clock, a precision low resistance and eight decoupling capacitors to generate a sine wave of up to 37.5 MHz in a digital manner. In addition to generating this RF signal, the chip can fully support various simple and complex modulation schemes. These modulation schemes are fully implemented in the digital domain, making it possible to use DSP technology to accurately and easily implement complex modulation algorithms. The internal circuit of the DDS chip U1 includes the following main parts: numerically controlled oscillator (NCO), frequency and phase modulator, SIN ROM, DAC, comparator, and voltage stabilizer.

[0056] Further, the DDS chip U1 directly synthesizes the required frequency and phase offset by digital accumulation and digital-to-analog conversion using the principle of linear increase of the phase of a sine signal. It is known that the phase of a sine wave is linear, and given a reference time interval (clock period), the phase rotation within the period can be determined:

[0057] ΔPhase = ωΔt (1)

[0058] where: ΔPhase is the phase, ω is the angular frequency, and Δt is the reference period. Solve ω:

[0059] ω = ΔPhase / (Δt = 2πf) (2)

[0060] Solve f and replace the reference period (1 / f MCLK = Δt) with the reference clock frequency, MCLK

[0061] f = ΔPhase x f MCLK / 2π (3)

[0062] Therefore, the DDS chip U1 constructs the output according to the above formula, and the NCO is mainly implemented by a phase accumulator using 28 bits. Therefore, 2π = 2 28 , and the ΔPhase term will also expand to this value range, so the frequency control word is determined by formula (4), where 0 < ΔPhase <= 2 28 -1,

[0063] f = ΔPhase x f MCLK / 2 28 (4)

[0064] ​The input to the phase accumulator of the DDS chip U1 can be selected from either the FREQ0 register or the FREQ1 register and controlled by the FSELECT pin or the FSEL bit. The NCO itself generates a continuous phase signal, so any discontinuity in the output should be avoided when switching between frequencies. After the NCO, a phase modulation can be performed by adding a phase offset using the 12-bit phase registers. The content of one of these phase registers is added to the MSB of the NCO.

[0065] As shown in Figure 2 , the DDS master circuit 1 comprises a DDS chip U1, a first modulation capacitor C1, a first modulation resistor R1, a second modulation capacitor C2, a first decoupling capacitor C11, a second decoupling capacitor C12, a third decoupling capacitor C10, a fourth decoupling capacitor C3, a fifth decoupling capacitor C5, a sixth decoupling capacitor C6, a seventh decoupling capacitor C7, a first load resistor R10, a second load resistor R7, a first isolation resistor R11, a second isolation resistor R8, a third isolation resistor R5, a fourth isolation resistor R6, a first current limiting resistor RP1, a second current limiting resistor RP2, a third current limiting resistor RP3, a fourth current limiting resistor RP4, a fifth current limiting resistor RP5, a sixth current limiting resistor RP6, a seventh current limiting resistor RP7, an eighth current limiting resistor RP8, a ninth current limiting resistor RP9, a tenth current limiting resistor RP10, and an eleventh current limiting resistor RP11.

[0066] Referring to Figure 2 , the AVDD pin of the DDS chip U1 is connected to a 5V DC voltage, the DVDD pin of the DDS chip U1 is connected to a 3.3V DC voltage, the COMP pin of the DDS chip U1 is connected to the 5V DC voltage through the fourth decoupling capacitor C3 to decouple the DAC bias voltage, and the FS_ADJUST pin of the DDS chip U1 is pulled down to GND through the 0.1 μF first modulation capacitor C1 and the 6.8K first modulation resistor R1, thereby setting the amplitude of the full-scale DAC current. When the first modulation resistor R1 is 6.8K, the full-amplitude output current is 3mA. The output compliance voltage ensures that the output impedance of the internal switch does not change, and the calculation method is shown in formula (5) and formula (6), where FSADJUST = 1.15V (nominal value), R SET = 6.8kΩ.

[0067] IOUT FULL SCALE = 18 x FSADJUST / R SET (5)

[0068] FSADJUST = 1.15V (nominal value), ΔPhase x f MCLK / 2 28 (6)

[0069] The REFOUT pin of the DDS chip U1 is pulled down to GND through the second modulation capacitor C2 to provide a 1.2V internal reference voltage output. The CAP / 2.5V pin of the DDS chip U1 is pulled down to GND through the first decoupling capacitor C11 and the second decoupling capacitor C12 to provide a 2.5V power supply for the internal digital circuit. The MCLK pin of the DDS chip U1 is connected to the output terminal of the crystal oscillator circuit 6 through the fifth isolation resistor R9 (see Figure 3 the seventh decoupling capacitor C7 and the first load resistor R10 of 200Ω to pull down to GND, forming an RC filter for high-impedance current source output, while taking into account the steady-state characteristics and dynamic characteristics, wherein the resistance and capacitance values can be replaced to select a suitable cut-off frequency FS. The first isolation resistor R11 is connected to the IOUTB pin and the input terminal of the filter circuit 2, thereby transmitting the current signal generated by the DDS chip to the filter circuit 2 for filtering. The IOUT pin of the DDS chip U1 is pulled down to GND through the sixth decoupling capacitor C6 and the second load resistor R7 of 200Ω to form an RC filter for high-impedance current source output, wherein the resistance and capacitance values can be replaced to select a suitable cut-off frequency FS. The second isolation resistor R8 is connected to the IOUT pin and the input terminal of the filter circuit 2, thereby transmitting the current signal generated by the DDS chip to the filter circuit 2 for filtering. The VIN pin of the DDS chip U1 is connected to the fourth isolation resistor R6 of 300Ω and the fifth decoupling capacitor C5 to generate a square wave from the sine DAC output and improve the jitter performance. The FSELECT frequency selection input pin, the PSELECT phase selection input pin, the RESET high-level effective digital input pin, the SLEEP high-level effective digital input pin, the SDATA serial data input pin, the SCLK serial clock input pin, and the FSYNC low-level effective control input pin of the DDS chip U1 are connected to the first current limiting resistor RP1, the second current limiting resistor RP2, the third current limiting resistor RP3, the fourth current limiting resistor RP4, the fifth current limiting resistor RP5, the sixth current limiting resistor RP6, and the seventh current limiting resistor RP7 to the external port, wherein the FSELECT frequency selection input pin, the PSELECT phase selection input pin, the RESET high-level effective digital input pin, and the SLEEP high-level effective digital input pin are connected through the eighth current limiting resistor RP8, the ninth current limiting resistor RP9, the tenth current limiting resistor RP10, and the eleventh current limiting resistor RP11 and pulled down to GND.

[0070] Further, the DDS chip U1 includes a high-impedance, current source 10-bit DAC that can drive various loads. The DAC can be configured to operate in single-ended mode or differential mode. OUT and I OUTBThe DDS chip U1 can be used to generate a synthesized frequency digital clock signal, and a sine wave signal of the DAC is converted into a square wave by using a self-biasing comparator inside the chip. The output of the DAC is first filtered externally and then applied to the input of the comparator. The reference voltage of the comparator is the time average of the signal applied to V IN p-p p-p

[0071] Further, the FSYNC low-level effective control input pin of the DDS chip U1 is connected to the first current-limiting resistor RP1 externally, and is used for frame synchronization and chip enable. Data can be transmitted to the device only when the FSYNC pin is at the low level. The FSYNC pin should be pulled low when starting the serial data transmission, and the minimum value of the time of the falling edge of the SCLK to the rising edge of the FSYNC pin should be noted. After the FSYNC pin becomes low, the serial data will be moved into the input shift register of the device at the falling edge of the 16th clock pulse SCLK. The FSYNC pin can be pulled high after the 16th falling edge of the SCLK, and the minimum value of the time of the falling edge of the SCLK to the rising edge of the FSYNC pin should be noted. The FSYNC can remain low during the 16 multiple SCLK pulses, and then becomes high at the end of the data transmission. In this way, 16-bit words can be loaded in a continuous stream during the FSYNC pin remains low; the FSYNC pin becomes high only after the 16th SCLK falling edge when the last word is loaded.

[0072] Further, the SCLK of the DDS chip U1 can be continuous, or can be placed in a high or low idle state during the write operation, but must be in a high state when the FSYNC becomes low.

[0073] Further, the FSELECT frequency selection input pin and the PSELECT phase selection input pin of the DDS chip U1 are both sampled at the internal falling edge of the MCLK, and each operation will cause a delay. When the values of the FSELECT pin and the PSELECT pin are changed, there will be a pipeline delay before the control information is transmitted to the selected register. Each asynchronous write operation will also cause a delay. If a new data word is loaded into the selected frequency or phase register, there will be a delay of 8 to 9 MCLK cycles before the analog output changes. The negative conversion of the RESET and SLEEP functions is also sampled at the internal falling edge of the MCLK, which will also cause a delay.

[0074] ​​​Further, the high level effective digital input pin of the RESET of the DDS chip U1 can reset the corresponding internal register to 0 to provide the intermediate level analog output. The RESET pin will not reset the phase, frequency or control register. The device is reset when powered on, the RESET pin / bit should be set to 1, and the device should be reset by setting the pin / bit to 0. Within 7 MCLK cycles after the RESET is set to 0, the DAC output end will appear a signal. The RESET function is controlled by the RESET pin and the RESET control bit, when PIN / SW = 0, the function is controlled by the RESET bit, and when PIN / SW = 1, the function is controlled by the RESET pin.

[0075] As a preferred, the model of the DDS chip U1 is preferably AD9834.

[0076] As shown in Figure 3 , the crystal oscillator circuit 6 includes a 75MHz active crystal oscillator U2, a fifth isolation resistor R9, an eighth decoupling capacitor C8 and a ninth decoupling capacitor C9.

[0077] The active crystal oscillator U2 mainly consists of a quartz crystal, an oscillation circuit, an amplification circuit, a filter circuit and a power supply circuit, etc., for generating a 75MHz clock signal. The VCC pin of U2 is connected with the output of the level conversion circuit 4, the eighth decoupling capacitor C8 and the ninth decoupling capacitor C9 are pulled down to GND and connected with the VCC pin, the OUTPUT pin of U2 is connected with the fifth isolation resistor R9 of 0Ω, which can form an RC integration circuit with the equivalent capacitor of the internal output end of the active crystal oscillator U2, to reduce harmonic interference and play a limiting role, the GND pin of U2 is connected to DGND, and the OE pin of U2 is left hanging.

[0078] As a preferred, the model of the active crystal oscillator U2 is selected as 1532D-75.000K33DTL, which is a 75MHz active crystal oscillator with high voltage stabilization, low temperature drift and strong anti-interference ability, and has advanced TCXO (temperature compensated crystal oscillator) technology and extremely low temperature drift ±10ppm temperature characteristics.

[0079] As shown in Figure 4 , the level conversion circuit 4 includes an LDO chip U3, a first current limiting resistor R01, a first LED light emitting diode LED1, a first filter capacitor C19, a second filter capacitor C20, a third filter capacitor C21 and a fourth filter capacitor C22.

[0080] Specifically, the VIN pin of the LDO chip U3 in the level conversion circuit 4 is connected with the VBUS pin of the external power supply circuit 9.

[0081] Wherein, the VIN of the LDO chip U3 is an input power supply pin, the first filter capacitor C19 and the second filter capacitor C20 are connected between the VIN pin and the GND pin to form a filter circuit to weaken the noise interference brought by the external power supply circuit 9. The VOUT pin of the LDO chip U3 is an output power supply, and the third filter capacitor C21 and the fourth filter capacitor C22 are connected to the VOUT pin and the GND pin to filter out the output ripple, thereby providing a stable 3.3V voltage for the DDS chip U1 and the active crystal oscillator U2. The size of the output capacitance determines the voltage ripple at the input end of the LDO chip U3. The VOUT pin of the LDO chip U3 is connected to the first LED light emitting diode LED1 and the first current limiting resistor R01 to determine whether the LDO chip U3 normally outputs a 3.3V high-level power supply signal.

[0082] As a preferred, the model of the LDO chip U3 is selected as ASM1117-3.3V. The ASM1117-3.3V is a fixed version 3.3V output, low dropout, high precision and high voltage regulator LDO chip, which has extremely high output voltage precision and excellent low output ripple effect.

[0083] Further, the filter circuit 2 filters out high-frequency stray signals caused by various errors. The signal output by the built-in DAC of the DDS chip is not a standard sine signal, but a stepped analog signal with a sine profile, which contains a large number of stray components. Based on the Nyquist sampling theorem, the output frequency of the DDS is only half of the maximum clock frequency, so more stray waves will be output during actual output. For a given passband ripple and order requirement, the transition band of the elliptic filter is very narrow, and it has equal ripple characteristics in the passband and the stopband, minimizes amplitude distortion in the passband, and maximizes signal suppression in the stopband. The zero-pole distribution of the transfer function determines the attenuation characteristics and notch points of the filter circuit, thereby achieving the filtering function with specific ripple requirements and steep transition band in the passband and the stopband.

[0084] As shown in Figure 5 , the filter circuit 2 includes a first filter branch and a second filter branch. The first filter branch is used to filter the I OUTB current output signal in the DDS master control circuit, and the second filter branch is used to filter the I OUTThe current output signal is filtered. The first filtering branch consists of capacitors C01, C02, C03, C04, C05, C06, C07, L1, L2, L3, and Cd1 (first isolation capacitor). The second filtering branch consists of capacitors C08, C09, C010, C011, C012, C013, C014, L4, L5, L6, and Cd2 (second isolation capacitor). OUTB The current output signal first enters a seventh-order elliptic filter circuit composed of a first capacitor C01, a second capacitor C02, a first filter inductor L1, a third capacitor C03, a fourth capacitor C04, a second filter inductor L2, a fifth capacitor C05, a sixth capacitor C06, a third filter inductor L3, and a seventh capacitor C07 for filtering. Then, it enters the first isolation capacitor Cd1 to achieve AC coupling and DC blocking while passing AC, simultaneously improving the frequency response due to signal attenuation after the seventh-order elliptic filter circuit. OUT The same applies to the output signal of the circuit current. Finally, the output of the filter circuit is connected to operational amplifier circuit 3.

[0085] like Figure 5 The amplitude response function of the filter circuit 2 shown is:

[0086]

[0087] In the formula, ω is a parameter related to ripple. C R is the cutoff frequency of the low-pass filter, n is the order of the filter, and R is the value of the filter. n 2 (ω / ω C The value varies depending on whether n is odd or even.

[0088] When n is odd

[0089] When n is even

[0090] Passband flatness parameter R p =10log(1+ε 2 (10).

[0091] Stopband attenuation R s =10log(1+ε 2 R n 2 (ω / ω C ))(11).

[0092] In the formula ω / ω C =fs f c f s = 120 MHz, f c = 100 MHz, R p = 0.1 dB, R s = 60 dB.

[0093] As shown in Figure 6 , the operational amplifier circuit 3 includes a first operational amplifier branch and a second operational amplifier branch, the first operational amplifier branch is connected with the first filter branch, and the second operational amplifier branch is connected with the second filter branch;

[0094] The first operational amplifier branch includes: a first operational amplifier chip U6, a first inverting resistor RT4, a first non-inverting resistor RT6, a second non-inverting resistor RT5, a first feedback resistor RTT1, a first compensation capacitor C001, a first isolation resistor RT1, a second feedback resistor RTT2, a second compensation capacitor C002, a first decoupling capacitor C005, a second decoupling capacitor C006, a third decoupling capacitor C007, and a fourth decoupling capacitor C008.

[0095] The second operational amplifier branch includes: a second operational amplifier chip U7, a second inverting resistor RT7, a third non-inverting resistor RT9, a fourth non-inverting resistor RT8, a third feedback resistor RTT3, a third compensation capacitor C003, a second isolation resistor RT3, a fourth feedback resistor RTT4, a fourth compensation capacitor C004, a fifth decoupling capacitor C009, a sixth decoupling capacitor C015, a seventh decoupling capacitor C016, and an eighth decoupling capacitor C017.

[0096] The -INA pin of the first operational amplifier chip U6 in the first operational amplifier branch is connected with the first inverting resistor RT4, the first feedback resistor RTT1, and the first compensation capacitor C001, and the other end of the first inverting resistor RT4 is connected with PSSD.

[0097] The -VS pin of the first operational amplifier chip U6 is connected with the first decoupling capacitor C005 and the second decoupling capacitor C006 to the output pin CS of the power supply circuit, and the other end of the first decoupling capacitor C005 is connected with the other end of the second decoupling capacitor C006 to VSSD.

[0098] The +VS pin of the first operational amplifier chip U6 is connected with the third decoupling capacitor C007 and the fourth decoupling capacitor C008 to the output pin +VO of the power supply circuit, and the other end of the third decoupling capacitor C007 is connected with the other end of the fourth decoupling capacitor C008 to VSSD.

[0099] The +INA pin of the first operational amplifier chip U6 is connected with the second non-inverting resistor RT5, the other end of the second non-inverting resistor RT5 is connected with the first non-inverting resistor RT6 to the output end IOUTB+ of the first filter branch, and the other end of the first non-inverting resistor RT6 is connected with VSSD.

[0100] The OUTA pin of the first operational amplifier chip U6 is connected with the first isolation resistor RT1, the first feedback resistor RTT1 and the first compensation capacitor C001, and the other end of the first isolation resistor RT1 is connected with the +INB pin of the operational amplifier chip U6;

[0101] The -INB pin of the first operational amplifier chip U6 is connected with the second feedback resistor RTT2 and the second compensation capacitor C002, and the other end of the second feedback resistor RTT2 and the second compensation capacitor C002 is connected with the OUTB pin of the operational amplifier chip U6;

[0102] The OUTB pin of the first operational amplifier chip U6 is output to the peripheral port.

[0103] The second operational amplifier branch is the same as the first operational amplifier branch.

[0104] Specifically, the supply pins of the first operational amplifier chip U6 and the second operational amplifier chip U7 of the operational amplifier circuit are connected with the supply output 6 pin +V O and the 8 pin CS pin of the supply circuit DC / DC power module U5.

[0105] Further, the amplitude of the signal output by the DDS chip U1 is small, and therefore, in order to meet the design target, the signal needs to be amplified. The first operational amplifier chip U6 of the operational amplifier circuit adopts a same-direction proportional operational amplifier circuit design for amplification, and is matched with the first inverting resistor RT4 and the first feedback resistor RTT1 to form a first-stage signal amplification circuit, and the amplification factor is A=(1+RTT1 / RT4). The first compensation capacitor C001 is used to prevent the output oscillation caused by the decrease of the operational amplifier phase margin. The second non-inverting resistor RT5 is an input impedance matching resistor, and the first non-inverting resistor RT6 is pulled down to ensure the stability of the front-end signal input. The second-stage operational amplifier design of the first operational amplifier chip U6 is a follower circuit, and the current is large at a voltage, and therefore, the second isolation resistor RT3 needs to suppress the large current to ensure the stability of the VOUT output waveform. The operational amplifier pressure swing rate is 20V / μs, and the requirement is ±24V p-p , and the SR pressure swing rate is calculated as: SR=2×3.14×24×10KHz×10 -3 =1.5V / μs, which fully meets the design requirement.

[0106] As a preferred, the model of the first operational amplifier chip U6 and the second operational amplifier chip U7 of the operational amplifier circuit is preferably LTA8092, which has the characteristics of rail-to-rail input and output, GBW up to 22MHz and SR of 20V / μA, which can ensure effective reduction of distortion and delay when processing high-frequency or rapidly changing signals. The robust design of LTA8092 and the suppression filter integrated with radio frequency electromagnetic interference do not have phase inversion under overdrive conditions. The core of the operational amplifier circuit is to amplify the tiny high-frequency voltage signal, filter out the interference signals caused by the parasitic parameters of the front-end filter circuit, offset the influence of signal interference between the power ground and the analog ground, and output stable AC signals.

[0107] In one embodiment, as shown in Figure 7 the power supply circuit 5 includes: a first pre-filtering capacitor C099, a second pre-filtering capacitor C100, a DC / DC power module U5, a first input capacitor C101, a second input capacitor C102, a filtering inductor L01, a first output capacitor C103, a second output capacitor C104, a third output capacitor C105, and a fourth output capacitor C106;

[0108] The VIN pin and the GND pin of the DC / DC power module U5 are connected with an external power supply circuit;

[0109] The first pre-filtering capacitor C099 and the second pre-filtering capacitor C100 are connected with the filtering inductor L01 and the first input capacitor C101, and the first pre-filtering capacitor C099 and the second pre-filtering capacitor C100 are connected with the EARTH pin;

[0110] The first input capacitor C102 and the filtering inductor L01 are both connected with the VIN pin of the DC / DC power module U5, and the first input capacitor C101 and the second input capacitor C102 are connected with the EARTH pin;

[0111] The +VO pin and the 0V pin of the DC / DC power module U5 are connected through one end of the first output capacitor C103 and one end of the second output capacitor C104, and the other end of the first output capacitor C103 and the other end of the second output capacitor C104 are connected with -15V;

[0112] The CS pin and the 0V pin of the DC / DC power module U5 are connected through one end of the third output capacitor C105 and one end of the fourth output capacitor C106, and the other end of the first output capacitor C103 and the other end of the second output capacitor C104 are connected with +15V;

[0113] The CTRL pin and the NC pin of the DC / DC power module U5 are left floating.

[0114] In one embodiment, referring to Figure 1The system further comprises a communication circuit 7 and an MCU circuit 8; the MCU circuit 8 is connected with the DDS master control circuit 1 and the communication circuit 7 respectively.

[0115] As shown in the figure, the communication circuit 7 comprises a CAN communication chip U9, a first impedance resistor R34, a first pull-down resistor R35, a first pull-up resistor R33, a second pull-up resistor R31, a third pull-up resistor R32, and a fifth filter capacitor C31. Figure 8

[0116] The TX pin and the RX pin of the communication chip U9 are connected with the MCU circuit 8, the VREF pin of the communication chip U9 is connected with the MCU circuit 8 through the first pull-up resistor R33, the RS pin of the communication chip U9 is connected with GND through the first pull-down resistor R35, the CAN bus differential output CANH pin and the CANL pin of the communication chip U9 are connected through the first impedance resistor R34, the CANH pin and the CANL pin are respectively connected to the high level and the low level line of the CAN bus, and the first impedance resistor R34 is used to match the characteristic impedance of the bus, reduce signal reflection, and ensure that the signals on the bus can be correctly received and transmitted.

[0117] The VCC pin of the communication chip U9 is connected with the MCU circuit 8 through the second pull-up resistor R31 and the third pull-up resistor R32, and the VCC pin is connected with the fifth filter capacitor C31 and pulled down to GND; the TX pin of the communication chip U9 is connected with the CANTX pin of the MCU circuit 8, and is used to receive the TTL level data signal transmitted by the microcontroller; the RX pin of the communication chip U9 is connected with the CANRX pin of the MCU circuit 8, and is used to transmit the data on the CAN bus to the MCU chip in the form of TTL level.

[0118] Specifically, the model of the CAN communication chip U9 is preferably CA-IF1051VS, which can convert the TTL level signal of the MCU and the differential signal on the CAN bus, and realize the communication between the MCU and the CAN bus device. It conforms to the ISO11898-2:2016 and ISO11898-5:2007 physical layer technical specification, and is designed for high-speed CAN FD network, which can support a transmission rate of up to 5Mbps. The CAN bus port provides up to ±58V fault protection, meeting the overvoltage protection requirement. The receiver input common mode range (CMR) is up to ±30V, with an independent logic power supply pin V IO .

[0119] The receiver converts the differential input (CANH and CANL) of the bus into a single-ended output signal RXD required by the CAN controller, and an internal comparator detects the differential voltage V DIFF =(V CANH -V CANL ​), the threshold voltage is about 0.7V. If V DIFF 0.9V, the RXD pin outputs a logic low level; if V DIFF <0.5V, the RXD outputs a logic high level. According to the ISO11898 standard, the maximum number of nodes of the CAN bus is 30, the communication chip U9 has a high input impedance (the minimum value is 30kΩ), and the driver can provide a minimum differential driving voltage of 1.5V under a 60Ω bus load (at least 1.4V differential output under a 45Ω bus load).

[0120] As shown in Figure 9 , the model of the MCU chip of the MCU circuit 8 is preferably QJ32F407RGT6, the I / O pins of the CANTX and CANRX defined by the MCU chip of the MCU circuit 8 are connected with the same defined output pins of the communication circuit, the I / O pins of the driving signal defined FSELSE, PSELE, RESET, SLEEP, FSYNC, SCLK, SDATA of the MCU chip of the MCU circuit are connected with the same defined pins of the DDS chip of the DDS master circuit, so as to generate high and low level signals controlled by timing logic, and the output pins of the DDS chip are connected to the I / O ports of the PB3 and PB4 of the MCU chip, so as to feed back the generated signals to the MCU chip to form a closed loop.

[0121] Specifically, the instructions of the communication circuit 7 are input to the I / O port of the MCU chip of the MCU circuit 8 through the CAN communication pin, the MCU chip of the MCU circuit 8 outputs high and low level signals to the DDS chip of the DDS master circuit to control it, so as to output current signals to the filter circuit 3 according to the instructions of the MCU circuit 8, then the current signals are input to the input pin of the operational amplifier of the analog signal acquisition circuit 4 through the sampling resistor of the power circuit 3 for signal acquisition, and the output pin of the DDS chip is connected to the I / O port of the PB3 and PB4 of the MCU chip, so as to feed back the generated signals to the MCU chip to form a closed loop.

[0122] As shown in Figure 10 , the external power supply circuit 9 is a Type-C power interface, which is based on the USB3.1 protocol standard, and the V BUS pin of the external power supply circuit 9 is connected with the level conversion circuit 4 and the power supply circuit 5. The design of this circuit not only can stabilize the +5V power supply voltage, but also can perform simple data transmission function.

[0123] Specifically, the communication circuit includes a first Type-C interface U4, a first Type-C interface U8, a first current limiting resistor R13, a first current limiting resistor R14, a first light emitting diode LED3, and a second light emitting diode LED4.

[0124] V of the first Type-C interface U4 BUS LDO chip U3 of the pin and level conversion circuit 4 IN Pin connection, through which the 5V is converted to 3.3V and the DDS master control circuit 1 and the crystal circuit 6 are powered; V of the second Type-C interface U8 BUS Pin connection with the POWER pin of the power supply circuit 5, used for powering the DC / DC power supply module U5 and outputting ±24V high voltage level, thereby powering the operational amplifier circuit 3.

[0125] The high-voltage signal generator circuit system provided by the present application, the master control chip in the DDS master control circuit has excellent frequency control capability, and the frequency resolution can reach 0.001Hz, which can accurately generate digital signals of various frequencies. The seven-order elliptical filter circuit is matched synchronously, which has steep cutoff characteristics and can effectively filter out noise and high-order harmonics in the signal, making the output signal more pure. Combined with the high-voltage operational amplifier chip in the operational amplifier circuit, it has high voltage slew rate and high output impedance characteristics, which can amplify the low-voltage signal generated by the DDS master control chip to ±24V high-voltage output, meeting the application requirements of many high-voltage and high-precision signals.

[0126] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited to this, any change or replacement within the technical scope disclosed in the present application should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A high voltage signal generator circuit system, characterized by, The application relates to a DDS (Direct Digital Synthesizer) circuit, which comprises a DDS master control circuit (1), a filter circuit (2), an operational amplifier circuit (3), a level conversion circuit (4), a power supply circuit (5) and a crystal oscillator circuit (6). The output end of the DDS master control circuit (1) is sequentially connected with the filter circuit (2) and the operational amplifier circuit (3); the operational amplifier circuit (3) is connected with the power supply circuit (5) and an external port; The DDS master control circuit (1) is further connected with the power supply circuit (5) and the crystal oscillator circuit (6) respectively; The level conversion circuit (4) is connected with the crystal oscillator circuit (6), the DDS master control circuit (1) and an external power supply circuit (9); The power supply circuit (5) is connected with the external power supply circuit (9). The output signal of the DDS master control circuit (1) comprises a first current signal and a second current signal; 2. The high voltage signal generator circuitry of claim 1, wherein, The filter circuit (2) comprises a first filter branch and a second filter branch; the first filter branch is connected with the first current signal, and the second filter branch is connected with the second current signal. The first filter branch and the second filter branch both comprise a seventh-order elliptic filter and an isolation capacitor; the input end of the seventh-order elliptic filter is connected with the output signal of the DDS master control circuit (1), the output end of the seventh-order elliptic filter is connected with one end of the isolation capacitor, and the other end of the isolation capacitor is connected with the operational amplifier circuit (3).

3. The high-voltage signal generator circuitry of claim 2, wherein, The operational amplifier circuit (3) comprises a first operational amplifier branch and a second operational amplifier branch; the first operational amplifier branch is connected with the first filter branch, and the second operational amplifier branch is connected with the second filter branch; 4. The high voltage signal generator circuitry of claim 2, wherein, The first operational amplifier branch comprises a first operational amplifier chip U6, a first inverting resistor RT4, a first non-inverting resistor RT6, a second non-inverting resistor RT5, a first feedback resistor RTT1, a first compensation capacitor C001, a first isolation resistor RT1, a second feedback resistor RTT2, a second compensation capacitor C002, a first decoupling capacitor C005, a second decoupling capacitor C006, a third decoupling capacitor C007 and a fourth decoupling capacitor C008; The second operational amplifier branch comprises a second operational amplifier chip U7, a second inverting resistor RT7, a third non-inverting resistor RT9, a fourth non-inverting resistor RT8, a third feedback resistor RTT3, a third compensation capacitor C003, a second isolation resistor RT3, a fourth feedback resistor RTT4, a fourth compensation capacitor C004, a fifth decoupling capacitor C009, a sixth decoupling capacitor C015, a seventh decoupling capacitor C016 and an eighth decoupling capacitor C017. The power supply circuit (5) comprises a first filter capacitor C099, a second filter capacitor C100, a DC / DC power supply module U5, a first input capacitor C101, a second input capacitor C102, a filter inductor L01, a first output capacitor C103, a second output capacitor C104, a third output capacitor C105 and a fourth output capacitor C106; 5. The high voltage signal generator circuitry of claim 4, wherein, The power supply pins of the first operational amplifier chip U6 and the second operational amplifier chip U7 are connected with the power supply output +V of the power supply circuit DC / DC power module U5 O The pin is connected with the CS pin.

6. The high voltage signal generator circuitry of claim 1, wherein, The VIN pin and the GND pin of the DC / DC power supply module U5 are connected with an external power supply circuit. ​ The front first filter capacitor C099 and the front second filter capacitor C100 are connected with the filter inductor L01 and the first input capacitor C101, and the front first filter capacitor C099 and the front second filter capacitor C100 are connected with the EARTH pin in common; The second input capacitor C102 and the filter inductor L01 are connected with the VIN pin of the DC / DC power module U5, and the first input capacitor C101 and the second input capacitor C102 are connected with the EARTH pin in common; The +VO pin and the 0V pin of the DC / DC power module U5 are connected through one end of the first output capacitor C103 and one end of the second output capacitor C104, and the other end of the first output capacitor C103 and the other end of the second output capacitor C104 are connected with -15V; The CS pin and the 0V pin of the DC / DC power module U5 are connected through one end of the third output capacitor C105 and one end of the fourth output capacitor C106, and the other end of the first output capacitor C103 and the other end of the second output capacitor C104 are connected with +15V; The CTRL pin of the DC / DC power module U5 is suspended with the NC pin.

7. The high voltage signal generator circuitry of claim 1, wherein, Further comprising a communication circuit (7) and an MCU circuit (8); The MCU circuit (8) is connected with the DDS master control circuit (1) and the communication circuit (7) respectively.

8. The high-voltage signal generator circuitry of claim 7, wherein, The communication circuit (7) comprises a communication chip U9; The TX pin and the RX pin of the communication chip U9 are connected with the MCU circuit (8), the VREF pin of the communication chip U9 is connected with the MCU circuit (8) through the first pull-up resistor R33, the RS pin of the communication chip U9 is connected with GND through the first pull-down resistor R35, the CAN bus differential output CANH pin and the CANL pin of the communication chip U9 are connected through the first impedance resistor R34, and the CANH pin and the CANL pin are respectively connected to the high level line and the low level line of the CAN bus; The VCC pin of the communication chip U9 is connected with the MCU circuit (8) through the second pull-up resistor R31 and the third pull-up resistor R32, and the VCC pin is connected with the fifth filter capacitor C31 and pulled down to GND; the TX pin of the communication chip U9 is connected with the CANTX pin of the MCU circuit (8), used for receiving the TTL level data signal sent by the microcontroller; and the RX pin of the communication chip U9 is connected with the CANRX pin of the MCU circuit (8), used for sending the data on the CAN bus to the MCU chip in the form of TTL level.

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