A redundant interlock circuit for automotive-grade chips

Abstract

The present invention provides a redundant interlocking circuit for an automotive-grade chip. The redundant interlocking circuit includes a first low-side driver module, a second low-side driver module, a first interlocking circuit, and a second interlocking circuit. When the first low-side driver module is working, the second low-side driver module is locked in a closed state through the first interlocking circuit and the second interlocking circuit. When the second low-side driver module is working, the first low-side driver module is locked in a closed state through the first interlocking circuit and the second interlocking circuit. The first interlocking circuit and the second interlocking circuit can each independently implement an interlocking function between the first low-side driver module and the second low-side driver module, that is, the first interlocking circuit and the second interlocking circuit implement redundant interlocking. After one of the first interlocking circuit and the second interlocking circuit is destroyed, the interlocking function between the first low-side driver module and the second low-side driver module can still be implemented through the other one, thereby preventing the interlocking function from failing.

Description

Technical Field

[0001] The present invention relates to the technical field of interlocking circuits, and in particular to a redundant interlocking circuit for automotive-grade chips. Background Art

[0002] With the rapid development of new energy vehicles in my country, vehicle functionality is becoming increasingly complex, requiring a greater number of chips and a higher level of integration. A single chip has multiple channels, capable of driving multiple loads. Sometimes, when one load is operating, another must be shut down, requiring interlocking between loads. For example, when a car is in forward gear, the system requires the reverse gear controller to be disabled, otherwise the vehicle's drive logic will malfunction. Another example is ensuring the accelerator is locked when the brake is applied.

[0003] In the actual application of automotive systems, automotive-grade chips have very high functional safety requirements, and the interlocking logic of the driving circuit must be accurate. However, the existing automotive interlocking circuits are likely to be damaged by external interference. Once damaged, the automotive-grade chips will lose the corresponding interlocking function. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide an interlocking circuit which can prevent the interlocking function from failing.

[0005] To solve the above technical problems, the present invention provides a redundant interlock circuit for automotive-grade chips, which is characterized by comprising a first low-side driver module, a second low-side driver module, a first interlock circuit and a second interlock circuit, wherein:

[0006] The first low-side driver module includes a first drive circuit and a first switch power tube, the first switch power tube is connected to the main circuit of the first low-side driver module, and the first drive circuit is connected to the control electrode of the first switch power tube; the second low-side driver module includes a second drive circuit and a second switch power tube, the second switch power tube is connected to the main circuit of the second low-side driver module, and the second drive circuit is connected to the control electrode of the second switch power tube;

[0007] The first interlock circuit includes a first logic AND gate, a second logic AND gate, a first inverter, a second inverter, a third inverter, and a control signal input terminal; the control signal input terminal is connected to the first input terminal of the first logic AND gate and connected to the first input terminal of the second logic AND gate via the first inverter; the output terminal of the first logic AND gate is connected to the first drive circuit, the first drive circuit is connected to the second input terminal of the second logic AND gate via the second inverter, the output terminal of the second logic AND gate is connected to the second drive circuit, and the second drive circuit is connected to the second input terminal of the first logic AND gate via the third inverter;

[0008] The second interlock circuit includes a third switching power tube, a fourth switching power tube, a first comparator and a second comparator. The contact between the first drive circuit and the first switching power tube is grounded via the third switching power tube, and the contact between the second drive circuit and the second switching power tube is grounded via the fourth switching power tube. The positive input terminal of the first comparator is connected to the contact between the first drive circuit and the first switching power tube, the negative input terminal is connected to the reference voltage, and the output terminal is connected to the control electrode of the fourth switching power tube. The positive input terminal of the second comparator is connected to the contact between the second drive circuit and the second switching power tube, the negative input terminal is connected to the reference voltage, and the output terminal is connected to the control electrode of the third switching power tube.

[0009] Furthermore, the output end of the first logic AND gate is specifically connected to the first driving circuit via a first buffer, and the output end of the second logic AND gate is specifically connected to the second driving circuit via a second buffer.

[0010] Furthermore, the first power tube is an N-type MOS tube, the drain of which is connected to the load in the main circuit of the first low-side driver module, the source is grounded, the gate is the control electrode, and is connected to the first driver circuit; the second power tube is an N-type MOS tube, the drain of which is connected to the load in the main circuit of the second low-side driver module, the source is grounded, the gate is the control electrode, and is connected to the second driver circuit.

[0011] Furthermore, the third power tube is an N-type MOS tube, a drain of which is connected to the connection between the first drive circuit and the first switching power tube, a source is grounded, and a gate is a control electrode connected to the output end of the second comparator; the fourth power tube is an N-type MOS tube, a drain of which is connected to the connection between the second drive circuit and the second switching power tube, a source is grounded, and a gate is a control electrode connected to the output end of the first comparator.

[0012] Furthermore, the third power tube is an NPN type transistor, whose collector is connected to the contact between the first drive circuit and the first switching power tube, the emitter is grounded, and the base serves as a control electrode and is connected to the output end of the second comparator; the fourth power tube is an NPN type transistor, whose collector is connected to the contact between the second drive circuit and the second switching power tube, the emitter is grounded, and the base serves as a control electrode and is connected to the output end of the first comparator.

[0013] Furthermore, the negative input terminal of the first comparator is connected to the reference voltage specifically: the negative input terminal of the first comparator is connected to the reference voltage circuit, the reference voltage circuit includes a power supply and two resistors, the power supply is grounded in turn through the two resistors, and a reference voltage obtained by dividing the power supply voltage by the resistors is generated between the two resistors, and the negative input terminal of the first comparator is connected to the connection point between the two resistors to access the reference voltage; the negative input terminal of the second comparator is connected to the reference voltage specifically: the negative input terminal of the second comparator is connected to the reference voltage circuit, the reference voltage circuit includes a power supply and two resistors, the power supply is grounded in turn through the two resistors, and a reference voltage obtained by dividing the power supply voltage by the resistors is generated between the two resistors, and the negative input terminal of the second comparator is connected to the connection point between the two resistors to access the reference voltage.

[0014] Furthermore, the negative phase input terminal of the first comparator and the negative phase input terminal of the second comparator are connected to a reference voltage, specifically, a bandgap reference circuit is connected to the bandgap reference voltage.

[0015] The present invention has the following beneficial effects: in an initial state, the first drive circuit and the second drive circuit are turned off to generate a low-level signal. The low-level signal generated by the first drive circuit is converted by the second inverter into a high-level signal and input to the second input of the second logic AND gate. The low-level signal generated by the second drive circuit is converted by the third inverter into a high-level signal and input to the second input of the first logic AND gate. When a high-level signal is input to the control signal input terminal, the high-level signal is directly input to the first input terminal of the first logic AND gate. Since the second input terminal of the first logic AND gate has already input a high-level signal in the initial state, both input terminals of the first logic AND gate are high-level. The output terminal of the first logic AND gate outputs a high-level signal to the first drive circuit, causing the first drive circuit to operate and generate a high-level signal to turn on the first switch power transistor, thereby causing the first low-side driver module to operate. At this time, the high-level signal generated by the operation of the first drive circuit is converted by the second inverter into a low-level signal and output to the second logic AND gate, causing the output terminal of the second logic AND gate to continuously output a low-level signal to the second drive circuit. The second drive circuit then generates a low-level signal to turn off the second switch power transistor, thereby locking the second low-side driver module in an off state. When a low-level signal is input to the control signal input terminal, the low-level signal is converted to a high-level signal by the first inverter and then input to the first input terminal of the second logic AND gate. Since a high-level signal is already input to the second input terminal of the second logic AND gate in the initial state, both input terminals of the second logic AND gate are at a high level. The second logic AND gate then outputs a high-level signal to the second driver circuit, causing the second driver circuit to operate and generate a high-level signal to turn on the second switching power transistor, thereby operating the second low-side driver module. At this time, the high-level signal generated by the second driver circuit is converted to a low-level signal by the third inverter and output to the first logic AND gate, causing the output terminal of the first logic AND gate to continuously output a low-level signal to the first driver circuit. The first driver circuit then generates a low-level signal to turn off the first switching power transistor, locking the first low-side driver module in an off state. In this way, the first interlock circuit locks the second low-side driver module in an off state when the first low-side driver module is operating, and locks the first low-side driver module in an off state when the second low-side driver module is operating.

[0016] During the operation of the first low-side driver module, the first driver circuit generates a high level to turn on the first switching power tube, and the contact between the first driver circuit and the first switching power tube inputs a high level to the positive input terminal of the first comparator. The high level is greater than the reference voltage connected to the negative input terminal of the first comparator, and the first comparator outputs a high level to the control electrode of the fourth switching power tube, so that the fourth switching power tube is turned on. After the fourth switching power tube is turned on, a strong pull-down path is created between the second driver circuit and the control electrode of the second switching power tube, so that the control electrode level of the second switching power tube is pulled down, ensuring that the second switching power tube is turned off. In this way, the second interlock circuit is used to lock the second low-side driver module in the off state when the first low-side driver module is operating. During the operation of the second low-side driver module, the second driver circuit generates a high level to turn on the second switch power tube, and the contact between the second driver circuit and the second switch power tube inputs a high level to the positive input terminal of the second comparator. The high level is greater than the reference voltage connected to the negative input terminal of the second comparator, and the second comparator outputs a high level to the control electrode of the third switch power tube, so that the third switch power tube is turned on. After the third switch power tube is turned on, a strong pull-down path is created between the first driver circuit and the control electrode of the first switch power tube, so that the control electrode level of the first switch power tube is pulled down, ensuring that the first switch power tube is turned off. In this way, the second interlock circuit is used to lock the first low-side driver module in the off state when the second low-side driver module is operating.

[0017] In summary, the first interlock circuit and the second interlock circuit can independently realize the interlocking function between the first low-side driver module and the second low-side driver module, that is, the first interlock circuit and the second interlock circuit realize redundant interlocking. After one of the first interlock circuit and the second interlock circuit is destroyed, the interlocking function between the first low-side driver module and the second low-side driver module can still be realized through the other one, thereby preventing the interlocking function from failing. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a circuit schematic diagram of a redundant interlocking circuit for an automotive-grade chip according to Example 1.

[0019] Figure 2 This is a circuit schematic diagram of the redundant interlocking circuit for automotive-grade chips in Example 2.

[0020] Figure 3 This is a circuit schematic diagram of the redundant interlocking circuit for automotive-grade chips in Example 3. DETAILED DESCRIPTION

[0021] The present invention is further described in detail below in conjunction with specific embodiments.

[0022] Example 1

[0023] This embodiment provides a redundant interlocking circuit for automotive-grade chips, such as Figure 1 As shown, the redundant interlock circuit includes a first low-side driver module 1, a second low-side driver module 2, a first interlock circuit 3, and a second interlock circuit 4. A low-side driver module refers to a module in an electronic circuit that drives a load by grounding a switch. The characteristic of the module is that the load is activated by closing the ground switch.

[0024] The first low-side driver module 1 includes a first drive circuit DC1 and a first switching power transistor M1. The first switching power transistor M1 is connected to the main circuit of the first low-side driver module 1. The first drive circuit DC1 is connected to the control electrode of the first switching power transistor M1. Specifically, the first switching power transistor M1 is an N-type MOS transistor, with its drain connected to the load in the main circuit of the first low-side driver module 1, its source grounded, and its gate serving as the control electrode, connected to the first drive circuit DC1. The second low-side driver module 2 includes a second drive circuit DC2 and a second switching power transistor M2. The second switching power transistor M2 is connected to the main circuit of the second low-side driver module 2. The second drive circuit DC2 is connected to the control electrode of the second switching power transistor M2. Specifically, the second switching power transistor M2 is an N-type MOS transistor, with its drain connected to the load in the main circuit of the second low-side driver module 2, its source grounded, and its gate serving as the control electrode, connected to the second drive circuit DC2.

[0025] The first interlock circuit 3 includes a first logic AND gate C1, a second logic AND gate C2, a first inverter D1, a second inverter D2, a third inverter D3, a first buffer B1, a second buffer B2, and a control signal input terminal IN. A logic AND gate is a basic logic gate circuit that performs an AND operation. It has multiple inputs and one output. The output is high (logic 1) only when all inputs are simultaneously high (logic 1); otherwise, the output is low (logic 0). In this embodiment, the first logic AND gate C1 and the second logic AND gate C2 each have two inputs and one output. An inverter, also known as a logical NOT gate, has one input and one output. When its input is high (logic 1), the output is low (logic 0), and when its input is low, the output is high. In other words, the input and output levels of an inverter are always in opposite phases. A buffer is an electronic device used in electronic circuits to enhance signals and isolate loads. When the level signal is weak or a stronger level is required, a buffer can be used to enhance the signal level. At the same time, the buffer can prevent the resistance between the input and output from affecting each other, so that the load circuit is not affected by fluctuations in the input signal level.

[0026] In the first interlock circuit 3, the control signal input terminal IN is connected to the first input terminal of the first logic AND gate C1, and is connected to the first input terminal of the second logic AND gate C2 via the first inverter D1. The output terminal of the first logic AND gate C1 is connected to the first drive circuit DC1 via the first buffer B1. The first drive circuit DC1 is connected to the second input terminal of the second logic AND gate C2 via the second inverter D2. The output terminal of the second logic AND gate C2 is connected to the second drive circuit DC2 via the second buffer B2. The second drive circuit DC2 is connected to the second input terminal of the first logic AND gate C1 via the third inverter D3.

[0027] In the initial state, the first drive circuit DC1 and the second drive circuit DC2 are turned off to generate a low-level signal. The low-level signal generated by the first drive circuit DC1 is converted into a high-level signal by the second inverter D2 and input into the second input end of the second logic AND gate C2. The low-level signal is also output to the control electrode of the first switching power tube M1, causing the first switching power tube M1 to be turned off. As a result, the load of the first low-side driver module 1 cannot be grounded through the first switching power tube M1, and the first low-side driver module 1 is in the off state. The low-level signal generated by the second drive circuit DC2 is converted into a high-level signal by the third inverter D3 and input into the second input end of the first logic AND gate C1. The low-level signal is also output to the control electrode of the second switching power tube M2, causing the second switching power tube M2 to be turned off. As a result, the load of the second low-side driver module 2 cannot be grounded through the second switching power tube M2, and the second low-side driver module 2 is in the off state.

[0028] When a high-level signal is input to the control signal input terminal IN, it is directly input to the first input terminal of the first logic AND gate C1. Since a high-level signal is already input to the second input terminal of the first logic AND gate C1 in the initial state, both input terminals of the first logic AND gate C1 are at a high level. The output terminal of the first logic AND gate C1 then outputs a high-level signal to the first driver circuit DC1, causing the first driver circuit DC1 to operate and generate a high-level signal, turning on the first power switch M1. This grounds the load of the first low-side driver module 1 through the first power switch M1, thus activating the first low-side driver module 1. The high-level signal input to the control signal input terminal IN is also converted to a low-level signal by the first inverter D1 and then input to the first input terminal of the second logic AND gate C2. The output terminal of the second logic AND gate C2 then outputs a low-level signal to the second driver circuit DC2. The low-level signal generated by the second driver circuit DC2 keeps the second power switch M2 off, preventing the load of the second low-side driver module 2 from being grounded through the second power switch M2. This shuts down the second low-side driver module 2. When the first low-side driver module 1 is operating, the high-level signal generated by the first driver circuit DC1 is converted into a low-level signal by the second inverter D2 and output to the second input end of the second logic AND gate C2, so that the output end of the second logic AND gate C2 continuously outputs a low-level signal to the second driver circuit DC2, ensuring that the second driver circuit DC2 generates a low level signal to turn off the second switching power tube M2, so that the load of the second low-side driver module 2 cannot be grounded through the second switching power tube M2, and the second low-side driver module 2 is locked in the off state.

[0029] When a low-level signal is input to the control signal input terminal IN, it is converted to a high-level signal by the first inverter D1 and then input to the first input terminal of the second logic AND gate C2. Since a high-level signal is initially input to the second input terminal of the second logic AND gate C2, both input terminals of the second logic AND gate C2 are high. The second logic AND gate C2 then outputs a high-level signal to the second driver circuit DC2, causing the second driver circuit DC2 to operate and generate a high-level signal, turning on the second power switch M2 and activating the second low-side driver module 2. The low-level signal input to the control signal input terminal IN is also directly input to the first input terminal of the first logic AND gate C1, causing the output terminal of the first logic AND gate C1 to output a low-level signal to the first driver circuit DC1. The low-level signal generated by the first driver circuit DC1 keeps the first power switch M1 in the off state, preventing the load of the first low-side driver module 1 from being connected to ground through the first power switch M1. Consequently, the first low-side driver module 1 is shut down and inoperative. When the second low-side driver module 2 is operating, the high-level signal generated by the second driver circuit DC2 is converted into a low-level signal by the third inverter D3 and output to the second input end of the first logic AND gate C1, so that the output end of the first logic AND gate C1 continuously outputs a low-level signal to the first driver circuit DC1, ensuring that the first driver circuit DC1 generates a low level to turn off the first switching power tube M1, so that the load of the first low-side driver module 1 cannot be grounded through the first switching power tube M1, and the first low-side driver module 1 is locked in the off state.

[0030] In summary, when a high-level signal is input to the control signal input terminal IN, the first interlock circuit 3 is used to enable the first low-side driver module 1 to operate and the second low-side driver module 2 to be locked in the off state. When a low-level signal is input to the control signal input terminal IN, the first interlock circuit 3 is used to enable the second low-side driver module 2 to operate and the first low-side driver module 1 to be locked in the off state.

[0031] The second interlock circuit 4 includes a third power switch M3, a fourth power switch M4, a first comparator COMP1, and a second comparator COMP2. The junction between the first drive circuit DC1 and the first power switch M1 is grounded via the third power switch M3. Specifically, the third power switch M3 is an N-type MOS transistor, with its drain connected to the junction between the first drive circuit DC1 and the first power switch M1, its source grounded, and its gate serving as a control electrode. The junction between the second drive circuit DC2 and the second power switch M2 is grounded via a fourth power switch M4. Specifically, the fourth power switch M4 is an N-type MOS transistor, with its drain connected to the junction between the second drive circuit DC2 and the second power switch M2, its source grounded, and its gate serving as a control electrode. The first comparator COMP1 has a positive input connected to the junction between the first drive circuit DC1 and the first switching power transistor M1, a negative input connected to a reference voltage, and an output connected to the control electrode of the fourth switching power transistor M4. The second comparator COMP1 has a positive input connected to the junction between the second drive circuit DC2 and the second switching power transistor M2, a negative input connected to a reference voltage, and an output connected to the control electrode of the third switching power transistor M3. The reference voltage is provided by using a resistor-divider power supply voltage solution. Specifically, the negative input of the first comparator COMP1 is connected to a reference voltage circuit comprising a power supply and two resistors. The power supply is connected to ground in sequence through the two resistors, generating a reference voltage between the two resistors by dividing the power supply voltage with resistors. The negative input of the first comparator COMP1 is connected to the junction between the two resistors to access the reference voltage. Similarly, the negative input terminal of the second comparator COMP2 is connected to another reference voltage circuit with the same structure. The reference voltage circuit includes a power supply and two resistors. The power supply is grounded in turn through the two resistors. A reference voltage is generated between the two resistors after the power supply voltage is divided by the resistors. The negative input terminal of the second comparator COMP2 is connected to the junction between the two resistors to access the reference voltage.

[0032] During operation of the first low-side driver module 1, the first drive circuit DC1 generates a high level to turn on the first power switch M1. The junction between the first drive circuit DC1 and the first power switch M1 then inputs a high level to the positive input terminal of the first comparator COMP1. This high level is greater than the reference voltage connected to the negative input terminal of the first comparator COMP1. The first comparator COMP1 then outputs a high level to the control electrode of the fourth power switch M4, turning on the fourth power switch M4. After the fourth power switch M4 is turned on, a strong pull-down path is created between the second drive circuit DC2 and the control electrode of the second power switch M2, pulling down the control electrode level of the second power switch M2. This ensures that the control electrode level of the second power switch M2 does not reach a high level, ensuring that the second power switch M2 is turned off. In this way, the second interlock circuit 4 is used to lock the second low-side driver module 2 in an off state when the first low-side driver module 1 is operating. During the operation of the second low-side driver module 2, the second drive circuit DC2 generates a high level to turn on the second switch power transistor M2. The junction between the second drive circuit DC2 and the second switch power transistor M2 inputs a high level to the positive-phase input terminal of the second comparator COMP2. This high level is greater than the reference voltage connected to the negative-phase input terminal of the second comparator COMP2. The second comparator COMP2 then outputs a high level to the control electrode of the third switch power transistor M3, turning on the third switch power transistor M3. After the third switch power transistor M3 is turned on, a strong pull-down path is created between the first drive circuit DC1 and the control electrode of the first switch power transistor M1, pulling down the control electrode level of the first switch power transistor M1. This ensures that the control electrode level of the first switch power transistor M1 will not be a high level, ensuring that the first switch power transistor M1 is turned off. In this way, the second interlock circuit 4 is used to lock the first low-side driver module 1 in the off state when the second low-side driver module 2 is operating.

[0033] In summary, the first interlock circuit 3 and the second interlock circuit 4 can independently realize the interlocking function between the first low-side driver module 1 and the second low-side driver module 2, that is, the first interlock circuit 3 and the second interlock circuit 4 realize redundant interlocking. After one of the first interlock circuit 3 and the second interlock circuit 4 is destroyed, the interlocking function between the first low-side driver module 1 and the second low-side driver module 2 can still be realized through the other one, thereby preventing the interlocking function from failing.

[0034] Example 2

[0035] This embodiment provides another redundant interlock circuit for automotive-grade chips, such as Figure 2As shown, the redundant interlock circuit is basically the same as that of the first embodiment, except that the reference voltage connected to the negative phase input terminal of the first comparator COMP1 and the negative phase input terminal of the second comparator COMP2 is not provided by a solution of using a resistor divider power supply voltage, but is connected to a bandgap reference circuit to access the bandgap reference voltage Bandgap, which is more accurate and stable than the solution of using a resistor divider power supply voltage.

[0036] Example 3

[0037] This embodiment provides another redundant interlock circuit for automotive-grade chips, such as Figure 3 As shown, this redundant interlock circuit is essentially the same as that of the first embodiment, except that the third and fourth power switches M3 and M4 are NPN transistors instead of N-type MOS transistors. The collector of the third power switch M3 is connected to the junction between the first drive circuit DC1 and the first power switch M1, the emitter is grounded, and the base serves as a control electrode connected to the output of the second comparator COMP2. The collector of the fourth power switch M4 is connected to the junction between the second drive circuit DC2 and the second power switch M2, the emitter is grounded, and the base serves as a control electrode connected to the output of the first comparator COMP1. Using transistors as pull-down transistors for the third and fourth power switches M3 and M4 can improve the response speed of the second interlock circuit 4.

[0038] The above is only an embodiment of the present invention and does not limit the scope of patent protection. Those skilled in the art can make non-substantial changes or substitutions based on the present invention and still fall within the scope of patent protection.

Claims

1. A redundant interlocking circuit for automotive-grade chips, characterized in that: It includes a first low-side driver module, a second low-side driver module, a first interlock circuit and a second interlock circuit, wherein: The first low-side driver module includes a first drive circuit and a first switch power tube, the first switch power tube is connected to the main circuit of the first low-side driver module, and the first drive circuit is connected to the control electrode of the first switch power tube; the second low-side driver module includes a second drive circuit and a second switch power tube, the second switch power tube is connected to the main circuit of the second low-side driver module, and the second drive circuit is connected to the control electrode of the second switch power tube; The first switching power tube is an N-type MOS tube, whose drain is connected to the load in the main circuit of the first low-side driver module, the source is grounded, the gate is the control electrode, and is connected to the first driver circuit; the second switching power tube is an N-type MOS tube, whose drain is connected to the load in the main circuit of the second low-side driver module, the source is grounded, the gate is the control electrode, and is connected to the second driver circuit; The first interlock circuit includes a first logic AND gate, a second logic AND gate, a first inverter, a second inverter, a third inverter, and a control signal input terminal; the control signal input terminal is connected to the first input terminal of the first logic AND gate and connected to the first input terminal of the second logic AND gate via the first inverter; the output terminal of the first logic AND gate is connected to the first drive circuit, the first drive circuit is connected to the second input terminal of the second logic AND gate via the second inverter, the output terminal of the second logic AND gate is connected to the second drive circuit, and the second drive circuit is connected to the second input terminal of the first logic AND gate via the third inverter; The second interlock circuit includes a third switching power tube, a fourth switching power tube, a first comparator and a second comparator. The contact between the first drive circuit and the first switching power tube is grounded via the third switching power tube, and the contact between the second drive circuit and the second switching power tube is grounded via the fourth switching power tube. The positive input terminal of the first comparator is connected to the contact between the first drive circuit and the first switching power tube, the negative input terminal is connected to the reference voltage, and the output terminal is connected to the control electrode of the fourth switching power tube. The positive input terminal of the second comparator is connected to the contact between the second drive circuit and the second switching power tube, the negative input terminal is connected to the reference voltage, and the output terminal is connected to the control electrode of the third switching power tube.

2. The redundant interlocking circuit for automotive-grade chips according to claim 1 is characterized in that: The output end of the first logic AND gate is specifically connected to the first driving circuit via a first buffer, and the output end of the second logic AND gate is specifically connected to the second driving circuit via a second buffer.

3. The redundant interlock circuit for automotive-grade chips according to claim 1 is characterized in that: The third switching power tube is an N-type MOS tube, whose drain is connected to the contact between the first drive circuit and the first switching power tube, the source is grounded, and the gate is a control electrode connected to the output end of the second comparator; the fourth switching power tube is an N-type MOS tube, whose drain is connected to the contact between the second drive circuit and the second switching power tube, the source is grounded, and the gate is a control electrode connected to the output end of the first comparator.

4. The redundant interlock circuit for automotive-grade chips according to claim 1 is characterized in that: The third switching power tube is an NPN type transistor, whose collector is connected to the contact between the first drive circuit and the first switching power tube, the emitter is grounded, and the base serves as a control electrode and is connected to the output end of the second comparator; the fourth switching power tube is an NPN type transistor, whose collector is connected to the contact between the second drive circuit and the second switching power tube, the emitter is grounded, and the base serves as a control electrode and is connected to the output end of the first comparator.

5. The redundant interlocking circuit for automotive-grade chips according to claim 1 is characterized in that: The negative input terminal of the first comparator is connected to a reference voltage. Specifically, the negative input terminal of the first comparator is connected to a reference voltage circuit, which includes a power supply and two resistors. The power supply is connected to ground via the two resistors in sequence, and a reference voltage is generated between the two resistors by dividing the power supply voltage by the resistors. The negative input terminal of the first comparator is connected to a junction between the two resistors to connect to the reference voltage. The negative input terminal of the second comparator is connected to the reference voltage. Specifically: the negative input terminal of the second comparator is connected to the reference voltage circuit, and the reference voltage circuit includes a power supply and two resistors. The power supply is grounded in turn through the two resistors, and a reference voltage is generated between the two resistors after the power supply voltage is divided by the resistors. The negative input terminal of the second comparator is connected to the junction between the two resistors to access the reference voltage.

6. The redundant interlock circuit for automotive-grade chips according to claim 1, characterized in that: The negative phase input terminal of the first comparator and the negative phase input terminal of the second comparator are connected to a reference voltage, specifically, a bandgap reference circuit is connected to the bandgap reference voltage.

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