Signal processing device and method

Abstract

The present application relates to a signal processing apparatus, comprising: a first switch unit configured to receive a first analog signal; a first analog-to-digital conversion unit coupled to the first switch unit and configured to convert the first analog signal into a first digital signal; a core processing unit coupled to the first analog-to-digital conversion unit and configured to process the first digital signal and output a second digital signal at least comprising digital pre-distortion information; a first digital-to-analog conversion unit coupled to the core processing unit and configured to convert the second digital signal into a second analog signal; and the second switch unit is coupled to the first digital-to-analog conversion unit and is configured to output the second analog signal. The invention further relates to a signal processing method and electronic equipment. According to the invention, the problems of performance and linearity caused by a power amplifier can be overcome, and the processing performance and the adaptability are relatively high.

Description

Technical Field

[0001] The present invention relates to the field of communications, and in particular to a signal processing device and method. Background Art

[0002] The development of communication systems has always been limited by components, especially the materials and process levels of RF components, and faces the mutually exclusive contradictions between transmission bandwidth, transmission power, signal linearity and system efficiency. Increasing the transmission power may cause signal distortion or poor linearity, while pursuing linear signal without distortion may reduce system efficiency and increase the heat dissipation burden.

[0003] Figures 1 to 3 This is a schematic diagram of the transmitting part of an existing communication system. A general communication system includes two parts: transmitting and receiving, and each part may have multiple channels working simultaneously or non-simultaneously.

[0004] RF power amplifiers (RF PAs or PAs) are used to amplify small RF signals to increase the transmission distance. Due to material limitations, the design of RF PAs requires trade-offs among important indicators such as output power, linearity, efficiency, and output bandwidth.

[0005] In order to reduce or eliminate nonlinear problems such as those caused by power amplifiers, current RF enhancement technologies are mainly concentrated in digital intermediate frequency positions or baseband chips. However, this solution has a high threshold for use and a fixed system structure, which limits the application of RF enhancement functions in the terminal field and is only used in a small range of high-power devices.

[0006] like Figure 1 and Figure 2 The system in the needs FPGA to support the implementation of digital signal processing functions in the baseband to achieve the purpose of optimizing RF performance, such as reducing or eliminating the nonlinear effects caused by power amplifiers. In both solutions, the digital signal processing modules are located in the baseband chip and are usually implemented using FPGA. However, FPGA has a large area and high production cost, so the system performance and cost will be affected by the performance of FPGA and RF chip. The system shown in Figure 3 requires the FPGA in the baseband chip and the digital signal processing module 410 in the highly integrated RF chip 400 to work together to achieve the purpose of optimizing RF performance. The digital signal processing module 410 in the highly integrated RF chip 400 has limited performance and poor adaptability and can only be used in limited application scenarios. The RF chip 400 needs to cooperate with the FPGA and needs to be connected using a high-speed digital interface. The high cost of this interface will increase the overall product cost. Summary of the invention

[0007] In response to the technical problems existing in the prior art, the present application proposes a signal processing device, comprising: a first switch unit, configured to receive a first analog signal; a first analog-to-digital conversion unit, coupled to the first switch unit, configured to convert the first analog signal into a first digital signal; a core processing unit, coupled to the first analog-to-digital conversion unit, configured to process the first digital signal and output a second digital signal including at least digital pre-distortion information; a first digital-to-analog conversion unit, coupled to the core processing unit, configured to convert the second digital signal into a second analog signal; and a second switch unit, coupled to the first digital-to-analog conversion unit, configured to output the second analog signal.

[0008] In particular, the device further includes a second analog-to-digital conversion unit configured to receive an output signal of a power amplifier outside the signal processing device, convert the output signal of the power amplifier into a third digital signal and provide it to the core processing unit.

[0009] Particularly, in the device, the second switch unit is also coupled to the first switch unit to jointly form an uplink channel.

[0010] Particularly, in the device, the core processing unit is configured to obtain a second digital signal with digital predistortion information based on the first digital signal and the third digital signal.

[0011] In particular, the device further comprises a main control unit, which is coupled to all other units and configures initialization parameters of other units.

[0012] In particular, the device, wherein the core processing unit includes a peak clipping function module, configured to clip and peak suppress the first digital signal; a digital pre-distortion function module, configured to implement a pre-distortion function; a DC compensation function module includes a receiving DC compensation subunit, a transmitting DC compensation subunit and a feedback DC compensation subunit, respectively configured to compensate for the DC components of the first digital signal, after digital pre-distortion processing and in the feedback observation channel; the equalization function module includes an input equalization subunit, a transmitting equalization subunit and a feedback equalization subunit, configured to compensate for the distortion and interference introduced in the channel; the frequency conversion orthogonal compensation function module includes an input down-conversion orthogonal compensation subunit, a transmitting up-conversion orthogonal compensation and a feedback down-conversion orthogonal compensation, configured to implement a mirror correction function.

[0013] The present application also relates to an electronic device, comprising any of the above-mentioned devices.

[0014] The present application also relates to a signal processing method performed by a signal processing device, including setting a switch mode to enter a downlink mode, receiving a first analog signal; performing analog-to-digital conversion on the first analog signal to obtain a first digital signal; performing a digital predistortion operation on the first digital signal to obtain a second digital signal including at least digital predistortion information; converting the second digital signal into a second analog signal and outputting it.

[0015] In particular, the method further includes obtaining a signal output by the power amplifier and converting it into a third digital signal.

[0016] In particular, the method further includes obtaining a second digital signal including digital predistortion information based on the first digital signal and the third digital signal.

[0017] The solution proposed in this application does not require any changes to the existing baseband chip or RF chip, while achieving compensation or calibration of the nonlinear distortion generated by the power amplifier, thereby reducing the cost of the equipment and being compatible with various communication devices or systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Below, the preferred embodiments of the present application will be further described in detail with reference to the accompanying drawings, wherein: Figures 1 to 3 It is a schematic diagram of the transmitting part of the existing communication system; Figure 4 Shown is a module schematic diagram of a signal processing device according to an embodiment of the present application; Figure 5 Shown is a comparison diagram of radio frequency signals before and after being processed by the signal processing device in the present application according to an embodiment of the present application; Figure 6 FIG. 4 is a schematic flow chart of a signal processing method according to an embodiment of the present application. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0020] In the following detailed description, reference may be made to the various specification drawings that are part of the present application and are used to illustrate specific embodiments of the present application. In the accompanying drawings, similar reference numerals describe substantially similar components in different figures. The various specific embodiments of the present application are described below in sufficient detail so that a person of ordinary skill in the art with relevant knowledge and skills in the art can implement the technical solutions of the present application. It should be understood that other embodiments may also be used or structural, logical or electrical changes may be made to the embodiments of the present application.

[0021] The technologies, methods and devices known to those skilled in the art may not be discussed in detail, but where appropriate, the technologies, methods and devices shall be considered as part of the specification. The lines between the units in the drawings are only for the convenience of explanation, indicating that at least the units at both ends of the lines are communicating with each other, and are not intended to limit the unconnected units from being unable to communicate. In addition, the number of lines between two units is intended to indicate at least the number of signals involved in the communication between the two units or at least the output terminals, and is not intended to limit the two units to only be able to communicate with each other through the signals shown in the figure.

[0022] The current plan is through Figure 1 or Figure 2 The digital signal processing module 120 or 220 or Figure 3 The digital signal processing module 410 in the system is used to compensate the digital signal in an attempt to solve problems such as signal linearity. In addition, it is necessary to match peripheral devices such as ADC and DAC and corresponding clock circuits, which makes the system design face challenges in terms of interface and electrical characteristics matching, and will further increase the cost, area and power consumption of the system. In addition, the signal processing algorithm is not targeted and cannot process the signal according to the usage scenario and signal quality. At present, there are some applications or devices that do not have such digital signal processing modules. Or, based on cost considerations, for some equipment manufacturers, the current expectation or trend is to provide equipment that does not include a digital processing module or only provides a digital processing module with basic functions. This situation causes the communication system to either reduce the efficiency of the power amplifier or exchange high costs for signal linearity performance. But more expectations are to achieve the improvement of linearity while achieving optimal efficiency at a lower cost and a better design solution.

[0023] The present application provides a signal processing device that overcomes the performance and linearity problems brought by the power amplifier in the form of an independent functional module, and has high processing performance and adaptability, thereby lowering the application threshold of RF enhancement technology and reducing the cost of the system. In addition, the signal processing algorithm installed in the signal processing device includes customized pre-distortion processing, which can more effectively improve the linearity of the RF signal. Under the same signal quality, the power, efficiency and bandwidth that the power amplifier can achieve are further improved.

[0024] Figure 4 The module schematic diagram of the signal processing device according to one embodiment of the present application is shown. In the present application, "analog" refers to a relatively low-frequency analog signal, whose center frequency is near the zero frequency; "radio frequency" refers to a relatively high-frequency analog signal, whose center frequency is outside the zero frequency, for example, 900MHz.

[0025] As shown in the figure, the signal processing device 500 may include: a switch unit 30, an analog-to-digital conversion unit 40 coupled thereto, the output end of the analog-to-digital conversion unit 40 is coupled to the input end of the core processing unit 50, the output end of the core processing unit 50 is coupled to the input end of the digital-to-analog conversion unit 40', the output end of the digital-to-analog conversion unit 40' is coupled to the switch unit 30', and the main control unit 60 is coupled or electrically connected to all other units. The switch unit 30 and the switch unit 30' may include analog switches with high bandwidth and high linearity characteristics, which can process high-frequency signals and maintain signal integrity. In some embodiments, the analog switch includes cascaded transistors, and the linearity of the analog switch can be adjusted by adjusting the size of the cascaded transistors.

[0026] According to one embodiment, the signal processing device proposed in this solution can be implemented as a general-purpose device or a chip manufactured using integrated circuit technology. To improve linearity, each component in the chip can provide more exclusive characteristics, which has more advantages in signal processing speed and efficiency, and reduces the power consumption and area of ​​the signal processing module, which is more cost-effective.

[0027] According to one embodiment, the switch unit 30 is configured to receive a baseband analog signal from a baseband.

[0028] According to one embodiment, one output terminal of the switch unit 30 ′ is configured to provide a processed high-speed analog signal to the outside of the signal processing device 500 .

[0029] According to an embodiment, the switch unit 30 ′ may be coupled to the switch unit 30 to form a transceiver mode shared by the analog interface.

[0030] According to other embodiments, in some application scenarios, the signal processing device 500 may not include the switch unit 30 and the switch unit 30 ′.

[0031] According to one embodiment, the main control unit 60 can be electrically connected to all other units and configure the initialization parameters and startup processes of other units, communicate with external control units such as an MCU, exchange commands and data, and can also monitor the working status of the signal processing device 500 system, perform abnormal recovery processing and maintainable and monitorable functions.

[0032] According to an embodiment, the switch unit 30 and the switch unit 30' can be used as an intermediary for signal exchange between the internal and external parts of the signal processing device 500, and can support two working modes, mode A: switching channels according to the instructions of the main control unit 60; mode B: switching channels according to the instructions of the external pin. By adapting the control signal to switch the uplink and downlink circuits, the uplink and downlink signal selection in the time division duplex (TDD) scenario can be supported, and it can also be always set to the TX or RX interval, used as a dedicated processing channel for the corresponding channel.

[0033] According to one embodiment, the signal processing device 500 may include an uplink and downlink circuit / channel. When the signal processing device 500 is in a receiving mode (RX), the switch unit 30 and the switch unit 30' in the signal processing device are switched to an uplink mode to receive and transmit, for example, an analog signal from a radio frequency chip. When the signal processing device 500 is in a transmitting mode (TX), the switch units 30 and 30' in the signal processing device are switched to a downlink mode, and the downlink circuit / channel includes a switch unit 30, an analog-to-digital conversion unit 40, a core processing unit 50, a digital-to-analog conversion unit 40', and a switch unit 30'.

[0034] In one embodiment of the present application, the signal processing device 500 may include N downlink channels, and the N channels share, for example, one core processing unit, where N is greater than or equal to 1.

[0035] According to one embodiment, the analog-to-digital conversion unit 40 or the digital-to-analog conversion unit 40' can respectively adopt a high-precision and high-sampling rate ADC or DAC module, and can support conventional analog signal formats such as I_P / I_N / Q_P / Q_N; or I / Q single-ended; or single-channel. The analog-to-digital conversion unit 40 can convert the corresponding analog signal into a digital signal. The digital-to-analog conversion unit 40' is configured to convert the digital signal processed by the core processing unit 50 into an analog signal. The compatibility of the signal processing device 500 is increased by the analog-to-digital conversion unit 40 or the digital-to-analog conversion unit 40'.

[0036] According to one embodiment, in the analog-to-digital conversion unit 40, the analog bandwidth of the ADC needs to be greater than the bandwidth of the baseband analog signal received by the switch 30, and its sampling rate is greater than twice the bandwidth of the baseband analog signal. For high-speed communication systems, the sampling rate of the ADC generally needs to be above 160MHz. The accuracy of the ADC determines the upper limit of the signal-to-noise ratio SNR, which may vary depending on the system indicator requirements. In addition, the indicators of sampling rate and resolution need to be balanced with system requirements.

[0037] According to one embodiment, the digital-to-analog conversion unit 40' includes an out-of-band predistortion signal for canceling the out-of-band distortion of the radio frequency signal. At this time, the actual bandwidth of the output signal of the signal processing device is larger than the bandwidth of the baseband analog signal. In the conventional technology, the actual bandwidth of the output signal of the data processing module is three times or more than that of the baseband analog signal. The core processing unit 50 of the present application has the function of reducing the conventional predistortion bandwidth, so the output bandwidth of the DAC needs to be at least 1.2 times the bandwidth of the baseband analog signal. The sampling rate of the DAC needs to be at least twice the output bandwidth of the DAC, that is, 2.4 times the bandwidth of the baseband analog signal. The requirements for the DAC resolution in the digital-to-analog conversion unit 40' are similar to the requirements for the ADC resolution in the analog-to-digital conversion unit 40, and a balance needs to be made in the system. Too large a resolution will increase the system power consumption and area, and too small a resolution will affect the system signal-to-noise ratio index.

[0038] Pure analog signal processing has the disadvantages of being difficult to realize complex functions, difficult to program and adjust, low integration, and difficult to achieve high integration and miniaturization. This is also the reason why there are very few high-performance analog processing chips on the market. By digitally converting the baseband analog signal, the core processing unit 50 can complete complex calculations and other functions, achieving the purpose of high-performance analog chips.

[0039] According to one embodiment, the signal processing device 500 may also include an analog-to-digital conversion unit 40", which may also include a high-precision and high-sampling rate ADC, whose input end is configured to receive the output signal of the power amplifier, and whose output end is coupled to the input end of the core processing unit 50, thereby forming a feedback observation channel, which can collect observation point data of the target and observe external data in real time, so that the signal processing device 500 calculates the corresponding parameters. The feedback observation channel can greatly improve the tracking performance of the system, allowing the signal processing device 500 to handle external scenarios such as rapid temperature drop, temperature rise, impedance change, etc. According to one embodiment, the core processing unit 50 compares the output of the analog-to-digital conversion unit 40" with the output of the analog-to-digital conversion unit 40, and uses the difference obtained after the comparison to make real-time adjustments to the signal with nonlinear information to minimize the difference.

[0040] According to one embodiment, the requirements for the analog-to-digital conversion unit 40 ″ are similar to the requirements for the analog-to-digital conversion unit 40 described above.

[0041] According to an embodiment, the core processing unit 50 may have functions such as image correction (QEC), digital pre-distortion (PD), clipping processing (CFR), digital filtering (FIR), signal rate conversion (Resample) and DC offset correction.

[0042] According to one embodiment, the core processing unit 50 may include a peak clipping function module, a direct current compensation function module, an equalization function module, a frequency conversion orthogonal compensation function module and a digital pre-distortion function module.

[0043] According to one embodiment, the peak clipping function module is configured to perform clipping and peak suppression on the input signal, wherein the input signal may be a digital signal from the analog-to-digital conversion unit 40 .

[0044] Clipping and peak suppression (Crest Factor Reduction, CFR) technology is a method used to reduce signal peaks to improve power amplifier (PA) efficiency and reduce signal distortion. By monitoring the amplitude of the input signal, the peak part exceeding the set threshold is detected; the peak part exceeding the threshold is clipped to limit its amplitude to the set maximum value; filtering or other technologies are used to restore the signal quality and reduce the negative impact of clipping.

[0045] According to one embodiment, the CFR functional structure in the core processing unit 50 may perform the following operations: According to one embodiment, the clipped signal y(t) can be expressed as: (1) Where x(t) is the input signal, |x(t)| is the amplitude of the input signal, and A clip is the clipping threshold. When the amplitude of the input signal is less than or equal to the clipping threshold, the output signal is When the amplitude of the input signal is greater than the clipping threshold, the output signal is .

[0046] According to one embodiment, the DC compensation functional module includes a receiving DC compensation subunit, a transmitting DC compensation subunit and a feedback DC compensation subunit, which are respectively configured to compensate for the DC components in the input signal, the digital pre-distortion processing and the feedback observation channel. The presence of the DC signal affects the system EVM and the calibration stability of the digital pre-processing PD, increases power consumption and even causes the RF power amplifier to burn out.

[0047] According to one embodiment, the equalization function module includes an equalization filter configured to perform a spectrum equalization correction (EQ) function for compensating for the distortion and interference related to the frequency response introduced in the channel, thereby restoring the original signal. The equalization function module may include an input equalization subunit, a transmission equalization subunit, and a feedback equalization subunit, which are respectively configured to perform spectrum flatness correction operations on the input signal, the distortion and interference introduced after digital pre-distortion processing, and the feedback observation channel. The purpose of the equalization filter is to reverse the influence of the channel on the signal.

[0048] According to one embodiment, the frequency conversion quadrature compensation function module is configured to implement the image correction (QEC) function to compensate for the IQ image problem caused by the inconsistency of the IQ signal link. The frequency conversion quadrature compensation function module includes an input down-conversion quadrature compensation subunit, a transmission up-conversion quadrature compensation and a feedback down-conversion quadrature compensation. The IQ image existing within the zero intermediate frequency signal bandwidth will have a great impact on the EVM performance of the entire system, and it can be reduced to below the system EVM index through image correction.

[0049] According to one embodiment, the image correction QEC functional structure in the core processing unit 50 may be configured to perform the following operations: Assume the input signal is an intermediate frequency signal : (2) After passing through a non-ideal inverter, it will contain Ingredients: (3) Such image components may be hidden in the main signal or symmetrical with the LO frequency, affecting the spectrum or in-band signal quality of the air interface.

[0050] According to one embodiment, the frequency conversion orthogonal compensation function module can collect the frequency converted signal through the feedback observation channel to compensate for the Ingredients to enhance performance.

[0051] According to one embodiment, the digital pre-distortion function module in the core processing unit 50 is configured to implement a digital pre-distortion PD function.

[0052] According to one embodiment, the PD functional structure in the core processing unit 50 may perform the following operations: The nonlinearity of the power amplifier (PA) in the RF signal processing system outside the signal processing device will cause the input signal to be distorted after amplification, usually manifested as gain compression and phase distortion. Nonlinear distortion can be described by nonlinear models, such as polynomial models or Volterra series.

[0053] (4) in Indicates enhanced signal, is the input signal, k and l are the memory depth, and LUT is the lookup table.

[0054] Digital predistortion (PD) is a function implemented in the digital domain. Its function is to introduce distortion opposite to the nonlinear characteristics of the power amplifier. After the output signal of the signal processing device processed by PD passes through the power amplifier, it can just balance the distortion generated by the power amplifier, so that the signal output by the RF signal processing system can be restored to linearity.

[0055] Figure 5 The figure shows a comparison diagram of the RF signal before and after being processed by the signal processing device in the present application according to an embodiment of the present application, wherein the PA signal is a distorted signal after passing through the power amplifier, and the PD signal is a pre-distortion signal that can balance the distorted part of the power amplifier. After PD processing, the output of the system can basically reach the level of an ideal signal.

[0056] According to one embodiment of the present application, by comparing the input signal with the output signal of the power amplifier, the signal processing device reversely adjusts the received input signal until the output signal of the power amplifier is consistent with the input signal received by the signal processing device, thereby achieving digital predistortion.

[0057] According to one embodiment, the design method of digital pre-distortion is as follows: set up is the input signal, is the output signal of the power amplifier, is the digital domain signal sample bit, then the difference signal: (5) The coefficients used to generate the predistortion signal are calculated as ,in, is a multidimensional coefficient, and the specific dimension depends on the complexity of the modeling. Assume that the predistortion weighting coefficient vector of the digital predistortion PD is Through the feedback observation channel, the weighted coefficient can be given by data modeling and applied to the input signal , to achieve pre-distortion effect (6) in, is the predistortion coefficient, n = 0, 1, 2, ..., N is the index of the time domain signal, N is the total length of the array, M is the order of the predistortion coefficient, for The Hilbert transform of for The transposed matrix of for The conjugate of , y(n) is the output.

[0058] For example, for a one-dimensional coefficient , is the coefficient series at sample time n, with The size of the sample moment , is the total number of samples. At this time, the coefficient for: (7) in for and The cross-correlation of for The autocorrelation of is the iteration step length.

[0059] The output signal with predistortion information is: (8)

[0060] in Matrix model calculated for predistortion.

[0061] After adopting the solution of the present application, the key linearity indicator, the ACLR, can be reduced by up to 40dB, and the vector magnitude error (EVM) can be reduced by more than 10dB.

[0062] According to an embodiment, the FIR functional structure in the core processing unit 50 can provide LPF filtering with a transition band <10Mhz suppression degree> 40dbc, which is more than 10 times better than the traditional analog LPF.

[0063] In some embodiments, the output of the analog-to-digital conversion module 40 flows sequentially through the peak clipping subunit, the receiving DC compensation subunit, the input equalization subunit, and the input down-conversion orthogonal compensation subunit in the form of a data stream, and is compared and calculated in the digital predistortion subunit with the output signal of the power amplifier that has passed through the digital-to-analog conversion unit 40", the feedback DC compensation subunit, the feedback equalization subunit, and the feedback down-conversion orthogonal compensation subunit, and a signal with digital predistortion information is generated. The obtained signal with digital predistortion information is output to the digital-to-analog conversion unit 40' via the transmitting DC compensation subunit, the transmitting up-conversion orthogonal compensation subunit, and the transmitting equalization subunit.

[0064] Figure 6 FIG. 1 is a schematic flow chart of a signal processing method according to an embodiment of the present application. The method can be executed by a signal processing device.

[0065] The switch mode is set to enter the downlink mode, and the first analog signal is received. According to one embodiment, the switch mode includes an uplink or downlink mode. When the switch mode is set to the downlink mode, the first analog signal is received. When the switch mode is set to the uplink mode, an output signal such as an amplifier from outside the signal processing device is received and transmitted. The first analog signal may be a baseband analog signal from a baseband.

[0066] According to one embodiment, the received first analog signal is converted into a digital signal to obtain a first digital signal.

[0067] According to one embodiment, a digital predistortion operation is performed on the first digital signal to obtain a second digital signal having at least digital predistortion information.

[0068] According to one embodiment, the second digital signal is digital-to-analog converted into a second analog signal, and the second analog signal is output.

[0069] According to one embodiment, the signal processing method proposed in the present application may further include obtaining an output signal of the power amplifier and converting it into a third digital signal, and obtaining a second digital signal including digital predistortion information based on the first digital signal and the third digital signal.

[0070] The present application also includes an electronic device, comprising a signal processing device as described above.

[0071] The signal processing device proposed in the present application helps to improve the performance and linearity of the power amplifier. It improves the adaptability of the signal processing device by utilizing the analog-to-digital conversion and digital-to-analog conversion units before and after the core processing unit and the feedback analog-to-digital conversion unit. It expands the application scenarios of the signal processing device through high-speed and high-linearity analog switches, and has stronger practicality and compatibility.

[0072] The above embodiments are only used to illustrate the present invention, but not to limit the present invention. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the scope of the present invention. Therefore, all equivalent technical solutions should also fall within the scope of the present invention.

Claims

1. A signal processing device, comprising: A first switch unit, configured to receive a first analog signal; A first analog-to-digital conversion unit, coupled to the first switch unit, configured to convert the first analog signal into a first digital signal; a core processing unit, coupled to the first analog-to-digital conversion unit, configured to process the first digital signal and output a second digital signal including at least digital predistortion information; A first digital-to-analog conversion module, coupled to the core processing unit, configured to convert the second digital signal into a second analog signal; The second switch unit is coupled to the first digital-to-analog conversion unit and is configured to output the second analog signal.

2. The device according to claim 1 further comprises a second analog-to-digital conversion unit configured to receive an output signal of a power amplifier outside the signal processing device, convert the output signal of the power amplifier into a third digital signal and provide it to the core processing unit.

3. The device according to claim 2, wherein: The second switch unit is also coupled to the first switch unit to form an uplink channel. 4 . The device according to claim 2 , wherein the core processing unit is configured to obtain a second digital signal with digital predistortion information based on the first digital signal and the third digital signal.

5. The device according to claim 4 further comprises a main control unit, which is coupled to all other units and configures initialization parameters of other units.

6. The device according to claim 5, wherein: The core processing unit includes: A peak clipping function module, configured to perform clipping and peak suppression on the first digital signal; A digital pre-distortion function module, configured to implement a pre-distortion function; The DC compensation function module includes a receiving DC compensation subunit, a transmitting DC compensation subunit and a feedback DC compensation subunit, which are respectively configured to compensate for the DC components of the first digital signal, the digital predistortion processing and the feedback observation channel; The equalization function module includes an input equalization subunit, a transmission equalization subunit, and a feedback equalization subunit, configured to compensate for distortion and interference introduced in the channel; The frequency conversion orthogonal compensation functional module includes an input down-conversion orthogonal compensation subunit, a transmission up-conversion orthogonal compensation and a feedback down-conversion orthogonal compensation, and is configured to realize an image correction function.

7. An electronic device comprising the device as claimed in any one of claims 1 to 6.

8. A signal processing method performed by a signal processing device, comprising: Setting the switch mode to enter a downlink mode and receiving a first analog signal; Performing analog-to-digital conversion on the first analog signal to obtain a first digital signal; Performing a digital predistortion operation on the first digital signal to obtain a second digital signal including at least digital predistortion information; The second digital signal is converted into a second analog signal and outputted. 9 . The method according to claim 8 , further comprising acquiring an output signal of the power amplifier and converting the output signal into a third digital signal. 10 . The method according to claim 9 , further comprising obtaining a second digital signal including digital predistortion information based on the first digital signal and the third digital signal.

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