Circuit and operating method thereof

Abstract

A circuit includes a signal source configured to provide a test signal to at least one of a plurality of conductive structures based on a decoded signal, a plurality of switches configured to connect the signal source to the plurality of conductive structures according to the decoded signal, respectively, a multiplexer, and an analog-to-digital converter (ADC), the multiplexer is configured to select a test voltage present on the at least one conductive structure as a function of the decoded signal, and the analog-to-digital converter is configured to provide a digital output by comparing the test voltage with a reference voltage. The embodiment of the invention also provides an operation method of the circuit.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to the field of semiconductors, and more particularly, to circuits and methods of operating the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the increasing integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.). In most cases, the increase in integration density comes from the continuous reduction of the minimum feature size (e.g., shrinking the semiconductor process node to sub-nanometer nodes), which allows more components to be integrated into a given area. As the demand for miniaturization, higher speed, greater bandwidth, and lower power consumption and latency has grown recently, the demand for advanced packaging technologies for semiconductor dies has also grown. Summary of the invention

[0003] One embodiment of the present invention provides a circuit, comprising: a signal source, configured to provide a test signal to at least one conductive structure among a plurality of conductive structures based on a decoded signal; a plurality of switches, configured to connect the signal source to the plurality of conductive structures, respectively, based on the decoded signal; a multiplexer, configured to select a test voltage present on the at least one conductive structure based on the decoded signal; and an analog-to-digital converter (ADC), configured to provide a digital output based on comparing the test voltage with a reference voltage.

[0004] Another embodiment of the present invention provides a circuit, comprising: a first die; a second die; at least one conductive structure between the first die and the second die or within at least one of the first die and the second die; a signal source within one of the first die and the second die; at least one switch configured to connect the signal source to the at least one conductive structure via a first conductor; and an analog-to-digital converter (ADC) within one of the first die and the second die, the analog-to-digital converter being connected to the at least one conductive structure via a second conductor at a first end of the at least one conductive structure and a third conductor at a second end of the at least one conductive structure.

[0005] Yet another embodiment of the present invention provides a method for operating a circuit, comprising: providing a test signal to at least one of a plurality of conductive structures by a signal source based on a decoded signal; connecting the signal source to the plurality of conductive structures respectively through a plurality of switches based on the decoded signal; selecting a test voltage present on the at least one conductive structure through a multiplexer based on the decoded signal; and providing a digital signal based on comparing the test voltage with a reference voltage through an analog-to-digital converter (ADC). BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A block diagram of an example circuit for testing conductive structures is shown in accordance with various embodiments.

[0008] Figure 2 A schematic diagram of an example circuit for testing conductive structures according to various embodiments is shown.

[0009] Figure 3 A schematic diagram of a portion of an example circuit for testing conductive structures according to various embodiments is shown.

[0010] Figure 4 Schematic diagram showing an example circuit for testing a conductive structure according to various embodiments

[0011] Figure 5 A schematic diagram of an example circuit for testing conductive structures according to various embodiments is shown.

[0012] Fig. 6A and Figure 6B Embodiments of example circuits for testing conductive structures according to various embodiments are shown.

[0013] Figure 6C and Fig.6D It shows various embodiments Fig. 6A and Figure 6B An example configuration of the first die and the second die is shown in FIG.

[0014] Figure 7 A flow chart illustrating an example method of operating a circuit for testing conductive structures in accordance with various embodiments is shown. DETAILED DESCRIPTION

[0015] The present invention provides many different embodiments or examples for realizing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0017] Modern semiconductor devices may be formed as integrated circuits (e.g., semiconductor dies, semiconductor chips, integrated circuit (IC) chips, etc.) that are operatively and physically coupled to one another. In a semiconductor device, different IC dies / chips (e.g., having logic functions) may be coupled to one another via one or more interconnect structures (e.g., not having logic functions), such as a die-to-die structure, while having one or more semiconductor structures therein (e.g., through silicon vias (TSVs), super power rails (SPRs), etc.). Over time, one or more interconnect structures and / or one or more semiconductor structures within a device may degrade, resulting in an undesirable change (e.g., increase) in the resistance through these structures. In existing devices that include hundreds or even thousands of such structures, it is difficult to detect and locate the degraded structures. For example, the RC characteristics of a single structure may Very small, making it difficult to detect outliers. By placing all the structures in series in a device and plotting the measured resistance, statistical models can often be used to detect degraded structures. But such tests may not be precise enough to detect such small changes in resistance and require a lot of manual work. Alternatively, degraded structures can be detected by measuring the delay caused by each structure in the device; however, in small-scale modern devices, even if the resistance of the degraded structure becomes 10,000 times larger, the delay difference may only be around 10 picoseconds, which may be difficult to detect. Therefore, there is a need for techniques for testing / monitoring the quality of integrated circuits (e.g., the above-mentioned interconnect structures and / or semiconductor structures).

[0018] To overcome these problems, embodiments described herein may provide techniques for testing / monitoring interconnect structures (e.g., die-to-die structures for testing / monitoring die-to-die connection quality, inter-die structure resistance distribution, etc.) and / or semiconductor structures (e.g., TSV, SPR, etc.) with improved resistance resolution. In addition, embodiments described herein may provide in-situ testing / monitoring techniques that allow yield analysis and / or yield improvement (e.g., yield of interconnect structures and / or semiconductor structures) to be performed while defects are being detected.

[0019] As described herein, a circuit may test a conductive structure, which may be or include an interconnect structure and / or a semiconductor structure within an IC as described above. The circuit may include a signal source to provide a test signal to at least one of a plurality of conductive structures based on a decoded signal. In some embodiments, the signal source may provide a test signal to a plurality of conductive structures through a plurality of switches. For example, a plurality of switches may connect the signal source to a plurality of conductive structures, respectively, based on a decoded signal. The circuit may include a multiplexer for selecting a test voltage on at least one conductive structure present in a plurality of conductive structures based on a decoded signal. In some embodiments, the multiplexer may receive a test voltage of at least one of a plurality of conductive structures to test the conductive structure. The circuit may include an analog-to-digital converter (ADC) to provide a digital output based on comparing the test voltage to a reference voltage. In some embodiments, the ADC may receive a test voltage or a signal associated therewith, and output an output signal representing the resistance of the selected conductive structure. In some embodiments, the ADC may be or include a one-bit sigma-delta ADC to obtain a higher resolution, thereby reducing the required current and wiring area.

[0020] This allows the circuit to measure the voltage difference via the ADC (e.g., rather than sensing the delay difference as described above). Thus, the circuit can test / monitor the interconnect structure and / or semiconductor structure with improved resistance resolution and allow yield analysis and / or yield improvement of the IC, such as by in-situ operation (e.g., testing / monitoring while operating the IC or conductive structure). In addition, this can further assist yield learning / improvement and maintenance (e.g., signal line (lane) repair, etc.).

[0021] Figure 1 A block diagram of an example circuit 100 for testing a conductive structure according to various embodiments is shown. The circuit 100 may include a signal source 110, a multiplexer 120, a switch 130, an analog-to-digital converter (ADC) 140, and a controller 150.

[0022] Circuit 100 can be used to test / monitor the conductive structure of an integrated circuit (IC). In some embodiments, the conductive structure may be or include a connector structure within a plurality of bonded dies. In some embodiments, the conductive structure may be or include a connector structure between two bonded dies. For example, circuit 100 can test or monitor any number and / or combination of interconnect structures and / or semiconductor structures in one or more ICs. In some embodiments, such an IC may include a substrate and a conductive structure (e.g., a semiconductor structure, an interconnect structure, etc. as described above). For example, the IC and / or the dies therein may include a through hole, such as a TSV or SPR as described above, which is configured to transmit a signal between a component below the substrate and a component above the substrate. The IC and / or the dies therein may include an interconnect and / or a metallization structure configured to connect the through hole to a component on or in the substrate, or to establish a connection between the dies. In some embodiments, the conductive structure may be or include at least one of a through silicon via (TSV), a super power rail (SPR), a uBump, a hybrid bonding member, or any interconnect structure between the dies. Circuit 100 can test / monitor test voltages associated with semiconductor structures (e.g., vias) and interconnect structures (e.g., die-to-die structures). In some embodiments, circuit 100 can test / monitor connectivity between dies of a three-dimensional integrated circuit (3DIC). In some embodiments, circuit 100 can detect the yield of such a 3DIC. In some embodiments, circuit 100 can be used to test / monitor a device under test (DUT) (e.g., IC, die, conductive structure, etc.) during operation of the DUT. For example, circuit 100 can be or include an in-situ circuit configured to test / monitor conductive structures within a DUT during operation of the conductive structures and / or the DUT.

[0023] In some embodiments, the circuit 100 may include a signal source 110. The signal source 110 may provide a test signal to at least one of the plurality of conductive structures based on the decoded signal. In some embodiments, the signal source 110 may provide a test signal to the plurality of conductive structures through at least one of the switches 130. For example, the switch 130 may connect the signal source 110 to the plurality of conductive structures, respectively, based on the decoded signal. In some embodiments, the circuit 100 may include a multiplexer 120. In some embodiments, the multiplexer 120 may select a test voltage present on at least one of the plurality of conductive structures based on the decoded signal. In some embodiments, the multiplexer 120 may receive a test voltage of at least one of the plurality of conductive structures to test the conductive structure. In some embodiments, the circuit 100 may include an ADC 140. In some embodiments, the ADC 140 may provide a digital output based on comparing the test voltage to a reference voltage. In some embodiments, the ADC 140 may receive a test voltage or a signal associated therewith, and output an output signal representing the resistance of a selected conductive structure (e.g., a conductive structure corresponding to the selected test voltage). In some embodiments, ADC 140 may be or include a one-bit sigma-delta ADC to achieve higher resolution, thereby reducing required current and wiring area.

[0024] The signal source 110 may be configured to provide a test signal to at least one conductive structure. In some embodiments, the signal source 110 may be or include a circuit, a circuit system, or any component that generates a current. In some embodiments, the signal source 110 may be or include a current source configured to provide a current supply (e.g., as a test signal). The signal source 110 may be electrically coupled to the at least one conductive structure via at least one switch 130. In some embodiments, the signal source 110 may provide a test signal to the at least one conductive structure via at least one switch 130.

[0025] The switch 130 may be configured to connect the signal source 110 to at least one conductive structure. In some embodiments, the switch 130 may be configured to connect the signal source 110 to a plurality of conductive structures, respectively, based on the decoded signal. In some embodiments, the switch 130 may be or include any semiconductor device (e.g., BJT, MOSFET, etc.), any semiconductor diode, any semiconductor switch, or any component that may control the current of a switch path (e.g., connecting the signal source 110 and the conductive structure).

[0026] Multiplexer 120 may be configured to be connected to at least one of the conductive structures. In some embodiments, multiplexer 120 may be configured to select a test voltage present on one of the conductive structures based on the decoded signal. For example, multiplexer 120 may receive a test voltage for a selected one of the conductive structures at a time. In some embodiments, multiplexer 120 may be or include an analog multiplexer configured to send an analog signal.

[0027] ADC 140 may be configured to provide a digital output. In some embodiments, ADC 140 may provide a digital output based on comparing a test voltage with a reference voltage. In some embodiments, the digital output may be an output signal representing the resistance of a selected conductive structure (e.g., a conductive structure corresponding to a selected test voltage). In some embodiments, ADC 140 may be or include a system, device, or any circuit component that converts an analog signal into a digital signal. In some embodiments, ADC 140 may be or include a system, device, or any circuit component that outputs a signal representing the resistance of a selected one of a plurality of conductive structures based on a test voltage. In some embodiments, ADC 140 may be or include a ∑-Δ ADC. In some embodiments, ADC 140 may be or include a single ∑-Δ ADC. In some embodiments, ADC 140 may be configured to output a digital output during operation of the conductive structure (e.g., during operation of a bonded die). In some embodiments, ADC 140 may be configured to output a digital output sequence corresponding to a plurality of conductive structures. For example, each signal or bit of the sequence may correspond to each of a plurality of conductive structures. In some embodiments, ADC 140 may be configured to be connected to the conductive structure via multiplexer 120. ADC 140 may receive a signal (eg, a test voltage) from multiplexer 120 and may output a digital signal representing the resistance of a selected conductive structure based on the test voltage.

[0028] Controller 150 may be configured to control at least one of signal source 110, multiplexer 120, switch 130, and ADC 140. Controller 150 may be or include a circuit, circuitry, or any component that may control at least one of signal source 110, multiplexer 120, switch 130, and ADC 140.

[0029] Figure 2A schematic diagram of an example circuit 200 for testing a conductive structure according to various embodiments is shown. The circuit 200 includes a signal source 210, a multiplexer 220, a switch 230 (e.g., a switch 230A connected to a first conductive structure 290A, a switch 230B connected to a second conductive structure 290B, and a switch 230N connected to an nth conductive structure 290N), and an ADC 240. The circuit 200 may be substantially similar to the circuit 100 or include components of the circuit 100. In some embodiments, the signal source 210, the multiplexer 220, the switch 230, and the ADC 240 may be substantially similar to the signal source 110, the multiplexer 120, the switch 130, and the ADC 140, respectively, or include components thereof. In some embodiments, the circuit 200 may include a decoder 225 configured to provide a decoded signal.

[0030] In some embodiments, the circuit 200 can test at least one of the conductive structures 290 (e.g., the first conductive structure 290A, the second conductive structure 290B, and the Nth conductive structure 290N). In some embodiments, the conductive structure 290 can be or include at least one of a through silicon via (TSV), a super power rail (SPR), a uBump, a hybrid bonding piece, or an interconnect structure between dies. In some embodiments, the conductive structure 290 can be or include a connection structure within a plurality of bonded dies. In some embodiments, the conductive structure 290 can be or include a connector between two bonded dies. The circuit 200 can be a non-limiting example of the circuit 100.

[0031] Circuit 200 can be used to test / monitor at least one of conductive structures 290. In some embodiments, conductive structure 290 can be an integrated circuit (IC). In some embodiments, conductive structure 290 can be or include a connection structure within a plurality of bonded dies. In some embodiments, conductive structure 290 can be or include a connection structure between two bonded dies. For example, circuit 200 can test or monitor any number and / or combination of interconnect structures and / or semiconductor structures in one or more ICs. In some embodiments, such an IC can include a substrate and a conductive structure (e.g., a semiconductor structure, an interconnect structure, etc. as described above). For example, the IC and / or the dies therein can include a through hole, such as a TSV or SPR as described above, which is configured to transmit a signal between a component below the substrate and a component above the substrate. The IC and / or the dies therein can include an interconnect and / or a metallization structure configured to connect the through hole to a component on or in the substrate, or configured to establish a connection between dies. In some embodiments, conductive structure 290 can be or include at least one of a through silicon via (TSV), a super power rail (SPR), a uBump, a hybrid bonding piece, or any interconnect structure between dies. The circuit 200 can test / monitor test voltages associated with semiconductor structures (e.g., vias) and interconnect structures (e.g., die-to-die structures). In some embodiments, the circuit 200 can test / monitor connectivity between dies of a three-dimensional integrated circuit (3DIC). In some embodiments, the circuit 200 can detect the yield of such a 3DIC. In some embodiments, the circuit 200 can be used to test / monitor a device under test (DUT) (e.g., IC, die, conductive structure, etc.) during operation of the DUT. For example, the circuit 200 can be or include an in-situ circuit configured to test / monitor at least one conductive structure 290 within the DUT during operation of the conductive structure 290 and / or the DUT.

[0032] In some embodiments, the circuit 200 may include a signal source 210. The signal source 210 may provide a test signal to at least one conductive structure 290 based on a decoded signal from the decoder 225. In some embodiments, the signal source 210 may provide a test signal to a corresponding one of the conductive structures 290 through at least one of the switches 230. For example, the switch 230 may connect the signal source 210 to the conductive structures 290, respectively, based on the decoded signal from the decoder 225. In some embodiments, the circuit 200 may include a multiplexer 220. In some embodiments, the multiplexer 220 may receive a test voltage of at least one conductive structure 290 to test the conductive structure. In some embodiments, the circuit 200 may include an ADC 240. In some embodiments, the ADC 240 may provide a digital output based on comparing the test voltage to a reference voltage. In some embodiments, the ADC 240 may receive a test voltage or a signal associated therewith, and output an output signal representing the resistance of a selected conductive structure (e.g., a conductive structure corresponding to the selected test voltage). In some embodiments, the ADC 240 may be or include a one-bit sigma-delta ADC to obtain higher resolution, thereby reducing the required current and wiring area. For example, ADC 240 may be or include a one-bit sigma-delta ADC configured to operate at a single quantization level (eg, to create a 1-bit digital data stream).

[0033] In some embodiments, the circuit 200 may include a first conductive line 231 (e.g., a first conductive line 231A connected to a first conductive structure 290A, a first conductive line 231B connected to a second conductive structure 290B, a first conductive line 231N connected to a first conductive structure 290N, etc.). In some embodiments, the circuit 200 may include a second conductive line 232 (e.g., a second conductive line 232A connected to a first conductive structure 290A, a second conductive line 232B connected to a second conductive structure 290B, a second conductive line 232N connected to an nth conductive structure 290N, etc.).

[0034] In some embodiments, the signal source 210 may be configured to provide a test signal I_In to the conductive structure 290. <p:1>. For example, when switch 230A is closed, signal source 210 can provide a test signal I_in to first conductive structure 290A through switch 230A. As shown, current can pass through first conductive structure 290A from a first end (e.g., an upper portion) to a second end (e.g., a lower portion) connected to ground 295. Similarly, switch 230B can be configured to connect signal source 210 to a first end of conductive structure 290B, a second end of conductive structure 290B, and ground. In a similar manner, current source 210 can be selectively provided to conductive structure 290 via switch 230 to sink to a ground terminal through a selected one of conductive structures 290.

[0035] In some embodiments, the multiplexer 220 may be connected to at least one conductive structure 290 through a corresponding first conductive line 231 to receive a test voltage of the conductive structure 290. For example, the multiplexer 220 may be connected to the first conductive structure 290A through a first conductive line 231A to receive a test voltage of the first conductive structure 290, the multiplexer 220 may be connected to the second conductive structure 290B through a first conductive line 231B to receive a test voltage of the second conductive structure 290B, and the multiplexer 230 may be connected to the nth conductive structure 290N through a first conductive line 231N to receive a test voltage of the Nth conductive structure 290N. In some embodiments, the multiplexer 220 may be configured to select a test voltage present on at least one of the conductive structures 290 based on a decoded signal. For example, the multiplexer 220 may select a test voltage present on the first conductive structure 290A based on a decoded signal from a decoder, the decoded signal indicating the first conductive structure 290. In some embodiments, the first conductive line 231 may be or include a second switch. In some embodiments, second conductor 232 may be or include a third switch. Multiplexer 220 may provide a test voltage received from at least one of conductive structures 290 to ADC 240. In some embodiments, multiplexer 220 may be connected to an input Vin of ADC 240 to provide the test voltage of conductive structure 290 to ADC 240.

[0036] In some embodiments, the ADC 240 may be connected to the conductive structure 290 through the multiplexer 220 to receive a test voltage for the conductive structure 290. In some embodiments, the ADC 240 may be connected to the conductive structure 290 through a second conductor 232. As shown, the second conductor 232 may be connected to a second end of the conductive structure 290, and the first conductor 231 may be connected to a first end of the conductive structure 290. In some embodiments, the first conductor 231 may be connected to the ADC 240 at a first input Vin of the ADC 240. In some instances, the second conductors 232 may all be shorted together and / or may be connected to a reference point Vref of the ADC 240 to provide a reference point for the test voltage received from the multiplexer 220. In some embodiments, the ADC 240 may be configured to provide a digital output Dout 270 representing the resistance of at least one of the conductive structures 290 based on the test voltage received from the multiplexer 220.

[0037] In some embodiments, Figure 2 As shown, when the first switch 230A is closed, a closed circuit including the first conductive structure 290A is formed, so that the current I_In passes through the conductive structure 290A. The first conductive line 231 and the second conductive line 232 can create a sensing path connected to the input Vin and to the reference point Vref through the multiplexer 220, and the sensing path can measure the voltage difference across the first conductive structure 290A. The ADC 240 can convert the analog signal corresponding to the voltage difference into a digital signal, that is, the digital output Dout 270.

[0038] In some embodiments, the digital output Dout 270 may be a binary signal that outputs "1" (high) or "0" (low) based on the measured voltage difference. The ADC 240 may be configured to switch from low to high, or from high to low, at a specific input threshold voltage. The threshold voltage may be set so that it corresponds to a resistance through one of the conductive structures 290, which indicates a degraded structure. Thus, the circuit 200 may measure whether one of the conductive structures 290 is degraded based on whether the ADC 240 outputs a high signal or a low signal. In some embodiments, a controller (e.g., the controller 150) may turn the switch 230 on and off in a specific order, thereby connecting different conductive structures 290 to the ADC 240 one at a time. In some embodiments, the ADC 240 may be configured to output a sequence of digital outputs (e.g., Dout 270) corresponding to the conductive structures 290. For example, the digital output Dout 270 of the ADC 240 may represent a voltage measurement value of each conductive structure 290 in the sequence. By monitoring the digital output Dout 270 of the ADC 240, the presence and / or location of the degraded structure may be determined.

[0039] In some embodiments, the circuit 200 may include a controller (e.g., Figure 1 The controller 150 in FIG. 10 can control a decoder 225 configured to receive a plurality of bits to control a switch 230. For example, the controller can provide a signal B to the decoder 225. <m:1>, the signal includes a bit that turns on one of the switches 230, thereby controlling the switch 230. The decoder 225 may provide a decoded signal (e.g., an n-bit signal) to select and turn on one of the switches 230. For example, the decoder 225 may provide a decoded signal one-hot encoding <00010...0> to select one of the switches 230 corresponding to bit "1" and turn it on, thereby allowing current to be supplied from the signal source 210 to the corresponding conductive structure 290.

[0040] In some embodiments, the ADC 240 may be connected to a clock generator to receive a clock signal CLK 260. In some embodiments, the ADC 240 may be configured to output a digital output Dout 270 based on the clock signal CLK 260. The clock signal CLK 260 may be synchronized with the decoder 225 so that the ADC 240 may provide a digital output Dout 270 corresponding to one of the switches 230 and the conductive structures 290 corresponding to a bit "1" in the decoded signal. For example, the decoder 225 may provide a decoded signal to select one of the switches 230 and the conductive structures 290, and the multiplexer 220 may receive a test voltage of the selected conductive structure 290 and provide the test voltage to the ADC 240. The ADC 240 synchronized with the clock signal CLK 260 may output a digital output Dout 270 indicating a resistance of the selected one of the conductive structures 290 based on the test voltage.

[0041] Figure 3 A schematic diagram of a portion of an example circuit 300 for testing a conductive structure according to various embodiments is shown. The circuit 300 includes a reference Figure 2 The signal source 210 and ADC 240 discussed above may also include a gain component 310. In some embodiments, the gain component 310 may be or include an amplifier. In some embodiments, the gain component 310 may be configured to connect at least one conductive structure 290 to the ADC 240. In some embodiments, the gain component 310 may receive a test voltage from the conductive structure 290 and provide an amplified test voltage to the ADC 240.

[0042] In some embodiments, ADC 240 may be a 10-bit ADC with a resolution of the least significant bit (VLSB) of approximately 1 mV. LSB can be determined as VLSB / I_In. For example, when the nominal resistance Rnom of the uBump is 0.01 ohms, 100 mA is required to generate a voltage difference of 1 mV. However, passing 100 mA through a switching device is challenging. When the Rnom of the TSV is 0.1 ohms, only 10 mA is required to generate a voltage difference of 1 mV. Since increasing the ADC resolution can be expensive, introducing a gain component 310 can improve the detection resolution at a smaller input current. For example, using the gain component 310, the minimum detectable resistance R LSB It can be determined as VLSB / I_in / Gain. In some embodiments, the gain of gain component 310 can range from 5 to 20.

[0043] Figure 4 Schematic diagram of an example circuit 400 for testing a conductive structure according to various embodiments is shown. Circuit 400 may be substantially similar to circuit 100 and / or circuit 200 or may incorporate components thereof. In some embodiments, as shown in FIG. Figure 4 As shown, the circuit 400 may be the circuit 200, and further includes Figure 3 The circuit 400 is a non-limiting example of the circuit 200 including the gain component 310.

[0044] like Figure 4 As shown, the gain component 310 can connect the conductive structure 290 and the ADC 240. In some embodiments, as shown, the gain component 310 can be configured to receive a test voltage of at least one of the conductive structures 290 by sensing the test voltage between the first end 405A and the second end 405B. At the first end 405A, the gain component 310 is connected to the first end of the conductive structure 290 through the multiplexer 220. At the second end 405B, the gain component 310 is connected to the second end of the conductive structure 290. The gain component 310 can thereby sense the test voltage of the corresponding one of the conductive structures 290 and provide the test voltage to the ADC 240 through the input Vin. In some embodiments, the second end of the conductive structure 290 can be grounded. As described above, the gain component 310 can improve the detection resolution of the circuit 400 at a smaller input current.

[0045] Figure 5 Schematic diagram of an example circuit 500 for testing conductive structures according to various embodiments is shown. Circuit 500 may be substantially similar to circuit 100, circuit 200, and / or circuit 400 or incorporate components thereof. Figure 5 As shown, circuit 500 may include signal source 510, switch 530, ADC 540, and gain component 545, which may be substantially similar to or incorporate components of signal source 110, switch 130, ADC 140, and gain component 310, respectively. Circuit 500, switch 531, switch 532, and switch 533 may operate to test conductive structure 590.

[0046] In some embodiments, the circuit 500 may be connected to or incorporated in at least one of the first die 501 and the second die 502. Figure 5 As shown, circuit 500 can be incorporated into first die 501. In some embodiments, second die 502 can be connected to first die 501 through at least one conductive structure 590. For example, first die 501 and second die 502 can be connected through conductive structure 590 therebetween. In some embodiments, conductive structure 590 can be in at least one of first die 501 or second die 502.

[0047] In some embodiments, at least one of the first die 501 and the second die 502 may include a signal source 510. For example, Figure 5 As shown, the signal source 510 can be incorporated into the first die 501. In some embodiments, the signal source 510 can be connected to a switch 530, which is configured to connect the signal source 510 to the conductive structure 590. In some embodiments, the signal source 510 can be connected to the switch 530, which is configured to connect the signal source 510 to the conductive structure 590 through the first wiring 530W.

[0048] In some embodiments, at least one of the first die 501 and the second die 502 may include an ADC 540. For example, Figure 5 As shown, ADC 540 can be incorporated into the first die 501. In some embodiments, ADC 540 can be connected to the conductive structure 590 through the second wiring 531W at the first end 591A of the conductive structure 590. In some embodiments, ADC 540 can be connected to the conductive structure 590 through the third wiring 532W at the second end 591B of the conductive structure 590. In some embodiments, at least one of the first die 501 and the second die 502 can include a resistor 534 or be connected through a resistor 534. In some embodiments, resistor 534 can be configured to connect ADC 540 to the second end 591B of the conductive structure 590. In some embodiments, resistor 534 can form a signal path from the second die 502 to the first die 501, thereby forming a reference voltage point. Resistor 543 can have any value.

[0049] In some embodiments, the circuit 500 can be an in-situ test circuit such that the ADC 540 can be configured to output a digital output (e.g., Dout 270) during operation of the conductive structure 590 (and / or the first die 501 and the second die 502). In some embodiments, at least one of the first die 501 and the second die 502 can include a first terminal 560 to provide an input signal to the conductive structure 590. In some embodiments, at least one of the first die 501 and the second die 502 can include a second terminal 561 to receive an output of the conductive structure 590. In some embodiments, the circuit 500 can be configured to sense a test voltage of the conductive structure 590 while operating the conductive structure 590, for example, by receiving an input (e.g., Tx) through the first terminal 560 and providing an output (e.g., Rx) through the second terminal 561. To test the quality of the conductive structure 590 (e.g., to sense a test voltage, thereby measuring the resistance of the conductive structure 590), the switches 530, 531, 532, 533 can be turned on with the Tx 560 in a high Z state. In some embodiments, ADC 540 may be or include a one-bit sigma-delta ADC. For example, ADC 540 may be or include a one-bit sigma-delta ADC configured to operate at a single quantization level (e.g., creating a 1-bit digital data stream). In some embodiments, resistor Rcom 570 may be added to shift the common-mode voltage on conductive structure 590. For example, when the gain stage is a differential amplifier, and / or the input will be at an intermediate voltage rail (e.g., Vdd / 2, or a voltage between Vss and Vdd), resistor Rcom 570 may be added to offset the common-mode voltage. The common-mode voltage may be R_com×I_in=V, where V may be a voltage close to the common-mode voltage of the gain stage (or a reference voltage to connect the second end of conductive structure 290 to a voltage source).

[0050] In some embodiments, the gain component 545 can amplify the test voltage (e.g., the voltage difference measured by the second wiring 531W and the third wiring 532W) and provide the amplified signal to the ADC 540. The ADC 540 can receive the test voltage from the gain component 545 and output a signal representing the resistance of the conductive structure 590 based on the test voltage.

[0051] Fig. 6A and Figure 6B An embodiment of an example circuit 600 for testing conductive structures according to various embodiments is shown. Fig. 6A A side view of a circuit 600 showing a conductive structure 690 for interconnecting a first die 610 and a second die 620, Figure 6B A top view of circuit 600 is shown. Circuit 600 may be substantially similar to circuit 100, circuit 200, and / or circuit 400 or incorporate components thereof. Although circuit 600 is shown as testing conductive structures 690 interconnecting first die 610 and second die 620, circuit 600 may be used to test semiconductor structures within first die 6.1 and / or second die 620. For example, first die 610 may include TSVs that may be tested using circuit 600.

[0052] As shown, circuit 600 may be connected to conductive structure 690 via conductors 630 and 631. Conductor 630 may include a switch (eg, switch 230) that may allow the corresponding conductive structure to receive a test signal from a signal source (eg, signal source 210). Figure 6B The wire 631 shown in FIG. 6A may be connected to an ADC (eg, ADC 240 ) to sense the test voltage of the conductive structure 690 and provide it to the ADC.

[0053] For example, Fig. 6A As shown, the interconnect structure (e.g., conductive structure 690N) between the first die 610 and the second die 620 can be disconnected. The quality of this connection between the first die 610 and the second die 620 can be detected, monitored and / or tested using circuit 600. As described above, a signal source can provide a test signal to the conductive structure 290. When the switch connected to the conductive structure 690N is closed (e.g., turned on), the signal source can be connected to the conductive structure 690N. The circuit 600 can then use the wire 631 to sense the test voltage between the first die 610 and the second die 620 across the conductive structure 690N. In some embodiments, a multiplexer (e.g., multiplexer 120) can be used to select one of the conductive structures 690 at a time. The circuit 600 outputs a signal representing the resistance of the selected conductive structure (e.g., conductive structure 690N). In some embodiments, as Fig. 6A As shown, when the conductive structure 690N is “disconnected”, the output signal of the circuit 600 may indicate the connection quality (eg, “disconnected”) of the conductive structure 690N.

[0054] In some embodiments, the first die 610 and / or the second die 620 may be or include a silicon on chip (SoC) die, an interposer die, etc. In some embodiments, the first die 610 and / or the second die 620 may be interconnected by various interconnect structures (e.g., uBump, TSV, hybrid bonding, etc.). In some embodiments, the first die 610 and / or the second die 620 may include a metal wiring layer, which may include wires 630, 631.

[0055] Figure 6C and Fig.6D It shows the various embodiments Fig. 6A and Figure 6B The circuit 600 can be used to test / monitor the interconnect quality of any die-to-die configuration in a 3DIC setup. In some embodiments, as shown in FIG. Figure 6C As shown, the first die 610 and the second die 620 may be arranged face to face, such that the front surface of the first die 6.1 faces the rear surface of the second die 620. Figure 6C As shown, the first die 610 and the second die 620 may be arranged face to face, such that the front surface of the first die 6 . 1 faces the front surface of the second die 620 . Figure 6C and Fig.6D Shown are non-limiting examples only, and any configuration of interconnects between dies (eg, 3DIC) may be tested / monitored using the circuits disclosed herein.

[0056] Figure 7 A flow chart of an example method 700 for operating a circuit (e.g., circuit 100, 200, 400, 500) to test a conductive structure according to various embodiments is shown. The method 700 may be performed by, with, or using a circuit (e.g., circuit 100, 200, 400, 500). It should be noted that the method 700 is merely an example and is not intended to limit the present disclosure. Therefore, it is understood that in Figure 7 Additional operations may be provided before, during, and after method 700, and some other operations may only be briefly described herein.

[0057] In short, the method 700 may start at operation 710, where a signal source (e.g., signal source 210) provides a test signal to at least one of a plurality of conductive structures (e.g., conductive structure 290) based on a decoded signal. The method 700 may continue to operation 720, where a plurality of switches (e.g., switch 230) respectively connect the signal source to the plurality of conductive structures based on the decoded signal. The method 700 may continue to operation 730, where a multiplexer (e.g., multiplexer 220) selects a test voltage present on at least one conductive structure based on the decoded signal. The method 700 may continue to operation 740, where a digital signal (e.g., Dout 270) is provided by an analog-to-digital converter (ADC) (e.g., ADC 240) based on comparing the test voltage with a reference voltage.

[0058] At operation 710, a signal source (e.g., signal source 210) may provide a test signal to at least one of a plurality of conductive structures (e.g., conductive structure 290) based on the decoded signal. In some embodiments, the signal source may provide the test signal to a corresponding one of the plurality of conductive structures (e.g., conductive structure 290) through at least one switch (e.g., switch 230).

[0059] At operation 720, a plurality of switches (eg, switches 230) may connect the signal sources to the plurality of conductive structures based on the decoded signals. In some embodiments, the switches may connect the signal sources to the conductive structures based on the decoded signals from a decoder (eg, decoder 225).

[0060] At operation 730, a multiplexer (eg, multiplexer 220) may select a test voltage present on the conductive structure based on the decoded signal. In some embodiments, the multiplexer may receive a test voltage for at least one conductive structure to test the conductive structure.

[0061] At operation 740, an analog-to-digital converter (ADC) (e.g., ADC 240) may provide a digital signal based on comparing the test voltage to a reference voltage. In some embodiments, the ADC may provide a digital output (e.g., Dout 270) based on comparing the test voltage to a reference voltage. In some embodiments, the ADC may receive the test voltage or a signal related thereto and output an output signal representing the resistance of the conductive structure (e.g., the conductive structure corresponding to the selected test voltage). In some embodiments, the ADC may be or include a one-bit sigma-delta ADC to obtain higher resolution, thereby reducing the required current and wiring area.

[0062] In some embodiments, method 700 may include amplifying the test voltage by a gain component (e.g., gain component 310). In some embodiments, the gain component may be or include an amplifier configured to receive the test voltage and amplify it. In some embodiments, method 700 may include outputting a digital output during operation of the conductive structure.

[0063] In one aspect of the present disclosure, a circuit is disclosed. The circuit includes a signal source, a plurality of switches, a multiplexer, and an analog-to-digital converter (ADC), wherein the signal source is configured to provide a test signal to at least one of a plurality of conductive structures based on a decoded signal, the switch is configured to connect the signal source to the plurality of conductive structures respectively according to the decoded signal, the multiplexer is configured to select a test voltage present on at least one conductive structure according to the decoded signal, and the analog-to-digital converter is configured to provide a digital output by comparing the test voltage with a reference voltage.

[0064] In some embodiments, the at least one conductive structure comprises a connection structure within one of the plurality of bonded dies or between two bonded dies.

[0065] In some embodiments, the analog-to-digital converter is configured to output the digital output during operation of the plurality of bonded dies or the two bonded dies.

[0066] In some embodiments, the plurality of conductive structures include at least one of a plurality of through silicon vias (TSVs), a plurality of super power rails (SPRs), a uBump, a hybrid bond, and an interconnect structure between dies.

[0067] In some embodiments, the digital output represents a resistance of the selected conductive structure.

[0068] In some embodiments, the circuit further comprises: a decoder connected to the multiplexer and configured to provide the decoded signal.

[0069] In some embodiments, the circuit further includes: a gain component configured to amplify the test voltage and provide an amplified signal to the analog-to-digital converter.

[0070] In some embodiments, the analog-to-digital converter is configured to output the digital output based on a clock signal.

[0071] In another aspect of the present disclosure, a circuit for testing a conductive structure is disclosed. The circuit includes a first die, a second die, at least one conductive structure between the first die and the second die or within at least one of the first die and the second die, a signal source within one of the first die and the second management chip, at least one switch configured to connect the signal source to the at least one conductive structure through a first wiring, an analog-to-digital converter (ADC) within one of the first die or the second die, and the ADC is connected to the at least one conductive structure through a second wiring located at a first end of the at least one conductive structure and a third wire located at a second end of the at least one conductive structure.

[0072] In some embodiments, the circuit further comprises: a multiplexer configured to connect the at least one conductive structure and the analog-to-digital converter.

[0073] In some embodiments, the circuit further comprises: a gain component configured to connect the at least one conductive structure and the analog-to-digital converter.

[0074] In some embodiments, the circuit further includes: a resistor configured to connect the analog-to-digital converter to the second end of the conductive structure.

[0075] In some embodiments, the analog-to-digital converter comprises a sigma-delta analog-to-digital converter.

[0076] In some embodiments, the circuit further includes: a first terminal and a second terminal, the first terminal being used to provide an input signal to the at least one conductive structure, and the second terminal being used to receive an output of the at least one conductive structure.

[0077] In some embodiments, the circuit further includes: a plurality of conductive structures and a plurality of switches, the plurality of conductive structures including the at least one conductive structure, the plurality of switches including the at least one switch, wherein the analog-to-digital converter is configured to output a digital output sequence corresponding to the plurality of conductive structures.

[0078] In some embodiments, the first die and the second die are arranged face to face or face to back.

[0079] In another aspect of the present disclosure, a method for simulating a semiconductor package is disclosed. The method includes providing a test signal to at least one of a plurality of conductive structures by a signal source based on a decoded signal, connecting the signal source to the plurality of conductive structures respectively through a plurality of switches based on the decoded signal, selecting a test voltage present on at least one conductive structure through a multiplexer based on the decoded signal, and providing a digital signal through an analog-to-digital converter (ADC) based on a comparison of the test voltage and a reference voltage.

[0080] In some embodiments, the method further includes: amplifying the test voltage by a gain component.

[0081] In some embodiments, the digital signal represents a resistance of the selected conductive structure.

[0082] In some embodiments, the method further comprises: outputting the signal during operation of the conductive structure.

[0083] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can be subjected to various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A circuit comprising: a signal source configured to provide a test signal to at least one of the plurality of conductive structures based on the decoded signal; a plurality of switches configured to connect the signal source to a plurality of conductive structures respectively based on the decoded signal; a multiplexer configured to select a test voltage present on the at least one conductive structure based on the decoded signal; as well as An analog-to-digital converter (ADC) is configured to provide a digital output based on comparing the test voltage to a reference voltage.

2. The circuit according to claim 1, wherein The at least one conductive structure includes a connection structure within one of the plurality of bonded dies or between two bonded dies.

3. The circuit according to claim 2, wherein: The analog-to-digital converter is configured to output the digital output during operation of the plurality of bonded dies or the two bonded dies.

4. The circuit according to claim 1, wherein: The plurality of conductive structures include at least one of a plurality of through silicon vias (TSVs), a plurality of super power rails (SPRs), a uBump, a hybrid bond, and an interconnect structure between dies.

5. The circuit according to claim 1, wherein: The digital output represents the resistance of the selected conductive structure.

6. The circuit according to claim 1, further comprising: A decoder is connected to the multiplexer and configured to provide the decoded signal.

7. The circuit according to claim 1, further comprising: A gain component is configured to amplify the test voltage and provide an amplified signal to the analog-to-digital converter.

8. A circuit comprising: a first tube core; A second tube core; at least one conductive structure between the first die and the second die or within at least one of the first die and the second die; a signal source in one of the first die and the second die; at least one switch configured to connect the signal source to the at least one conductive structure via a first conductor; as well as An analog-to-digital converter (ADC) is within one of the first die and the second die, and the analog-to-digital converter is connected to the at least one conductive structure through a second conductive line at the first end of the at least one conductive structure and a third conductive line at the second end of the at least one conductive structure.

9. A method of operating a circuit, comprising: providing, by a signal source, a test signal to at least one of the plurality of conductive structures based on the decoded signal; Based on the decoded signal, connecting the signal source to the plurality of conductive structures respectively through a plurality of switches; selecting, via a multiplexer, a test voltage present on the at least one conductive structure based on the decoded signal; as well as A digital signal is provided by an analog-to-digital converter (ADC) based on comparing the test voltage to a reference voltage.

10. The method according to claim 9, further comprising: The test voltage is amplified by a gain component.

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