Modulation circuit, microprocessor chip and motor control circuit

Abstract

The present application provides a modulation circuit, a microprocessor chip and a motor control circuit, wherein the modulation circuit includes: a first circuit, the first circuit is used to output a first digital signal; a second circuit, the second circuit is used to output a second digital signal corresponding to the analog signal in differential form; an output circuit, the output circuit is used to add the first digital signal and the second digital signal to obtain a third digital signal, and the third digital signal is the digital signal corresponding to the current time node. By obtaining the second digital signal corresponding to the differential form of the analog signal, that is, the digital signal corresponding to the slope signal of the analog signal, and adding the first digital signal to the second digital signal, the digital signal corresponding to the current time node can be obtained. In other words, the present application obtains a more accurate digital signal corresponding to the current time point through the slope compensation method, and compensates for the impact of data delay to a certain extent.

Description

Technical Field

[0001] The present application relates to the technical field of signal modulation, and in particular to a modulation circuit, a microprocessor chip and a motor control circuit. Background Art

[0002] Some electronic devices must be equipped with motors to make them work properly. In order for the motors in these electronic devices to work properly, the electronic devices also need to be equipped with motor control circuits. The motor control circuit needs to obtain current and control the working state of the motor based on the current. The motor control circuit includes a digital filter device, which is used to filter the digital signal.

[0003] In the related art, the digital filter is usually a SDFM filter (four-channel digital filter), and the four channels of the SDFM filter can independently receive bit streams, that is, the four channels of the SDFM filter can independently sample digital signals.

[0004] However, after the synchronization signal is triggered, the sampling principle of the SDFM filter determines that the digital signal sampled by the SDFM has a high hysteresis, which has a great impact on the overall responsiveness of the motor control circuit.

[0005] It should be pointed out that the information disclosed in the background technology section of this application is only intended to deepen the understanding of the general background technology of this application, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to those skilled in the art. Summary of the invention

[0006] In view of this, the present application provides a modulation circuit, a microprocessor chip and a motor control circuit, so as to solve the problem in the related art that after the synchronization signal is triggered, the sampling principle of the SDFM filter determines that the digital signal sampled by the SDFM has a high hysteresis, which has a great impact on the overall responsiveness of the motor control circuit.

[0007] In a first aspect, an embodiment of the present application provides a modulation circuit, including: A first circuit, wherein the first circuit is used to acquire an analog signal and output a first digital signal; a second circuit, the second circuit being configured to receive the analog signal and output a second digital signal corresponding to the analog signal in a differentiated form; an output circuit, wherein a first input end of the output circuit is electrically connected to an output end of the first circuit, a second input end of the output circuit is electrically connected to an output end of the second circuit, the output circuit is used to receive the first digital signal and the second digital signal, and add the first digital signal and the second digital signal to obtain a third digital signal, wherein the third digital signal is a digital signal corresponding to a current time node; The node between the input end of the first circuit and the input end of the second circuit is the input end of the modulation circuit, and the output end of the output circuit is the output end of the modulation circuit.

[0008] In an embodiment of the present application, a first digital signal corresponding to an analog signal is obtained through a first circuit, and a second digital signal corresponding to a differential form of the analog signal is obtained through a second circuit, and the first digital signal is added to the second digital signal to obtain a digital signal corresponding to the current time node. It can be understood that because there is a delay in the acquisition of data by the modulation circuit, that is, the first digital signal obtained by the modulation circuit at the current time point actually corresponds to the analog signal collected at the previous time node. In an embodiment of the present application, the digital signal corresponding to the current time node can be obtained by obtaining the second digital signal corresponding to the differential form of the analog signal, that is, the digital signal corresponding to the slope signal of the analog signal, and adding the first digital signal to the second digital signal. In other words, the present application obtains a more accurate digital signal corresponding to the current time point through the slope compensation method, which compensates for the impact of data delay to a certain extent.

[0009] In a possible implementation, the first circuit includes: a first adding module, wherein a first input end of the first adding module is an input end of the first circuit, and the first adding module is used to obtain an analog signal, and generate and output a first output signal according to the analog signal and a first negative feedback signal; a first integration module, wherein an input end of the first integration module is electrically connected to an output end of the first addition module, and the first integration module is used to receive the first output signal and output a second output signal; A first quantization module, wherein an input end of the first quantization module is electrically connected to an output end of the first addition module, and the first quantization module is used to receive the first output signal and convert the first output signal into a first digital signal; a first negative feedback module, wherein an input end of the first negative feedback module is electrically connected to an output end of the first quantization module, an output end of the first negative feedback module is electrically connected to a second input end of the first addition module, and the first negative feedback module is used to receive the first digital signal, convert the first digital signal into the first negative feedback signal, and output the first negative feedback signal; The output end of the first quantization module is the output end of the first circuit.

[0010] In the embodiment of the present application, the first circuit converts the acquired analog signal into a first digital signal through a first addition module, a first integration module, a first quantization module and a first negative feedback module. It can be understood that through the first circuit in the embodiment of the present application, a relatively accurate first digital signal can be obtained, thereby ensuring the accuracy of the third digital signal, that is, obtaining a more accurate digital signal corresponding to the current time node. And a first integration module is added to the first circuit, and the stability of the entire first circuit is ensured by the first integration module.

[0011] In a possible implementation manner, the first integration module is a second-order integrator.

[0012] In the embodiment of the present application, the first integration module is a second-order integrator. Since the second-order integrator is more stable and has smaller errors than the first-order integrator, the use of the second-order integrator is more conducive to ensuring the stability of the entire circuit.

[0013] In a possible implementation, the first quantization module includes: an analog comparator, wherein the positive input terminal of the analog comparator is the input terminal of the first quantization module, the negative input terminal of the analog comparator is grounded, and the analog comparator is used to receive the second output signal and convert the second output signal into a first digital signal; A D flip-flop, wherein an input terminal of the D flip-flop is electrically connected to an output terminal of the analog comparator, and the D flip-flop is used to output the first digital signal; Among them, the output end of the D trigger is the output end of the first quantization module.

[0014] In the embodiment of the present application, the quantization module includes an analog comparator and a D flip-flop, and converts the analog signal into a digital signal through the analog comparator and the D flip-flop, and outputs the digital signal.

[0015] In a possible implementation, the second circuit includes: A difference calculation module, the input end of the difference calculation module is the input end of the second circuit, and the difference calculation module is used to calculate the difference between the analog signal corresponding to the current time node and the analog signal corresponding to the previous time node, and obtain and output a second output signal; a second adding module, wherein a first input terminal of the second adding module is electrically connected to an output terminal of the difference calculating module, and the second adding module is used to receive the second output signal and the second negative feedback signal, and generate and output a third output signal; a second quantization module, wherein an input end of the second quantization module is electrically connected to an output end of the second addition module, and the second quantization module is used to receive the third output signal and convert the third output signal into a second digital signal; a second negative feedback module, wherein an input end of the second negative feedback module is electrically connected to an output end of the second quantization module, an output end of the second negative feedback module is electrically connected to a second input end of the second addition module, and the second negative feedback module is used to receive the second digital signal, convert the second digital signal into a second negative feedback signal, and output the second negative feedback signal; The output end of the second quantization module is the output end of the second circuit.

[0016] In the embodiment of the present application, the second circuit converts the acquired analog signal into a second digital signal through a difference calculation module, a second addition module, a second quantization module, and a second negative feedback module. It can be understood that through the second circuit in the embodiment of the present application, a relatively accurate second digital signal can be obtained, thereby ensuring the accuracy of the third digital signal, that is, obtaining a more accurate digital signal corresponding to the current time node.

[0017] In a possible implementation, the second circuit includes: A difference calculation module, the input end of the difference calculation module is the input end of the second circuit, and the difference calculation module is used to calculate the difference between the analog signal corresponding to the current time node and the analog signal corresponding to the previous time node, and obtain and output a second output signal; a second adding module, wherein a first input terminal of the second adding module is electrically connected to an output terminal of the difference calculating module, and the second adding module is used to receive the second output signal and the second negative feedback signal, and generate and output a third output signal; a second quantization module, wherein an input end of the second quantization module is electrically connected to an output end of the second addition module, and the second quantization module is used to receive the third output signal and convert the third output signal into a second digital signal; a second negative feedback module, wherein the input end of the second negative feedback module is electrically connected to the output end of the second quantization module and the input end of the second quantization module respectively, the output end of the second negative feedback module is electrically connected to the second input end of the second addition module, and the second negative feedback module is used to receive the third output signal and output the second negative feedback signal; The output end of the second quantization module is the output end of the second circuit.

[0018] In a possible implementation manner, the second circuit further includes: A second integration module, wherein the input end of the second integration module is electrically connected to the output end of the second addition module, the output end of the second integration module is electrically connected to the input end of the second quantization module, and the second integration module is a second-order integrator.

[0019] In the embodiment of the present application, a second integration module is added to the second circuit, and the stability of the entire second circuit is ensured by the second integration module. The second integration module is a second-order integrator, because the second-order integrator is more stable and has smaller errors than the first-order integrator, so the use of the second-order integrator is more conducive to ensuring the stability of the entire circuit.

[0020] In a possible implementation, the difference calculation module includes: A delay unit, the delay unit is used to receive an analog signal and output a delay signal according to a preset time interval; an adding unit, wherein a first input terminal of the adding unit is electrically connected to an output terminal of the delay unit, and the adding unit is used to obtain the analog signal and the delay signal, and generate and output a second output signal according to the analog signal and the delay signal; The node between the input end of the delay unit and the second input end of the adding unit is the input end of the difference calculation module, and the output end of the adding module is the output end of the difference calculation module.

[0021] In an embodiment of the present application, the difference calculation module is used to obtain the difference between the analog signal corresponding to the current time point and the analog signal corresponding to the previous time point, so as to facilitate obtaining the second digital signal corresponding to the analog signal in differential form.

[0022] In an embodiment of the present application, the difference calculation module includes a delay unit and an addition unit. The difference calculation module uses the principle of difference compensation to infer the actual current x(t) at the current time node, thereby compensating for the impact of the modulation circuit delay.

[0023] In a second aspect, an embodiment of the present application provides a microprocessor chip, including: The modulation circuit according to any one of the first aspects.

[0024] In a possible implementation, the microprocessor chip further includes: a filter, wherein an input end of the filter is electrically connected to an output end of the modulation circuit, and the filter is used to filter the third digital signal output by the modulation circuit and output a fourth digital signal; an amplifier, wherein an input end of the amplifier is electrically connected to an output end of the filter, and the amplifier is used to amplify or reduce the fourth digital signal and output a fifth digital signal; A configurator, wherein the input end of the configurator is used to receive a control signal, the first output end of the configurator is electrically connected to the control end of the filter, the second output end of the configurator is electrically connected to the control end of the gain device, and the configurator is used to control the filter and the gain device according to the received control signal.

[0025] In the embodiment of the present application, the configuration of the filter and the scaling factor of the gainer are controlled by the configurator, and there is an external interface outside the configurator, through which the user can control the configurator, and then control the configuration of the filter and the scaling factor of the gainer, thereby providing convenience to the user and improving work efficiency.

[0026] In a third aspect, an embodiment of the present application provides a motor control circuit, including: A control module, used to obtain a current detection result and generate a driving instruction according to the current detection result; A power module, used to start or stop providing driving power to the motor according to the driving instruction sent by the control module; A current detection module, used to detect the current value output by the power module and output the current value; The microprocessor chip described in the second aspect is used to output the current detection result according to the current value output by the current detection module. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0028] Figure 1 A schematic diagram of the structure of a SDFM filter provided by the prior art of this application; Figure 2 A schematic diagram of a modulation circuit provided in an embodiment of the present application; Figure 3 A schematic diagram of a modulation circuit provided in an embodiment of the present application; Figure 4 A schematic diagram of the structure of a first circuit provided in an embodiment of the present application; Figure 5 A schematic diagram of the structure of another first circuit provided in an embodiment of the present application; Figure 6 A schematic diagram of the structure of another first circuit provided in an embodiment of the present application; Figure 7A schematic diagram of the structure of a quantization module provided in an embodiment of the present application; Figure 8 A schematic diagram of the structure of a second circuit provided in an embodiment of the present application; Fig. 9 A schematic diagram of the structure of another second circuit provided in an embodiment of the present application; Fig.10 A schematic diagram of the structure of another second circuit provided in an embodiment of the present application; Fig.11 A schematic diagram of the structure of a difference calculation module provided in an embodiment of the present application; Fig.12 A schematic diagram of the structure of another modulation circuit provided in an embodiment of the present application; Fig.13 A schematic diagram of the structure of an analog-to-digital conversion device provided in an embodiment of the present application; Fig.14 A schematic diagram of the structure of another analog-to-digital conversion device provided in an embodiment of the present application; Fig.15 A schematic diagram of the structure of a motor control circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0030] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0031] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0032] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0033] Some electronic devices must be equipped with motors to make them work properly. In order for the motors in these electronic devices to work properly, the electronic devices also need to be equipped with motor control circuits. The motor control circuit needs to obtain current and control the working state of the motor based on the current. The motor control circuit includes a digital filter device, which is used to filter the digital signal.

[0034] In the related art, the digital filter is usually a SDFM filter (four-channel digital filter), and the four channels of the SDFM filter can independently receive bit streams, that is, the four channels of the SDFM filter can independently sample digital signals.

[0035] However, after the synchronization signal is triggered, the sampling principle of the SDFM filter determines that the digital signal sampled by the SDFM has a high hysteresis, which has a great impact on the overall responsiveness of the motor control circuit.

[0036] For ease of understanding, an embodiment of the present application provides a structural diagram of an SDFM filter.

[0037] See also Figure 1 , is a structural diagram of a SDFM filter provided in an embodiment of the present application. Figure 1The structure of a single filter is shown in FIG. 1 , which includes an input control unit (Input Control Unit), a data filter unit (DataFilter Unit), a data shift unit (Data Shift Unit), a FIFO memory, a synchronization signal output unit, and a comparison filter unit (Comparator Filter Unit). The input control unit receives Sigma-Delta modulated data through the SD-Dx interface and the SD-Cx interface respectively. Specifically, the input control unit includes a decoder (Decoding), which is used to receive Sigma-Delta modulated data. The input control unit is also used to receive the Sigma-Delta modulated clock (SYSCLK). The data filter unit is used to receive the signal output by the input control unit and filter the signal. In a possible implementation, the data filter unit includes a SINC filter, which can be any one of Sinc1, Sinc2, Sinc3 and SincFast. After the data conversion unit converts the data output by the data filter unit, it can directly output the SDDATAx signal, or send the converted signal to the programmable unit. The programmable unit performs synchronization processing on the received signal according to the synchronization signal output by the synchronization signal output unit, and then outputs the processed signal (FIFOx). In addition, the synchronization signal output unit is also used to send a synchronization signal to the data filtering unit. After receiving the signal output by the input control unit, the comparison filtering unit filters the signal and outputs the filtered signal (SDCDATAx). Specifically, the comparison filtering unit includes a SINC filter and a digital comparator. The SINC filter is used to perform the first filtering of the signal, and the digital comparator is used to perform the second filtering of the signal. The digital comparator includes 3 comparators, and the user can control the corresponding comparator through the COMPHx, COMPHZx and COMPLx interfaces respectively. Through the digital comparator, the user can quickly monitor the input conditions and protect the system through the PWM signal to prevent the system from potential damage.

[0038] Although there are many types of SINC filters, most of the signals collected after the SINC filters are enabled have some errors to a greater or lesser extent. As shown in Table 1, after the Sinc1 filter is enabled and configured, there are no error samples; after the Sinc2 filter is enabled and configured, the first sample is incorrect; after the SincFast filter is enabled and configured, the first two samples are incorrect; after the Sinc3 filter is enabled and configured, the first two samples are incorrect.

[0039] Table 1: Because the data collected by the SINC filter has errors, and the erroneous data are concentrated in the first two data, the SDFM filter usually discards the first two data when acquiring data and starts recording from the more accurate third data.

[0040] Although discarding the first two data can make the SDFM filter avoid the risk of errors in the first two data, because the SDFM filter takes a long time to complete a complete sampling, the SDFM filter has a high lag in collecting data. For example, under a 20M clock (SD_CLK=20M), the oversampling rate (OSR) of the SDFM filter is 250, and the time required for the SDFM filter to complete a complete sampling is 250 / 20=12.5us. The delay of more than 10us has a great impact on the overall responsiveness of the closed-loop control, thereby affecting the accuracy of the data.

[0041] In view of the above problems, an embodiment of the present application provides a modulation circuit, which can obtain a digital signal corresponding to the current time node by obtaining a second digital signal corresponding to the differential form of the analog signal, that is, a digital signal corresponding to the slope signal of the analog signal, and adding the first digital signal to the second digital signal. In other words, the present application obtains a more accurate digital signal corresponding to the current time point through a slope compensation method, and compensates for the impact of data delay to a certain extent. The details are described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0042] See also Figure 2 , is a schematic diagram of a modulation circuit provided in an embodiment of the present application. Figure 2 As shown, the modulation circuit 200 includes a first circuit 201, a second circuit 202, and an output circuit 203. The first circuit 201 is used to obtain an analog signal and output a first digital signal; the second circuit 202 is used to receive an analog signal and output a second digital signal corresponding to the analog signal in a differential form; the first input end of the output circuit 203 is electrically connected to the output end of the first circuit 201, and the second input end of the output circuit 203 is electrically connected to the output end of the second circuit 202. The output circuit 203 is used to receive the first digital signal and the second digital signal, and add the first digital signal and the second digital signal to obtain a third digital signal, which is the digital signal corresponding to the current time node. The node between the input end of the first circuit 201 and the input end of the second circuit 202 is the input end of the modulation circuit, and the output end of the output circuit 203 is the output end of the modulation circuit.

[0043] For ease of understanding, the principle of the modulation circuit is described in detail below.

[0044] join Figure 3, is a schematic diagram of the principle of a modulation circuit provided in an embodiment of the present application. Figure 3 As shown, the PWM timer is an upward counting timer with a counting period of 0-Prd. The CMPB node in the PWM signal corresponds to the modulation circuit receiving the SOC synchronization signal, but the modulation circuit obtains the current analog signal at the CMPA node, and the time interval between CMPB and CMPA is T1≥3*OSR / SD_CLK. As mentioned above, because the first two data collected by the filter usually have errors, T1≥3*OSR / SD_CLK, thereby ensuring the accuracy of the data.

[0045] like Figure 3 As shown in the figure, the time point corresponding to the CMPA node is moment t. Since there is a delay in the filter obtaining data, the current obtained by the filter at moment t is actually the current value corresponding to moment t-1, that is, the current obtained by the filter at moment t is actually x(t-1), and the delay time difference between them is dt= OSR / SD_CLK, which is the generation time of 0-1bit stream under the corresponding oversampling rate.

[0046] In the embodiment of the present application, in order to obtain the actual current x(t) corresponding to time t, while obtaining the current curve, the current curve is regarded as linear within the time dt (dt is small enough), thereby generating a current differential curve. Figure 3 As shown in the figure, the current differential value corresponding to the current differential curve at time t is dx(t-1). According to the principle of differential derivative, x(t)-x(t-1)=x'dt, where x' is the derivative of x, we can know that x(t)= x(t-1)+ x'dt. Therefore, the real current x(t) at time t can be estimated by adding the actual current obtained at time t and the differential corresponding to the current, that is, the real current x(t) is obtained through the principle of slope compensation.

[0047] In an embodiment of the present application, a first digital signal corresponding to an analog signal is obtained by a first circuit, and a second digital signal corresponding to a differential form of the analog signal is obtained by a second circuit, and the output circuit adds the first digital signal to the second digital signal to obtain a digital signal corresponding to the current time node. It can be understood that because there is a delay in the acquisition of data by the modulation circuit, that is, the first digital signal obtained by the modulation circuit at the current time point actually corresponds to the analog signal collected at the previous time node. In an embodiment of the present application, the digital signal corresponding to the current time node can be obtained by obtaining the second digital signal corresponding to the differential form of the analog signal, that is, the digital signal corresponding to the slope signal of the analog signal, and adding the first digital signal to the second digital signal. In other words, the present application obtains a more accurate digital signal corresponding to the current time point through the slope compensation method, which compensates for the impact of data delay to a certain extent.

[0048] In a possible implementation, the first circuit includes a first adding module, a first quantization module, and a first negative feedback module. To facilitate understanding, an embodiment of the present application provides a schematic diagram of the structure of the first circuit.

[0049] See also Figure 4 , is a schematic diagram of the structure of a first circuit provided in an embodiment of the present application. Figure 4 As shown, the first circuit 201 includes a first adding module 401, a first quantization module 402 and a first negative feedback module 403. The first input end of the first adding module 401 is the input end of the first circuit 201, and the first adding module 401 is used to obtain an analog signal, and generate and output a first output signal according to the analog signal and the first negative feedback signal; the input end of the first quantization module 402 is electrically connected to the output end of the first adding module 401, and the first quantization module 402 is used to receive the first output signal and convert the first output signal into a first digital signal; the input end of the first negative feedback module 403 is electrically connected to the output end of the first quantization module 402, and the output end of the first negative feedback module 403 is electrically connected to the second input end of the first adding module 401, and the first negative feedback module 403 is used to receive the first digital signal, convert the first digital signal into a first negative feedback signal, and output the first negative feedback signal; the output end of the first quantization module 402 is the output end of the first circuit 201.

[0050] In the embodiment of the present application, the first adding module 401 is an adder, the first quantization module 402 is a quantizer, and the first negative feedback module 403 is a digital to analog converter (DAC). It can be understood that after the adder obtains the analog signal and the first negative feedback signal, it outputs the first output signal according to the two signals, and the quantizer converts the signal type of the first output signal from an analog signal to a digital signal, and outputs the digital signal. Because the DAC receives a digital signal, but the signal that the adder can use is an analog signal, the DAC converts the received digital signal into an analog signal, that is, the first negative feedback signal, and feeds the first negative feedback signal back to the adder. Of course, this is only an exemplary description. Those skilled in the art can set the first adding module, the first quantization module and the first negative feedback module to other components without changing the inventive concept, and the embodiment of the present application does not make specific restrictions on this.

[0051] Through the first circuit in the embodiment of the present application, a relatively accurate first digital signal can be obtained, thereby ensuring the accuracy of the third digital signal, that is, obtaining a more accurate digital signal corresponding to the current time node.

[0052] In addition, in a possible implementation, the first circuit has another connection mode. To facilitate understanding, the embodiment of the present application also provides another structural schematic diagram of the first circuit.

[0053] See also Figure 5 , is a schematic diagram of another structure of a first circuit provided in an embodiment of the present application. Figure 5 As shown, the first input end of the first adding module 401 is the input end of the first circuit 201, and the first adding module 401 is used to obtain an analog signal, and generate and output a first output signal according to the analog signal and the first negative feedback signal; the input end of the first quantization module 402 is electrically connected to the output end of the first adding module 401, and the first quantization module 402 is used to receive the first output signal and convert the first output signal into a first digital signal; the input end of the first negative feedback module 403 is electrically connected to the output end of the first adding module 401 and the input end of the first quantization module 402 respectively, the output end of the first negative feedback module 403 is electrically connected to the second input end of the first adding module 401, and the first negative feedback module 403 is used to receive the first output signal and output a first negative feedback signal; wherein, the output end of the first quantization module 402 is the output end of the first circuit 201.

[0054] In the embodiment of the present application, because the signal type received by the first negative feedback module 403 is an analog signal, the first negative feedback module 403 does not need to convert the signal type, so the first negative feedback module 403 can be any negative feedback element with a delay function, and the embodiment of the present application does not impose specific restrictions on this. It can be understood that the first negative feedback module uses ordinary elements without data conversion function, which can save material costs.

[0055] In practical applications, the first circuit may have the risk of instability, therefore, in the embodiment of the present application, a first integration module is added to the first circuit to maintain the stability of the entire circuit. Detailed description will be given below in conjunction with the accompanying drawings.

[0056] See also Figure 6 , is a schematic diagram of another structure of a first circuit provided in an embodiment of the present application. Figure 6 As shown, the first circuit 201 is Figure 4 A first integration module 601 is added on the basis of the first circuit shown in the figure. The input end of the first integration module 601 is electrically connected to the output end of the first addition module 401 , and the output end of the first integration module 601 is electrically connected to the input end of the first quantization module 402 .

[0057] In another possible implementation, Figure 5A first integral module is added to the first circuit shown. At this time, the input end of the first negative feedback module can be between the first integral module and the first quantization module, that is, the input end of the first negative feedback module is electrically connected to the output end of the first integral module and the input end of the first quantization module respectively; the input end of the first negative feedback module can also be between the first addition module and the first integral module, that is, the input end of the first negative feedback module is electrically connected to the output end of the first addition module and the input end of the first integral module respectively. The embodiment of the present application does not impose specific restrictions on this.

[0058] In the embodiment of the present application, a first integration module is added to the first circuit, and the stability of the entire first circuit is ensured by the first integration module.

[0059] In a possible implementation, the first integration module is a second-order integrator. Since the second-order integrator is more stable and has a smaller error than the first-order integrator, the use of the second-order integrator is more conducive to ensuring the stability of the entire circuit.

[0060] In addition, to facilitate understanding, the embodiment of the present application also provides a structural schematic diagram of a quantization module.

[0061] See also Figure 7 , is a schematic diagram of the structure of a quantization module provided in an embodiment of the present application. Figure 7 As shown, the quantization module 402 includes an analog comparator 4021 and a D trigger 4022, wherein the positive input terminal of the analog comparator 4021 is the input terminal of the first quantization module 402, the negative input terminal of the analog comparator 4021 is grounded, and the analog comparator is used to receive the second output signal and convert the second output signal into a first digital signal; the input terminal of the D trigger 4022 is electrically connected to the output terminal of the analog comparator 4021, and the D trigger 4022 is used to output the first digital signal; wherein the output terminal of the D trigger 4022 is the output terminal of the first quantization module 402.

[0062] The analog comparator 4021 generates a logic 1 for the positive input and a logic 0 for the negative input, thereby converting the analog signal into a digital signal. In addition, the D flip-flop 4022 can prevent the analog comparator 4021 from being directly connected to other circuits and causing failure. That is, the D flip-flop 4022 ensures the stability of the circuit while outputting a digital signal.

[0063] To facilitate understanding, the embodiment of the present application also provides a structural schematic diagram of a second circuit.

[0064] See also Figure 8 , is a schematic diagram of the structure of a second circuit provided in an embodiment of the present application. Figure 8As shown, the second circuit 202 includes a difference calculation module 801 , a second addition module 802 , a second quantization module 803 and a second negative feedback module 804 . Among them, the input end of the difference calculation module 801 is the input end of the second circuit 202, and the difference calculation module 801 is used to calculate the difference between the analog signal corresponding to the current time node and the analog signal corresponding to the previous time node, and obtain and output the second output signal; the first input end of the second addition module 802 is electrically connected to the output end of the difference calculation module 801, and the second addition module 802 is used to receive the second output signal and the second negative feedback signal, and generate and output the third output signal; the input end of the second quantization module 803 is electrically connected to the output end of the second addition module 802, and the second quantization module 803 is used to receive the third output signal and convert the third output signal into a second digital signal; the input end of the second negative feedback module 804 is electrically connected to the output end of the second quantization module 803, and the output end of the second negative feedback module 804 is electrically connected to the second input end of the second addition module 802, and the second negative feedback module 804 is used to receive the second digital signal, convert the second digital signal into a second negative feedback signal, and output the second negative feedback signal; wherein, the output end of the second quantization module 803 is the output end of the second circuit 202.

[0065] In the embodiment of the present application, the second adding module 802 is an adder, the second quantization module 803 is a quantizer, and the second negative feedback module 804 is a DAC. It can be understood that after the adder obtains the analog signal and the second negative feedback signal, it outputs the second output signal according to the two signals, and the quantizer converts the signal type of the second output signal from an analog signal to a digital signal, and outputs the digital signal. Because the DAC receives a digital signal, but the signal that the adder can use is an analog signal, the DAC converts the received digital signal into an analog signal, that is, the second negative feedback signal, and negatively feeds the second negative feedback signal back to the adder. Of course, this is only an exemplary description. Those skilled in the art can set the second adding module, the second quantization module and the second negative feedback module to other components without changing the inventive concept, and the embodiment of the present application does not make specific restrictions on this.

[0066] In the embodiment of the present application, a difference calculation module is added to calculate the digital signal corresponding to the analog signal in differential form, that is, the second digital signal. Through the second circuit in the embodiment of the present application, a relatively accurate second digital signal can be obtained, thereby ensuring the accuracy of the third digital signal, that is, obtaining a more accurate digital signal corresponding to the current time node.

[0067] In addition, in a possible implementation, the second circuit has another connection mode. To facilitate understanding, the embodiment of the present application also provides another structural schematic diagram of the second circuit.

[0068] join Fig. 9 , is a schematic diagram of the structure of another second circuit provided in an embodiment of the present application. Fig. 9 As shown, the input end of the difference calculation module 801 is the input end of the second circuit 202, and the difference calculation module 801 is used to calculate the difference between the analog signal corresponding to the current time node and the analog signal corresponding to the previous time node, and obtain and output the second output signal; the first input end of the second addition module 802 is electrically connected to the output end of the difference calculation module 801, and the second addition module 802 is used to receive the second output signal and the second negative feedback signal, and generate and output the third output signal; the input end of the second quantization module 803 is electrically connected to the output end of the second addition module 802, and the second quantization module 803 is used to receive the third output signal and convert the third output signal into a second digital signal; the input end of the second negative feedback module 804 is electrically connected to the output end of the second quantization module 803 and the input end of the second quantization module 803 respectively, and the output end of the second negative feedback module 804 is electrically connected to the second input end of the second addition module 802, and the second negative feedback module 804 is used to receive the third output signal and output the second negative feedback signal; wherein, the output end of the second quantization module 803 is the output end of the second circuit 202.

[0069] In the embodiment of the present application, because the signal type received by the second negative feedback module 804 is an analog signal, the second negative feedback module 804 does not need to convert the signal type, so the second negative feedback module 804 can be any negative feedback element with a delay function, and the embodiment of the present application does not impose specific restrictions on this. It can be understood that the second negative feedback module uses ordinary elements without data conversion function, which can save material costs.

[0070] In practical applications, the second circuit may have the risk of instability, therefore, in the embodiment of the present application, a second integration module is added to the second circuit to maintain the stability of the entire circuit. Detailed description will be given below in conjunction with the accompanying drawings.

[0071] See also Fig.10 , is a schematic diagram of the structure of another second circuit provided in an embodiment of the present application. Fig.10 As shown, the second circuit 202 Figure 8 A second integration module 1001 is added on the basis of the second circuit shown in the figure. The input end of the second integration module 1001 is electrically connected to the output end of the second addition module 802 , and the output end of the second integration module 1001 is electrically connected to the input end of the second quantization module 803 .

[0072] In another possible implementation, Fig. 9A second integral module is added to the second circuit shown. At this time, the input end of the second negative feedback module can be between the second integral module and the second quantization module, that is, the input end of the second negative feedback module is electrically connected to the output end of the second integral module and the input end of the second quantization module respectively; the input end of the second negative feedback module can also be between the second addition module and the second integral module, that is, the input end of the second negative feedback module is electrically connected to the output end of the second addition module and the input end of the second integral module respectively. The embodiment of the present application does not impose specific restrictions on this.

[0073] In the embodiment of the present application, a second integration module is added to the second circuit, and the stability of the entire second circuit is ensured by the second integration module.

[0074] In a possible implementation, the second integration module is a second-order integrator. Since the second-order integrator is more stable and has a smaller error than the first-order integrator, the use of the second-order integrator is more conducive to ensuring the stability of the entire circuit.

[0075] It should be noted that the first integration module and the second integration module in the present application can be different integrators, for example, the first integration module is a first-order integrator, and the second integration module is a second-order integrator; or the first integration module is a second-order integrator, and the second integration module is a first-order integrator; or the first integration module and the second integration module are both second-order integrators. The present application embodiment does not specifically limit this.

[0076] The function of the above-mentioned difference calculation module 801 is to calculate the difference between the analog signal corresponding to the current time node and the analog signal corresponding to the previous time node, obtain and output the second output signal. For ease of understanding, the embodiment of the present application also provides a structural diagram of a difference calculation module.

[0077] See also Fig.11 , is a schematic diagram of the structure of a difference calculation module provided in an embodiment of the present application. Fig.11 As shown, the difference calculation module 801 includes a delay unit 8011 and an addition unit 8012. The delay unit 8011 is used to receive an analog signal and output a delay signal according to a preset time interval; the addition unit 8012, the first input end of the addition unit 8012 is electrically connected to the output end of the delay unit 8011, the addition unit 8012 is used to obtain the analog signal and the delay signal, and generate and output a second output signal according to the analog signal and the delay signal; wherein, the node between the input end of the delay unit 8011 and the second input end of the addition unit 8012 is the input end of the difference calculation module 801, and the output end of the addition module is the output end of the difference calculation module 801.

[0078] In the embodiment of the present application, the delay module 8011 may be a delay device (Z -1), it can be understood that when a signal x(n) enters the delay device, the signal output by the delay device is the signal value x(n-1) corresponding to the previous moment. Of course, the delay module in this application is only an exemplary description and should not be used as a limitation on the scope of protection of this application.

[0079] Corresponding to the above embodiment, the present application also provides a structural schematic diagram of another modulation circuit.

[0080] See also Fig.12 , is a schematic diagram of the structure of another modulation circuit provided in an embodiment of the present application. Fig.12 As shown, the input analog signal passes through the first addition module 401, the first integration module 601, the first quantization module 402 and the first negative feedback module 403, and finally the first quantization module 402 outputs the first digital signal, which is the digital signal corresponding to the analog signal. At the same time, the analog signal passes through the delay unit 8011, the addition unit 8012, the second addition module 802, the second integration module 1001, the second quantization module 803 and the second negative feedback module 804, and finally the second quantization module 803 outputs the second digital signal, which is the digital signal corresponding to the analog signal in differential form. The output circuit 203 adds the first digital signal and the second digital signal to obtain and output the third digital signal.

[0081] By obtaining the second digital signal corresponding to the differential form of the analog signal, that is, the digital signal corresponding to the slope signal of the analog signal, and adding the first digital signal to the second digital signal, the digital signal corresponding to the current time node can be obtained. In other words, the present application obtains a more accurate digital signal corresponding to the current time point through the slope compensation method, compensating for the impact of data delay to a certain extent.

[0082] Corresponding to the above embodiments, the present application also provides an analog-to-digital conversion device.

[0083] See also Fig.13 , is a schematic diagram of the structure of an analog-to-digital conversion device provided in an embodiment of the present application. Fig.13 As shown, the analog-to-digital conversion device 1300 includes the above Figure 2-Figure 12 The modulation circuit 200, the filter 1301 and the gain device 1302 shown in the figure. The input end of the filter 1301 is electrically connected to the output end of the modulation circuit 200, and the filter 1301 is used to filter the third digital signal output by the modulation circuit 200 and output the fourth digital signal; the input end of the gain device 1302 is electrically connected to the output end of the filter 1301, and the gain device 1302 is used to amplify or reduce the fourth digital signal and output the fifth digital signal; wherein the input end of the modulation circuit 200 is the input end of the analog-to-digital conversion device, and the output end of the gain device 1302 is the output end of the analog-to-digital conversion device.

[0084] In the embodiment of the present application, the modulation circuit 200 samples the analog signal at the input end at a sampling frequency fs, and converts the analog signal into a third digital signal for output. The third digital signal output by the modulation circuit 200 may be a single-bit data stream (e.g., a digital data sequence with a single-bit resolution). Of course, the third digital signal may also be a multi-bit data stream, which is not specifically limited in the embodiment of the present application. The sampling frequency fs is usually much higher than the Nyquist sampling frequency of the analog input signal (e.g., fs is 1000 or 10000 times the Nyquist sampling frequency).

[0085] For example, for a motor system with a Nyquist sampling frequency of 20 KHz, the sampling frequency fs of the modulation circuit may be approximately 20 MHz. Alternatively, for a motor system with a Nyquist sampling frequency of 20 KHz, the sampling frequency fs of the modulation circuit may be approximately 200 MHz.

[0086] The filter (also called sigma-delta demodulator) 1301 includes a low-pass filter and a decimator. In practical applications, the low-pass filter and the decimator can be implemented in the same circuit module or hardware module, or in different circuit modules or hardware modules. There are many types of low-pass filters, for example, infinite impulse response (IIR) filter, finite impulse response (FIR) filter, synchronous filter, comb filter, etc.

[0087] Specifically, the low-pass filter has a digital cutoff frequency π / D, where π is a normalized digital frequency (in radians / second) corresponding to half the sampling frequency fs, and D is the decimation factor of the decimator. The low-pass filter can reduce or remove frequency components of the input signal (e.g., a one-bit digital stream) above the digital frequency π / D, and prevent aliasing during the decimation process when the decimator performs decimation. The decimator reduces the sampling frequency of the digital signal by the decimation factor D. Because the modulation circuit 200 uses a larger sampling frequency fs, the low-pass filter can use a simpler low-pass filter, and the decimator can output more bit resolution.

[0088] In one possible implementation, the filter may include multiple stages of processing, each stage of processing including a low-pass filter and a decimator, and the low-pass filter in each stage is also used to "average" the input signal, thereby converting the digital signal into a multi-bit digital value. The decimator uses a decimation factor D to decimate the multi-bit digital value output by the low-pass filter and outputs the multi-bit digital value.

[0089] The gainer 1302 scales the data output by the filter 1301 by a scaling factor. In one possible implementation, the gainer 1302 includes a multiplier, which is used to multiply the data output by the filter 1301 by the scaling factor. In one possible implementation, the gainer 1302 includes a divider, which is used to output data in a normalized format.

[0090] In practical applications, the configuration of the filter and the gain device is fixed, which cannot meet the various needs of users. Therefore, the embodiment of the present application adds a configurator to the analog-to-digital conversion device, which is described in detail below with reference to the accompanying drawings.

[0091] See also Fig.14 , is a schematic diagram of the structure of another analog-to-digital conversion device provided in an embodiment of the present application. Fig.14 As shown, the analog-to-digital conversion device 1300 further includes a configurator 1401. The input end of the configurator 1401 is the control end of the analog-to-digital conversion device 1300, the first output end of the configurator 1401 is electrically connected to the control end of the filter 1301, the second output end of the configurator 1401 is electrically connected to the control end of the gain device 1302, and the configurator 1401 is used to control the filter 1301 and the gain device 1302 according to the received control signal.

[0092] In the embodiment of the present application, the configuration of the filter and the scaling factor of the gainer are controlled by the configurator, and there is an external interface outside the configurator, through which the user can control the configurator, and then control the configuration of the filter and the scaling factor of the gainer, thereby providing convenience to the user and improving work efficiency.

[0093] Corresponding to the above embodiment, the present application embodiment further provides a microprocessor chip, the microprocessor chip comprising Fig.13 and Fig.14 The analog-to-digital conversion device shown. The microprocessor chip can be a micro central control chip or system-on-chip chip such as MCU, DSP, MPU, micro CPU, etc. that can process digital signals, analog signals, or perform signal control functions, instruction processing and calculation functions, etc., and the embodiments of the present application do not specifically limit this.

[0094] Corresponding to the above embodiment, the embodiment of the present application also provides a motor control circuit.

[0095] See also Fig.15 , is a schematic diagram of the structure of a motor control circuit provided in an embodiment of the present application. Fig.15As shown, the motor control circuit 1500 includes a control module 1501, a power module 1502, a current detection module 1503 and a microprocessor chip (microprocessor chip 1 and microprocessor chip 2 shown in the figure). Among them, the control module 1501 is used to obtain the current detection result and generate a driving instruction according to the current detection result; the power module 1502 is used to start or stop providing driving power to the motor according to the driving instruction sent by the control module 1501; the current detection module 1503 is used to detect the current value output by the power module 1502 and output the current value; the microprocessor chip is used to output the current detection result according to the current value output by the current detection module 1503.

[0096] In an embodiment of the present application, the control module 1501 includes an instruction generation module and an abnormal current detection module, and the abnormal current detection module is used to detect whether the current flowing from the power module 1502 to the motor is abnormal. The instruction generation module is used to generate a stop instruction for controlling the power module 1502 to stop supplying driving power when the abnormal current detection module detects the occurrence of abnormal current, so as to stop the drive of the motor. Exemplarily, in the case where the power module 1502 is composed of a PWM-controlled power conversion device, the instruction generation module generates a PWM switching signal as a stop instruction. According to the PWM switching signal generated by the instruction generation module, the switching action of the semiconductor switching element inside the control module 1501 stops.

[0097] In an embodiment of the present application, the power module 1502 includes a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, and a sixth transistor Q6. Of course, the power module shown in the figure is only an exemplary description and should not be used as a limitation on the scope of protection of the present application. The power module 1502 is used to supply driving power to the motor according to the driving instruction sent by the control module 1501. Exemplarily, the power module 1502 controls the internal switching element (i.e., the above-mentioned transistor) to perform switching action through a PWM control signal, converts the input power into the desired power, and outputs the desired power to the motor.

[0098] In the embodiment of the present application, the current detection module 1503 includes a first current detection module R1 and a second current detection module R2. Since it is sufficient to detect the current of at least two phases of the coils of the three-phase AC motor M, only two current detection modules are provided in the embodiment of the present application, thereby saving material costs. In actual applications, technicians in this field can provide any number of current detection modules according to actual needs.

[0099] In the embodiment of the present application, the microprocessor chip includes a microprocessor chip 1 and a microprocessor chip 2, and the microprocessor chip 1 includes a low-pass filter 1 and a low-pass filter 2, and the microprocessor chip 2 includes a low-pass filter 3 and a low-pass filter 4. Among them, the low-pass filter 1 and the low-pass filter 3 are electrically connected to the instruction generation module in the control module 1501, and are used to output digital signals so that the instruction generation module generates drive instructions; the low-pass filter 2 and the low-pass filter 4 are electrically connected to the abnormal current detection module in the control module 1501, and are used to convert the analog current signal output by the current detection module 1503 into a digital form, and output the digital current to the abnormal current detection module, so that the abnormal current detection module detects the occurrence of current anomalies. Of course, the number of low-pass filters in the embodiment of the present application is only an exemplary description. In practical applications, those skilled in the art can set the low-pass filter to any number according to actual needs.

[0100] In order to improve work efficiency, the characteristics of the low-pass filters are respectively set in the embodiment of the present application, so that any one of the characteristics of the resolution and accuracy of the low-pass filter 1 and the low-pass filter 3 is higher than that of the low-pass filter 2 and the low-pass filter 4, but the filtering processing speed of the low-pass filter 2 and the low-pass filter 4 is higher than that of the low-pass filter 2 and the low-pass filter 3. In other words, the analog signal obtained from the current detection module 1503 can obtain a high-resolution and high-precision digital signal through the low-pass filter 1 and the low-pass filter 3, thereby controlling the action of the motor with high precision. At the same time, the occurrence of abnormal current of the motor can be monitored through the low-pass filter 2 and the low-pass filter 4, so as to quickly obtain the abnormal current situation.

[0101] In summary, the motor control circuit provided in the embodiment of the present application can, on the one hand, provide power to the motor, and on the other hand, can timely detect abnormal current conditions, thereby accurately controlling the movement of the motor.

[0102] In the embodiments of the present application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent the existence of A alone, the existence of A and B at the same time, and the existence of B alone. Among them, A and B can be singular or plural. The character " / " generally indicates that the previous and subsequent associated objects are in an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c can be represented by: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0103] Those of ordinary skill in the art will appreciate that the various units and algorithm steps described in the embodiments disclosed herein can be implemented in a combination of electronic hardware, computer software, and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0104] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0105] In several embodiments provided in the present application, if any function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., various media that can store program codes.

[0106] In this specification, the same or similar parts between the various embodiments can be referred to each other. In particular, for the device embodiment and the terminal embodiment, since they are basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the description in the method embodiment.

Claims

1. A modulation circuit, characterized in that: include: A first circuit, wherein the first circuit is used to acquire an analog signal and output a first digital signal; a second circuit, the second circuit being configured to receive the analog signal and output a second digital signal corresponding to the analog signal in a differentiated form; an output circuit, wherein a first input end of the output circuit is electrically connected to an output end of the first circuit, a second input end of the output circuit is electrically connected to an output end of the second circuit, the output circuit is used to receive the first digital signal and the second digital signal, and add the first digital signal and the second digital signal to obtain a third digital signal, wherein the third digital signal is a digital signal corresponding to a current time node; The node between the input end of the first circuit and the input end of the second circuit is the input end of the modulation circuit, and the output end of the output circuit is the output end of the modulation circuit.

2. The modulation circuit according to claim 1, characterized in that: The first circuit comprises: a first adding module, wherein a first input end of the first adding module is an input end of the first circuit, and the first adding module is used to obtain an analog signal, and generate and output a first output signal according to the analog signal and a first negative feedback signal; a first integration module, wherein an input end of the first integration module is electrically connected to an output end of the first addition module, and the first integration module is used to receive the first output signal and output a second output signal; a first quantization module, wherein an input end of the first quantization module is electrically connected to an output end of the first integration module, and the first quantization module is used to receive the second output signal and convert the second output signal into a first digital signal; a first negative feedback module, wherein an input end of the first negative feedback module is electrically connected to an output end of the first quantization module, an output end of the first negative feedback module is electrically connected to a second input end of the first addition module, and the first negative feedback module is used to receive the first digital signal, convert the first digital signal into the first negative feedback signal, and output the first negative feedback signal; The output end of the first quantization module is the output end of the first circuit.

3. The modulation circuit according to claim 2, characterized in that: The first integration module is a second-order integrator.

4. The modulation circuit according to claim 2, characterized in that: The first quantization module includes: an analog comparator, wherein the positive input terminal of the analog comparator is the input terminal of the first quantization module, the negative input terminal of the analog comparator is grounded, and the analog comparator is used to receive the second output signal and convert the second output signal into a first digital signal; A D flip-flop, wherein an input terminal of the D flip-flop is electrically connected to an output terminal of the analog comparator, and the D flip-flop is used to output the first digital signal; Among them, the output end of the D trigger is the output end of the first quantization module.

5. The modulation circuit according to claim 1, characterized in that: The second circuit comprises: A difference calculation module, the input end of the difference calculation module is the input end of the second circuit, and the difference calculation module is used to calculate the difference between the analog signal corresponding to the current time node and the analog signal corresponding to the previous time node, and obtain and output a second output signal; a second adding module, wherein a first input terminal of the second adding module is electrically connected to an output terminal of the difference calculating module, and the second adding module is used to receive the second output signal and the second negative feedback signal, and generate and output a third output signal; a second quantization module, wherein an input end of the second quantization module is electrically connected to an output end of the second addition module, and the second quantization module is used to receive the third output signal and convert the third output signal into a second digital signal; a second negative feedback module, wherein an input end of the second negative feedback module is electrically connected to an output end of the second quantization module, an output end of the second negative feedback module is electrically connected to a second input end of the second addition module, and the second negative feedback module is used to receive the second digital signal, convert the second digital signal into a second negative feedback signal, and output the second negative feedback signal; The output end of the second quantization module is the output end of the second circuit.

6. The modulation circuit according to claim 5, characterized in that: The second circuit further includes: A second integration module, wherein the input end of the second integration module is electrically connected to the output end of the second addition module, the output end of the second integration module is electrically connected to the input end of the second quantization module, and the second integration module is a second-order integrator.

7. The modulation circuit according to claim 5, characterized in that: The difference calculation module comprises: A delay unit, the delay unit is used to receive an analog signal and output a delay signal according to a preset time interval; an adding unit, wherein a first input terminal of the adding unit is electrically connected to an output terminal of the delay unit, and the adding unit is used to obtain the analog signal and the delay signal, and generate and output a second output signal according to the analog signal and the delay signal; The node between the input end of the delay unit and the second input end of the adding unit is the input end of the difference calculation module, and the output end of the adding module is the output end of the difference calculation module.

8. A microprocessor chip, characterized in that: include: The modulation circuit according to any one of claims 1 to 7.

9. The microprocessor chip according to claim 8, characterized in that: The microprocessor chip also includes: a filter, wherein an input end of the filter is electrically connected to an output end of the modulation circuit, and the filter is used to filter the third digital signal output by the modulation circuit and output a fourth digital signal; an amplifier, wherein an input end of the amplifier is electrically connected to an output end of the filter, and the amplifier is used to amplify or reduce the fourth digital signal and output a fifth digital signal; A configurator, wherein the input end of the configurator is used to receive a control signal, the first output end of the configurator is electrically connected to the control end of the filter, the second output end of the configurator is electrically connected to the control end of the gain device, and the configurator is used to control the filter and the gain device according to the received control signal.

10. A motor control circuit, characterized in that: include: A control module, used to obtain a current detection result and generate a driving instruction according to the current detection result; A power module, used to start or stop providing driving power to the motor according to the driving instruction sent by the control module; A current detection module, used to detect the current value output by the power module and output the current value; The microprocessor chip according to claim 8 or 9 is used to output the current detection result according to the current value output by the current detection module.

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