A system and method for delay control in a radio frequency signal sampling conversion optical transmission device

Abstract

The present application relates to the technical field of optical fiber communication, and particularly relates to a delay control system and method for radio frequency signal sampling conversion optical transmission equipment, which comprises a transmitter and a receiver, the transmitter comprises a first switch, an ADC module, a first FPGA module, a first optical module, a first frequency synchronization module, a first wavelength division multiplexer and a first delay measurement module, and the receiver comprises a second wavelength division multiplexer, a second optical module, a second FPGA module, a DAC module, a power divider, a second switch, a synchronization detection module, a second frequency synchronization module and a second delay measurement module; the second FPGA module is used for adjusting the FIFO data storage position of the second FPGA module according to the measured delay value and taking the system delay value set by the receiver as a reference, so that the transmission delay of all channels remains unchanged in relation to the transmitter time, and after the adjustment is completed, the first FPGA module and the second FPGA module control the first switch and the second switch to be connected to the radio frequency input and output and transmit the radio frequency signal.

Description

Technical Field

[0001] The present invention relates to the field of optical fiber communication technology, and in particular to a delay control system and method for optical transmission equipment used for sampling and converting radio frequency signals. Background Art

[0002] Fiber optic transmission can be categorized into two modes: analog transmission and data transmission. The types of signals transmitted in optical fibers differ: analog transmission uses analog modulated optical signals, while data transmission uses optical signals modulated with "0" and "1."

[0003] In analog transmission, the RF signal directly modulates the laser intensity at the transmitter, converting it into an optical signal. This signal is then transmitted via optical fiber to the receiver, where the photodetector converts the input optical signal into an analog electrical output. Signal processing and transmission are both implemented in hardware, with no software involved. Signal transmission delay is determined by the physical properties of the hardware, and the transmission delay stability of analog signals can reach the picosecond level.

[0004] For data transmission, the analog signal is first converted into a digital signal at the transmitter, and then converted into a "0" or "1" data signal. After multiplexing, the optical module converts the analog signal into a data optical signal for transmission. The receiver converts the input data optical signal into a data electrical signal, and restores the analog signal through data demultiplexing and digital / analog conversion.

[0005] Signal transmission undergoes analog-to-digital conversion, data multiplexing / demultiplexing, and digital-to-analog conversion. These processes include digital up / down conversion, interpolation filtering, JESD204B encoding / decoding, time-stamp data insertion, multi-channel high-speed data multiplexing / demultiplexing, and data line encoding / decoding. Without corrective measures, transmission delay stability can be in the tens of nanoseconds, which is insufficient. For example, using Beidou satellite navigation signals for synchronization, transmission delay stability is approximately 3 nanoseconds, equivalent to approximately 1 meter of distance accuracy in a vacuum. However, in applications like positioning, higher precision is crucial. Summary of the Invention

[0006] The purpose of the present invention is to provide a delay control system and method for radio frequency signal sampling and conversion optical transmission equipment, aiming to solve the problem of insufficient transmission delay stability of existing radio frequency signals during data optical transmission.

[0007] To achieve the above objectives, in a first aspect, the present invention provides a delay control system for radio frequency signal sampling and conversion optical transmission equipment, comprising a transmitter and a receiver, wherein the transmitter comprises a first switch, an ADC module, a first FPGA module, a first optical module, a first frequency synthesis synchronization module, a first wavelength division multiplexer, and a first delay measurement module, and the receiver comprises a second wavelength division multiplexer, a second optical module, a second FPGA module, a DAC module, a power splitter, a second switch, a synchronization detection module, a second frequency synthesis synchronization module, and a second delay measurement module;

[0008] The first switch is respectively connected to the first frequency synthesis synchronization module, the ADC module and the first FPGA module, the ADC module is respectively connected to the first FPGA module and the first frequency synthesis synchronization module, the first FPGA module is respectively connected to the first optical module, the first frequency synthesis synchronization module and the first delay measurement module, the first wavelength division multiplexer is respectively connected to the first optical module, the first delay measurement module and the second wavelength division multiplexer, the first frequency synthesis synchronization module and the first delay measurement module are connected, the second wavelength division multiplexer is respectively connected to the second optical module and the second delay measurement module, the second FPGA module is respectively connected to the second optical module, the DAC module, the second switch, the synchronization detection module, the second frequency synthesis synchronization module and the second delay measurement module, the DAC module is respectively connected to the power divider and the second frequency synthesis synchronization module, the power divider is respectively connected to the second switch and the synchronization detection module, and the second frequency synthesis synchronization module is connected to the second delay measurement module.

[0009] In a second aspect, the present invention further provides a method for controlling delay of a radio frequency signal sampling and conversion optical transmission device, which is applied to the delay control system for a radio frequency signal sampling and conversion optical transmission device as described in the first aspect above, comprising the following steps:

[0010] Measure the optical cable transmission time to obtain the optical cable delay;

[0011] Measure transmitter trigger delay time;

[0012] Measure receiver synchronous modulation pulse delay;

[0013] Calculate the delay difference between the trigger delay time and the synchronous modulation pulse delay;

[0014] adjusting a FIFO data storage location based on the delay difference;

[0015] Switching the first switch and the second switch connects the radio frequency input and output to transmit the radio frequency signal.

[0016] The specific method of measuring the optical cable transmission time to obtain the optical cable delay is as follows:

[0017] The external input synchronization signal is shaped and processed by the second FPGA module to obtain a synchronization pulse, and is output to the second delay measurement module;

[0018] The second delay measurement module synchronously multiplexes the synchronization pulses to convert them into optical signals, which are transmitted to the transmitter via the first wavelength division multiplexer, the second wavelength division multiplexer and the optical cable;

[0019] The optical signal is restored to a synchronization pulse by the first delay measurement module and is transmitted back to the receiver. The second delay measurement module calculates the transmission time of the synchronization pulse and the restored synchronization pulse to obtain the optical cable delay.

[0020] The specific method of measuring the synchronous modulation pulse delay of the receiver is as follows:

[0021] The synchronous modulation signal is sampled and processed at high speed by the ADC module, and then transmitted through the first FPGA module, the first optical module, the first wavelength division multiplexer, the second wavelength division multiplexer, the second optical module, and the second FPGA module and processed by the DAC module. The recovered synchronous modulation signal is recovered by the second synchronization detection module to obtain the synchronization pulse, and the second FPGA module calculates the delay time between the synchronization pulse and the synchronization signal.

[0022] The optical cable delay includes the optical cable transmission time and the processing time of the first delay measurement module and the second delay measurement module. The processing time of the first delay measurement module and the second delay measurement module is 200ns, and the optical cable transmission time is 5us / km.

[0023] The present invention is a delay control system for radio frequency signal sampling and conversion optical transmission equipment, wherein the ADCLK of the ADC module is connected to the sampling clock output of the first frequency synthesis synchronization module, CH1 is connected to the external radio frequency input CH1, CH2 is connected to the output of the first switch C, JESD data is connected to the first FPGA module, the CLK4 clock of the first FPGA module is connected to the output of the first frequency synthesis synchronization module, ctrl1 is connected to the control input of the first switch C, GTX1 is connected to the high-speed serial data electrical signal input of the first optical module, JESD is connected to the data output of the ADC module, SYN2R is connected to the output of the first delay measurement module, TRIG1 is connected to the external main trigger input, and TRIG2 is connected to the first The trigger signal input of the delay measurement module and the first frequency synthesis synchronization module, the GTX1 of the first optical module is connected to the high-speed serial data output of the first FPGA module, the optical output is connected to the λ3 and λ4 inputs of the first wavelength division multiplexer, the λ1 and λ2 interfaces of the first wavelength division multiplexer are connected to the optical interface of the first delay measurement module, the λ3 and λ4 interfaces are connected to the optical output of the first optical module, the COM port is connected to the transmission optical cable, the optical interface of the first delay measurement module is connected to the λ1 and λ2 interfaces of the first wavelength division multiplexer, RCLK is connected to the recovered clock input of the first frequency synthesis synchronization module, the SYNA pulse is connected to the output of the first frequency synthesis synchronization module, and the SYN2R synchronization signal is locally looped back and connected to the first FPGA module and the first frequency synthesis synchronization module input, the ADCLK of the first frequency synthesis synchronization module is connected to the ADC module sampling clock input, CLK4 is connected to the first FPGA module clock input, TRIG2 trigger input is connected to the first FPGA trigger output, RCLK is connected to the first delay measurement module recovery clock output, SYN2R is connected to the first delay measurement module output, SYNA synchronous modulation signal output is connected to the first switch B input, SYNA pulse is connected to the delay measurement input, the A interface of the first switch is connected to the external RF input CH2, the B interface is connected to the first frequency synthesis synchronization module SYNA synchronous modulation signal output, the ctrl1 interface is connected to the first FPGA module control output, the first The COM interface of the second wavelength division multiplexer is connected to the transmission optical cable, the λ3 and λ4 interfaces are connected to the optical port of the second optical module, the λ1 and λ2 interfaces are connected to the optical port of the second delay measurement module, the optical port of the second optical module is connected to the λ3 and λ4 interfaces of the wavelength division multiplexer, GTX2 is connected to the high-speed serial data input of the second FPGA module, the CLK3 of the second FPGA module is connected to the clock input and output of the second frequency synthesis synchronization module, ctrl2 is connected to the second switch control input, GTX2 is connected to the electrical signal of the second optical module, JESD is connected to the sampling data input of the DAC module, SYN1 is connected to the external synchronization signal input, SYN2 and SYN2R are connected to the synchronization signal input and output of the second delay measurement module,The SYNAR pulse is connected to the synchronous modulation signal output of the synchronous detection module, TRIG2R is connected to the output of the second delay measurement module, the CH1 of the DAC module is connected to the external user RF signal output, CH2 is connected to the power divider input, DACclk is connected to the second frequency synthesis synchronization module conversion clock output, JESD is connected to the second FPGA module sampling data output, the power divider input is connected to the DAC module CH2 output, and the two outputs are respectively connected to the second switch A input and the synchronous detection module input, the switch input input is connected to the power divider output, the output is connected to the external CH2 RF signal output, ctrl2 is connected to the second FPGA module control output, and the synchronous The input of the step detection module is connected to the output of the power divider, and the output is connected to the SYNAR pulse input of the second FPGA module. The CLK1 of the second frequency synthesis synchronization module is connected to the external reference clock input, CLK2 is connected to the clock input of the second delay measurement module, CLK3 is connected to the clock input and output of the second FPGA module, DACclk is connected to the DAC conversion clock input, CLK2 of the second delay measurement module is connected to the synchronization clock output of the second frequency synthesis synchronization module, SYN2 and SYN2R are connected to the synchronization signal output and input of the second FPGA module, the TRIG2R output is connected to the trigger signal input of the second FPGA module, and the optical interface is connected to the λ1 and λ2 interfaces of the second wavelength division multiplexer;

[0024] The ADC module is a dual-channel TXADC with a resolution of 14 bits, a maximum sampling frequency of 1.25 GHz, an analog input full power bandwidth of 2 GHz, and a JESD204B (subtype) encoded serial digital output. The main chips of the first FPGA module and the second FPGA module are XC7K325T-2FFG900. The first optical module is a dual-light emitting module with a wavelength of DWDM CH32 and CH33 (1551.72 nm, 1550.92 nm), an output optical power of 0 dBm to 2 dBm, a transmission data rate of 10 Gbit / s, and a maximum transmission distance of 100 km. The second optical module is a dual-receiving module with a wavelength of DWDM CH32, CH33 (1551.72nm, 1550.92nm), receiving sensitivity ≤ -24dBm, saturated receiving power ≥ 0dBm, transmission data rate 10Gbit / s, maximum transmission distance 100km, the first wavelength division multiplexer and the second wavelength division multiplexer are 4-channel DWDM wavelength division multiplexers, the wavelengths are CH32\CH33\CH34\CH35, the insertion loss is ≤ 1dB, the first delay measurement module and the second delay measurement module are 16-bit multiplexing / demultiplexing low-jitter transmission delay measurement modules with a measurement accuracy of 200ps, the wavelengths are DWDM CH34 and CH35 (1550.12nm, 1549.32nm), the output optical power is 0dBm to 2dBm, the transmission rate is 1.25Gbit / s, the receiving sensitivity is ≤ -36dBm, the saturated receiving power is ≥ 0dBm, the maximum transmission distance is 120km, the first frequency synthesis synchronization module and the second frequency synthesis synchronization module are ZERO The DELAY phase-locked module has a reference frequency input range of DC to 250 MHz, input levels of CMOS, LVDS, or LVPECL, and output levels of CMOS or LVPECL. The output frequency range is 0 to 2.4 GHz, and there are 12 output channels. The output additive jitter is ≤ 225 fs, and the output delay error between channels is ≤ 16 ps. The DAC module is a dual-channel TxDAC with a resolution of 16 bits and a conversion rate of 1.6 Gbit / s. The digital interpolation filter has no / 2X / 4X / 8X / 16V options, and the inherent delay difference of the TxDAC conversion is ≤ 2 DACCLK cycles, the synchronous detection module is a microwave detector with an input frequency range of 0.01 to 4 GHz, in-band fluctuation ≤±0.3 dB, and low-level sensitivity (at -30 dBm) ≥0.5 mV. The power divider operates in a frequency range of 0 to 6 GHz and has an insertion loss of 3.5 dB. The first and second switches are single-pole double-throw non-reflective microwave switch circuits with an on / off rate of 5 n, an operating frequency of DC to 12 GHz, an insertion loss of 1.4 dB, an isolation of 57 dB, a 1 dB compression point of +30 dBm, and a control interface level of TTL / PLECL;

[0025] The system adjusts the FIFO data storage position of the second FPGA module based on the measured delay value and the system delay value set by the receiver, so that the transmission delay of all channels remains unchanged with the time relationship of the transmitter, that is, after the delay is adjusted, the mutual time relationship of the TRIG signals of each channel remains unchanged with the time relationship of the TRIG signal of the transmitting station. After the adjustment is completed, the first FPGA module and the second FPGA module control the first switch and the second switch to connect the RF input and output to transmit the RF signal. The system uses the synchronous modulation signal sent during the main trigger period to measure and adjust the RF transmission delay, which does not affect the transmission of the echo RF signal, and solves the problem of insufficient transmission delay stability of the existing RF signal during data optical transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0027] Figure 1 The present invention provides a connection diagram of a delay control system for radio frequency signal sampling and conversion optical transmission equipment.

[0028] Figure 2 This is a schematic diagram of the SYNA pulse generation timing.

[0029] Figure 3 This is a schematic diagram of delay measurement and adjustment.

[0030] Figure 4 This is a flow chart of a delay control method for radio frequency signal sampling and conversion optical transmission equipment provided by the present invention.

[0031] Figure 5 This is a diagram of instance delay measurement adjustment.

[0032] In the figure: 1-transmitter, 2-receiver, 3-first switch, 4-ADC module, 5-first FPGA module, 6-first optical module, 7-first frequency synthesis synchronization module, 8-first wavelength division multiplexer, 9-first delay measurement module, 10-second wavelength division multiplexer, 11-second optical module, 12-second FPGA module, 13-DAC module, 14-power divider, 15-second switch, 16-synchronization detection module, 17-second frequency synthesis synchronization module, 18-second delay measurement module. DETAILED DESCRIPTION

[0033] The following describes embodiments of the present invention in detail, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and are not to be construed as limiting the present invention.

[0034] See also Figure 1 In a first aspect, the present invention provides a delay control system for radio frequency signal sampling and conversion optical transmission equipment, comprising a transmitter 1 and a receiver 2. The transmitter 1 comprises a first switch 3 (switch 1), an ADC module 4, a first FPGA module 5 (FPGA module 1), a first optical module 6 (optical module 1), a first frequency synthesis synchronization module 7 (frequency synthesis synchronization module 1), a first wavelength division multiplexer 8 (wavelength division multiplexer 1) and a first delay measurement module 9 (delay measurement module 1). The receiver 2 comprises a second wavelength division multiplexer 10 (wavelength division multiplexer 2), a second optical module 11 (optical module 2), a second FPGA module 12 (FPGA module 2), a DAC module 13, a power divider 14, a second switch 15 (switch 2), a synchronization detection module 16, a second frequency synthesis synchronization module 17 (frequency synthesis synchronization module 2) and a second delay measurement module 18 (delay measurement module 2). The first switch 3 is connected to the first frequency synthesis synchronization module 7, the ADC module 4 and the first FPGA module 5 respectively, and the ADC module 4 is connected to the first FPGA Module 5 is connected to the first frequency synthesis synchronization module 7, the first FPGA module 5 is respectively connected to the first optical module 6, the first frequency synthesis synchronization module 7 and the first delay measurement module 9, the first wavelength division multiplexer 8 is respectively connected to the first optical module 6, the first delay measurement module 9 and the second wavelength division multiplexer 10, the first frequency synthesis synchronization module 7 is connected to the first delay measurement module 9, the second wavelength division multiplexer 10 is respectively connected to the second optical module 11 and the second delay measurement module 18, the second FPGA module 12 is respectively connected to the second optical module 11, the DAC module 13, the second switch 15, the synchronization detection module 16, the second frequency synthesis synchronization module 17 and the second delay measurement module 18, the DAC module 13 is respectively connected to the power divider 14 and the second frequency synthesis synchronization module 17, the power divider 14 is respectively connected to the second switch 15 and the synchronization detection module 16, the second frequency synthesis synchronization module 17 and the second delay measurement module 18 are connected.

[0035] In an embodiment of the present invention, the ADCLK of the ADC module 4 is connected to the sampling clock output of the first frequency synthesis synchronization module 7, CH1 is connected to the external RF input CH1, CH2 is connected to the output of the first switch 3C, the JESD data is connected to the first FPGA module 5, the CLK4 clock of the first FPGA module 5 is connected to the output of the first frequency synthesis synchronization module 7, ctrl1 is connected to the control input of the first switch 3C, GTX1 is connected to the high-speed serial data electrical signal input of the first optical module 6, JESD is connected to the data output of the ADC module 4, SYN2R is connected to the output of the first delay measurement module 9 and the input of the first frequency synthesis synchronization module 7, TRIG1 is connected to the external main trigger input, TRIG2 is connected to the trigger signal input of the first delay measurement module 9 and the first frequency synthesis synchronization module 7, GTX1 of the first optical module 6 is connected to the high-speed serial data output of the first FPGA module 5, the optical output is connected to the λ3 and λ4 inputs of the first wavelength division multiplexer 8, and the λ1 and λ2 interfaces of the first wavelength division multiplexer 8 are connected to the first delay measurement module 9 optical interface, λ3 and λ4 interfaces are connected to the optical output of the first optical module 6, the COM port is connected to the transmission optical cable, the optical interface of the first delay measurement module 9 is connected to the λ1 and λ2 interfaces of the first wavelength division multiplexer 8, RCLK is connected to the first frequency synthesis synchronization module 7 recovery clock input, STNA pulse is connected to the first frequency synthesis synchronization module 7 output, SYN2R synchronization signal is locally looped back and connected to the first FPGA module 5 and the first frequency synthesis synchronization module 7 input, ADCLK of the first frequency synthesis synchronization module 7 is connected to the ADC module 4 sampling clock input, CLK4 is connected to the first FPGA module 5 clock input, TRIG2 trigger input is connected to the first FPGA module 5 trigger output, RCLK is connected to the first delay measurement module 9 recovery clock output, SYN2R is connected to the first delay measurement module 9 output, SYNA synchronization modulation signal output is connected to the first switch 3B input, SYNA pulse is connected to the delay measurement input, the A interface of the first switch 3 is connected to the external RF input CH2, and the B interface is connected to the first frequency synthesis synchronization module 7 SYNAM1 synchronous modulation signal output, ctrl1 interface connected to the first FPGA module 5 control output, the COM interface of the second wavelength division multiplexer 10 is connected to the transmission optical cable, λ3, λ4 interfaces are connected to the optical port of the second optical module 11, λ1, λ2 interfaces are connected to the optical port of the second delay measurement module 18, the optical port of the second optical module 11 is connected to the λ3, λ4 interfaces of the wavelength division multiplexer, GTX2 is connected to the high-speed serial data input of the second FPGA module 12, CLK3 of the second FPGA module 12 is connected to the clock input and output of the second frequency synthesis synchronization module 17, ctrl2 is connected to the control input of the second switch 15, and GTX2 is connected to the electrical signal of the second optical module 11.JESD is connected to the sampling data input of the DAC module 13, SYN1 is connected to the external synchronization signal input, SYN2 and SYN2R are connected to the synchronization signal input and output of the second delay measurement module 18, SYNAR pulse is connected to the synchronization modulation signal output of the synchronization detection module 16, TRIG2R is connected to the output of the second delay measurement module 18, CH1 of the DAC module 13 is connected to the external user RF signal output, CH2 is connected to the input of the power divider 14, DACclk is connected to the conversion clock output of the second frequency synthesis synchronization module 17, JESD is connected to the sampling data output of the second FPGA module 12, the input of the power divider 14 is connected to the CH2 output of the DAC module 13, and the two outputs are respectively connected to the second switch 15 A input and the input of the synchronization detection module 16, the input of the switch input is connected to the output of the power divider 14, the output is connected to the external CH2 RF signal output, ctrl2 is connected to the control output of the second FPGA module 12, the input of the synchronization detection module 16 is connected to the output of the power divider 14, the output is connected to the SYNAR pulse input of the second FPGA module 13, CLK1 of the second frequency synthesis synchronization module 17 is connected to the external reference clock input, CLK2 is connected to the clock input of the second delay measurement module 18, CLK3 is connected to the clock input and output of the second FPGA module 12, DACclk is connected to the DAC conversion clock input, CLK2 of the second delay measurement module 18 is connected to the synchronization clock output of the second frequency synthesis synchronization module 17, SYN2 and SYN2RR are connected to the synchronization signal output and input of the second FPGA module, TRIG2R output is connected to the trigger signal input of the second FPGA module 12, and the optical interface is connected to the λ1 and λ2 interfaces of the second wavelength division multiplexer 10;

[0036] The ADC module 4 is a dual-channel TXADC with a resolution of 14 bits, a maximum sampling frequency of 1.25 GHz, an analog input full power bandwidth of 2 GHz, and a JESD204B (subtype) encoded serial digital output. The main chips of the first FPGA module 5 and the second FPGA module 12 are XC7K325T-2FFG900. The first optical module 6 is a dual-light emitting module with a wavelength of DWDM CH32 and CH33 (1551.72 nm, 1550.92 nm), an output optical power of 0 dBm to 2 dBm, a transmission data rate of 10 Gbit / s, and a maximum transmission distance of 100 km. The second optical module 11 is a dual-receiving module with a wavelength of DWDM CH32, CH33 (1551.72nm, 1550.92nm), receiving sensitivity ≤ -24dBm, saturated receiving power ≥ 0dBm, transmission data rate 10Gbit / s, maximum transmission distance 100km, the first wavelength division multiplexer 8 and the second wavelength division multiplexer 10 are 4-channel DWDM wavelength division multiplexers, the wavelengths are CH32\CH33\CH34\CH35, the insertion loss ≤ 1dB, the first delay measurement module 9 and the second delay measurement module Block 18 is a 16-bit multiplexing / demultiplexing low jitter transmission delay measurement module with a measurement accuracy of 200ps. The wavelength is CH34 and CH35 of DWDM (1550.12nm and 1549.32nm). The output optical power is 0dBm to 2dBm, the transmission rate is 1.25Gbit / s, the receiving sensitivity is ≤-36dBm, the saturated receiving power is ≥0dBm, and the maximum transmission distance is 120km. The first frequency synthesis synchronization module 7 and the second frequency synthesis synchronization module 17 are ZERO. The DELAY phase-locked module has a reference frequency input range of DC to 250 MHz, an input level of CMOS, LVDS or LVPECL, an output level of CMOS or LVPECL, an output frequency range of 0 to 2.4 GHz, 12 output channels, an output additive jitter of ≤ 225 fs, and an output delay error between channels of ≤ 16 ps. The DAC module 13 is a dual-channel TxDAC with a resolution of 16 bits and a conversion rate of 1.6 Gbit / s. The digital interpolation filter has none / 2X / 4X / 8X / 16 V is optional, the inherent delay difference of TxDAC conversion is ≤ 2 DACCLK cycles, the synchronous detection module 16 is a microwave detector with an input frequency range of 0.01 to 4 GHz, in-band fluctuation ≤ ±0.3 dB, and low-level sensitivity (at -30 dBm) ≥ 0.5 mV. The power divider 14 operates in a frequency range of 0 to 6 GHz and has an insertion loss of 3.5 dB. The first switch 3 and the second switch 15 are single-pole double-throw non-reflective microwave switch circuits with an on / off rate of 5 n, an operating frequency of DC to 12 GHz, and an insertion loss of 1.4dB, isolation 57dB, 1dB compression point +30dBm, control interface level TTL / PLECL;.

[0037] The system adjusts the FIFO data storage position of the second FPGA module 13 based on the measured delay value and the system delay value set by the receiver 2, so that the transmission delay of all channels remains unchanged with the time relationship of the transmitter 1, that is, after the delay is adjusted, the mutual time relationship of the TRIG signals of each channel remains unchanged with the time relationship of the TRIG signal of the transmitting station. After the adjustment is completed, the first FPGA module 5 and the second FPGA module 13 control the first switch 3 and the second switch 15 to connect the RF input and output to transmit the RF signal. The system uses the synchronous modulation signal sent during the main trigger period to measure and adjust the RF transmission delay, which does not affect the transmission of the echo RF signal, and solves the problem of insufficient transmission delay stability of the existing RF signal during data optical transmission.

[0038] See also Figure 2-Figure 4 In a second aspect, the present invention further provides a method for controlling delay of a radio frequency signal sampling and conversion optical transmission device, which is applied to the delay control system for a radio frequency signal sampling and conversion optical transmission device as described in the first aspect above, comprising the following steps:

[0039] S1 measures the optical cable transmission time and obtains the optical cable delay;

[0040] In the embodiment of the present invention, when the power is turned on, the second frequency synthesis synchronization module 17 of the receiver 2 synchronizes the external input 10MH reference clock with zero delay phase lock, generates the CLK2 (40MHz), CLK3 (250MHz) and DACCLK conversion clock (1GHz) required by the second delay measurement module 18, the second FPGA module 13 and the DAC module 13, and the external input synchronization signal SYN1 is shaped by the second FPGA module 13 to obtain the SYN2 synchronization pulse output to the second delay measurement module 18, and the second delay measurement module 18 performs synchronization. The optical signal is multiplexed and then converted into an optical signal, which is transmitted to the transmitter 1 through the first wavelength division multiplexer 8, the second wavelength division multiplexer 10 and the optical cable. The transmitter 1 receives the optical signal and recovers the synchronization pulse SYN2R through the optical / electrical conversion inside the first delay measurement module 9. SYN2R is locally looped back and transmitted back to the receiver 2. The second delay measurement module 18 calculates the transmission time of SYN2 and SYN2R. Since the circuits and transmission optical cables of the two delay measurement modules are the same, the time required for transmission in both directions is the same. Therefore, the round-trip transmission time (SYN2R-SYN2) divided by 2 is the one-way optical cable transmission time t 光缆 Then the second delay measurement module 18 sets t 光缆are transmitted to the receiver 2 and the transmitter 1 respectively. 光缆 Including the optical cable transmission time and the processing time of the second delay measurement module 18 and the first delay measurement module 9, the processing time of the second delay measurement module 18 and the first delay measurement module 9 is about 200ns, and the optical cable transmission time is about 5us / km. After the optical cable of the transmitter 1 and the receiver 2 is laid, t 光缆 The delay of the optical cable transmission is relatively unchanged. Ambient temperature changes have a slight impact on the transmission delay of the optical cable. The impact of G.652 optical fiber is about 30ps to 50ps / km.°C. The SYN2R signal of the first delay measurement module 9 is also sent to the first FPGA module 5 and the first frequency synthesizer synchronization module 7 for signal synchronization.

[0041] The clock recovered by the first delay measurement module 9 is de-jittered, phase-locked, and divided before outputting a 10 MHz low-jitter clock (RCLK) to the first frequency synthesizer synchronization module 7. This generates the 250 MHz clock CLK4 for the first FPGA module 5 and the 1 GHz sampling clock ADCCLK for the ADC module 4. The clocks used by each module in the transmitter 1 and receiver 2 are all derived from the same source clock, CLK1.

[0042] Specific method:

[0043] S11: The external input synchronization signal is shaped and processed by the second FPGA module 13 to obtain a synchronization pulse, which is then output to the second delay measurement module 18;

[0044] S12: the second delay measurement module 18 synchronously multiplexes the synchronization pulses to convert them into optical signals, which are transmitted to the transmitter 1 via the first wavelength division multiplexer 8, the second wavelength division multiplexer 10 and the optical cable;

[0045] S13: The optical signal is restored to a synchronization pulse by the first delay measurement module 9 and transmitted back to the receiver 2. The second delay measurement module calculates the transmission time of the synchronization pulse and the restored synchronization pulse to obtain the optical cable delay.

[0046] S2 measures the trigger delay time of transmitter 1;

[0047] In the embodiment of the present invention, the TRIG1 trigger delay time (denoted as t TRIG) The delay time of the rising edge of the first TRIG1 pulse based on the rising edge of SYN2R. After being shaped by the first FPGA module 5, TRIG1 is converted into TRIG2 and is also transmitted to the receiver 2 through the first delay measurement module 9. The first FPGA module 5 generates a ctrl1 control signal based on the rising edge of the first pulse of TRIG1 to control the first switch 3B interface to connect to the synchronous modulation signal. The time for the ctrl1 control signal to open the first switch 3B interface should be slightly longer than the duration of the SYNA synchronous modulation signal to ensure that the synchronous modulation signal can pass through completely. Figure 2 shown.

[0048] S3 measures the synchronous modulation pulse delay of receiver 2;

[0049] In an embodiment of the present invention, the SYNA synchronous modulation signal is sampled and processed at high speed by the ADC module 4, transmitted through the first FPGA module 5, the first optical module 6, the first wavelength division multiplexer 8, the second wavelength division multiplexer 10, the second optical module 12, and the second FPGA module 13, and processed by the DAC module 13. The recovered synchronous modulation signal is recovered by the synchronous detection module 16 to obtain a SYNAR synchronization pulse.

[0050] S4 calculates the delay difference between the trigger delay time and the synchronous modulation pulse delay;

[0051] In the embodiment of the present invention, the second FPGA module 12 calculates the delay time between the SYNAR pulse and SYN1, which is subtracted from t 光缆 That is, the time t taken for the RF input of the transmitter 1 to be transmitted to the receiver 2 through the RF transmission channel error .

[0052] S5 adjusts the FIFO data storage location based on the delay difference;

[0053] In the embodiment of the present invention, since the transmission delay of the signal processing transmission link from the ADC module 4 to the DAC module 13 changes each time the device is turned on and off, the delay time between the SYNAR pulse and SYN1 changes each time the device is turned on and off. The second FPGA module 12 needs to adjust the FIFO data storage position of the second FPGA module 12 based on the measured delay value and the system delay value set by the receiver 2 (denoted as t1) so that the transmission delay of all channels remains unchanged with the time relationship of the transmitter 1, that is, after the delay is adjusted, the mutual time relationship of the TRIG signals of each channel (station) remains unchanged with the time relationship of the TRIG signal of the transmitting station, such as Figure 3 shown.

[0054] S6 switches the first switch 3 and the second switch 15 to connect the RF input and output to transmit the RF signal.

[0055] In order to better understand the present technical solution, the following examples are provided for further explanation:

[0056] Assume that the optical cable transmission distances from the receiver 2 to the transmitter 1A and the transmitter 1B are 80 km and 90 km respectively, the optical fiber transmission delay is calculated as 5 us / km, the processing time of the first delay measurement module 9 and the second delay measurement module 18 is 0.2 us, the time required for the synchronization signal SYN2 to be transmitted from the receiver 2 to the transmitting station is 400.2 us and 450.2 us respectively, and the delay time t between the trigger TRIG input from the transmitter 1A and SYN2 is TRIGa The delay time t between the trigger TRIG and SYN2 of the external input of the transmitter 1B is 10us. TRIGb Assuming that the time it takes for the synchronous SYNA modulation signal generated by the trigger TRIG signal to be transmitted from the transmitter 1 to the receiver 2 via the RF transmission channel and detected by SYN1 is 840.2us and 940.2us respectively, and the system delay value is set to 800us, the FIFO adjustment time should be 800us-840.2us+400.2us+t TRIGa =370us and 800us - 940.2us + 450.2us + t TRIGb =340us. Figure 5 As shown. At the transmitter t TRIG1A and t TRIG1B The time difference is 70us. After being transmitted to the receiver 2 and before adjustment, the time difference is 98us. After FIFO adjustment, the time difference is 70us, which is the same time relationship as the transmitting end.

[0057] The above disclosure is merely a preferred embodiment of a delay control system and method for radio frequency signal sampling and conversion optical transmission equipment of the present invention. It is certainly not intended to limit the scope of the rights of the present invention. A person skilled in the art will understand that implementing all or part of the processes of the above embodiment and making equivalent changes in accordance with the claims of the present invention still fall within the scope of the invention.

Claims

1. A delay control system for radio frequency signal sampling and conversion optical transmission equipment, characterized in that ； The transmitter comprises a first switch, an ADC module, a first FPGA module, a first optical module, a first frequency synthesis synchronization module, a first wavelength division multiplexer, and a first delay measurement module; the receiver comprises a second wavelength division multiplexer, a second optical module, a second FPGA module, a DAC module, a power splitter, a second switch, a synchronization detection module, a second frequency synthesis synchronization module, and a second delay measurement module; The first switch is respectively connected to the first frequency synthesis synchronization module, the ADC module and the first FPGA module, the ADC module is respectively connected to the first FPGA module and the first frequency synthesis synchronization module, the first FPGA module is respectively connected to the first optical module, the first frequency synthesis synchronization module and the first delay measurement module, the first wavelength division multiplexer is respectively connected to the first optical module, the first delay measurement module and the second wavelength division multiplexer, the first frequency synthesis synchronization module and the first delay measurement module are connected, the second wavelength division multiplexer is respectively connected to the second optical module and the second delay measurement module, the second FPGA module is respectively connected to the second optical module, the DAC module, the second switch, the synchronization detection module, the second frequency synthesis synchronization module and the second delay measurement module, the DAC module is respectively connected to the power splitter and the second frequency synthesis synchronization module, the power splitter is respectively connected to the second switch and the synchronization detection module, and the second frequency synthesis synchronization module is connected to the second delay measurement module; The ADCLK of the ADC module is connected to the sampling clock output of the first frequency synthesis synchronization module, CH1 is connected to the external RF input CH1, CH2 is connected to the output of the first switch C, JESD data is connected to the first FPGA module, the CLK4 clock of the first FPGA module is connected to the output of the first frequency synthesis synchronization module, ctrl1 is connected to the control input of the first switch C, GTX1 is connected to the high-speed serial data electrical signal input of the first optical module, JESD is connected to the data output of the ADC module, SYN2R is connected to the output of the first delay measurement module, TRIG1 is connected to the external main trigger input, TRIG2 is connected to the trigger signal input of the first delay measurement module and the first frequency synthesis synchronization module, and the first The GTX1 of an optical module is connected to the high-speed serial data output of the first FPGA module, the optical output is connected to the λ3 and λ4 inputs of the first wavelength division multiplexer, the λ1 and λ2 interfaces of the first wavelength division multiplexer are connected to the optical interface of the first delay measurement module, the λ3 and λ4 interfaces are connected to the optical output of the first optical module, the COM port is connected to the transmission optical cable, the optical interface of the first delay measurement module is connected to the λ1 and λ2 interfaces of the first wavelength division multiplexer, RCLK is connected to the recovered clock input of the first frequency synthesis synchronization module, the SYNA pulse is connected to the output of the first frequency synthesis synchronization module, the SYN2R synchronization signal is locally looped back and connected to the first FPGA module and the first frequency synthesis synchronization module input, the ADC of the first frequency synthesis synchronization module LK is connected to the sampling clock input of the ADC module, CLK4 is connected to the clock input of the first FPGA module, TRIG2 trigger input is connected to the trigger output of the first FPGA, RCLK is connected to the recovered clock output of the first delay measurement module, SYN2R is connected to the output of the first delay measurement module, SYNA synchronous modulation signal output is connected to the B input of the first switch, SYNA pulse is connected to the delay measurement input, the A interface of the first switch is connected to the external RF input CH2, the B interface is connected to the SYNA synchronous modulation signal output of the first frequency synthesis synchronization module, the ctrl1 interface is connected to the control output of the first FPGA module, the COM interface of the second wavelength division multiplexer is connected to the transmission optical cable, and the λ3 and λ4 interfaces are connected Connect to the optical port of the second optical module, λ1 and λ2 interfaces are connected to the optical port of the second delay measurement module, the optical port of the second optical module is connected to the λ3 and λ4 interfaces of the wavelength division multiplexer, GTX2 is connected to the high-speed serial data input of the second FPGA module, CLK3 of the second FPGA module is connected to the clock input and output of the second frequency synthesis synchronization module, ctrl2 is connected to the second switch control input, GTX2 is connected to the interface of the second optical module electrical signal, JESD is connected to the DAC module sampling data input, SYN1 is connected to the external synchronization signal input, SYN2 and SYN2R are connected to the synchronization signal input and output of the second delay measurement module, and SYNAR pulse is connected to the synchronization modulation signal output of the synchronization detection module.TRIG2R is connected to the output of the second delay measurement module, CH1 of the DAC module is connected to the external user RF signal output, CH2 is connected to the power divider input, DACclk is connected to the conversion clock output of the second frequency synthesis synchronization module, JESD is connected to the sampling data output of the second FPGA module, the input of the power divider is connected to the CH2 output of the DAC module, and the two outputs are respectively connected to the second switch A input and the synchronous detection module input, the input of the switch input is connected to the power divider output, and the output is connected to the external CH2 RF signal output, ctrl2 is connected to the second FPGA module control output, and the input of the synchronous detection module is connected to the power divider output. The output of the splitter is connected to the SYNAR pulse input of the second FPGA module. The CLK1 of the second frequency synthesis synchronization module is connected to the external reference clock input. CLK2 is connected to the clock input of the second delay measurement module. CLK3 is connected to the clock input and output of the second FPGA module. DACclk is connected to the DAC conversion clock input. CLK2 of the second delay measurement module is connected to the synchronization clock output of the second frequency synthesis synchronization module. SYN2 and SYN2R are connected to the synchronization signal output and input of the second FPGA module. The TRIG2R output is connected to the trigger signal input of the second FPGA module. The optical interface is connected to the λ1 and λ2 interfaces of the second wavelength division multiplexer.

2. A method for controlling the delay of radio frequency signal sampling and conversion optical transmission equipment, applied to the delay control system for radio frequency signal sampling and conversion optical transmission equipment according to claim 1, characterized in that: The following steps are included: Measure the optical cable transmission time to obtain the optical cable delay; Measure transmitter trigger delay time; Measure receiver synchronous modulation pulse delay; Calculate the delay difference between the trigger delay time and the synchronous modulation pulse delay; adjusting a FIFO data storage location based on the delay difference; Switching the first switch and the second switch connects the radio frequency input and output to transmit the radio frequency signal.

3. The delay control method for radio frequency signal sampling and conversion optical transmission equipment according to claim 2, characterized in that ； The specific method of measuring the optical cable transmission time and obtaining the optical cable delay is as follows: The external input synchronization signal is shaped and processed by the second FPGA module to obtain a synchronization pulse, and is output to the second delay measurement module; The second delay measurement module synchronously multiplexes the synchronization pulses to convert them into optical signals, which are transmitted to the transmitter via the first wavelength division multiplexer, the second wavelength division multiplexer and the optical cable; The optical signal is restored to a synchronization pulse by the first delay measurement module and is transmitted back to the receiver. The second delay measurement module calculates the transmission time of the synchronization pulse and the restored synchronization pulse to obtain the optical cable delay.

4. The method for delay control of radio frequency signal sampling and conversion optical transmission equipment according to claim 2, characterized in that ； The specific method of measuring the synchronous modulation pulse delay of the receiver is as follows: The synchronous modulation signal is sampled and processed at high speed by the ADC module, and then transmitted through the first FPGA module, the first optical module, the first wavelength division multiplexer, the second wavelength division multiplexer, the second optical module, and the second FPGA module and processed by the DAC module. The recovered synchronous modulation signal is recovered by the second synchronization detection module to obtain the synchronization pulse, and the second FPGA module calculates the delay time between the synchronization pulse and the synchronization signal.

5. The delay control method for radio frequency signal sampling and conversion optical transmission equipment according to claim 2, characterized in that ； The optical cable delay includes the optical cable transmission time and the processing time of the first delay measurement module and the second delay measurement module. The processing time of the first delay measurement module and the second delay measurement module is 200ns, and the optical cable transmission time is 5us / km.

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