On-chip virtual network analyzer, method, computer device and medium

Abstract

The present application relates to the field of signal processing technology and provides an on-chip virtual network analyzer, method, computer device and medium. The on-chip virtual network analyzer establishes a loss model of the first channel in a training mode, and uses the loss model of the first channel in a working mode to adjust the adjustable equalization gain based on the frequency of the input signal and the waveform peak of the output signal detected by the peak detector, so that the amplitude of the output signal is consistent with the amplitude of the input signal, and realizes accurate and reliable judgment on how to perform channel loss compensation and how to amplify or attenuate the signal to adapt to the needs of the lower-level module, which is conducive to improving the overall performance of the system.

Description

Technical Field

[0001] The present application relates to the field of signal processing technology, and in particular to an on-chip virtual network analyzer, method, computer device and medium. Background Art

[0002] In applications such as data centers, high-performance computers, and high-speed digital communications, data transmission and data processing between different nodes and machines are involved, such as analog-to-digital conversion and digital-to-analog conversion. Therefore, it may be necessary to frequently amplify or attenuate the signal to match the differences between the front-end and rear-end circuits. For example, a variable gain amplifier (VGA) or its subcategory programmable gain amplifier (PGA) is deployed on the lower module of the digital to analog converter to adjust the voltage level of the voltage signal within the dynamic signal range, thereby amplifying or attenuating the signal. However, the prior art scheme of relying on VGA and PGA to amplify or attenuate the signal does not fully consider the differences between different channels in a multi-channel scenario, and generally applies modulation according to a preset gain, such as the same gain. However, in applications such as data centers and high-performance servers, the data channel used to transmit the signal, such as the connecting line between two servers, is fixed after the installation is completed, so it is difficult to directly inspect it by disassembly after installation. During use, these channels are affected by the aging and loss of their respective devices, resulting in greater differences in the channel loss performance of these channels, and greater deviations from the conditions during installation. Therefore, if channel loss compensation is continued for these channels according to the preset gain, it may lead to inconsistent signal amplitudes at the receiving end, which is not conducive to improving the overall system performance.

[0003] To this end, the present application provides an on-chip virtual network analyzer, method, computer device and medium for addressing the technical difficulties in the prior art. Summary of the invention

[0004] In a first aspect, the present application provides an on-chip virtual network analyzer. The on-chip virtual network analyzer includes: an equalizer, which is deployed at the receiving end of a first channel, and is used to modulate an intermediate signal according to an adjustable equalization gain to obtain an output signal, wherein the intermediate signal is obtained by transmitting an input signal through the first channel; and a peak detector, which is deployed at the receiving end, and is used to detect the waveform peak of the output signal. The on-chip virtual network analyzer is used to establish a loss model of the first channel in a training mode, wherein the loss model of the first channel indicates the loss of multiple signals of different frequencies with fixed amplitudes passing through the first channel respectively, and the equalizer does not perform modulation in the training mode. The on-chip virtual network analyzer is used to adjust the adjustable equalization gain in an operating mode based on the frequency of the input signal and the waveform peak of the output signal detected by the peak detector using the loss model of the first channel, so that the amplitude of the output signal is consistent with the amplitude of the input signal.

[0005] Through the first aspect of the present application, the on-chip virtual network analyzer establishes a loss model of the first channel in a training mode, and uses the loss model of the first channel in a working mode to adjust the adjustable equalization gain based on the frequency of the input signal and the waveform peak of the output signal detected by the peak detector, so that the amplitude of the output signal is consistent with the amplitude of the input signal; not only the channel attenuation performance brought by the first channel is taken into account, but also the influence caused by the devices and circuits of the equalizer itself is taken into account; in the working mode, by using the collaboration of the equalizer and the peak detector, the loss model of the first channel can be used to determine the scanning result corresponding to the frequency of the current input signal, thereby determining the channel loss performance of the first channel at a specific frequency point corresponding to the frequency of the input signal, and then combining the difference between the amplitude of the output signal and the amplitude of the input signal, improve the negative feedback control, determine how to adjust the adjustable equalization gain, and finally achieve the purpose of system stability, that is, to make the amplitude of the output signal consistent with the amplitude of the input signal; it is realized that how to perform channel loss compensation and how to amplify or attenuate the signal to adapt to the needs of the lower-level module are accurately and reliably judged, which is conducive to improving the overall performance of the system.

[0006] In a possible implementation manner of the first aspect of the present application, the equalizer modulates the intermediate signal according to the adjusted adjustable equalization gain in the working mode to obtain the output signal.

[0007] In a possible implementation manner of the first aspect of the present application, the adjustable equalization gain is fixed to 1.0 in the training mode.

[0008] In a possible implementation manner of the first aspect of the present application, the loss model of the first channel indicates the amplitudes of intermediate signals respectively obtained when a plurality of signals having the same fixed amplitude and different frequencies are transmitted through the first channel.

[0009] In a possible implementation of the first aspect of the present application, the peak detector is used to provide a frequency scanning function in the training mode to determine the S21 parameter of the system including the first channel and the on-chip virtual network analyzer, and the S21 parameter is a curve of gain change relative to bandwidth.

[0010] In a possible implementation manner of the first aspect of the present application, the equalizer and the peak detector together form a negative feedback loop in the working mode to provide a swing control function.

[0011] In a possible implementation of the first aspect of the present application, the input signal and the output signal are both electrical signals, and an on-chip oscilloscope is deployed at the receiving end to perform waveform analysis on the output signal to obtain a waveform analysis result, which is used to improve the performance of the on-chip virtual network analyzer.

[0012] In a possible implementation of the first aspect of the present application, the input signal and the output signal are both optical pulse signals, a photodiode and an on-chip oscilloscope are deployed at the receiving end, the photodiode is used to convert the output signal into an electrical signal corresponding to the output signal, and the on-chip oscilloscope is used to perform waveform analysis on the electrical signal corresponding to the output signal to obtain a waveform analysis result, and the waveform analysis result is used to improve the performance of the on-chip virtual network analyzer.

[0013] In a possible implementation of the first aspect of the present application, the first channel belongs to multiple channels, and the on-chip virtual network analyzer is deployed at the receiving end of each of the multiple channels, and the on-chip virtual network analyzers corresponding to each of the multiple channels are used to establish loss models of each of the multiple channels in the training mode, and to adjust the adjustable equalization gain of the equalizer in the on-chip virtual network analyzer corresponding to each of the multiple channels using the loss models of each of the multiple channels in the working mode.

[0014] In a possible implementation of the first aspect of the present application, the multiple channels correspond to multiple connecting lines on the same panel, and the round-trip loss of each of the multiple connecting lines is determined based on the position of each of the multiple connecting lines on the panel and the length of each of the multiple connecting lines.

[0015] In a second aspect, the present application provides a method for on-chip virtual network analysis. The method includes: providing an equalizer of an on-chip virtual network analyzer, wherein the equalizer is deployed at the receiving end of a first channel, and the equalizer is used to modulate an intermediate signal according to an adjustable equalization gain to obtain an output signal, wherein the intermediate signal is obtained by transmitting an input signal through the first channel; and providing a peak detector of the on-chip virtual network analyzer, wherein the peak detector is deployed at the receiving end, and the peak detector is used to detect the waveform peak of the output signal. The on-chip virtual network analyzer is used to establish a loss model of the first channel in a training mode, and the loss model of the first channel indicates the loss of multiple signals of different frequencies with fixed amplitudes passing through the first channel respectively, and the equalizer is not modulated in the training mode. The on-chip virtual network analyzer is used to adjust the adjustable equalization gain in an operating mode based on the frequency of the input signal and the waveform peak of the output signal detected by the peak detector, so that the amplitude of the output signal is consistent with the amplitude of the input signal.

[0016] According to the second aspect of the present application, the on-chip virtual network analyzer establishes a loss model of the first channel in the training mode, and uses the loss model of the first channel in the working mode to adjust the adjustable equalization gain based on the frequency of the input signal and the waveform peak of the output signal detected by the peak detector, so that the amplitude of the output signal is consistent with the amplitude of the input signal; not only the channel attenuation performance brought by the first channel is taken into account, but also the influence caused by the devices and circuits of the equalizer itself is taken into account; in the working mode, by using the collaboration of the equalizer and the peak detector, the loss model of the first channel can be used to determine the scanning result corresponding to the frequency of the current input signal, thereby determining the channel loss performance of the first channel at a specific frequency point corresponding to the frequency of the input signal, and then combining the difference between the amplitude of the output signal and the amplitude of the input signal, improve the negative feedback control, determine how to adjust the adjustable equalization gain, and finally achieve the purpose of system stability, that is, to make the amplitude of the output signal consistent with the amplitude of the input signal; it is realized that how to perform channel loss compensation and how to amplify or attenuate the signal to adapt to the needs of the lower-level module are accurately and reliably judged, which is conducive to improving the overall performance of the system.

[0017] In a possible implementation manner of the second aspect of the present application, the loss model of the first channel indicates the amplitudes of intermediate signals respectively obtained when a plurality of signals having the same fixed amplitude and different frequencies are transmitted through the first channel.

[0018] In a possible implementation of the second aspect of the present application, the peak detector is used in the training mode to provide a frequency scanning function so as to determine the S21 parameter of the system including the first channel and the on-chip virtual network analyzer, wherein the S21 parameter is a curve of gain variation relative to bandwidth.

[0019] In a possible implementation manner of the second aspect of the present application, the equalizer and the peak detector together form a negative feedback loop in the working mode to provide a swing control function.

[0020] In a possible implementation of the second aspect of the present application, the first channel belongs to multiple channels, and the on-chip virtual network analyzer is deployed at the receiving end of each of the multiple channels, and the on-chip virtual network analyzers corresponding to each of the multiple channels are used to establish loss models of each of the multiple channels in the training mode, and to adjust the adjustable equalization gain of the equalizer in the on-chip virtual network analyzer corresponding to each of the multiple channels using the loss models of each of the multiple channels in the working mode.

[0021] In a third aspect, an embodiment of the present application further provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements a method according to any one of the implementation modes of any of the above aspects when executing the computer program.

[0022] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, which, when executed on a computer device, enable the computer device to execute a method according to any one of the implementation modes of any of the above aspects.

[0023] In a fifth aspect, an embodiment of the present application further provides a computer program product, which includes instructions stored on a computer-readable storage medium, and when the instructions are executed on a computer device, the computer device executes a method according to any one of the implementation methods of any of the above aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1 A schematic diagram of a multi-channel application scenario;

[0026] Figure 2 A schematic diagram of an on-chip virtual network analyzer provided in an embodiment of the present application;

[0027] Figure 3 A flowchart of a method for on-chip virtual network analysis provided in an embodiment of the present application;

[0028] Figure 4 A schematic diagram of a panel with multiple connection line interfaces provided in an embodiment of the present application;

[0029] Figure 5 A schematic diagram of the structure of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] The embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0031] It should be understood that, in the description of this application, "at least one" means one or more, and "a plurality of" means two or more. In addition, unless otherwise specified, the words "first", "second", etc. are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order.

[0032] Figure 1 is a schematic diagram of a multi-channel application scenario. Figure 1 As shown, multiple transmitters send to multiple receivers through multiple channels. Among them, transmitter A101 sends to receiver A103 through channel A102, transmitter B111 sends to receiver B113 through channel B112, and transmitter C121 sends to receiver C123 through channel C122. In applications such as data centers, high-performance computers, and high-speed digital communications, data transmission and data processing between different nodes and machines are involved, such as analog-to-digital conversion and digital-to-analog conversion. Therefore, it may be necessary to frequently amplify or attenuate the signal to match the differences between the previous and next stage circuits. For example, a variable gain amplifier (VGA) or its subcategory programmable gain amplifier (PGA) is deployed on the lower-level module of the digital to analog converter to adjust the voltage level of the voltage signal within the dynamic signal range, thereby amplifying or attenuating the signal. With Figure 1Taking the multi-channel application scenario shown as an example, in a multi-channel scenario, there may be differences in channel loss between different channels, and signals of the same frequency may have different degrees of loss after passing through different channels. For example, a signal with an amplitude of 1 volt and a frequency of 1 Giga Hertz (GHz) may be a signal with an amplitude of 0.8 volts after passing through channel A102, and may be a signal with an amplitude of 0.5 volts after passing through channel B112. In order to compensate for channel loss compensation and to meet the adaptation between the front and rear circuits, the signal transmitted through the channel is generally amplified or attenuated. However, if multiple channels are modulated according to a preset gain, as these channels are used during use due to the aging, loss, etc. of their respective devices, the difference in channel loss performance may cause the preset gain to be unable to cope with the current state of each channel. For example, there may be a large difference in channel loss performance between channel A102 and channel B112, and there may be a large change compared to the situation at the time of installation. On the other hand, in applications such as data centers and high-performance servers, the data channel used to transmit signals, such as the connecting line between two servers, is fixed after installation, so it is difficult to directly check by disassembly after installation. To this end, when sending signals through multiple channels, for example, sending signals to receiving terminal A103 through transmitting terminal A101 and sending signals to receiving terminal C123 through transmitting terminal C121, it is necessary to consider the current status of channel A102 and channel C122, including the channel loss performance of these channels at the frequency of the input signal, so as to accurately and reliably determine how to perform channel loss compensation and how to amplify or attenuate the signal to adapt to the needs of the lower-level modules. The following is a detailed description of how to achieve these technical effects in an on-chip virtual network analyzer, method, computer device and medium provided by the present application in conjunction with the drawings and specific embodiments of the present application.

[0033] Figure 2 A schematic diagram of an on-chip virtual network analyzer provided in an embodiment of the present application. Figure 2As shown, the transmitting end D201 sends a signal to the receiving end D203 through the first channel D202. The on-chip virtual network analyzer (On-chip Virtual Network Analyzer, On-chip VNA) 200 is deployed at the receiving end D203. The on-chip virtual network analyzer 200 includes: an equalizer (Equalizer, EQ) 210, which is deployed at the receiving end D203 of the first channel D202, and is used to modulate the intermediate signal according to the adjustable equalization gain to obtain an output signal, wherein the intermediate signal is obtained by transmitting the input signal through the first channel D202; and a peak detector (Peak Detector, PD) 212, which is deployed at the receiving end D203, and is used to detect the waveform peak of the output signal. The on-chip virtual network analyzer 200 is used to establish a loss model of the first channel D202 in a training mode, wherein the loss model of the first channel D202 indicates the losses of a plurality of signals of different frequencies with fixed amplitudes passing through the first channel D202, respectively, and the equalizer 210 is not modulated in the training mode. The on-chip virtual network analyzer 200 is used to adjust the adjustable equalization gain in an operating mode, based on the frequency of the input signal and the waveform peak value of the output signal detected by the peak detector 212, using the loss model of the first channel D202, so that the amplitude of the output signal is consistent with the amplitude of the input signal.

[0034] refer to Figure 2, the on-chip virtual network analyzer 200 is deployed at the receiving end D203. The on-chip virtual network analyzer 200 and the receiving end D203 can correspond to applications such as data centers, high-performance computers, high-speed digital communications, such as data transmission from one node to another or from one machine to another, and signal amplification or signal attenuation between the front and rear circuits of analog-to-digital conversion and digital-to-analog conversion. One end of the first channel D202 is the receiving end D203, and the other end is the corresponding transmitting end. In practical applications, the first channel D202 is generally fixed after the installation of the entire data transmission system is completed, such as a connecting line connecting two servers. During the use of the first channel D202, affected by device aging, loss, etc., the channel loss performance of the first channel D202 for the signal transmitted through the first channel D202 may deviate from the initial installation situation. Moreover, in a multi-channel application scenario, the first channel D202 can be regarded as any one of the multiple channels or a representative channel. During the use of each channel, the aging and loss of each device may cause differences in channel loss performance. Therefore, if the channel compensation is set according to the situation of the multiple channels during installation, it is difficult to deal with the current status of each of the multiple channels. However, because each channel is generally fixed after the system is installed, it is difficult to directly check it by disassembly. In addition, there may be large differences in channel loss performance between different channels. For example, signals of the same frequency and amplitude may have different degrees of loss after passing through two different channels. As mentioned above, different channels may have differences in channel loss performance during use due to the aging and loss of each device. Therefore, it is necessary to consider the current status of each of the multiple channels, including the channel loss performance of these channels at the frequency point of the input signal, so as to accurately and reliably determine how to perform channel loss compensation and how to amplify or attenuate the signal to adapt to the needs of the lower-level module 220.

[0035] Continue to refer Figure 2, the on-chip virtual network analyzer 200 includes an equalizer 210. The equalizer 210 is deployed at the receiving end D203 of the first channel D202. The equalizer 210 is used to modulate the intermediate signal according to the adjustable equalization gain to obtain an output signal. The intermediate signal is obtained by transmitting the input signal through the first channel D202. The on-chip virtual network analyzer 200 also includes a peak detector 212. The peak detector 212 is deployed at the receiving end D203. The peak detector 212 is used to detect the waveform peak of the output signal. The on-chip virtual network analyzer 200 operates in a training mode or a working mode by using the cooperation between the equalizer 210 and the peak detector 212 included therein. Specifically, the on-chip virtual network analyzer 200 is used to establish a loss model of the first channel D202 in the training mode. The loss model of the first channel D202 indicates the loss of multiple signals of different frequencies with fixed amplitudes passing through the first channel D202 respectively, and the equalizer 210 does not perform modulation in the training mode. The on-chip virtual network analyzer 200 is also used to adjust the adjustable equalization gain in the working mode, based on the frequency of the input signal and the waveform peak value of the output signal detected by the peak detector 212, using the loss model of the first channel D202, so that the amplitude of the output signal is consistent with the amplitude of the input signal. In this way, the on-chip virtual network analyzer 200 uses the equalizer 210 and the peak detector 212 to construct a closed-loop system with negative feedback. When the on-chip virtual network analyzer 200 is in the working mode, the amplitude of the output signal can be determined by the waveform peak value of the output signal detected by the peak detector 212, and then the adjustable equalization gain is adjusted, so that the amplitude of the output signal is consistent with the amplitude of the input signal. Therefore, when the closed-loop system is stable, the amplitude of the output signal is consistent with the amplitude of the input signal. Furthermore, in view of the above-mentioned problem that the channel loss performance of the first channel D202 deviates during use, the on-chip virtual network analyzer 200 establishes a loss model of the first channel D202 in the training mode, and the loss model of the first channel D202 indicates the loss of multiple signals of different frequencies with fixed amplitudes passing through the first channel D202. For example, in the training mode, multiple signals of different frequencies with fixed amplitudes are sent to the receiving end D203 through the first channel D202, because the equalizer 210 does not perform modulation in the training mode, so that the waveform peak of the output signal detected by the peak detector 212 in the training mode can be used to detect the current state of the first channel D202 and the channel loss performance at different frequency points.For example, multiple signals of different frequencies with fixed amplitudes, such as three signals of 1 GHz, 5 GHz, and 20 GHz, are sent to the receiving end D203 through the first channel D202, and then the equalizer 210 does not perform modulation in the training mode. In other words, the adjustable equalization gain provided by the equalizer 210 in the training mode is fixed to 1.0. Therefore, in the training mode, the equalizer 210 and the peak detector 212 do not provide negative feedback control together, but the equalizer 210 provides a gain fixed to 1.0 and the peak detector 212 detects the amplitude of the output signal. In this way, in the training mode, the on-chip virtual network analyzer 200 does not provide negative feedback control by using the equalizer 210 and the peak detector 212, but provides a scanning mechanism with the frequency of the input signal as a variable, so as to detect how the input signals of different frequencies with fixed amplitudes are attenuated after passing through the first channel D202, that is, the channel loss performance of the first channel D202 for the input signals of different frequencies with fixed amplitudes. For example, three signals with fixed amplitudes of 1 GHz, 5 GHz and 20 GHz are sent to the receiving end D203 through the first channel D202. The on-chip virtual network analyzer 200 detects the amplitudes of the output signals as 1 volt (corresponding to 1 GHz), 0.8 volts (corresponding to 5 GHz) and 0.2 volts (corresponding to 20 GHz) through the scanning mechanism in the training mode. In this way, in the training mode, the on-chip virtual network analyzer 200 uses the equalizer 210 and the peak detector 212 to provide a scanning mechanism. When the equalizer 210 does not perform modulation, that is, does not perform compensation and gain control, the input signals at different frequencies are detected. After passing through the first channel D202, the signal attenuation received at the receiving end D203 is detected. This can not only reflect the channel attenuation performance brought by the first channel D202, but also take into account the influence caused by the components and circuits of the equalizer 210 itself. The scanning result can be depicted as a curve, the horizontal axis can be the different frequencies of the input signal, and the vertical axis is the amplitude of the output signal detected by the corresponding peak detector 212. For example, on the curve of the scanning results, for three signals with fixed amplitudes and frequencies of 1 GHz, 5 GHz and 20 GHz, there may be three scanning results, namely (1 GHz, 1 volt), (5 GHz, 0.8 volts) and (20 GHz, 0.2 volts). Here, the scanning result of (1 GHz, 1 volt) means that at a frequency point of 1 GHz, for an input signal with a fixed amplitude, the amplitude of the corresponding output signal is 1 volt. The scanning result of (5 GHz, 0.8 volts) means that at a frequency point of 5 GHz, for an input signal with a fixed amplitude, the amplitude of the corresponding output signal is 0.8 volts. The scanning result of (20 GHz, 0.2 volts) means that at a frequency point of 20 GHz, for an input signal with a fixed amplitude, the amplitude of the corresponding output signal is 0.2 volts.In this way, the S21 parameter, that is, the gain and bandwidth curve, can be detected. The vertical axis, that is, the Y-axis, can represent the amplitude of the output signal relative to the amplitude of the input signal, and the horizontal axis, that is, the X-axis, can represent the operating frequency range. In addition, the input signal can be an electrical signal transmitted through the first channel D202, such as a differential voltage signal, or an optical signal transmitted through the first channel D202. Therefore, in optoelectronic application scenarios, the optoelectronic S21 parameter, that is, the relative ratio of the optical modulation output power to the input electrical power, can be detected to represent the relative modulation efficiency roll-off compared to the DC or low-frequency electro-optical response. Therefore,. Figure 2 The on-chip virtual network analyzer 200 shown can be used in application scenarios such as data centers, high-performance computers, and high-speed digital communications, and can be used for high-speed transmission of electrical and optical signals, such as data centers that use optical interconnection technology.

[0036] Continue to refer Figure 2, the on-chip virtual network analyzer 200 provides a scanning mechanism and scanning results in the training mode, establishes a loss model of the first channel D202, and the loss model of the first channel D202 indicates the losses of multiple signals of different frequencies with fixed amplitudes passing through the first channel D202 respectively. Therefore, the scanning results obtained in the training mode and the established loss model of the first channel D202 provide a reliable reference basis for the negative feedback control provided by the on-chip virtual network analyzer 200 in the working mode, that is, a closed-loop system with negative feedback, so as to effectively solve the problem that the channel loss performance of the first channel D202 deviates during use. Specifically, the on-chip virtual network analyzer 200 is used to adjust the adjustable equalization gain based on the frequency of the input signal and the waveform peak of the output signal detected by the peak detector 212 in the working mode using the loss model of the first channel D202, so that the amplitude of the output signal is consistent with the amplitude of the input signal. Assuming that the front-stage circuit is a digital to analog converter (DAC), the amplitude of the signal output by the DAC may be a reference value, such as 1 volt or 5 volts. By establishing a corresponding loss model in the training mode, the loss of multiple signals of different frequencies with a fixed amplitude (such as 5 volts) output by the front-stage circuit through the first channel D202 can be determined, which can not only reflect the channel attenuation performance brought by the first channel D202, but also take into account the impact caused by the components and circuits of the equalizer 210 itself. In this way, in the working mode, by using the cooperation of the equalizer 210 and the peak detector 212, the loss model of the first channel D202 can be used to determine the scanning result corresponding to the frequency of the current input signal, thereby determining the channel loss performance of the first channel D202 at a specific frequency point corresponding to the frequency of the input signal, and then combining the difference between the amplitude of the output signal and the amplitude of the input signal, the negative feedback control can be improved to determine how to adjust the adjustable equalization gain, and finally achieve the purpose of system stability, that is, to make the amplitude of the output signal consistent with the amplitude of the input signal. Therefore, in the working mode, the on-chip virtual network analyzer 200 uses the loss model of the first channel D202 to adjust the adjustable equalization gain based on the frequency of the input signal and the waveform peak of the output signal detected by the peak detector 212, so that the amplitude of the output signal is consistent with the amplitude of the input signal. From the perspective of the S21 parameter or the gain and bandwidth curve, the training mode is used to establish the loss model and then the working mode is used to use the established loss model, so that the amplitude of the output signal of different frequencies is increased to obtain a relatively flat curve.Taking the three scanning results in the scanning curve mentioned above as an example, they are (1 GHz, 1 volt), (5 GHz, 0.8 volt) and (20 GHz, 0.2 volt). By adjusting the adjustable equalization gain so that the amplitude of the output signal is consistent with the amplitude of the input signal, the three scanning results on the scanning curve obtained after gain control become (1 GHz, 1 volt), (5 GHz, 1 volt) and (20 GHz, 1 volt). In this way, through the loss model established by the on-chip virtual network analyzer 200 in the training mode and the gain control in the working mode, at the frequency of 1 GHz, at the frequency of 5 GHz, and at the frequency of 20 GHz, for the input signal provided by the front-stage circuit such as DAC, the amplitude of the output signal is consistent with the amplitude of the input signal, thereby maintaining the consistency of the amplitude of the output signal at different frequencies, which is conducive to adapting to the needs of the back-stage circuit and realizing real-time adaptation of the current state of the first channel D202.

[0037] Continue to refer Figure 2 In a multi-channel application scenario, the first channel D202 can be regarded as any channel or a representative channel in the multi-channel. The channels may have differences in channel loss performance due to the aging and loss of their respective components during use. Figure 2The on-chip virtual network analyzer 200 shown in the figure, with reference to the on-chip virtual network analyzer 200 establishing a loss model of the first channel D202 in the training mode and using the established loss model of the first channel D202 to perform gain control in the working mode, the on-chip virtual network analyzer 200 corresponding to each channel can also establish a corresponding loss model and perform gain control. In this way, when all channels deployed at the receiving end and their corresponding on-chip virtual network analyzers 200 have been trained, the on-chip virtual network analyzer 200 corresponding to each channel can adapt to input signals of any frequency point, and control the adjustable equalization gain of the corresponding equalizer 210, so that the amplitude of the output signal of each channel is consistent with the amplitude of the input signal. As long as the frequency point of the input signal falls within the range of the loss model established in the training mode, in other words, as long as the frequency range covered by the loss model established in the training mode is wide enough, the gain control needs of each channel can be met. Furthermore, because the scanning mechanism in the training mode has taken into account the different lengths and frequency sensitivities that may exist between different channels, the current status of each of the multiple channels is taken into account, including the channel loss performance of these channels at the frequency point of the input signal. In this way, the on-chip virtual network analyzer 200 that has been trained for each channel can ensure that the outputs of all channels are consistent, and achieve accurate and reliable judgment of how to perform channel loss compensation and how to amplify or attenuate the signal to adapt to the needs of the lower-level module 220, which is conducive to improving the overall performance of the system.

[0038] In conclusion, Figure 2The on-chip virtual network analyzer 200 shown in the figure establishes a loss model of the first channel D202 in the training mode, and in the working mode, uses the loss model of the first channel D202 to adjust the adjustable equalization gain based on the frequency of the input signal and the waveform peak value of the output signal detected by the peak detector 212, so that the amplitude of the output signal is consistent with the amplitude of the input signal; not only the channel attenuation performance caused by the first channel D202 is taken into account, but also the influence caused by the components and circuits of the equalizer 210 itself; in the working mode, the cooperation of the equalizer 210 and the peak detector 212 is used to adjust the adjustable equalization gain. The loss model of the first channel D202 can determine the scanning result corresponding to the frequency of the current input signal, thereby determining the channel loss performance of the first channel D202 at a specific frequency point corresponding to the frequency of the input signal, and then combining the difference between the amplitude of the output signal and the amplitude of the input signal to improve negative feedback control and determine how to adjust the adjustable equalization gain, ultimately achieving the purpose of system stability, that is, making the amplitude of the output signal consistent with the amplitude of the input signal; achieving accurate and reliable judgment on how to perform channel loss compensation and how to amplify or attenuate the signal to adapt to the needs of the lower-level module 220, which is conducive to improving the overall performance of the system.

[0039] refer to Figure 2 In a possible implementation, the equalizer 210 modulates the intermediate signal according to the adjusted adjustable equalization gain in the working mode to obtain the output signal. In this way, in the working mode, by utilizing the collaboration of the equalizer 210 and the peak detector 212, the loss model of the first channel D202 can be used to determine the scanning result corresponding to the frequency of the current input signal, thereby determining the channel loss performance of the first channel D202 at a specific frequency point corresponding to the frequency of the input signal, and then combining the difference between the amplitude of the output signal and the amplitude of the input signal, the negative feedback control can be improved to determine how to adjust the adjustable equalization gain, and finally achieve the purpose of system stability, that is, to make the amplitude of the output signal consistent with the amplitude of the input signal; it realizes accurate and reliable judgment on how to perform channel loss compensation and how to amplify or attenuate the signal to adapt to the needs of the lower-level module 220, which is conducive to improving the overall performance of the system.

[0040] In one possible implementation, the adjustable equalization gain is fixed to 1.0 in the training mode. Thus, the adjustable equalization gain provided by the equalizer 210 in the training mode is fixed to 1.0, and therefore, in the training mode, the equalizer 210 and the peak detector 212 together do not provide negative feedback control, but the equalizer 210 provides a gain fixed to 1.0 and the peak detector 212 detects the amplitude of the output signal. Thus, in the training mode, the on-chip virtual network analyzer 200 does not provide negative feedback control by using the equalizer 210 and the peak detector 212, but provides a scanning mechanism with the frequency of the input signal as a variable, so as to detect how the input signals of different frequencies with a fixed amplitude are attenuated after passing through the first channel D202, that is, the channel loss performance of the first channel D202 for the input signals of different frequencies with a fixed amplitude. In this way, the scanning results obtained in the training mode and the loss model of the first channel D202 established provide a reliable reference basis for the negative feedback control provided by the on-chip virtual network analyzer 200 in the working mode, that is, a closed-loop system with negative feedback, thereby effectively solving the problem of deviation of the channel loss performance of the first channel D202 during use.

[0041] In a possible implementation, the loss model of the first channel D202 indicates the amplitude of the intermediate signal obtained by transmitting multiple signals with the same fixed amplitude and different frequencies through the first channel D202. Thus, in the training mode, the on-chip virtual network analyzer 200 uses the equalizer 210 and the peak detector 212 to provide a scanning mechanism. When the equalizer 210 does not perform modulation, that is, does not perform compensation and gain control, the signal attenuation of the input signal at different frequencies received at the receiving end D203 after passing through the first channel D202 is detected. This can not only reflect the channel attenuation performance brought by the first channel D202, but also take into account the influence caused by the components and circuits of the equalizer 210 itself. Thus, the scanning results obtained in the training mode and the loss model of the first channel D202 established provide a reliable reference basis for the negative feedback control provided by the on-chip virtual network analyzer 200 in the working mode, that is, the closed-loop system with negative feedback, so that the problem of deviation of the channel loss performance of the first channel D202 during use can be effectively solved.

[0042] In a possible implementation, the peak detector 212 is used to provide a frequency scanning function in the training mode to determine the S21 parameter of the system including the first channel D202 and the on-chip virtual network analyzer 200, and the S21 parameter is a curve of gain change relative to bandwidth. In this way, the S21 parameter, i.e., the gain and bandwidth curve, can be detected, and the vertical axis, i.e., the Y-axis, can represent the amplitude of the output signal relative to the amplitude of the input signal, and the horizontal axis, i.e., the X-axis, can represent the operating frequency range. In this way, by using the scanning results obtained in the training mode and the loss model of the first channel D202 established, a reliable reference basis is provided for the negative feedback control provided by the on-chip virtual network analyzer 200 in the working mode, i.e., a closed-loop system with negative feedback, so that the problem of deviation of the channel loss performance of the first channel D202 during use can be effectively solved.

[0043] In a possible implementation, the equalizer 210 and the peak detector 212 together form a negative feedback loop in the working mode to provide a swing control function. In this way, the on-chip virtual network analyzer 200 uses the equalizer 210 and the peak detector 212 to construct a closed-loop system with negative feedback. When the on-chip virtual network analyzer 200 is in the working mode, the amplitude of the output signal can be determined by the waveform peak of the output signal detected by the peak detector 212, and then the adjustable equalization gain is adjusted, so that the amplitude of the output signal is consistent with the amplitude of the input signal. Therefore, when the closed-loop system is stable, the amplitude of the output signal is consistent with the amplitude of the input signal.

[0044] In a possible implementation, the input signal and the output signal are both electrical signals, and an on-chip oscilloscope (On-chip OSC) is deployed at the receiving end D203 to perform waveform analysis on the output signal to obtain a waveform analysis result, and the waveform analysis result is used to improve the performance of the on-chip virtual network analyzer 200. The input signal may be an electrical signal transmitted through the first channel D202, such as a differential voltage signal. By deploying an on-chip oscilloscope to analyze the waveform of the electrical signal, the waveform analysis result can be used to further improve the gain control and negative feedback mechanism, so as to accurately and reliably determine how to perform channel loss compensation and how to amplify or attenuate the signal to adapt to the needs of the lower-level module 220, which is conducive to improving the overall performance of the system.

[0045] In one possible implementation, the input signal and the output signal are both optical pulse signals, a photodiode (PD) and an on-chip oscilloscope are deployed at the receiving end D203, the photodiode is used to convert the output signal into an electrical signal corresponding to the output signal, and the on-chip oscilloscope is used to perform waveform analysis on the electrical signal corresponding to the output signal to obtain a waveform analysis result, and the waveform analysis result is used to improve the performance of the on-chip virtual network analyzer 200. The input signal can be an electrical signal transmitted through the first channel D202, such as a differential voltage signal, or an optical signal transmitted through the first channel D202. Therefore, in optoelectronic application scenarios, the optoelectronic S21 parameter can be detected, that is, the relative ratio of the optical modulated output power to the input electrical power, which is used to represent the relative modulation efficiency roll-off compared to the DC or low-frequency electro-optical response. Therefore, Figure 2 The on-chip virtual network analyzer 200 shown can be applied in application scenarios such as data centers, high-performance computers, and high-speed digital communications, and can be used for high-speed transmission of electrical and optical signals, such as data centers using optical interconnection technology. In this way, by deploying a photodiode and an on-chip oscilloscope, using a photodiode to convert the output signal into an electrical signal corresponding to the output signal, and using an on-chip oscilloscope to analyze the waveform of the electrical signal, the waveform analysis result can be used to further improve the gain control and negative feedback mechanism, and to accurately and reliably determine how to perform channel loss compensation and how to amplify or attenuate the signal to adapt to the needs of the lower-level module 220, which is conducive to improving the overall performance of the system.

[0046] In one possible implementation, the first channel D202 belongs to a plurality of channels, and the on-chip virtual network analyzer is respectively deployed on the receiving end of each of the plurality of channels, and the on-chip virtual network analyzers corresponding to each of the plurality of channels are used to respectively establish the loss models of the plurality of channels in the training mode, and, in the working mode, respectively use the loss models of the plurality of channels to adjust the adjustable equalization gain of the equalizer in the on-chip virtual network analyzer corresponding to each of the plurality of channels. In this way, in a multi-channel application scenario, the first channel D202 can be regarded as any one of the multi-channels or a representative channel. The differences in channel loss performance between the channels are caused by the aging and loss of their respective devices during use. By deploying on the receiving end of each channel Figure 2The on-chip virtual network analyzer 200 shown in the figure, with reference to the on-chip virtual network analyzer 200 establishing a loss model of the first channel D202 in the training mode and using the established loss model of the first channel D202 to perform gain control in the working mode, the on-chip virtual network analyzer 200 corresponding to each channel can also establish a corresponding loss model and perform gain control. In this way, when all channels deployed at the receiving end and their corresponding on-chip virtual network analyzers 200 have been trained, the on-chip virtual network analyzer 200 corresponding to each channel can adapt to input signals of any frequency point, and control the adjustable equalization gain of the corresponding equalizer 210, so that the amplitude of the output signal of each channel is consistent with the amplitude of the input signal. As long as the frequency point of the input signal falls within the range of the loss model established in the training mode, in other words, as long as the frequency range covered by the loss model established in the training mode is wide enough, the gain control needs of each channel can be met. Furthermore, because the scanning mechanism in the training mode has taken into account the different lengths and frequency sensitivities that may exist between different channels, the current status of each of the multiple channels is taken into account, including the channel loss performance of these channels at the frequency point of the input signal. In this way, the on-chip virtual network analyzer 200 that has been trained for each channel can ensure that the outputs of all channels are consistent, and achieve accurate and reliable judgment of how to perform channel loss compensation and how to amplify or attenuate the signal to adapt to the needs of the lower-level module 220, which is conducive to improving the overall performance of the system.

[0047] In some embodiments, the multiple channels correspond to multiple connecting lines on the same panel, and the round-trip loss of each of the multiple connecting lines is determined based on the position of each of the multiple connecting lines on the panel and the length of each of the multiple connecting lines. In practical applications, the first channel D202 is generally fixed after the entire data transmission system is installed, such as a connecting line connecting two servers. On the same panel, affected by the length of each connecting line, generally speaking, the length of the connecting line located at the center of the panel is shorter, so the loss is smaller, while the length of the connecting line located at the edge of the panel is longer, so the loss is also larger. Therefore, based on the position of each of the multiple connecting lines on the panel and the length of each of the multiple connecting lines, the round-trip loss of each of the multiple connecting lines varies. Through the application of the above-mentioned on-chip virtual network analyzer 200 in a multi-channel application scenario, the on-chip virtual network analyzer 200 corresponding to each channel can ensure that the output of all channels is consistent, and realizes accurate and reliable judgment on how to perform channel loss compensation and how to amplify or attenuate the signal to adapt to the needs of the lower-level module 220, which is conducive to improving the overall performance of the system.

[0048] Figure 3 A flowchart of a method for on-chip virtual network analysis provided in an embodiment of the present application. Figure 3 As shown, the method for on-chip virtual network analysis includes the following steps.

[0049] Step S301: Provide an equalizer for an on-chip virtual network analyzer, wherein the equalizer is deployed at the receiving end of a first channel, and is used to modulate an intermediate signal according to an adjustable equalization gain to obtain an output signal, wherein the intermediate signal is obtained by transmitting an input signal through the first channel.

[0050] Step S303: providing a peak detector of the on-chip virtual network analyzer, wherein the peak detector is deployed at the receiving end, and the peak detector is used to detect a waveform peak of the output signal.

[0051] The on-chip virtual network analyzer is used to establish a loss model of the first channel in a training mode, the loss model of the first channel indicates the loss of multiple signals of different frequencies with fixed amplitudes passing through the first channel respectively, and the equalizer is not modulated in the training mode. The on-chip virtual network analyzer is used to adjust the adjustable equalization gain in an operating mode, using the loss model of the first channel, based on the frequency of the input signal and the waveform peak of the output signal detected by the peak detector, so that the amplitude of the output signal is consistent with the amplitude of the input signal.

[0052] refer to Figure 3In a multi-channel application scenario, the first channel can be regarded as any channel or a representative channel in the multi-channel. The channels have differences in channel loss performance due to the aging and loss of their respective devices during use. By deploying an on-chip virtual network analyzer on the receiving end of each channel, referring to the on-chip virtual network analyzer to establish a loss model of the first channel in the training mode and using the established loss model of the first channel in the working mode to perform gain control, the on-chip virtual network analyzer corresponding to each channel can also establish a corresponding loss model and perform gain control. In this way, when all channels deployed at the receiving end and their corresponding on-chip virtual network analyzers have been trained, the on-chip virtual network analyzer corresponding to each channel can adapt to input signals of any frequency point and control the adjustable equalization gain of the corresponding equalizer so that the amplitude of the output signal of each channel is consistent with the amplitude of the input signal. As long as the frequency point of the input signal falls within the range of the loss model established in the training mode, in other words, as long as the frequency range covered by the loss model established in the training mode is wide enough, the gain control needs of each channel can be met. Moreover, because the scanning mechanism in the training mode has taken into account the different lengths and frequency sensitivities that may exist between different channels, the current status of each channel is taken into account, including the channel loss performance of these channels at the frequency point of the input signal. In this way, the on-chip virtual network analyzer that has been trained for each channel can ensure that the output of all channels is consistent, and realizes accurate and reliable judgment on how to perform channel loss compensation and how to amplify or attenuate the signal to adapt to the needs of the lower-level modules, which is conducive to improving the overall performance of the system.

[0053] In conclusion, Figure 3In the method shown, the on-chip virtual network analyzer establishes a loss model of the first channel in a training mode, and uses the loss model of the first channel in a working mode to adjust the adjustable equalization gain based on the frequency of the input signal and the waveform peak of the output signal detected by the peak detector, so that the amplitude of the output signal is consistent with the amplitude of the input signal; not only the channel attenuation performance caused by the first channel is taken into account, but also the influence caused by the devices and circuits of the equalizer itself is taken into account; in the working mode, the loss model of the first channel can be used to determine the scanning result corresponding to the frequency of the current input signal by using the collaboration of the equalizer and the peak detector, thereby determining the channel loss performance of the first channel at a specific frequency point corresponding to the frequency of the input signal, and then combining the difference between the amplitude of the output signal and the amplitude of the input signal, improve the negative feedback control, determine how to adjust the adjustable equalization gain, and finally achieve the purpose of system stability, that is, to make the amplitude of the output signal consistent with the amplitude of the input signal; it realizes accurate and reliable judgment on how to perform channel loss compensation and how to amplify or attenuate the signal to adapt to the needs of the lower-level module, which is conducive to improving the overall performance of the system.

[0054] refer to Figure 3 In a possible implementation, the loss model of the first channel indicates the amplitude of the intermediate signal obtained by transmitting multiple signals with the same fixed amplitude and different frequencies through the first channel. Thus, in the training mode, the on-chip virtual network analyzer provides a scanning mechanism using an equalizer and a peak detector. When the equalizer does not perform modulation, that is, does not perform compensation and gain control, the signal attenuation of the input signal at different frequencies received at the receiving end after passing through the first channel is detected. This not only reflects the channel attenuation performance brought by the first channel, but also takes into account the influence caused by the components and circuits of the equalizer itself. Thus, the scanning results obtained in the training mode and the loss model of the first channel established provide a reliable reference basis for the negative feedback control provided by the on-chip virtual network analyzer in the working mode, that is, a closed-loop system with negative feedback, thereby effectively solving the problem of deviation of the channel loss performance of the first channel during use.

[0055] In a possible implementation, the peak detector is used to provide a frequency scanning function in the training mode to determine the S21 parameter of the system including the first channel and the on-chip virtual network analyzer, and the S21 parameter is a curve of gain change relative to bandwidth. In this way, the S21 parameter, that is, the gain and bandwidth curve, can be detected, and the vertical axis, that is, the Y-axis, can represent the amplitude of the output signal relative to the amplitude of the input signal, and the horizontal axis, that is, the X-axis, can represent the operating frequency range. In this way, the scanning results obtained in the training mode and the loss model of the first channel established provide a reliable reference basis for the negative feedback control provided by the on-chip virtual network analyzer in the working mode, that is, a closed-loop system with negative feedback, so that the problem of deviation of the channel loss performance of the first channel during use can be effectively solved.

[0056] In a possible implementation, the equalizer and the peak detector together form a negative feedback loop in the working mode to provide a swing control function. In this way, the on-chip virtual network analyzer uses the equalizer and the peak detector to construct a closed-loop system with negative feedback. When the on-chip virtual network analyzer is in the working mode, the amplitude of the output signal can be determined by the waveform peak of the output signal detected by the peak detector, and then the adjustable equalization gain is adjusted so that the amplitude of the output signal is consistent with the amplitude of the input signal. Therefore, when the closed-loop system is stable, the amplitude of the output signal is consistent with the amplitude of the input signal.

[0057] In a possible implementation, the first channel belongs to a plurality of channels, and the on-chip virtual network analyzer is respectively deployed at the receiving end of each of the plurality of channels, and the on-chip virtual network analyzers corresponding to the plurality of channels are used to respectively establish the loss models of the plurality of channels in the training mode, and to respectively use the loss models of the plurality of channels in the working mode to adjust the adjustable equalization gain of the equalizer in the on-chip virtual network analyzer corresponding to the plurality of channels. In this way, in a multi-channel application scenario, the first channel can be regarded as any one of the channels or a representative channel. During use, the channels have differences in channel loss performance due to the aging and loss of their respective devices. By deploying an on-chip virtual network analyzer at the receiving end of each channel, referring to the on-chip virtual network analyzer to establish the loss model of the first channel in the training mode and to use the established loss model of the first channel in the working mode to perform gain control, the on-chip virtual network analyzer corresponding to each channel can also establish a corresponding loss model and perform gain control. In this way, when all channels deployed at the receiving end and their corresponding on-chip virtual network analyzers have been trained, the on-chip virtual network analyzer corresponding to each channel can adapt to the input signal of any frequency point, and control the adjustable equalization gain of the corresponding equalizer, so that the amplitude of the output signal of each channel is consistent with the amplitude of the input signal. As long as the frequency point of the input signal falls within the range of the loss model established in the training mode, in other words, as long as the frequency range covered by the loss model established in the training mode is wide enough, the gain control needs of each channel can be met. In addition, because the scanning mechanism in the training mode has taken into account the different lengths and frequency sensitivity that may exist between different channels, the current status of each of the multiple channels is taken into account, including the channel loss performance of these channels at the frequency point of the input signal. In this way, the on-chip virtual network analyzer corresponding to each channel can ensure that the output of all channels is consistent, and realizes accurate and reliable judgment on how to perform channel loss compensation and how to amplify or attenuate the signal to adapt to the needs of the lower-level modules, which is conducive to improving the overall performance of the system.

[0058] Figure 4 A schematic diagram of a panel with multiple connection line interfaces provided in an embodiment of the present application. Figure 4As shown, there are multiple connection line interfaces on the panel 400, and these connection line interfaces are represented by circular patterns. The multiple channels correspond to multiple connection lines on the same panel, and the round-trip loss of each of the multiple connection lines is determined based on the position of each of the multiple connection lines on the panel and the length of each of the multiple connection lines. In practical applications, the first channel is generally fixed after the entire data transmission system is installed, such as a connection line connecting two servers. On the same panel, affected by the lengths of the respective connection lines, generally speaking, the length of the connection line located at the center of the panel is shorter and therefore the loss is smaller, while the length of the connection line located at the edge of the panel is longer and therefore the loss is larger. Therefore, based on the position of each of the multiple connection lines on the panel and the length of each of the multiple connection lines, the round-trip loss of each of the multiple connection lines varies. Reference Figure 4 , the area A410 at the center of the panel 400 includes a plurality of connection line interfaces, and the length of the connection line corresponding to the connection line interface in the area A410 is shorter, so the loss is also smaller. The areas B412 and C414 at the edge of the panel 400 also include a plurality of connection line interfaces, and the length of the connection line corresponding to the connection line interfaces in the areas B412 and C414 is longer, so the loss is also greater. Therefore, in the multi-channel application scenario taking the panel 400 as an example, it is necessary to consider the influence caused by the length of the connection line corresponding to the connection line interfaces in different areas, for example, the length of the connection line corresponding to the connection line interface in the area A410 is generally shorter than the length of the connection line corresponding to the connection line interface in the area B412. Through the application of the above-mentioned on-chip virtual network analyzer in the multi-channel application scenario, the on-chip virtual network analyzer corresponding to each channel after training can ensure that the output of all channels is consistent, and realizes accurate and reliable judgment on how to perform channel loss compensation and how to amplify or attenuate the signal to adapt to the needs of the lower-level module, which is conducive to improving the overall performance of the system.

[0059] Figure 5: is a structural diagram of a computing device provided in an embodiment of the present application, and the computing device 500 includes: one or more processors 510, a communication interface 520 and a memory 530. The processor 510, the communication interface 520 and the memory 530 are interconnected via a bus 540. Optionally, the computing device 500 may also include an input / output interface 550, and the input / output interface 550 is connected to an input / output device for receiving parameters set by a user, etc. The computing device 500 can be used to implement some or all of the functions of the device embodiment or system embodiment in the above-mentioned embodiment of the present application; the processor 510 can also be used to implement some or all of the operating steps of the method embodiment in the above-mentioned embodiment of the present application. For example, the specific implementation of the computing device 500 performing various operations can refer to the specific details in the above-mentioned embodiments, such as the processor 510 is used to perform some or all of the steps in the above-mentioned method embodiment or some or all of the operations in the above-mentioned method embodiment. For another example, in an embodiment of the present application, the computing device 500 may be used to implement part or all of the functions of one or more components in the above-mentioned device embodiment. In addition, the communication interface 520 may be specifically used to perform the communication functions necessary to implement the functions of these devices and components, and the processor 510 may be specifically used to perform the processing functions necessary to implement the functions of these devices and components.

[0060] It should be understood that Figure 5 The computing device 500 may include one or more processors 510, and the multiple processors 510 may provide processing capabilities in a parallel connection mode, a serial connection mode, a serial-parallel connection mode, or any connection mode, or the multiple processors 510 may form a processor sequence or a processor array, or the multiple processors 510 may be divided into a main processor and an auxiliary processor, or the multiple processors 510 may have different architectures such as a heterogeneous computing architecture. In addition, Figure 5 The computing device 500 shown in the figure, and the related structural description and functional description are exemplary and non-limiting. In some exemplary embodiments, the computing device 500 may include Figure 5 More or fewer components may be shown, or some components may be combined or separated, or may have a different arrangement of components.

[0061] The processor 510 may have a variety of specific implementation forms. For example, the processor 510 may include a central processing unit (CPU), a graphic processing unit (GPU), a neural-network processing unit (NPU), a tensor processing unit (TPU) or a data processing unit (DPU), etc., and the embodiment of the present application does not specifically limit it. The processor 510 may also be a single-core processor or a multi-core processor. The processor 510 may be a combination of a CPU and a hardware chip. The above-mentioned hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The above-mentioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof. The processor 510 may also be implemented using a logic device with built-in processing logic alone, such as an FPGA or a digital signal processor (DSP). The communication interface 520 may be a wired interface or a wireless interface for communicating with other modules or devices. The wired interface may be an Ethernet interface, a local interconnect network (LIN), etc., and the wireless interface may be a cellular network interface or a wireless local area network interface, etc.

[0062] The memory 530 may be a non-volatile memory, such as a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The memory 530 may also be a volatile memory, which may be a random access memory (RAM) used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM). The memory 530 may also be used to store program codes and data, so that the processor 510 calls the program codes stored in the memory 530 to execute some or all of the operation steps in the above method embodiments, or to execute the corresponding functions in the above device embodiments. Figure 5 Show more or fewer components, or have different component configurations.

[0063] The bus 540 may be a peripheral component interconnect express (PCIe) bus, an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus 540 may be divided into an address bus, a data bus, a control bus, etc. In addition to the data bus, the bus 540 may also include a power bus, a control bus, and a status signal bus, etc. However, for the sake of clarity, Figure 5 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0064] The method and device provided in the embodiments of the present application are based on the same inventive concept. Since the principles of solving the problems in the methods and devices are similar, the embodiments, implementation methods, examples or implementation methods of the methods and devices can refer to each other, and the repeated parts will not be repeated. The embodiments of the present application also provide a system, which includes multiple computing devices, and the structure of each computing device can refer to the structure of the computing device described above. The functions or operations that can be implemented by the system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, which will not be repeated here.

[0065] The present application also provides a computer-readable storage medium, in which computer instructions are stored. When the computer instructions are executed on a computer device (such as one or more processors), the method steps in the above method embodiment can be implemented. The specific implementation of the processor of the computer-readable storage medium in executing the above method steps can refer to the specific operations described in the above method embodiment and / or the specific functions described in the above device embodiment, which will not be repeated here.

[0066] It should be understood by those skilled in the art that the embodiments of the present application may be provided as methods, systems, or computer program products. The present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. The embodiments of the present application may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented using software, the above embodiments may be implemented in whole or in part in the form of a computer program product. The present application may take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program codes. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiments of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. Computer-readable storage media can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media. Available media can be magnetic media (such as floppy disks, hard disks, tapes), optical media, or semiconductor media. Semiconductor media can be solid-state hard disks, random access memory, flash memory, read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, or any other form of suitable storage media.

[0067] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. Each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0068] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiment of the present application can be adjusted in order, merged or deleted according to actual needs; the modules in the system of the embodiment of the present application can be divided, merged or deleted according to actual needs. If these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. An on-chip virtual network analyzer, characterized in that: The on-chip virtual network analyzer comprises: an equalizer, disposed at a receiving end of the first channel, for modulating an intermediate signal according to an adjustable equalization gain to obtain an output signal, wherein the intermediate signal is obtained by transmitting the input signal through the first channel; and A peak detector is disposed at the receiving end to detect the waveform peak of the output signal, The on-chip virtual network analyzer is used to establish a loss model of the first channel in a training mode, wherein the loss model of the first channel indicates the loss of multiple signals of different frequencies with fixed amplitudes passing through the first channel respectively, and the equalizer is not modulated in the training mode. The on-chip virtual network analyzer is used to adjust the adjustable equalization gain in the working mode, using the loss model of the first channel, based on the frequency of the input signal and the waveform peak of the output signal detected by the peak detector, so that the amplitude of the output signal is consistent with the amplitude of the input signal.

2. The on-chip virtual network analyzer according to claim 1, characterized in that: The equalizer modulates the intermediate signal according to the adjusted adjustable equalization gain in the working mode to obtain the output signal.

3. The on-chip virtual network analyzer according to claim 1, characterized in that: The adjustable equalization gain is fixed to 1.0 in the training mode.

4. The on-chip virtual network analyzer according to claim 1, characterized in that: The loss model of the first channel indicates the amplitudes of intermediate signals respectively obtained when a plurality of signals having the same fixed amplitude and different frequencies are transmitted through the first channel.

5. The on-chip virtual network analyzer according to claim 1, characterized in that: The peak detector is used in the training mode to provide a frequency scanning function to determine an S21 parameter of a system including the first channel and the on-chip virtual network analyzer, wherein the S21 parameter is a curve of gain versus bandwidth.

6. The on-chip virtual network analyzer according to claim 1, characterized in that: The equalizer and the peak detector together form a negative feedback loop in the operating mode to provide a swing control function.

7. The on-chip virtual network analyzer according to claim 1, characterized in that: The input signal and the output signal are both electrical signals. The on-chip oscilloscope is deployed at the receiving end to perform waveform analysis on the output signal to obtain a waveform analysis result, and the waveform analysis result is used to improve the performance of the on-chip virtual network analyzer.

8. The on-chip virtual network analyzer according to claim 1, characterized in that: The input signal and the output signal are both optical pulse signals. A photodiode and an on-chip oscilloscope are deployed at the receiving end. The photodiode is used to convert the output signal into an electrical signal corresponding to the output signal. The on-chip oscilloscope is used to perform waveform analysis on the electrical signal corresponding to the output signal to obtain a waveform analysis result. The waveform analysis result is used to improve the performance of the on-chip virtual network analyzer.

9. The on-chip virtual network analyzer according to claim 1, characterized in that: The first channel belongs to multiple channels, and the on-chip virtual network analyzer is deployed at the receiving end of each of the multiple channels. The on-chip virtual network analyzers corresponding to each of the multiple channels are used to establish loss models of each of the multiple channels in the training mode, and to adjust the adjustable equalization gain of the equalizer in the on-chip virtual network analyzer corresponding to each of the multiple channels using the loss models of each of the multiple channels in the working mode.

10. The on-chip virtual network analyzer according to claim 9, characterized in that: The multiple channels correspond to multiple connection lines on the same panel, and the round-trip loss of each of the multiple connection lines is determined based on the position of each of the multiple connection lines on the panel and the length of each of the multiple connection lines.

11. A method for on-chip virtual network analysis, characterized in that: The method comprises: An equalizer of an on-chip virtual network analyzer is provided, wherein the equalizer is deployed at a receiving end of a first channel, and the equalizer is used to modulate an intermediate signal according to an adjustable equalization gain to obtain an output signal, wherein the intermediate signal is obtained by transmitting an input signal through the first channel; and A peak detector of the on-chip virtual network analyzer is provided, wherein the peak detector is deployed at the receiving end, and the peak detector is used to detect a waveform peak of the output signal, The on-chip virtual network analyzer is used to establish a loss model of the first channel in a training mode, wherein the loss model of the first channel indicates the loss of multiple signals of different frequencies with fixed amplitudes passing through the first channel respectively, and the equalizer is not modulated in the training mode. The on-chip virtual network analyzer is used to adjust the adjustable equalization gain in the working mode, using the loss model of the first channel, based on the frequency of the input signal and the waveform peak of the output signal detected by the peak detector, so that the amplitude of the output signal is consistent with the amplitude of the input signal.

12. The method according to claim 11, characterized in that The loss model of the first channel indicates the amplitudes of intermediate signals respectively obtained when a plurality of signals having the same fixed amplitude and different frequencies are transmitted through the first channel.

13. The method according to claim 11, characterized in that The peak detector is used in the training mode to provide a frequency scanning function to determine an S21 parameter of a system including the first channel and the on-chip virtual network analyzer, wherein the S21 parameter is a curve of gain versus bandwidth.

14. The method according to claim 11, characterized in that The equalizer and the peak detector together form a negative feedback loop in the operating mode to provide a swing control function.

15. The method according to claim 11, characterized in that The first channel belongs to multiple channels, and the on-chip virtual network analyzer is deployed at the receiving end of each of the multiple channels. The on-chip virtual network analyzers corresponding to each of the multiple channels are used to establish loss models of each of the multiple channels in the training mode, and to adjust the adjustable equalization gain of the equalizer in the on-chip virtual network analyzer corresponding to each of the multiple channels using the loss models of each of the multiple channels in the working mode.

16. A computer device, characterized in that: The computer device comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method according to any one of claims 11 to 15 when executing the computer program.

17. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, which, when executed on a computer device, cause the computer device to perform the method according to any one of claims 11 to 15.

Images