Signal processing method, system, equipment, medium and product

Abstract

The invention provides a signal processing method, system and device, a medium and a product, and relates to the technical field of communication, and the method comprises the steps: obtaining a to-be-processed digital signal, carrying out the delay adjustment, and obtaining a signal after the delay adjustment; if the first preset condition is met, outputting the signal after delay adjustment; if the first preset condition and the second preset condition are not met, aliasing distortion compensation is carried out on the image, and the image is obtained and output; and if the signal after delay adjustment does not meet the first preset condition but meets a second preset condition, continuously performing at least one time of delay adjustment on the signal until the current signal after delay adjustment meets the first preset condition or the number of times of delay adjustment reaches a first preset threshold, and outputting the current signal after delay adjustment. Therefore, through multi-level condition judgment and dynamic adjustment, the digital signals can be effectively processed and optimized, it is ensured that the quality and performance of the output signals reach expected standards, the digital pre-distortion effect can be improved, and the power consumption of hardware can be reduced.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of communication technology, and in particular, to a signal processing method, system, device, medium and product. Background Art

[0002] Looking at the existing multi-phase digital pre-distortion (DPD) technology, the industry and academia face some common challenges and limitations when designing and implementing solutions. In order to reduce hardware complexity and power consumption, the industry often chooses to only retain the multi-phase module and ignores the necessity of the aliasing distortion compensation part. Although this choice can reduce the complexity and cost of the system in the short term, it may lead to a decrease in signal quality, especially in high-frequency and high-power applications, where aliasing distortion may significantly affect the overall performance of the system.

[0003] On the other hand, some companies choose to keep both the polyphase module and the aliasing distortion compensation in order to find a balance between performance and complexity. However, such a design often increases the cost and power consumption of the system, especially when high-bandwidth signals need to be processed. At this time, the contradiction between the consumption of hardware resources and the improvement of performance becomes more prominent, especially in the field of mobile communications, where the requirements for energy efficiency and processing power are increasing.

[0004] In academia, research is mainly focused on reducing the number of filters through multi-phase interpolation technology to reduce the complexity of implementation. Although this method optimizes system design to a certain extent, it often ignores the in-depth analysis of hardware computing power. With the rapid development of mobile communication technology, especially the advent of 5G and future 6G networks, users' demand for data throughput and signal processing capabilities continues to increase, and traditional design methods cannot meet the needs of flexible loading of multiple computing power in the future.

[0005] In summary, in current wireless communication technologies, especially for next-generation base station applications, with the increasing demand for large bandwidth, high transmission rate and low latency, existing linear pre-distortion processing technologies face significant challenges. Although existing technologies can meet the basic linear pre-distortion processing effects to a certain extent, they are obviously insufficient in balancing processing accuracy and computing power requirements. Summary of the invention

[0006] The embodiments of the present application provide a signal processing method, system, device, medium and product to solve the technical problem that the existing linearization pre-correction processing technology can meet the basic linear pre-distortion processing effect to a certain extent, but has obvious deficiencies in the balance between processing accuracy and computing power requirements.

[0007] In order to solve the above technical problems, this application is implemented as follows: In a first aspect, an embodiment of the present application provides a signal processing method, which is applied to a signal processing system, and the method includes: The signal processing system acquires a digital signal to be processed, and performs delay adjustment on the digital signal to be processed to obtain a signal after delay adjustment; If the delay-adjusted signal satisfies a first preset condition, the signal processing system outputs the delay-adjusted signal; If the delay-adjusted signal does not satisfy the first preset condition and does not satisfy the second preset condition, the signal processing system performs aliasing distortion compensation on the delay-adjusted signal to obtain and output the aliasing distortion compensated signal; If the delay-adjusted signal does not satisfy the first preset condition but satisfies the second preset condition, continue to perform at least one delay adjustment on the delay-adjusted signal until the current delay-adjusted signal satisfies the first preset condition, or the number of delay adjustments reaches a first preset threshold, outputting the current delay-adjusted signal; The first preset condition is that the sum of the mean square error between the current delay-adjusted signal and the preset target signal and the inverse of the signal-to-noise ratio of the current delay-adjusted signal is less than a second preset threshold; The second preset condition is that the signal-to-noise ratio of the signal after delay adjustment is greater than a third preset threshold.

[0008] Optionally, the delay adjustment of the digital signal to be processed to obtain a signal after the delay adjustment includes: The signal processing system divides the digital signal to be processed into P parallel sub-digital signals; P is a positive integer, which is the number of multi-phase branches that the signal processing system can support; The signal processing system performs delay adjustment on the P parallel sub-digital signals respectively and then combines them to obtain the delay-adjusted signal.

[0009] Optionally, performing aliasing distortion compensation on the delay-adjusted signal to obtain and output the aliasing distortion compensated signal includes: The signal processing system configures a preset filter order according to the aliasing distortion degree of the delay-adjusted signal; The delay-adjusted signal is subjected to aliasing distortion compensation by the filter to obtain an aliasing distortion compensated signal; and the aliasing distortion compensated signal is output.

[0010] Optionally, the signal processing system configures a preset filter order according to the aliasing distortion degree of the delay-adjusted signal, and performs aliasing distortion compensation on the delay-adjusted signal through the filter, to obtain the aliasing distortion compensated signal, including: The signal processing system calculates a signal-to-noise ratio of the delay-adjusted signal; The signal processing system normalizes the signal-to-noise ratio to obtain a normalized signal-to-noise ratio; The signal processing system determines a target order of the filter according to the normalized signal-to-noise ratio and a preset maximum order of the filter, and adjusts a current order of the filter to the target order; The signal processing system performs aliasing distortion compensation on the delay-adjusted signal based on the filter to obtain an aliasing distortion compensated signal; The higher the aliasing distortion degree is, the larger the target order of the filter is, and the lower the aliasing distortion degree is, the smaller the target order of the filter is.

[0011] Optionally, continuing to perform at least one delay adjustment on the delay-adjusted signal until the current delay-adjusted signal satisfies the first preset condition, or the number of delay adjustments reaches a preset threshold, outputting the current delay-adjusted signal includes: The signal processing system divides the delay-adjusted signal into PN parallel sub-digital signals; and respectively performs delay adjustment on the PN parallel sub-digital signals again and then merges them, and determines whether the current delay-adjusted signal meets the first preset condition. If not, the current delay-adjusted signal is divided into P-(N+1) parallel sub-digital signals, and respectively performs delay adjustment on the P-(N+1) parallel sub-digital signals again and then merges them, and so on, wherein N∈[1, P-3], N is a positive integer, the value of N is 1 when the delay adjustment is performed again, and each delay adjustment increases by 1 until the current delay-adjusted signal meets the first preset condition, or until the value of N is equal to P-3, and the current delay-adjusted signal is output, wherein when the value of N is equal to P-3, the number of delay adjustments reaches the first preset threshold.

[0012] In a second aspect, an embodiment of the present application provides a signal processing system, the signal processing system comprising: Multi-phase DPD module, delay adjustment module and computing power scheduling optimization module; The multi-phase DPD module is used to obtain a digital signal to be processed; and send the digital signal to be processed to the delay adjustment module; The delay adjustment module is connected to the multi-phase DPD module, and is used to receive the digital signal to be processed, and perform delay adjustment on the digital signal to be processed to obtain a signal after the delay adjustment; and send the signal after the delay adjustment to the computing power scheduling optimization module; The computing power scheduling optimization module is connected to the multi-phase DPD module, and is used to receive the delay-adjusted signal, and output the delay-adjusted signal when the delay-adjusted signal meets a first preset condition; When the signal after the delay adjustment does not satisfy the first preset condition and does not satisfy the second preset condition, performing aliasing distortion compensation on the signal after the delay adjustment to obtain and output the aliasing distortion compensated signal; When the signal after the delay adjustment does not satisfy the first preset condition but satisfies the second preset condition, returning the signal after the delay adjustment to the multi-phase DPD module; The multi-phase DPD module is used to send the delay-adjusted signal to the delay adjustment module; The delay adjustment module is used to continue to perform at least one delay adjustment on the delay-adjusted signal until the computing power scheduling optimization module determines that the current delay-adjusted signal meets the first preset condition, or the number of delay adjustments reaches a first preset threshold, and the computing power scheduling optimization module outputs the current delay-adjusted signal; The first preset condition is that the sum of the mean square error between the current delay-adjusted signal and the preset target signal and the inverse of the signal-to-noise ratio of the current delay-adjusted signal is less than a second preset threshold; The second preset condition is that the signal-to-noise ratio of the signal after delay adjustment is greater than a third preset threshold.

[0013] Optionally, the multi-phase DPD module is further used to divide the digital signal to be processed into P parallel sub-digital signals; and send the P parallel sub-digital signals to the delay adjustment module, where P is a positive integer and is the number of multi-phase branches that the signal processing system can support; The delay adjustment module is used to receive the P parallel sub-digital signals, and perform delay adjustment on the P parallel sub-digital signals respectively and then merge them to obtain the delay-adjusted signal.

[0014] Optionally, the computing power scheduling optimization module includes: a judgment switching module and an aliasing distortion compensation module; The judgment switching module is connected to the delay adjustment module and the aliasing distortion compensation module, and is used to receive the delay-adjusted signal, and input the delay-adjusted signal to the aliasing distortion compensation module when the delay-adjusted signal does not meet the first preset condition and does not meet the second preset condition; The aliasing distortion compensation module is used to configure a preset filter order according to the aliasing distortion degree of the delay-adjusted signal; The delay-adjusted signal is subjected to aliasing distortion compensation by the filter to obtain an aliasing distortion compensated signal; and the aliasing distortion compensated signal is output.

[0015] Optionally, the aliasing distortion compensation module is further used to calculate the signal-to-noise ratio of the delay-adjusted signal; Normalizing the signal-to-noise ratio to obtain a normalized signal-to-noise ratio; Determining a target order of the filter according to the normalized signal-to-noise ratio and a preset maximum order of the filter, and adjusting a current order of the filter to the target order; Performing aliasing distortion compensation on the delay-adjusted signal based on the filter to obtain an aliasing distortion compensated signal; The higher the aliasing distortion degree is, the larger the target order of the filter is, and the lower the aliasing distortion degree is, the smaller the target order of the filter is.

[0016] Optionally, the multi-phase DPD module is connected to the judgment switching module, and is further used to receive the delay-adjusted signal returned by the judgment switching module when the judgment switching module determines that the delay-adjusted signal does not meet the first preset condition but meets the second preset condition; Dividing the delay-adjusted signal into PN parallel sub-digital signals; and sending the PN parallel sub-digital signals to the delay adjustment module; The delay adjustment module is used to receive the PN parallel sub-digital signals, and respectively perform delay adjustment on the PN parallel sub-digital signals and then merge them; and send the signal after the current delay adjustment to the judgment switching module; The judgment switching module is used to judge whether the signal after the current delay adjustment meets the first preset condition, and if not, send the signal after the current delay adjustment to the multi-phase DPD module again; The multi-phase DPD module is used to divide the current delay-adjusted signal into P-(N+1) parallel sub-digital signals and send them to the delay adjustment module; The delay adjustment module is used to perform delay adjustment on the P-(N+1) parallel sub-digital signals again and then merge them, and so on, wherein N∈[1, P-3], N is a positive integer, the value of N is 1 when the delay adjustment is performed again, and each delay adjustment is increased by 1 until the judgment switching module determines that the signal after the current delay adjustment meets the first preset condition, or until the value of N is equal to P-3, the judgment switching module outputs the signal after the current delay adjustment, wherein when the value of N is equal to P-3, the number of delay adjustments reaches the first preset threshold.

[0017] In a third aspect, an embodiment of the present application provides a network device, comprising: a processor, a memory, and a program stored in the memory and executable on the processor, wherein the program, when executed by the processor, implements the steps of a signal processing method as described in the first aspect.

[0018] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of a signal processing method as described in the first aspect are implemented.

[0019] In a fifth aspect, an embodiment of the present application provides a computer program product, comprising computer instructions, which, when executed by a processor, implement the steps of a signal processing method as described in the first aspect.

[0020] In the embodiments of the present application, through multi-level conditional judgment and dynamic adjustment, digital signals can be effectively processed and optimized to ensure that the final output signal meets the expected standards in quality and performance, and can improve the effect of digital pre-distortion and reduce hardware costs and power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present application. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings: Figure 1 A flowchart of a signal processing method provided in an embodiment of the present application; Figure 2 A flowchart of a signal processing method provided in an embodiment of the present application; Figure 3 A structural block diagram of a signal processing system provided in an embodiment of the present application; Figure 4 A structural block diagram of a signal processing system provided in an embodiment of the present application; Figure 5 A schematic diagram of the principle of achieving aliasing cancellation through delay adjustment in a dual-phase DPD module provided in an embodiment of the present application; Figure 6 A structural block diagram of a network device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0023] Figure 1 A signal processing method provided according to an embodiment of the present application is shown, and the method is applied to a signal processing system, and the method includes: Step S101: The signal processing system obtains a digital signal to be processed, and performs delay adjustment on the digital signal to be processed to obtain a signal after delay adjustment; In step S101, delay adjustment is performed on the digital signal to be processed, and the signal after delay adjustment is obtained, including: the signal processing system divides the digital signal to be processed into P parallel sub-digital signals; P is a positive integer, which is the number of multi-phase branches that the signal processing system can support; the signal processing system performs delay adjustment on the P parallel sub-digital signals respectively and then merges them to obtain the signal after delay adjustment.

[0024] Step S102: If the delay-adjusted signal meets a first preset condition, the signal processing system outputs the delay-adjusted signal; Step S103: If the signal after delay adjustment does not satisfy the first preset condition and does not satisfy the second preset condition, the signal processing system performs aliasing distortion compensation on the signal after delay adjustment to obtain and output the aliasing distortion compensated signal; In step S103, aliasing distortion compensation is performed on the delay-adjusted signal, and the aliasing distortion compensated signal is obtained and output, including: the signal processing system configures a preset filter order according to the aliasing distortion degree of the delay-adjusted signal; aliasing distortion compensation is performed on the delay-adjusted signal through the filter to obtain the aliasing distortion compensated signal; and the aliasing distortion compensated signal is output.

[0025] Step S104: if the signal after delay adjustment does not meet the first preset condition but meets the second preset condition, continue to perform at least one delay adjustment on the signal after delay adjustment until the current signal after delay adjustment meets the first preset condition or the number of delay adjustments reaches the first preset threshold, then output the current signal after delay adjustment; In step S104, continuing to perform at least one delay adjustment on the delay-adjusted signal until the current delay-adjusted signal satisfies the first preset condition, or the number of delay adjustments reaches a preset threshold, outputting the current delay-adjusted signal includes: the signal processing system divides the delay-adjusted signal into PN parallel sub-digital signals; and performs delay adjustment on the PN parallel sub-digital signals again and then merges them, and determines whether the current delay-adjusted signal satisfies the first preset condition. If not, the current delay-adjusted signal is divided into P-(N+1) parallel sub-digital signals, and performs delay adjustment on the P-(N+1) parallel sub-digital signals again and then merges them, and so on, wherein N∈[1, P-3], N is a positive integer, the value of N is 1 when the delay adjustment is performed again, and each delay adjustment increases by 1 until the current delay-adjusted signal satisfies the first preset condition, or until the value of N is equal to P-3, and outputting the current delay-adjusted signal, wherein when the value of N is equal to P-3, the number of delay adjustments reaches the first preset threshold.

[0026] It should be noted that the first preset condition is: the sum of the mean square error between the current delay-adjusted signal and the preset target signal and the inverse of the signal-to-noise ratio of the current delay-adjusted signal is less than the second preset threshold; the second preset condition is: the signal-to-noise ratio of the delay-adjusted signal is greater than the third preset threshold.

[0027] In one possible implementation, Figure 2 As shown, the signal processing system configures a preset filter order according to the aliasing distortion degree of the delay-adjusted signal, and performs aliasing distortion compensation on the delay-adjusted signal through the filter, and the aliasing distortion compensated signal includes: Step S201, the signal processing system calculates the signal-to-noise ratio of the signal after delay adjustment; Step S202: The signal processing system normalizes the signal-to-noise ratio to obtain a normalized signal-to-noise ratio; Step S203: The signal processing system determines a target order of the filter according to the normalized signal-to-noise ratio and a preset maximum order of the filter, and adjusts the current order of the filter to the target order; Step S204: the signal processing system performs aliasing distortion compensation on the delay-adjusted signal based on the filter to obtain an aliasing distortion compensated signal; The higher the aliasing distortion is, the larger the target order of the filter is, and the lower the aliasing distortion is, the smaller the target order of the filter is.

[0028] Through multi-level conditional judgment and dynamic adjustment, digital signals can be effectively processed and optimized to ensure that the final output signal meets the expected standards in quality and performance, and can improve the effect of digital pre-distortion and reduce hardware costs and power consumption.

[0029] Figure 3 A signal processing system 30 provided according to an embodiment of the present application is shown, and the signal processing system 30 includes: Multi-phase DPD module 301, delay adjustment module 302 and computing power scheduling optimization module 303; The multi-phase DPD module 301 is used to obtain the digital signal to be processed; and send the digital signal to be processed to the delay adjustment module 302; The delay adjustment module 302 is connected to the multi-phase DPD module 301, and is used to receive the digital signal to be processed, and perform delay adjustment on the digital signal to be processed to obtain a signal after the delay adjustment; and send the signal after the delay adjustment to the computing power scheduling optimization module 303; A computing power scheduling optimization module 303 is connected to the multi-phase DPD module 301, and is used to receive the delay-adjusted signal, and output the delay-adjusted signal when the delay-adjusted signal meets a first preset condition; When the signal after delay adjustment does not satisfy the first preset condition and does not satisfy the second preset condition, performing aliasing distortion compensation on the signal after delay adjustment to obtain and output the aliasing distortion compensated signal; When the signal after delay adjustment does not satisfy the first preset condition but satisfies the second preset condition, returning the signal after delay adjustment to the multi-phase DPD module 301; The multi-phase DPD module 301 is used to send the delay-adjusted signal to the delay adjustment module 302; The delay adjustment module 302 is used to continue to perform at least one delay adjustment on the delay-adjusted signal until the computing power scheduling optimization module 303 determines that the current delay-adjusted signal meets the first preset condition, or the number of delay adjustments reaches the first preset threshold, and the computing power scheduling optimization module 303 outputs the current delay-adjusted signal; The first preset condition is that the sum of the mean square error between the current delay-adjusted signal and the preset target signal and the inverse of the signal-to-noise ratio of the current delay-adjusted signal is less than the second preset threshold; The second preset condition is that the signal-to-noise ratio of the signal after the delay adjustment is greater than a third preset threshold.

[0030] In a possible implementation, the multi-phase DPD module 301 is further used to divide the digital signal to be processed into P parallel sub-digital signals; and send the P parallel sub-digital signals to the delay adjustment module 302, where P is a positive integer and is the number of multi-phase branches that the signal processing system 30 can support; The delay adjustment module 302 is used to receive P parallel sub-digital signals, and perform delay adjustment on the P parallel sub-digital signals respectively and then combine them to obtain a delay-adjusted signal.

[0031] In a possible implementation, the computing power scheduling optimization module 303 includes: a judgment switching module and an aliasing distortion compensation module; A judgment switching module, connected to the delay adjustment module 302 and to the aliasing distortion compensation module, for receiving the signal after delay adjustment, and inputting the signal after delay adjustment to the aliasing distortion compensation module when the signal after delay adjustment does not meet the first preset condition and does not meet the second preset condition; An aliasing distortion compensation module, used to configure a preset filter order according to the aliasing distortion degree of the delay-adjusted signal; The delay-adjusted signal is subjected to aliasing distortion compensation through a filter to obtain an aliasing distortion compensated signal; and the aliasing distortion compensated signal is output.

[0032] In a possible implementation, the aliasing distortion compensation module is also used to calculate the signal-to-noise ratio of the delay-adjusted signal; normalize the signal-to-noise ratio to obtain a normalized signal-to-noise ratio; determine the target order of the filter based on the normalized signal-to-noise ratio and a preset maximum order of the filter, and adjust the current order of the filter to the target order; perform aliasing distortion compensation on the delay-adjusted signal based on the filter to obtain an aliasing distortion compensated signal; wherein, the higher the degree of aliasing distortion, the larger the target order of the filter, and the lower the degree of aliasing distortion, the smaller the target order of the filter.

[0033] In a possible implementation, the multi-phase DPD module 301 is connected to the judgment switching module, and is also used to receive the delay-adjusted signal returned by the judgment switching module when the judgment switching module determines that the delay-adjusted signal does not meet the first preset condition but meets the second preset condition; divide the delay-adjusted signal into PN parallel sub-digital signals; send the PN parallel sub-digital signals to the delay adjustment module 302; the delay adjustment module 302 is used to receive the PN parallel sub-digital signals, and respectively perform delay adjustment on the PN parallel sub-digital signals again and then merge them; and send the current delay-adjusted signal to the judgment switching module; the judgment switching module is used to determine whether the current delay-adjusted signal meets the first preset condition, and if not, send the current delay-adjusted signal to the multi-phase DPD module 301 again; the multi-phase DPD module 301 is used to divide the current delay-adjusted signal into P-(N+1) parallel sub-digital signals, and send them to the delay adjustment module 302; the delay adjustment module 302 is used to respectively perform delay adjustment on the P-(N+1) parallel sub-digital signals again and then merge them, and so on, wherein, N∈[1, P-3], N is a positive integer, the value of N is 1 when the delay adjustment is performed again, and each delay adjustment increases by 1 until the judgment switching module determines that the signal after the current delay adjustment meets the first preset condition, or until the value of N is equal to P-3, the judgment switching module outputs the signal after the current delay adjustment, wherein when the value of N is equal to P-3, the number of delay adjustments reaches the first preset threshold.

[0034] It should be noted that the problem to be solved by the embodiments of the present application is to balance the computing power of high-precision digital pre-distortion processing, so as to optimize the system computing power while ensuring the effect of linear pre-distortion processing. Through the novel delay adjustment module and computing power scheduling optimization module, the algorithm execution efficiency is further improved, the hardware computing power application efficiency is improved, and the flexible loading of the computing power module is realized.

[0035] Figure 4 A signal processing system according to an embodiment of the present application is shown. Figure 4 As shown, the signal processing system is mainly composed of a multi-phase DPD module, a delay adjustment module, and a computing power scheduling optimization module, and the computing power scheduling optimization module can be divided into a judgment switching module and an aliasing distortion compensation module.

[0036] Now we introduce several main modules respectively: Multi-phase DPD module: The basic idea of ​​multi-phase is to divide the incoming data samples into multiple parallel signal processing chains. This module uses this idea to divide the input broadband digital signal x(n) into p parallel narrowband signals [x1(n), x2(n)...xp(n)] for digital pre-distortion processing to achieve the purpose of reducing the sampling rate. The size of the downsampling rate is determined by P.

[0037] like Figure 4 As shown, this module receives the signal S1 transmitted by the computing power scheduling optimization module, and decides whether to adjust the sampling rate based on S1. If S1=1, it is considered that the signal processing system has serious aliasing, and the signal branches should be reduced and the sampling rate should be increased. At this time, p=qL*S1 is calculated, where the initial value of L is set to 0. Each time the cycle judges that S1=1, the L value is increased by 1, that is, L=L+1; q is the maximum number of multi-phase branches that the system can support, and p=q at the first processing; the minimum threshold of the P value is designed to be 2. If qL*S1<2 is calculated, P=2 is assigned.

[0038] If S1=0, the computing power scheduling optimization module determines that the output meets the system requirements. At this time, the size of P is fixed and subsequent work is performed at a stable sampling rate.

[0039] Since the signal will generate partial aliasing distortion during the low sampling parallel processing, the p parallel signals are input into the delay adjustment module to separate the aliasing distortion from the desired signal.

[0040] Delay adjustment module: This module dynamically adjusts the delay of p parallel signals [x1(n), x2(n)…xp(n)] transmitted by the multi-phase DPD module to obtain signals [y1(n-Δ1), y2(n-Δ2)…yp(n-Δp)], linearly adds the delayed signals to obtain signal y(n), and outputs it to the computing power scheduling optimization module for processing, where Δ is only related to p.

[0041] This module uses a variable tap delay filter (Delay Adjustment Filter, DAF) to achieve dynamic adjustment of signal delay. The variable tap delay filter has the advantages of high real-time performance, parallel processing, and fine delay control. By setting the filter tap, it is possible to ensure appropriate group delay and a relatively flat amplitude response within the linearization bandwidth. The variable tap delay filter can generate signals with different delays in different branches according to the signal characteristics, prepare for subsequent aliasing cancellation, and reduce additional distortion while accurately adjusting the group delay. The specific implementation is as follows: Taking the bi-phase DPD as an example, delay adjustment is used to achieve aliasing cancellation. There is an additional group delay in the parallel signal component. The delay adjustment filter is used to reverse the influence of the group delay, and a linear combination of the desired component and the aliasing component is obtained in the upper branch. In the lower branch, the aliasing component will have a 180° phase shift after adjustment. Therefore, after adjusting the group delay, the signal can be directly output to the parallel signal summing output module. After the parallel signals are added, the aliasing distortion will be offset and the desired signal component will be obtained, such as Figure 5 shown.

[0042] The obtained parallel expected signal components [y1(n-Δ1), y2(n-Δ2)…yp(n-Δp)] are linearly added to obtain y(n) and passed to the computing power scheduling optimization module for processing, that is, y(n)=y1(n-Δ1)+y2(n-Δ2)+…+yp(n-Δp).

[0043] Since the coefficients of the filter do not change with the input signal characteristics of the power amplifier (PA) and are only related to the downsampling rate (coefficient P), the multi-phase DPD module and the delay adjustment module can be run offline to determine the sampling rate and dynamic delay adjustment coefficient in advance according to the system performance requirements. In actual implementation, P and Δ can be regarded as constants. Under specific signal bandwidth and system performance requirements, the design of the downsampling rate P and the dynamic delay adjustment Δ can strike a balance between system performance and complexity, thereby reducing the overall computational complexity and design cost.

[0044] Computing power scheduling optimization module: This module monitors the output y(n) of the delay adjustment module in real time, and decides whether to continue the aliasing distortion compensation process and whether to adjust the downsampling rate according to the set judgment criteria. The design concept of this module is based on the precise control of system stability and the optimal configuration of computing resources, and dynamically adjusts the allocation of computing resources to achieve the best digital pre-distortion effect.

[0045] This module is divided into two parts: aliasing distortion compensation module and switching judgment module.

[0046] Switching judgment module: In the design of this module, a designable threshold is introduced to determine whether the system needs to adjust the downsampling rate and compensate for aliasing distortion.

[0047] This module receives the output y(n) of the delay adjustment module, obtains the signal S1 according to the mean square error between y(n) and the ideal output t(n) and the signal-to-noise ratio of y(n), and outputs it to the multi-phase DPD module to determine whether the system needs further sampling adjustment. If not, it outputs the signal y(n). If sampling adjustment is required, it further calculates the signals S2 and S3 and outputs them to the aliasing distortion compensation module. It determines whether aliasing distortion compensation is required according to S2. If aliasing distortion compensation is required, the filter order is configured according to the S3 signal size. The specific implementation is as follows: Calculate the mean square error of y(n) and t(n) to verify whether the output y(n) of the delay adjustment module can ensure that signal information is not lost. The calculation method is as follows: , The smaller the mean square error, the closer y(n) is to the ideal output.

[0048] Calculate the signal-to-noise ratio of y(n) to verify whether the delay adjustment module achieves precise cancellation of aliasing. The calculation method is as follows: , where Ps is the useful signal power and Pn is the noise power. In practical applications, it is desirable to have a smaller MSE and a larger SNR. Therefore, the judgment switch for designing the delay adjustment module is T1 = MSE + 1 / SNR. If T1 < m, it is considered that the output y(n) of the delay adjustment module meets the system output requirements. S1 is assigned a value of 0, that is, the fixed signal sampling rate and the delay state Δ. S2 is assigned a value of 0, that is, no further aliasing distortion compensation is required, avoiding unnecessary computational overhead, thus saving a large amount of computing power resources and directly outputting the signal y(n). m represents the designable threshold, which can be flexibly designed according to the actual capabilities of the circuit and the requirements of the application scenario. If T1 > m, it is considered that the output y(n) of the delay adjustment module does not meet the system output requirements. S1 is assigned a value of 1, that is, the polyphase DPD module and the delay adjustment module need to be further adjusted. At this time, compare the signal-to-noise ratio SNR calculated from the output y(n) of the delay adjustment module with the minimum acceptable signal-to-noise ratio SNRmin of the system. If SNR > SNRmin, it is considered that no anti-aliasing processing is required and S2 is assigned a value of 0. At this time, the system does not output the signal and continues to perform sampling rate and delay adjustment. If SNR < SNRmin, S2 is assigned a value of 1, and the signal y(n) is transmitted to the aliasing distortion compensation module for processing, triggering the calculation of S3, which is used to determine the order of the filter in the aliasing distortion compensation module. The order of the filter in the aliasing distortion compensation module is determined by the noise level of y(n). If the signal-to-noise ratio of y(n) is close to the minimum acceptable signal-to-noise ratio of the system at this time, the order of the filter in the aliasing distortion compensation is reduced. If the signal-to-noise ratio difference is large from the minimum acceptable signal-to-noise ratio of the system at this time, the order of the filter in the aliasing distortion compensation is increased for fine-grained anti-aliasing filtering. The specific implementation method is as follows: Normalize the signal-to-noise ratio calculated from the output y(n) of the delay adjustment module: , where SNRmin is the minimum acceptable signal-to-noise ratio of the system, S3 = round(T2 × P), where round represents taking an integer and P represents the maximum order of the filter in the aliasing distortion compensation module. Although the design of this module consumes a certain amount of computing power resources, it can, to a certain extent, reduce unnecessary computational burdens while ensuring the accuracy of the output results and saving overall computing resources.

[0049] Aliasing distortion compensation module: This module adopts a configurable filter order design, and configures the filter order according to the degree of aliasing distortion of the system. This design can avoid unnecessary computational overhead, thereby saving a lot of computing resources. According to the signals S2 and S3 transmitted from the switching judgment submodule, y(n) is subjected to anti-aliasing filtering and the signal z(n) is output. The specific implementation is as follows: This module uses a variable order filter for anti-aliasing filtering, and monitors the signal S2 transmitted from the switching judgment submodule in real time. If S2=0, this module does not work. If S2=1, it receives the signal S3 and y(n) transmitted from the switching judgment submodule, configures the filter order according to the size of S3, performs anti-aliasing filtering on the signal y(n), and outputs the signal z(n) after processing. The design of this module is mainly to flexibly call the anti-aliasing filter module according to the actual needs of the system, rather than forcing anti-aliasing filtering in all cases, and to flexibly configure the filter order according to system requirements. This design can not only reduce unnecessary computational burden, but also help reduce hardware power consumption and cost. The released computing resources can be invested in other key DFE (Decision Feedback Equalization) processes to further improve the overall performance and computing power utilization of the system.

[0050] In general, the design of the computing power scheduling optimization module fully considers the stability of the system and the optimal configuration of computing power resources. Through real-time monitoring and dynamic adjustment, it not only helps to improve the effect of digital pre-distortion, but also reduces the cost and power consumption of hardware. This is of great significance to improving the overall performance and reliability of the system.

[0051] The present application embodiment provides a network device 60, such as Figure 6 As shown, the network device 60 includes: a processor 601, a memory 602, and a program stored in the memory 602 and executable on the processor 601. When the program is executed by the processor 601, the steps of the signal processing method shown in the above embodiment are implemented.

[0052] The embodiment of the present application also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the signal processing method shown in the above embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, it is not repeated here. The computer-readable storage medium is, for example, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0053] An embodiment of the present application also provides a computer program product, including computer instructions, which, when executed by a processor, implement the steps of the above-mentioned signal processing method and can achieve the same technical effect. To avoid repetition, they are not described here.

[0054] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0055] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0056] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A signal processing method, characterized in that: The method is applied to a signal processing system, and the method comprises: The signal processing system acquires a digital signal to be processed, and performs delay adjustment on the digital signal to be processed to obtain a signal after delay adjustment; If the delay-adjusted signal satisfies a first preset condition, the signal processing system outputs the delay-adjusted signal; If the delay-adjusted signal does not satisfy the first preset condition and does not satisfy the second preset condition, the signal processing system performs aliasing distortion compensation on the delay-adjusted signal to obtain and output the aliasing distortion compensated signal; If the delay-adjusted signal does not satisfy the first preset condition but satisfies the second preset condition, continue to perform at least one delay adjustment on the delay-adjusted signal until the current delay-adjusted signal satisfies the first preset condition, or the number of delay adjustments reaches a first preset threshold, outputting the current delay-adjusted signal; The first preset condition is that the sum of the mean square error between the current delay-adjusted signal and the preset target signal and the inverse of the signal-to-noise ratio of the current delay-adjusted signal is less than a second preset threshold; The second preset condition is that the signal-to-noise ratio of the signal after delay adjustment is greater than a third preset threshold.

2. The method according to claim 1, characterized in that The delay adjustment of the digital signal to be processed to obtain a signal after the delay adjustment comprises: The signal processing system divides the digital signal to be processed into P parallel sub-digital signals; P is a positive integer, which is the number of multi-phase branches that the signal processing system can support; The signal processing system performs delay adjustment on the P parallel sub-digital signals respectively and then combines them to obtain the delay-adjusted signal.

3. The method according to claim 1, characterized in that Performing aliasing distortion compensation on the delay-adjusted signal to obtain and output the aliasing distortion compensated signal includes: The signal processing system configures a preset filter order according to the aliasing distortion degree of the delay-adjusted signal; The delay-adjusted signal is subjected to aliasing distortion compensation by the filter to obtain an aliasing distortion compensated signal; and the aliasing distortion compensated signal is output.

4. The method according to claim 3, characterized in that The signal processing system configures a preset filter order according to the aliasing distortion degree of the delay-adjusted signal, and performs aliasing distortion compensation on the delay-adjusted signal through the filter to obtain the aliasing distortion compensated signal, including: The signal processing system calculates a signal-to-noise ratio of the delay-adjusted signal; The signal processing system normalizes the signal-to-noise ratio to obtain a normalized signal-to-noise ratio; The signal processing system determines a target order of the filter according to the normalized signal-to-noise ratio and a preset maximum order of the filter, and adjusts a current order of the filter to the target order; The signal processing system performs aliasing distortion compensation on the delay-adjusted signal based on the filter to obtain an aliasing distortion compensated signal; The higher the aliasing distortion degree is, the larger the target order of the filter is, and the lower the aliasing distortion degree is, the smaller the target order of the filter is.

5. The method according to claim 2, characterized in that: Continuing to perform at least one delay adjustment on the delay-adjusted signal until the current delay-adjusted signal meets the first preset condition, or the number of delay adjustments reaches a preset threshold, outputting the current delay-adjusted signal includes: The signal processing system divides the delay-adjusted signal into PN parallel sub-digital signals; and respectively performs delay adjustment on the PN parallel sub-digital signals again and then merges them, and determines whether the current delay-adjusted signal meets the first preset condition. If not, the current delay-adjusted signal is divided into P-(N+1) parallel sub-digital signals, and respectively performs delay adjustment on the P-(N+1) parallel sub-digital signals again and then merges them, and so on, wherein N∈[1, P-3], N is a positive integer, the value of N is 1 when the delay adjustment is performed again, and each delay adjustment increases by 1 until the current delay-adjusted signal meets the first preset condition, or until the value of N is equal to P-3, and the current delay-adjusted signal is output, wherein when the value of N is equal to P-3, the number of delay adjustments reaches the first preset threshold.

6. A signal processing system, characterized in that: The signal processing system comprises: Multi-phase DPD module, delay adjustment module and computing power scheduling optimization module; The multi-phase DPD module is used to obtain a digital signal to be processed; and send the digital signal to be processed to the delay adjustment module; The delay adjustment module is connected to the multi-phase DPD module, and is used to receive the digital signal to be processed, and perform delay adjustment on the digital signal to be processed to obtain a signal after the delay adjustment; and send the signal after the delay adjustment to the computing power scheduling optimization module; The computing power scheduling optimization module is connected to the multi-phase DPD module, and is used to receive the delay-adjusted signal, and output the delay-adjusted signal when the delay-adjusted signal meets a first preset condition; When the signal after the delay adjustment does not satisfy the first preset condition and does not satisfy the second preset condition, performing aliasing distortion compensation on the signal after the delay adjustment to obtain and output the aliasing distortion compensated signal; When the signal after the delay adjustment does not satisfy the first preset condition but satisfies the second preset condition, returning the signal after the delay adjustment to the multi-phase DPD module; The multi-phase DPD module is used to send the delay-adjusted signal to the delay adjustment module; The delay adjustment module is used to continue to perform at least one delay adjustment on the delay-adjusted signal until the computing power scheduling optimization module determines that the current delay-adjusted signal meets the first preset condition, or the number of delay adjustments reaches a first preset threshold, and the computing power scheduling optimization module outputs the current delay-adjusted signal; The first preset condition is that the sum of the mean square error between the current delay-adjusted signal and the preset target signal and the inverse of the signal-to-noise ratio of the current delay-adjusted signal is less than a second preset threshold; The second preset condition is that the signal-to-noise ratio of the signal after delay adjustment is greater than a third preset threshold.

7. The system according to claim 6, characterized in that The multi-phase DPD module is further used to divide the digital signal to be processed into P parallel sub-digital signals; and send the P parallel sub-digital signals to the delay adjustment module, where P is a positive integer and is the number of multi-phase branches that the signal processing system can support; The delay adjustment module is used to receive the P parallel sub-digital signals, and perform delay adjustment on the P parallel sub-digital signals respectively and then merge them to obtain the delay-adjusted signal.

8. The system according to claim 6, characterized in that The computing power scheduling optimization module includes: a judgment switching module and an aliasing distortion compensation module; The judgment switching module is connected to the delay adjustment module and the aliasing distortion compensation module, and is used to receive the delay-adjusted signal, and input the delay-adjusted signal to the aliasing distortion compensation module when the delay-adjusted signal does not meet the first preset condition and does not meet the second preset condition; The aliasing distortion compensation module is used to configure a preset filter order according to the aliasing distortion degree of the delay-adjusted signal; The delay-adjusted signal is subjected to aliasing distortion compensation by the filter to obtain an aliasing distortion compensated signal; and the aliasing distortion compensated signal is output.

9. The system according to claim 8, characterized in that The aliasing distortion compensation module is further used to calculate the signal-to-noise ratio of the delay-adjusted signal; Normalizing the signal-to-noise ratio to obtain a normalized signal-to-noise ratio; Determining a target order of the filter according to the normalized signal-to-noise ratio and a preset maximum order of the filter, and adjusting a current order of the filter to the target order; Performing aliasing distortion compensation on the delay-adjusted signal based on the filter to obtain an aliasing distortion compensated signal; The higher the aliasing distortion degree is, the larger the target order of the filter is, and the lower the aliasing distortion degree is, the smaller the target order of the filter is.

10. The system according to claim 8, characterized in that The multi-phase DPD module is connected to the judgment switching module, and is also used to receive the delay-adjusted signal returned by the judgment switching module when the judgment switching module determines that the delay-adjusted signal does not meet the first preset condition but meets the second preset condition; Dividing the delay-adjusted signal into PN parallel sub-digital signals; and sending the PN parallel sub-digital signals to the delay adjustment module; The delay adjustment module is used to receive the PN parallel sub-digital signals, and respectively perform delay adjustment on the PN parallel sub-digital signals and then merge them; and send the signal after the current delay adjustment to the judgment switching module; The judgment switching module is used to judge whether the signal after the current delay adjustment meets the first preset condition, and if not, send the signal after the current delay adjustment to the multi-phase DPD module again; The multi-phase DPD module is used to divide the current delay-adjusted signal into P-(N+1) parallel sub-digital signals and send them to the delay adjustment module; The delay adjustment module is used to perform delay adjustment on the P-(N+1) parallel sub-digital signals again and then merge them, and so on, wherein N∈[1, P-3], N is a positive integer, the value of N is 1 when the delay adjustment is performed again, and each delay adjustment is increased by 1 until the judgment switching module determines that the signal after the current delay adjustment meets the first preset condition, or until the value of N is equal to P-3, the judgment switching module outputs the signal after the current delay adjustment, wherein when the value of N is equal to P-3, the number of delay adjustments reaches the first preset threshold.

11. A network device, characterized in that: include: A processor, a memory, and a program stored in the memory and executable on the processor, wherein when the program is executed by the processor, the steps of a signal processing method according to any one of claims 1 to 5 are implemented.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of a signal processing method according to any one of claims 1 to 5 are implemented.

13. A computer program product, characterized in that The method comprises computer instructions, which, when executed by a processor, implement the steps of a signal processing method as claimed in any one of claims 1 to 5.

Images