A method and apparatus for detecting protocol bit errors in a can bus controller

Abstract

The application discloses a CAN bus controller protocol bit error detection method and device, simulates a CAN bus network based on an integrated circuit automatic test equipment (ATE), designs a simulation system, simulates normal function logic of a to-be-tested CAN bus controller, simulates bit error logic, and then utilizes the ATE to efficiently realize normal function verification and bit error detection of the to-be-tested CAN bus controller. The technical problem that whether the CAN bus controller can effectively identify and handle bit errors when the CAN bus causes bit flip due to electromagnetic interference, improper wiring or other reasons is effectively solved, so that the situation that the whole bus system is abnormal or paralyzed due to untimely error handling is prevented.

Description

Technical Field

[0001] This invention relates to the field of aerospace component quality assurance and testing technology, and in particular to a method and apparatus for detecting CAN bus controller protocol bit errors. Background Technology

[0002] Since its inception, the CAN bus has been widely used in the automotive industry and industrial automation. In recent years, with the increasing demands for switching speed and component standardization in aerospace electronic systems, it has gradually penetrated into aerospace engineering. Its most significant feature is the elimination of traditional station address encoding, replacing it with encoding of communication data. Through message filtering, it can achieve various data transmission methods such as point-to-point, multi-point, and broadcast. The entire network connects all nodes through two lines, with no limit on the number of nodes. Each node can actively send messages, and the communication rate can reach up to 1 Mbps. The most important component in the entire CAN bus network is the CAN bus controller, which implements the entire CAN communication protocol, including frame ID, frame data, frame format, frame type, CRC check, processing procedures, and response detection. This allows CAN bus nodes to only need to consider the communication between the microprocessor and the CAN bus controller when connecting, greatly improving system design efficiency. However, this design also means that all anomalies and errors on the CAN bus need to be identified and handled by the CAN bus controller. Therefore, it is urgent to test and verify the error identification and handling capabilities of the CAN bus controller to prevent the entire bus system from malfunctioning or paralyzing due to untimely error handling.

[0003] Due to the complex and diverse on-site environment, the CAN bus inevitably encounters various interference factors, among which bit errors are the most common. A bit error refers to a bit flipping phenomenon caused by electromagnetic interference, improper wiring, or other reasons, resulting in a discrepancy between the information received by the receiver and the original information sent by the sender. If this error is not identified in time, it not only affects communication quality but may also cause system malfunctions in severe cases, becoming a channel for attackers to compromise the system. Summary of the Invention

[0004] The technical problem solved by this invention is to overcome the shortcomings of the prior art and provide a method and device for detecting bit errors in the CAN bus controller protocol, thereby verifying whether the CAN bus controller has a vulnerability that cannot be identified due to bit errors.

[0005] The technical solution of the present invention is: 1. A method for detecting protocol bit errors in a CAN bus controller, comprising the following steps:

[0006] (1) Set up the hardware environment, simulate the CAN bus network through ATE, and connect the CAN bus controller under test to ATE through the test interface board;

[0007] (2) Design and implement a simulation system to simulate the normal functional logic of the CAN bus controller under test, simulate bit error logic, and generate VCD files and simulation waveforms; the VCD files include VCD files generated based on the normal functional logic or VCD files generated after injecting bit error logic into the normal functional logic;

[0008] (3) According to the vector format required by ATE, convert the VCD file generated according to the normal function logic into a test vector. After verifying that the CAN bus controller under test is running normally, convert the VCD file generated after injecting bit error logic into the normal function logic into a test vector, import it into ATE, trigger the CAN bus controller under test, and collect the output waveform of the CAN bus controller.

[0009] (4) Compare and analyze the simulation waveform and the output waveform to determine the response of the CAN bus controller to bit errors and obtain the detection results.

[0010] Furthermore, in step (1), the ATE simulates the CAN bus network, including simulating a microprocessor to provide upstream control information to the CAN bus controller and simulating a bus transceiver to provide a data transmission channel to the CAN bus controller.

[0011] Furthermore, in step (2), the input and output signal characteristics of the CAN bus controller under test are analyzed according to the different functional items of the CAN bus controller under test, and the simulation program of the normal function logic and the simulated bit error logic of the CAN bus controller under test is written using Verilog language.

[0012] Furthermore, in step (2), the simulated waveform is the normal simulated waveform output by the CAN bus controller when it effectively identifies and processes the bit error, or the erroneous simulated waveform output by the CAN bus controller when it fails to effectively identify and process the bit error.

[0013] Furthermore, in step (3), the operation verification of the CAN bus controller includes verifying the parameters and functions of the CAN bus controller. The parameter verification includes DC parameters and AC parameters, and the function verification is the normal function verification. The specific verification method is as follows: According to the datasheet of the CAN bus controller, the Level, Timing and test program are defined on the ATE. The VCD file without bit error logic is obtained by using the simulation system, converted into a test vector, imported into the ATE, and the CAN bus controller under test is triggered. If the output waveform of the CAN bus controller under test is normal, the verification is passed.

[0014] Furthermore, different specific error logics were simulated and tested sequentially on the CAN bus controller under test.

[0015] The present invention also provides a CAN bus controller protocol bit error detection device, comprising:

[0016] ATE is used to simulate a CAN bus network; it triggers the CAN bus controller under test according to the test vector.

[0017] Test interface board, used to connect ATE and CAN bus controller under test;

[0018] The simulation system is used to simulate the normal functional logic of the CAN bus controller under test and to simulate bit error logic, generating a VCD file; the VCD file includes a VCD file generated based on the normal functional logic, or a VCD file generated after injecting bit error logic into the normal functional logic; it is also used to generate simulation waveforms;

[0019] The vector conversion tool is used to convert VCD files into test vectors according to the vector format required by ATE, and then import them into ATE.

[0020] The comparative analysis tool is used to compare and analyze the output waveform of the CAN bus controller with the simulation waveform generated by the simulation system, to determine the CAN bus controller's response to bit errors, and to obtain the detection results.

[0021] Furthermore, in the ATE, the ATE simulates a CAN bus network, including simulating a microprocessor to provide upstream control information to the CAN bus controller, and simulating a bus transceiver to provide a data transmission channel to the CAN bus controller.

[0022] Furthermore, in the simulation system, based on the different functional items of the CAN bus controller under test, the characteristics of its input and output signals are analyzed, and simulation programs for the normal functional logic and simulated bit error logic of the CAN bus controller under test are written using Verilog language; the generated simulation waveforms are normal simulation waveforms output by the CAN bus controller when it effectively identifies and processes bit errors, or error simulation waveforms output by the CAN bus controller when it fails to effectively identify and process bit errors.

[0023] Furthermore, the simulation system simulates different specific bit error logics; the comparative analysis tool compares and analyzes the output waveform of the CAN bus controller with the simulation waveform generated by the simulation system to determine whether the CAN bus controller under test can effectively identify and process a certain bit error logic, and thus detect whether it has a vulnerability that cannot correctly detect a certain bit error.

[0024] The advantages of this invention compared to the prior art are:

[0025] (1) The method proposed in this invention does not establish an actual CAN bus network when testing the CAN bus controller under test. Instead, it simulates the CAN bus network based on the automatic test equipment (ATE) for integrated circuits, that is, it simulates the operating environment of the CAN bus controller. There is no need to design upstream and downstream circuits and different nodes to build the CAN bus network. By designing a simulation system, the normal functional logic of the CAN bus controller under test is simulated and the bit error logic is simulated. Then, the ATE is used to efficiently realize the normal verification and bit error detection of the CAN bus controller under test.

[0026] (2) The architecture of the device proposed in this invention is universal, and there is no need to design CAN bus controllers from different manufacturers from scratch; the ATE can detect the operating status of all pins on the bus controller in real time and can easily inject errors; during the in-place error vulnerability detection process, this device can completely control the entire test process and avoid interference to other nodes in the actual network. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the device of the present invention. Detailed Implementation

[0028] To better understand the technical solution of the present invention, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0029] The CAN bus controller protocol bit error detection method proposed in this invention mainly includes the following steps:

[0030] (1) Setting up the hardware environment

[0031] The CAN bus network is simulated using an ATE (Automatic Test Equipment). The CAN bus controller under test is connected to the ATE via a test interface board. Since no actual CAN bus network exists in this invention, both the upstream processing circuitry and the downstream bus transceiver are simulated by the ATE. The ATE not only simulates the microprocessor providing upstream control information to the CAN bus controller, but also simulates the bus transceiver providing a data transmission channel to the CAN bus controller, ensuring the normal operation of the CAN bus controller.

[0032] Reference Figure 1 As shown, the CAN bus controller is connected to the ATE (Automatic Test Equipment) via a test interface board. Each pin of the CAN bus controller under test is connected to a designated channel on the ATE, and the connection is made on the test interface board using a non-destructive testing fixture. Oscilloscope test points are deployed on the relevant pins of the CAN bus controller under test on the test interface board (for some advanced ATE systems, the waveform capture software provided with the equipment can be used).

[0033] (2) Design and implement the simulation system

[0034] The simulation system can simulate the normal functional logic of the CAN bus controller, as well as specific bit error logic. By running the simulation system, VCD files and simulation waveforms can be generated. The VCD file can be the VCD file corresponding to the normal functional logic or the VCD file corresponding to the normal functional logic after bit error logic is injected. The simulation waveform can be the normal simulation waveform output by the CAN bus controller when it effectively recognizes and processes bit errors, or the error simulation waveform output by the CAN bus controller when it fails to effectively recognize and process bit errors.

[0035] Specifically, simulation programs for driving the normal function logic and bit error logic of the CAN bus controller are implemented using the Verilog high-level programming language. The different functions of the CAN bus controller can be divided into various sub-modules. The simulation program mainly focuses on the design of input and output signals for different functions. Based on the different functional items of the CAN bus controller under test, its input and output signal characteristics are analyzed to write simulation programs that simulate the normal function logic and bit error logic of the CAN bus controller under test. The internal logic circuits of the CAN bus controller can be treated as a "black box".

[0036] (3) Obtain test vectors

[0037] The simulation system generates VCD files using a vector conversion tool, which are then converted into the test vectors required by the corresponding ATE (Automatic Test Equipment) and imported into the ATE.

[0038] Different manufacturers' ATE test equipment, such as Teradyne and Advantest, have different test software and test vector formats. During the conversion process, the tools selected or the code written depends on the specific test equipment.

[0039] (4) Parameter and Function Test

[0040] Since this invention does not have actual CAN bus network support, the DC parameters, AC parameters, and normal functional logic of the CAN bus controller need to be verified before bit error vulnerability detection. Once all the above tests are passed, it indicates that the CAN bus controller under test can operate normally in this environment.

[0041] The specific verification method is as follows: According to the datasheet of the CAN bus controller, define the Level, Timing and test program on the ATE, use the simulation system to obtain the VCD file without injecting bit error logic, convert it into test vectors, import it into the ATE, trigger the CAN bus controller under test, and if the output waveform of the CAN bus controller under test is normal, the verification is passed.

[0042] (5) Bit error vulnerability detection

[0043] After verifying that the CAN bus controller is operating normally, the simulation system is run according to the vector format required by the ATE, bit error logic is injected into the normal functional logic, the corresponding VCD file is generated, the VCD file is converted into test vectors, imported into the ATE, the CAN bus controller under test is triggered, and the output waveform of the CAN bus controller is collected.

[0044] (6) Analysis of test results

[0045] Compare and analyze the simulated waveform and the output waveform to determine the CAN bus controller's response to bit errors and whether there are any differences between them. If there are differences (when the simulated waveform is a normal simulated waveform output by the CAN bus controller effectively identifying and processing bit errors), it indicates that the CAN bus controller under test cannot identify the current bit error and has a detection vulnerability for this bit error.

[0046] For example, in the non-arbitration zone, the CAN bus controller's transmission of "00001" and reception of "00000" cannot be recognized as an "error" (bit error), which is inconsistent with the description in the manual and relevant standards. Specifically, when tx_0 sends a 1 and rx_0 is 0, the simulation waveform judges it as a bit misalignment. After this moment, tx_0 should send an error frame of "6 consecutive 0s", and the interrupt int_n should be pulled low, meeting the bit error detection function requirements in the ISO11898-1 protocol. However, the execution process of the CAN bus controller under test is that tx_0 continues to send a frame of "01", and then the interrupt int_n is pulled low.

[0047] For the remaining bit error identification test, repeat steps (5) and (6) to complete the detection.

[0048] The present invention also provides a CAN bus controller protocol bit error detection device, which can be referred to Figure 1 It includes the following components:

[0049] ATE is used to simulate a CAN bus network; it triggers the CAN bus controller under test according to the test vector.

[0050] Test interface board, used to connect ATE and CAN bus controller under test;

[0051] The simulation system is used to simulate the normal functional logic of the CAN bus controller under test and to simulate bit error logic, generating a VCD file; the VCD file includes a VCD file generated based on the normal functional logic, or a VCD file generated after injecting bit error logic into the normal functional logic; it is also used to generate simulation waveforms;

[0052] The vector conversion tool is used to convert VCD files into test vectors according to the vector format required by ATE, and then import them into ATE.

[0053] The comparative analysis tool is used to compare and analyze the output waveform of the CAN bus controller with the simulation waveform generated by the simulation system, to determine the CAN bus controller's response to bit errors, and to obtain the detection results.

[0054] Specifically, in ATE, ATE simulates the CAN bus network, including simulating a microprocessor to provide upstream control information to the CAN bus controller, and simulating a bus transceiver to provide a data transmission channel to the CAN bus controller.

[0055] Specifically, in the simulation system, based on the different functional items of the CAN bus controller under test, the characteristics of its input and output signals are analyzed, and simulation programs are written in Verilog language to simulate the normal functional logic and bit error logic of the CAN bus controller under test. The generated simulation waveforms are the normal simulation waveforms output by the CAN bus controller when it effectively identifies and processes bit errors, or the error simulation waveforms output by the CAN bus controller when it fails to effectively identify and process bit errors.

[0056] Specifically, the simulation system simulates different specific bit error logics; the comparative analysis tool compares and analyzes the output waveform of the CAN bus controller with the simulation waveform generated by the simulation system to determine whether the CAN bus controller under test can effectively identify and process a certain bit error logic, and thus detect whether it has a vulnerability that cannot correctly detect a certain bit error.

[0057] It is understood that this invention has been described through embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of this invention. Furthermore, under the teachings of this invention, these features and embodiments can be modified to adapt to specific circumstances without departing from the spirit and scope of this invention. Therefore, this invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are protected by this invention.

[0058] The contents not described in detail in this specification are common knowledge to those skilled in the art.

Claims

1. A method for detecting protocol bit errors in a CAN bus controller, characterized in that, Includes the following steps: Set up the hardware environment, simulate a CAN bus network through ATE, and connect the CAN bus controller under test to ATE through the test interface board; wherein, the ATE simulates the CAN bus network, including simulating a microprocessor to provide upstream control information to the CAN bus controller, and simulating a bus transceiver to provide a data transmission channel to the CAN bus controller; Design and implement a simulation system. The simulation system is based on a simulation program written in Verilog language to simulate the normal functional logic of the CAN bus controller under test and to simulate different specific protocol bit error logics, generating VCD files and simulation waveforms. The VCD files include VCD files generated based on the normal functional logic or VCD files generated after injecting protocol bit error logic into the normal functional logic. The simulation waveforms are normal simulation waveforms output by the CAN bus controller when it effectively identifies and processes protocol bit errors, or error simulation waveforms output by the CAN bus controller when it fails to effectively identify and process protocol bit errors. According to the vector format required by ATE, the VCD file generated according to the normal functional logic is converted into test vectors. After verifying that the CAN bus controller under test is running normally, the VCD file generated after injecting protocol bit error logic into the normal functional logic is converted into test vectors, imported into ATE, and the CAN bus controller under test is triggered to collect the output waveform of the CAN bus controller. By comparing and analyzing the simulated waveform and the output waveform, the response of the CAN bus controller to protocol bit errors is determined, the detection results are obtained, and it is determined whether there is a vulnerability in that it cannot correctly detect a certain protocol bit error.

2. The CAN bus controller protocol bit error detection method according to claim 1, characterized in that: The operational verification of the CAN bus controller includes verifying its parameters and functions. Parameter verification includes both DC and AC parameters, while functional verification is a normal function verification. The specific verification method is as follows: According to the CAN bus controller's datasheet, define the Level, Timing, and test program on the ATE (Automatic Test Equipment). Use a simulation system to obtain a VCD file without injecting protocol bit error logic, convert it into a test vector, import it into the ATE, and trigger the CAN bus controller under test. If the output waveform of the CAN bus controller under test is normal, the verification is successful.

3. A CAN bus controller protocol bit error detection device, characterized in that, include: ATE is used to simulate a CAN bus network, including simulating a microprocessor to provide upstream control information to the CAN bus controller and simulating a bus transceiver to provide a data transmission channel to the CAN bus controller. Trigger the CAN bus controller under test according to the test vector; Test interface board, used to connect ATE and CAN bus controller under test; The simulation system, based on a Verilog program, simulates the normal functional logic of the CAN bus controller under test and different specific protocol bit error logics, generating VCD files and simulation waveforms. The VCD files include those generated based on the normal functional logic or those generated after injecting protocol bit error logic into the normal functional logic. The simulation waveforms are normal simulation waveforms output by the CAN bus controller when it effectively identifies and processes protocol bit errors, or error simulation waveforms output by the CAN bus controller when it fails to effectively identify and process protocol bit errors. The vector conversion tool is used to convert VCD files into test vectors according to the vector format required by ATE, and then import them into ATE. The comparative analysis tool is used to compare and analyze the output waveform of the CAN bus controller with the simulation waveform generated by the simulation system, to determine the CAN bus controller's response to protocol bit errors, obtain the detection results, and detect whether there are vulnerabilities in the controller that cannot correctly detect certain protocol bit errors.

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