Multi-stage power supply series-parallel communication control circuit and master-slave address automatic establishment method thereof

Abstract

The present invention provides a multi-stage power supply serial-parallel communication control circuit and a method for automatically establishing a master-slave address thereof, and provides multi-stage power supply units connected to each other in a serial-parallel communication control manner. A signal line pair of each stage power supply unit in the multi-stage power supply unit is connected in parallel, and an IO output pin of each stage power supply unit in the multi-stage power supply unit is connected to an IO input pin of a power supply unit of the next stage to transmit an enable signal. After each of the multi-stage power supply units executes the method flow of the present invention, each stage in the multi-stage power supply unit can be automatically set as a local machine or a slave machine, and the master-slave relationship and addresses between the multi-stage power supply units can be automatically established. There is no need to manually set the address, delay the response time of the slave machine, and add an additional controller, which can avoid problems caused by human operation.

Description

Technical Field

[0001] The present invention relates to the technical field of multi-stage power supply series-parallel communication control circuits, and in particular to a multi-stage power supply series-parallel communication control circuit and a method for automatically establishing master-slave addresses thereof. Background Art

[0002] An AC power supply system is often composed of multiple AC power supply units, and the control signals of the multiple AC power supply units are often interconnected in the form of a master-slave structure of a serial flow to reduce the wiring complexity of the control signals of the multiple AC power supply units and improve their reliability. In order for the AC power supply system to realize external serial flow control, each unit needs to have a unique communication address; the existing practices are roughly divided into: manually setting the address, delaying the response time of the slave, and adding additional controllers or components. However, the method of manually setting the address will cause the problem of communication failure due to repeated manual operation of the address; the method of delaying the response time of the slave will cause the connection establishment time to be uncontrollable, or even communication failure; the method of adding additional controllers or components will increase the component cost; therefore, there is an urgent need to overcome the above shortcomings. Summary of the invention

[0003] To solve the aforementioned problem, the present invention discloses a method for automatically establishing master and slave addresses of a multi-stage power supply series-parallel communication control circuit, comprising the following steps:

[0004] First, a multi-stage power supply unit is provided, which is connected to each other in a serial-parallel communication control mode, wherein a signal line pair of each stage power supply unit in the multi-stage power supply unit is connected in parallel, and an IO output pin of each stage power supply unit in the multi-stage power supply unit is connected to an IO input pin of the next stage power supply unit to transmit an enable signal;

[0005] Setting a first-stage power supply unit in the multi-stage power supply unit as a host;

[0006] The host outputs an enable signal to a slave of the host via an IO output pin;

[0007] After receiving the enable signal via an IO input pin, the slave device exchanges hands with the host device to establish communication;

[0008] The host assigns the slave a first communication address;

[0009] The slave device outputs an enable signal to a slave device of a lower level of the slave device via an IO output pin;

[0010] After receiving the enable signal via an IO input pin, the next-level slave exchanges hands with the slave to establish communication;

[0011] The slave machine allocates a second communication address to the next-level slave machine.

[0012] The present invention also discloses another method for automatically establishing master and slave addresses of a multi-stage power supply series-parallel communication control circuit, comprising the following steps:

[0013] First, a multi-stage power supply unit is provided, which is connected to each other in a serial-parallel communication control mode, wherein a signal line pair of each stage power supply unit in the multi-stage power supply unit is connected in parallel, and an IO output pin of each stage power supply unit in the multi-stage power supply unit is connected to an IO input pin of the next stage power supply unit to transmit an enable signal;

[0014] Step S22: a local unit is any level power unit in the multi-level power unit, and the local unit sends a reset signal to a next level power unit of the local unit;

[0015] Step S23: If the local device is set as a host, go to the next step;

[0016] Step S24: the host sets an enable signal to enable the next level power supply unit;

[0017] Step S25: the host waits to receive data from the next-level power supply unit;

[0018] Step S26: The host determines whether the data transmitted by the next-level power supply unit is received. If the data has not been received, the process returns to step S25.

[0019] Step S27: The host confirms an identification code of the next power supply unit. If the host confirms that the received data contains the identification code, the host transmits the identification code and an address of the next power supply unit that the next power supply unit is waiting for.

[0020] Preferably, the method further comprises the following steps:

[0021] In step S23, if the local machine is set as a slave machine, the following steps are performed:

[0022] Step S31: the slave machine waits to receive an enable signal from an upper power supply of the slave machine;

[0023] Step S32: the slave determines whether the enable signal from the upper power supply is received. If the enable signal is not received, the process returns to step S31.

[0024] Step S33: the local slave transmits an identification code that the upper power source unit is waiting for;

[0025] Step S34: the local slave machine waits to receive data transmitted from the upper power supply unit;

[0026] Step S35: the slave determines whether the data transmitted from the upper power supply unit is received. If the slave has received the data transmitted from the upper power supply unit, the process goes to step S37.

[0027] Step S37: the local slave determines whether it has received the identification code transmitted from the upper power supply unit. If the local slave has received the identification code transmitted from the upper power supply unit, the local slave has also received a local slave address transmitted from the upper power supply unit.

[0028] Preferably, the method further comprises the following steps:

[0029] Step S39: The local slave determines whether the local slave is a last-stage power supply unit according to the received local slave address. If the local slave is not the last-stage power supply unit, the following steps are performed:

[0030] Step S41: the slave sends an enable signal to enable the next level power supply of the slave;

[0031] Step S42: the slave machine waits to receive data from the next-level power supply machine;

[0032] Step S43: the slave determines whether the data transmitted by the next-level power supply unit is received. If the slave does not receive the data transmitted by the next-level power supply unit, the process returns to step S42.

[0033] Step S44: the slave confirms an identification code of the next power supply unit. If the slave confirms that the received data contains the identification code, the slave transmits the identification code and an address of the next power supply unit that the next power supply unit is waiting for.

[0034] The present invention also discloses a multi-stage power supply series-parallel communication control circuit, comprising:

[0035] A plurality of power supply units are connected to each other in a serial-parallel communication control mode, wherein each power supply unit in the plurality of power supply units has:

[0036] A processor;

[0037] a signal converter, the signal converter is connected to the processor, and the signal transmitted between the processor and the signal converter uses a first signal format;

[0038] a signal line pair for transmitting a signal in a second signal format;

[0039] an IO input pin, the IO input pin being connected to the signal converter via the signal line pair; and

[0040] an IO output pin, the IO output pin is also connected to the signal converter via the signal line pair;

[0041] The signal line pairs of the multi-stage power supply units are connected in parallel, and the IO output pins of each stage of the multi-stage power supply units are connected to the IO input pins of the next stage of the power supply units step by step to transmit the enable signal step by step;

[0042] A first-stage power supply unit in the multi-stage power supply unit is a host, and the remaining power supply units are slaves; and the first signal format is different from the second signal format.

[0043] The present invention discloses a method for automatically establishing the master-slave address of a multi-stage power supply serial-parallel communication control, which provides a multi-stage power supply unit connected in series step by step, and sets each stage of the multi-stage power supply unit as a master or a slave. After the multi-stage power supply unit 10 executes the above-mentioned method for automatically establishing the master-slave address of the multi-stage power supply serial-parallel communication control of the present invention, the multi-stage power supply unit can establish a master-slave relationship and address with each other, so that the control signal sent by the host can be transmitted to the slaves step by step in sequence, so that there is no need to manually set the address, delay the response time of the slave, and add an additional controller or component, which can avoid the problem of communication failure due to repeated manual operation of the address, the problem of uncontrollable connection establishment time, and even communication failure, as well as the problem of increased component cost. In this way, the purpose of the present invention can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1a , Figure 1b : A schematic structural diagram of an embodiment of a power supply stand-alone circuit used in the present invention.

[0045] Figure 2 : A structural diagram of an embodiment of a multi-stage power supply single-machine series-parallel communication control circuit of the present invention.

[0046] Figure 3 : A flow chart of an embodiment of a method for automatically establishing master and slave addresses of a multi-stage power supply series-parallel communication control circuit of the present invention.

[0047] Figure 4a , Figure 4b : Flow chart of another embodiment of the method for automatically establishing master-slave addresses for series-parallel communication control of multi-stage power supplies of the present invention. DETAILED DESCRIPTION

[0048] Please see Figure 1a and Figure 1b The structure of an embodiment of a power supply stand-alone circuit used in the present invention is shown, wherein Figure 1b The circuit shown is Figure 1aThe detailed circuit structure of the power supply unit 10 is shown. The power supply unit 10 has a processor 11, a signal converter 12 connected to a communication interface 111 of the processor 11, an input interface 13 connected to an IO input pin 112 of the processor 11 and a signal line pair 121 of the signal converter 12, and an output interface 14 connected to an IO output pin 113 of the processor 11 and the pair of signal lines of the signal converter 12. The signal converter 12 is used to convert the signal transmitted by the communication interface 111 of the processor 11 into a signal that is more suitable for long-distance transmission and has a higher anti-noise capability. For example, the signal transmitted by the communication interface 111 is a universal asynchronous transceiver transmission (UART) signal, and the signal transmitted by the signal line pair 121 of the signal converter 12 is a bidirectional half-duplex serial communication (RS-485) signal. The communication interface 111 has a data read pin DR, a data output pin DT, and an output / read pin R / T. The output / read pin R / T uses a general digital signal, and the data read pin DR and the data output pin DT use a UART signal. The output / read pin R / T is used to control the signal converter 12, so that the UART signal output by the processor 11 through the data output pin DT is converted into an RS-485 signal, which is then outputted by the output interface 13 or the output interface 14, or the RS-485 input signal received by the input interface 13 or the output interface 14 is converted into a UART signal, which is then inputted to the processor 11 through the data input pin DR for reading. The processor 11 can be, for example, a microcontroller or a central processing unit (CPU), and the signal converter 12 can be, for example, a general TTL UART to RS-485 conversion module, but the present invention is not limited thereto.

[0049] Please see Figure 2 , Figure 2 1 is a structure of an embodiment of a series-parallel communication control circuit between multi-stage power supply units 10 used in the present invention. Figure 2 The output interfaces / input interfaces of three power supply units are shown to be bidirectionally connected in series via transmission cables 51 and 52. The first power supply unit can be referred to as a host 20, the second power supply unit can be referred to as a slave 30, and the third power supply unit can be referred to as a lower-level slave 40. Figure 1b, the output interface 14 of the host 20 is connected to the input interface 13 of the slave 30 via a transmission cable 51, so that the IO output pin 113 of the host 20 is connected to the IO input pin 112 of the slave 30, and the signal line pair 121 of the host 20 is connected to the signal line pair 121 of the slave 30; similarly, the output interface 14 of the slave 30 is connected to the input interface 13 of the next-level slave 40 via a transmission cable 52, so that the IO output pin 113 of the slave 30 is connected to the IO input pin 112 of the next-level slave 40, and the signal line pair 121 of the slave 30 is connected to the signal line pair 121 of the next-level slave 40. As can be seen from the above, the signal line pair 121 of the host 20, the signal line pair 121 of the slave 30, and the signal line pair 121 of the next-level slave 40 are in a signal parallel relationship, so the three can share signal data in a broadcasting manner, and the signal line pair 121 is mainly used to transmit RS-485 data, but the present invention is not limited to this. As for the IO input pins 112 and IO output pins 113 of the host 20, the slave 30, and the next-level slave 40, they form a signal series relationship between the three through the transmission cables 51-52, wherein the IO input pins 112 and the IO output pins 113 are mainly used to transmit general digital signals, such as an enable signal, but the present invention is not limited to this.

[0050] Please see Figure 3 , Figure 3 An embodiment of the method for automatically establishing master and slave addresses for serial and parallel communication control of multi-stage power supplies of the present invention is shown, which can be applied to Figure 2 The master-slave addresses of the serial-parallel communication control between the host 20, the slave 30, and the next-level slave 40 are automatically established. The method flow includes the following steps:

[0051] Step S10: After the host 20 is started, it outputs an enabling signal to a slave 30 via an IO output pin 113;

[0052] Step S11: After the slave device 30 receives the enabling signal via an IO input pin 112 and is enabled, it exchanges hands with the host device 20 to establish communication;

[0053] Step S12: The host 20 assigns a communication address #01 to the slave 30;

[0054] Step S13: The slave 30 outputs an enable signal to the next-level slave 40 via an IO output pin 113;

[0055] Step S14: After the next-level slave 40 receives the enable signal via an IO input pin 112 and is enabled, it exchanges hands with the slave 30 to establish communication;

[0056] Step S15: The slave 30 assigns a communication address #02 to the next-level slave 40.

[0057] like Figure 2 In one embodiment of the three power supply units connected in series, after a host 20 and a slave 30 have established communication by handshake, when an abnormality occurs in the slave 30, that is, when a next-level slave 40 detects that an enable signal received from the slave 30 by its IO input pin 112 is abnormal, the next-level slave 40 can actively notify the slave 30 that a fault has occurred.

[0058] Please see Figure 4a and Figure 4b , Figure 4a and Figure 4b Another embodiment of the method for automatically establishing master and slave addresses for serial and parallel communication control of multi-stage power supplies of the present invention, wherein, Figure 2 Each of the three power supply units connected in series as shown executes Figure 4a and Figure 4b The following process steps are shown to automatically establish the master-slave relationship and master-slave address of each power supply unit:

[0059] Step S21: start;

[0060] Step S22: setting an IO output signal outputted by an IO output pin 113 of the local device to a logic 0 level (ie, the local device sets a reset signal to the next power supply unit of the local device);

[0061] Step S23: If the local machine is set as a slave (hereinafter referred to as the slave), jump to step S31; if the local machine is set as a master (hereinafter referred to as the master), go to the next step;

[0062] Step S24: setting the IO output signal of the host to a logic 1 level (ie, the host sets an enable signal to enable the next power supply unit of the host);

[0063] Step S25: Waiting for the communication interface 111 of the host to receive RS485 data (ie, the host waits to receive data transmitted from the next level power supply unit of the host);

[0064] Step S26: If the RS485 data has not been received, return to step S25 (i.e. the host determines whether the data transmitted by the next level power supply unit of the host is received);

[0065] Step S27: If the identification code (0XAB) in the received RS485 data is correct, jump to step S28 (i.e. the host confirms the identification code (0XAB) of the next level power supply of the host);

[0066] Step S27': the connection is abnormal (ie, the connection between the host and the power supply unit at the next level of the host is abnormal);

[0067] Step S28: The communication interface 111 of the host transmits the identification code (0XAB) and the RS485 data of the address of the next power supply unit of the host through the signal converter 12 (i.e., the host transmits an identification code and an address of the next power supply unit of the host that the next power supply unit of the host is waiting for);

[0068] Step S29: Waiting for the communication interface 111 of the host to receive RS485 data (sent from the last power supply unit) (i.e., the host waits to receive data from the last power supply unit);

[0069] Step S30: If the received RS485 data does not contain a completion code (0XBA), return to step S29 (i.e., the host confirms a completion code (0XBA) of the last power supply unit);

[0070] Step S30': end (i.e. end the master-slave address automatic establishment process of the host);

[0071] Step S31: Waiting for an IO input signal received by the IO input pin 112 of the slave (sent from the upper power supply unit of the slave) to be at a logic 1 level (i.e., the slave is waiting to receive an enable signal sent from the upper power supply unit of the slave);

[0072] Step S32: If the IO input signal is not at a logic 1 level, return to step S31 (i.e. the slave determines whether an enable signal is received from the upper power supply unit of the slave);

[0073] Step S33: The communication interface 111 of the slave transmits RS485 data of the identification code (0XAB) via a signal converter 12 (to the upper power supply unit of the slave) (i.e., the slave transmits the identification code (0XAB) that the upper power supply unit of the slave is waiting for);

[0074] Step S34: Waiting for the communication interface 111 of the slave to receive the RS485 data (sent from the upper power supply unit of the slave) (i.e., the slave waits to receive the data sent from the upper power supply unit of the slave);

[0075] Step S35: If the communication interface 111 of the slave has received the RS485 data (sent from the upper power supply of the slave), jump to step S37 (i.e. the slave determines whether the data is received from the upper power supply of the slave);

[0076] Step S36: If it has not timed out, return to step S34 (i.e. the slave determines whether the waiting time has not timed out);

[0077] Step S36': the connection is abnormal (ie, the connection between the slave machine and the upper-level power supply unit of the slave machine is abnormal);

[0078] Step S37: If it is an identification code (0XAB), jump to step S38 (i.e. the slave determines whether it has received the identification code (0XAB) from the master or the upper-level slave);

[0079] Step S37': the connection is abnormal (i.e. the connection between the slave machine and the upper-level power supply unit of the master slave machine is abnormal);

[0080] Step S38: the communication interface 111 of the slave receives a slave address (sent from the upper power supply of the slave) (i.e., the slave receives a slave address sent from the upper power supply of the slave);

[0081] Step S39: Compare the received address of the slave machine to determine whether the slave machine is a last-level power supply stand-alone machine. If the slave machine is not a last-level power supply stand-alone machine, jump to step S41 (i.e., the slave machine determines whether the slave machine is a last-level power supply stand-alone machine according to the received address of the slave machine);

[0082] Step S40: The communication interface 111 of the slave (hereinafter referred to as the last power supply unit) transmits RS485 data of a completion code (0XBA) via a signal converter 12 (to all power supply units before the last power supply unit) (i.e., the last power supply unit transmits the completion code (0XBA) that all power supply units before the last power supply unit are waiting for);

[0083] Step S40': end (i.e., end the master-slave address automatic establishment process of the last-level power supply stand-alone);

[0084] Step S41: setting an IO output signal outputted by the IO output pin 113 of the slave to a logic 1 level (enabling the next power supply unit of the slave) (i.e., the slave sends an enable signal to enable the next power supply unit of the slave);

[0085] Step S42: Waiting for the communication interface 111 of the slave to receive RS485 data (sent from the next level power supply unit of the slave) (i.e., the slave waits to receive data sent from the next level power supply unit of the slave);

[0086] Step S43: If the communication interface 111 does not receive RS485 data, return to step S42 (i.e. the slave determines whether it has received data from the next-level power supply unit of the slave);

[0087] Step S44: If the identification code (0XAB) is received, jump to step S45 (i.e. the slave confirms the identification code (0XAB) of the next-level slave);

[0088] Step S44': the connection is abnormal (ie the connection between the slave and the slave at the next level is abnormal);

[0089] Step S45: The communication interface 111 of the slave transmits the identification code (0XAB) and the RS485 data of the next slave address (to the next slave) via a signal converter 12 (i.e., the slave transmits the identification code (0XAB) and the address of the next slave power supply unit waiting for the slave);

[0090] Step S46: Waiting for the communication interface 111 of the slave to receive the RS485 data (sent from the last power supply unit) (i.e., the slave waits to receive the data sent from the last power supply unit);

[0091] Step S47: If the communication interface 111 of the slave has received the completion code (0XBA) in the RS485 data, jump to step S47'; (ie, the slave confirms the completion code (0XBA) of the last power supply unit);

[0092] Step S48: If it has not timed out, return to step S46 (i.e. the slave determines whether the waiting time has not timed out);

[0093] Step S48': connection abnormality (i.e. the slave machine fails to receive the completion code (0XBA) from the last power supply unit within the time limit, and the master-slave address automatic establishment process of the slave machine fails to complete within the time limit);

[0094] Step S47': end (ie, end the automatic establishment process of the master-slave address of the slave machine).

[0095] Based on the above description, it can be seen that this embodiment is obviously applicable to a configuration of a host and a slave, a configuration of a host, a slave, and a lower-level slave, and also a configuration of a host, a slave, a lower-level slave, and more other slaves.

[0096] From the interaction between the host, the slave, and the next-level slave in the above process, it can be seen that: when the host, the slave, and the next-level slave are each executing their own master-slave address automatic establishment process, first, in step S24, the host enables the slave, and then in steps S25 and S33, the host performs an identification code (0XAB) confirmation on the slave (referred to as: identification code confirmation), and then in steps S28 and S34, the slave performs an identification code (0XAB) confirmation on the host, and then the slave can obtain the address of the slave (referred to as: identification code and address confirmation), and this is completed. To complete the handshake between the host and the slave, similarly, first in step S41 the slave enables the next-level slave, then the slave executing step S42 confirms the identification code (0XAB) of the next-level slave executing step S33 (referred to as: identification code confirmation), and then the next-level slave executing step S34 confirms the identification code (0XAB) of the slave executing step S42, and then the next-level slave can obtain the address of the next-level slave (referred to as: identification code and address confirmation), thus completing the handshake between the slave and the next-level slave; the interaction of other slaves can be deduced in the same way. Finally, when the last-level power supply unit completes the identification code and address confirmation, the last-level power supply unit sends a completion code (0XBA) to all slaves and the host before the last-level power supply unit, and then all slaves and the host before the last-level power supply unit respectively confirm the completion code (0XBA). After each confirmation, each ends the master-slave address automatic establishment process executed by each. After the last-level power supply unit sends the completion code (0XBA), it also ends the master-slave address automatic establishment process executed by it. In this way, the automatic establishment of the master-slave address of the multi-level power supply series-parallel communication control in this embodiment is completed.

[0097] As described above, after the multi-stage power supply units 10 are connected in series in sequence, and each stage of the multi-stage power supply units 10 is set as a host or a slave, and the multi-stage power supply units 10 each execute the master-slave address automatic establishment method flow of the multi-stage power supply serial-parallel communication control of the present invention, the multi-stage power supply units 10 can establish a master-slave relationship and address between each other, so that the control signal sent by the host can be transmitted to the slaves in sequence and level by level, so that there is no need to manually set the address, nor to delay the response time of the slave, and no need to add additional controllers or components, which can avoid the problem of communication failure due to repeated manual operation of the address, the problem of uncontrollable connection establishment time, and even communication failure, as well as the problem of increased component costs. In this way, the purpose of the present invention can be achieved.

Claims

1. A method for automatically establishing master and slave addresses of a multi-stage power supply series-parallel communication control circuit, characterized in that: The following steps are involved: A multi-stage power supply unit is provided which is connected to each other in a serial-parallel communication control mode, wherein a pair of signal lines of each stage of the power supply unit in the multi-stage power supply unit is connected in parallel, and an IO output pin of each stage of the power supply unit in the multi-stage power supply unit is connected to an IO input pin of the next stage of the power supply unit to transmit an enable signal; Setting a first-stage power supply unit in the multi-stage power supply unit as a host; The host outputs an enable signal to a slave of the host via an IO output pin; After receiving the enable signal via an IO input pin, the slave device exchanges hands with the host device to establish communication; The host assigns the slave a first communication address.

2. The method according to claim 1, characterized in that The method further comprises the following steps: The slave device outputs an enable signal to a slave device of a lower level of the slave device via an IO output pin; After receiving the enable signal via an IO input pin, the next-level slave exchanges hands with the slave to establish communication; The slave machine allocates a second communication address to the next-level slave machine.

3. A method for automatically establishing master and slave addresses of a multi-stage power supply series-parallel communication control circuit, characterized in that: The following steps are involved: A multi-stage power supply unit is provided which is connected to each other in a serial-parallel communication control mode, wherein a pair of signal lines of each stage of the power supply unit in the multi-stage power supply unit is connected in parallel, and an IO output pin of each stage of the power supply unit in the multi-stage power supply unit is connected to an IO input pin of the next stage of the power supply unit to transmit an enable signal; Step S22: a local unit is any level power unit in the multi-level power unit, and the local unit sets a reset signal to a next level power unit of the local unit; Step S23: If the local device is set as a host, go to the next step; Step S24: the host sets an enable signal to enable the next level power supply unit; Step S25: the host waits to receive data from the next-level power supply unit; Step S26: The host determines whether the data transmitted by the next-level power supply unit is received. If the data has not been received, the process returns to step S25. Step S27: The host confirms an identification code of the next power supply unit. If the host confirms that the received data contains the identification code, the host transmits the identification code and an address of the next power supply unit that the next power supply unit is waiting for.

4. The method according to claim 3, characterized in that The method further comprises the following steps: Step S29: the host waits to receive data from the last power supply unit; Step S30: the host confirms a completion code of the last power supply unit. If the data received by the host does not contain the completion code, the process returns to step S29. End the process.

5. The method according to claim 3, characterized in that The method further comprises the following steps: In step S23, if the local machine is set as a slave machine, the following steps are performed: Step S31: the slave machine waits to receive an enable signal from an upper power supply of the slave machine; Step S32: the slave determines whether the enable signal from the upper power supply is received. If the enable signal is not received, the process returns to step S31. Step S33: the local slave transmits an identification code that the upper power source unit is waiting for; Step S34: the local slave machine waits to receive data transmitted from the upper power supply unit; Step S35: the local slave determines whether the data transmitted from the upper power supply unit is received. If the local slave has received the data transmitted from the upper power supply unit, the process goes to step S37. Step S37: the local slave determines whether it has received the identification code transmitted from the upper power supply unit. If the local slave has received the identification code transmitted from the upper power supply unit, the local slave has also received a local slave address transmitted from the upper power supply unit.

6. The method according to claim 5, characterized in that The method further comprises the following steps: Step S39: the local slave determines whether the local slave is a last-level power supply unit according to the received local slave address; Step S40: If the slave is the last power supply, the last power supply transmits a completion code that all the previous power supplies are waiting for; and the process ends.

7. The method according to claim 5, characterized in that The method further comprises the following steps: Step S39: The local slave determines whether the local slave is a last-stage power supply unit according to the received local slave address. If the local slave is not the last-stage power supply unit, the following steps are performed: Step S41: the slave sends an enable signal to enable the next level power supply of the slave; Step S42: the slave machine waits to receive data from the next-level power supply machine; Step S43: the local slave determines whether the data transmitted by the next-level power supply unit is received. If the local slave does not receive the data transmitted by the next-level power supply unit, the process returns to step S42. Step S44: the slave confirms an identification code of the next power supply unit. If the slave confirms that the received data contains the identification code, the slave transmits the identification code and an address of the next power supply unit that the next power supply unit is waiting for.

8. The method according to claim 7, characterized in that The method further comprises the following steps: Step S46: the slave device waits to receive data from the last power source device; Step S47: the slave device confirms a completion code of the last power supply unit. If the slave device has confirmed that the received data contains the completion code, the process ends.

9. A multi-stage power supply series-parallel communication control circuit, characterized in that: Include: A plurality of power supply units are connected to each other in a serial-parallel communication control mode, wherein each power supply unit in the plurality of power supply units has: A processor; a signal converter, the signal converter is connected to the processor, and the signal transmitted between the processor and the signal converter uses a first signal format; a signal line pair for transmitting a signal in a second signal format; an IO input pin, the IO input pin being connected to the signal converter via the signal line pair; and an IO output pin, the IO output pin is also connected to the signal converter via the signal line pair; The signal line pairs of the multi-stage power supply units are connected in parallel, and the IO output pins of each stage of the multi-stage power supply units are connected to the IO input pins of the next stage of the power supply units to transmit the enable signal step by step.

10. The multi-stage power supply series-parallel communication control circuit according to claim 9, characterized in that: The first signal format is different from the second signal format.

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