Semiconductor device, vehicle-mounted charger and vehicle

Abstract

The invention relates to the technical field of power electronics, in particular to a semiconductor device, a vehicle-mounted charger and a vehicle wherein the semiconductor device comprises: a substrate, a power circuit, a power pin (102) and a signal pin (101); the power circuit is arranged on the substrate; the power pin (102) and the signal pin (101) are connected with a power circuit; the signal pins (101) arranged on the same side edge of the substrate are arranged in groups, and the distance between the signal pins (101) in different groups is larger than the distance between the power pins (102). According to the embodiment of the invention, the power line and the signal line in the semiconductor device are separated, so that the cross line and mutual interference of the power line and the signal line are avoided; and the problem that wiring is difficult due to many pins on the side of the signal pin (101) is avoided.

Description

Technical Field

[0001] The present disclosure relates to the field of power electronics technology, and in particular to a semiconductor device, a vehicle charger and a vehicle. Background Art

[0002] With the rapid development of new energy vehicles and the updating and iteration of their product technologies, people have increasingly higher requirements for the performance of new energy vehicles.

[0003] The control circuit of new energy vehicles includes a large number of rectifiers, inverters, boost circuits and buck circuits, etc. These devices are all based on power converter settings, and power converters generally include power semiconductor devices. Power semiconductor devices include various types of controllable and uncontrollable transistors; among them, uncontrollable transistors include diodes, and controllable transistors include at least any one of the following: thyristors, metal-oxide semiconductor field effect transistors (Metal Oxide Semiconductor Field Effect Transistor, MOSFET), insulated gate bipolar transistors (Insulated Gate Bipolar Transistor, IGBT), silicon carbide tubes and gallium nitride tubes, etc.

[0004] In order to adapt to different circuit and process requirements, the industry has produced different types of power semiconductor devices. However, the current packaging of power semiconductor devices is generally suitable for specific occasions and has a single packaging type. Therefore, the application of power semiconductor devices is not flexible enough. Summary of the invention

[0005] The embodiments of the present disclosure provide a semiconductor device, an on-board charger and a vehicle, which separate the power wiring and the signal wiring in the semiconductor device to avoid cross wiring and mutual interference between the power wiring and the signal wiring.

[0006] In order to achieve the above-mentioned purpose, the first aspect of the present disclosure provides a semiconductor device, comprising: a substrate, a power circuit, a power pin (102) and a signal pin (101); the power circuit is arranged on the substrate; the power pin (102) and the signal pin (101) are connected to the power circuit; the signal pins (101) arranged on the same side of the substrate are arranged in groups, and the spacing between signal pins (101) in different groups is greater than the spacing between power pins (102).

[0007] In some embodiments, the spacing between signal pins (101) in the same group is smaller than the spacing between power pins (102).

[0008] In some embodiments, the power pins (102) are disposed on a first side of the substrate, and at least some of the signal pins (101) are disposed on a second side of the substrate, and the first side and the second side are different sides of the substrate.

[0009] In some embodiments, the first side and the second side are opposite sides of the substrate.

[0010] In some embodiments, the signal pins (101) arranged on the second side are arranged in groups, and the spacing between signal pins (101) in different groups is greater than the spacing between power pins (102).

[0011] In some embodiments, the power circuit includes at least two power elements, and signal pins (101) corresponding to different power elements are arranged in different groups.

[0012] In some embodiments, the width of the power pin (102) is greater than the width of the signal pin (101).

[0013] In some embodiments, different power pins (102) have different widths.

[0014] In some embodiments, the semiconductor device (100) further includes a detection element, and the signal pin (101) includes a control pin (111) and a detection pin (121); the detection pin (121) is connected to the detection element, and the control pin (111) is used to receive a drive signal corresponding to the power circuit; wherein the detection pin (121) and the power pin (102) are arranged on the same side, and / or the detection pin (121) and the control pin (111) are arranged on the same side.

[0015] In some embodiments, the detection pin (121) includes: a first type of detection pin and a second type of detection pin; the first type of detection pin and the control pin (111) are arranged on the same side; the second type of detection pin and the power pin (102) are arranged on the same side.

[0016] In some embodiments, the width of the second type pin (201) is less than or equal to the width of the control pin (111).

[0017] In some embodiments, the width of the second type of detection pins is less than or equal to the width of the first type of detection pins.

[0018] In some embodiments, the distance between the detection pin (121) and the power pin (102) is less than or equal to the distance between the detection pin (121) and the control pin (111).

[0019] In some embodiments, the packaging form of the signal pin (101) and the power pin (102) includes at least one of the following: a small outline package, a J-type pin small outline package, a quad flat package, a plastic chip carrier with leads, or a direct-plug pin package.

[0020] In some embodiments, at least some of the signal pins (101) and / or the power pins (102) have different packaging styles.

[0021] In some embodiments, the signal pin (101) and / or the power pin (102) include: a first connection portion, a first end of which is connected to a power circuit on a substrate, and a second end of which extends outside the substrate; a bending portion, a first end of which is connected to a second end of the first connection portion, and a second end of which is connected to a first end of the second connection portion, and the bending portion is at a first angle to the first connection portion and at a second angle to the second connection portion; and the second end of the second connection portion is used to connect to a circuit board carrying the semiconductor device (100).

[0022] In some embodiments, the first angle and the second angle are set in the range of 120° to 150°, and the second angle is greater than the first angle.

[0023] In some embodiments, the first connecting portion is a first length, the bending portion is a second length, and the second connecting portion is a third length; wherein the first length is greater than the third length, and the third length is greater than the second length.

[0024] In a second aspect, the present disclosure provides an on-board charger, the components of which include the semiconductor device mentioned in the first aspect.

[0025] In a third aspect, the present disclosure provides a vehicle, comprising the semiconductor device mentioned in the first aspect, or comprising the on-board charger mentioned in the second aspect.

[0026] The semiconductor device provided by the embodiment of the present disclosure separates the power routing from the signal routing by reasonably setting the spacing between the signal pins and the power pins, thereby avoiding the cross routing of the power routing and the signal routing and mutual interference; and avoiding the problem of difficult wiring on the signal pin side due to the large number of pins.

[0027] Other features and advantages of the present disclosure will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0029] Figure 1 A schematic diagram of the structure of a semiconductor device provided by an embodiment of the present disclosure;

[0030] Figure 2 A schematic diagram of the circuit structure of a half-bridge circuit provided in an embodiment of the present disclosure;

[0031] Figure 3 A schematic diagram of the spacing dimensions of a semiconductor device provided in an embodiment of the present disclosure;

[0032] Figure 4 A schematic diagram of the circuit structure of a power circuit with a detection function provided in an embodiment of the present disclosure;

[0033] Figure 5 Corresponding to the embodiments of the present disclosure Figure 4 A schematic diagram of a packaging structure of a semiconductor device with a detection function;

[0034] Figure 6 A schematic diagram of pin lengths provided for an embodiment of the present disclosure;

[0035] Figure 7 A schematic diagram of pin angles provided for an embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0037] In the description of the present disclosure, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the described features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0038] In this disclosure, the word "exemplary" is used to mean "serving as an example, illustration, or illustration." Any embodiment described in this disclosure as "exemplary" is not necessarily to be construed as being preferred or advantageous over other embodiments. The following description is given to enable any person skilled in the art to implement and use the present disclosure. In the following description, details are listed for the purpose of explanation. It should be understood that a person of ordinary skill in the art can recognize that the present disclosure can be implemented without using these specific details. In other instances, well-known structures and processes are not elaborated in detail to avoid obscuring the description of the present disclosure with unnecessary details. Therefore, the present disclosure is not intended to be limited to the embodiments shown, but is consistent with the widest scope consistent with the principles and features disclosed in the present disclosure.

[0039] At the same time, the present disclosure uses specific words to describe the embodiments of the present disclosure. For example, "one embodiment", "an embodiment", and / or "some embodiments" refer to a certain feature, structure or characteristic related to at least one embodiment of the present disclosure. Therefore, it should be emphasized and noted that "one embodiment" or "an embodiment" or "an alternative embodiment" mentioned twice or more in different locations in this specification does not necessarily refer to the same embodiment. In addition, certain features, structures or characteristics in one or more embodiments of the present disclosure may be appropriately combined.

[0040] Similarly, it should be noted that in order to simplify the description of the disclosure and thus facilitate the understanding of one or more disclosed embodiments, in the foregoing description of the embodiments of the disclosure, multiple features are sometimes grouped into one embodiment, drawing, or description thereof. However, this disclosure method does not mean that the disclosed object requires more features than those mentioned in the claims. In fact, the features of the embodiments are less than all the features of the single embodiment disclosed above.

[0041] In some embodiments, numbers are used to describe the number of components and attributes. It should be understood that such numbers used to describe the embodiments are modified by the modifiers "about", "approximately" or "substantially" in some examples. Unless otherwise specified, "about", "approximately" or "substantially" indicate that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which may change according to the required features of individual embodiments. In some embodiments, numerical parameters should consider specifying significant digits and adopting a general method of retaining digits. Although the numerical domains and parameters used to confirm the breadth of their range in some embodiments of the present disclosure are approximate values, in specific embodiments, such numerical values ​​are set as accurately as possible within the feasible range.

[0042] Each patent, patent application, patent application publication, and other materials, such as articles, books, specifications, publications, documents, etc., cited in this disclosure are hereby incorporated by reference in their entirety, except for application history documents that are inconsistent with or conflicting with the content of this disclosure, and documents that limit the broadest scope of the claims of this disclosure (currently or later attached to this disclosure). It should be noted that if the descriptions, definitions, and / or use of terms in the accompanying materials of this disclosure are inconsistent or conflicting with the examples of this disclosure, the descriptions, definitions, and / or use of terms in this disclosure shall prevail.

[0043] This embodiment provides a semiconductor device, which separates the power wiring and the signal wiring in the semiconductor device to avoid cross wiring and mutual interference between the power wiring and the signal wiring. The semiconductor device provided by this embodiment is described in detail below with reference to the accompanying drawings.

[0044] refer to Figure 1 , Figure 1 This is a schematic structural diagram of a semiconductor device provided in this embodiment. The semiconductor device 100 provided in this embodiment includes: a substrate (not shown), a power circuit (not shown), a power pin 102 and a signal pin 101.

[0045] The power circuit is arranged on the substrate, the power pins 102 and the signal pins 101 are connected to the power circuit, the signal pins 101 arranged on the same side of the substrate are arranged in groups, and the spacing between signal pins 101 in different groups is greater than the spacing between the power pins 102.

[0046] In one example, refer to Figure 1 The signal pins 101 arranged on the same side include a first group Z1 and a second group Z2, the minimum distance between the signal pins 101 in the first group Z1 and the second group Z2 is X1, the spacing between the power pins 102 is X2, and X1 is greater than X2.

[0047] The semiconductor device 100 provided in this embodiment separates the power routing and the signal routing by reasonably setting the distance between the signal pin 101 and the power pin 102, thereby avoiding the cross routing of the power routing and the signal routing and mutual interference; and avoiding the problem of difficult wiring on the signal pin 101 side due to the large number of pins.

[0048] exist Figure 1In the exemplary semiconductor device 100, the first group Z1 signal pins 101 includes two signal pins 101, and the second group Z2 signal pins 101 includes three signal pins 101, which is only used to illustrate the grouping of the signal pins 101 described in this embodiment, and does not constitute a limitation on this embodiment. In other embodiments, the number of groups of the signal pins 101 may be three groups, four groups, etc.; in addition, the number of signal pins 101 in each group of signal pins 101 is also only used to illustrate the grouping of the signal pins 101 described in this embodiment, and does not constitute a limitation on this embodiment. The number of signal pins 101 in different groups can be set to be the same or different, and the specific number is set based on demand.

[0049] In some embodiments, the spacing between signal pins 101 in the same group may be the same or different, and the minimum spacing between signal pins 101 in different groups may be the same or different. As long as the minimum spacing between signal pins 101 in different groups is greater than the spacing between power pins 102, they should all fall within the protection scope of the present disclosure.

[0050] It should be noted that in the drawings of this embodiment, the semiconductor device 100 further includes a package 103, which packages the substrate and the power circuit. The package 103 is packaged around the DBC substrate. In some embodiments, the package 103 can be made of plastic, i.e., a plastic package.

[0051] In some embodiments, the spacing between the signal pins 101 in the same group is smaller than the spacing between the power pins 102. The signal pins 101 in the same group are arranged close to each other to reduce the area of ​​the semiconductor device 100.

[0052] In some embodiments, the power pin 102 is arranged on the first side of the substrate, and at least part of the signal pin 101 is arranged on the second side of the substrate, and the first side and the second side are different sides of the substrate. By distributing the power pin 102 and the signal pin 101 on different sides of the semiconductor device 100, in practical applications, the power routing and the signal routing in the semiconductor device 100 are separated to avoid cross routing and mutual interference between the power routing and the signal routing; and to avoid the problem that the signal pin 101 side is difficult to route due to the large number of pins. In one example, the first side and the second side can also be adjacent sides of the substrate; in another example, the first side and the second side can also be opposite sides of the substrate. By distributing the power pin 102 and the signal pin 101 on opposite sides of the semiconductor device 100, the power routing and the signal routing can be separated to the greatest extent.

[0053] Specifically, the signal pins 101 arranged on the second side are arranged in groups, and the spacing between signal pins 101 in different groups is greater than the spacing between power pins 102. Figure 1 The signal pins 101 arranged on the same side include a first group Z1 and a second group Z2, the minimum distance between the signal pins 101 in the first group Z1 and the second group Z2 is X1, the spacing between the power pins 102 is X2, and X1 is greater than X2.

[0054] In some embodiments, the power circuit includes at least two power elements, and the signal pins 101 corresponding to different power elements are arranged in different groups. The signal pins of different power elements are arranged in different groups to separate the signal routings of different power elements, avoid the cross routing of the signal routings corresponding to different power elements, and interfere with each other; and avoid the problem that the signal pin 101 side is difficult to wire due to too many pins. In addition, in some embodiments, the signal pins 101 corresponding to the same power element can be arranged in the same group.

[0055] In some embodiments, two power components are arranged close to two opposite sides of the substrate, and two groups of signal pins 101 are also arranged on both sides to increase the distance between the signal pins and the power components, thereby reducing parasitic parameters caused by the lead distance, thereby reducing the impact on the control signal.

[0056] The semiconductor device provided in the embodiment of the present disclosure can be regarded as a power semiconductor device. In order to facilitate those skilled in the art to better understand the technical solution provided in the embodiment of the present disclosure, the semiconductor device corresponding to the half-bridge circuit is introduced as an example below.

[0057] It should be noted that the embodiments of the present disclosure do not specifically limit the specific application scenarios of semiconductor devices; in one example, semiconductor devices can be applied to power supply systems, such as photovoltaic power generation systems, wind power systems, or energy storage systems. In another example, semiconductor devices can be applied to charging piles of electric vehicles or chargers or motor drivers of electric vehicles, such as charging circuits inside charging piles; in another example, semiconductor devices can be applied to power supplies for artificial intelligence (AI).

[0058] refer to Figure 2 , Figure 2 This is a schematic diagram of the circuit structure of a half-bridge circuit provided in this embodiment. This embodiment is introduced by taking a half-bridge circuit including two power elements as an example, that is, the two power elements are packaged together as a semiconductor device.

[0059] It should be noted that the embodiments of the present disclosure do not specifically limit the number of power elements included in the semiconductor device. For example, one power element may be included, two power elements may be included, or a greater number of power elements may be included. The number of power elements in the semiconductor device may be set according to the actual application scenario. For example, the semiconductor device may include at least two power elements corresponding to a half-bridge circuit, or may include four power elements corresponding to a full-bridge circuit.

[0060] In addition, the present embodiment uses a power tube as an example for explanation of the power element, which does not constitute a limitation on the present embodiment; in other embodiments, the power element may be other power elements other than the power tube.

[0061] Specifically, refer to Figure 1 The two power tubes are respectively a first MOS tube M1 and a second MOS tube M2.

[0062] The drain of the first MOS tube M1 is connected to the power pin P1, the source of the first MOS tube M1 is connected to the drain of the second MOS tube M2 and connected to the power pin P2, and the source of the second MOS tube M2 is connected to the power pin P3. The gate of the first MOS tube M1 is connected to the signal pin G1, and the source is connected to the signal pin S1, and the gate of the second MOS tube M2 is connected to the signal pin G2, and the source is connected to the signal pin S2.

[0063] The gate and source of the first MOS tube M1 are used to receive an external driving signal, that is, the conduction state of the first MOS tube M1 depends on the level of the external driving signal received by the signal pin G1 and the signal pin S1; similarly, the conduction state of the second MOS tube M2 depends on the level of the external driving signal received by the signal pin G2 and the signal pin S2.

[0064] For the package of the semiconductor device corresponding to the half-bridge circuit, the corresponding pins include: power pins P1, P2 and P3, and signal pins G1, S1, G2 and S2.

[0065] It should be noted that the power circuit described in this embodiment corresponds to Figure 2 The half-bridge circuit shown is used to realize the function of the power semiconductor device. In addition, the description of the semiconductor device 100 with two power tubes in this embodiment does not constitute a limitation of this embodiment. In other embodiments, the power circuit includes at least two power tubes, and each power tube includes a corresponding power pin 102 and a signal pin 101. For example, the power circuit includes four power tubes to realize the function of the full-bridge circuit.

[0066] In some embodiments, each of the first power tube and the second power tube may correspond to at least one wafer, and this embodiment is described by taking one power tube corresponding to one wafer as an example. In other embodiments, each power tube may correspond to multiple wafers, and multiple wafers may be arranged in series or in parallel, which is not specifically limited in this embodiment.

[0067] In some embodiments, the substrate may be in the form of direct bonding copper (DBC). It should be noted that this embodiment does not specifically limit the specific implementation form of the substrate. The embodiments of this application are only for the convenience of description and for those skilled in the art to understand the implementation scheme, and the DBC substrate is used as an example for introduction.

[0068] Since each power tube corresponds to a wafer, the wafer is a conductor, and the substrate is in the form of direct copper cladding, and the copper material is also a conductor, therefore, in some embodiments, the wafer can be directly soldered on the DBC substrate.

[0069] In some embodiments, the wafers corresponding to the first power tube and the second power tube need to be insulated and isolated by an insulating tape to avoid a short circuit between the wafers corresponding to the first power tube and the second power tube.

[0070] Based on the foregoing description, it can be known that the wafer can be directly welded on the substrate, that is, the power circuit is welded and set on the substrate; accordingly, the signal pin 101 and the power pin 102 can also be directly welded on the DBC substrate.

[0071] Figure 3 Schematic diagram of the spacing dimensions of the semiconductor device provided in this embodiment. Since this embodiment is introduced by taking the semiconductor device corresponding to the half-bridge circuit as an example, the at least two power elements include a first power tube and a second power tube, wherein the first power tube corresponds to Figure 2 The first MOS tube M1 in the second power tube corresponds to Figure 2 The second MOS tube M2 in.

[0072] This embodiment is described by assuming that the signal pins 101 corresponding to the same power element are arranged in the same group. In one example,

[0073] The spacing between the signal pins 101 corresponding to the same power element is the first distance A1 / A2, that is, the spacing between the signal pins 101 corresponding to the first MOS tube M1 is the first distance A1, and the spacing between the signal pins 101 corresponding to the second MOS tube M2 is the first distance A2; the spacing between the signal pins 101 corresponding to different power elements is the second distance, that is, the spacing between the signal pins 101 in different groups is the second distance B1; the spacing between the power pins is the third distance C, wherein the second distance B1 is greater than the third distance C, and the third distance C is greater than the first distance A1 / A2.

[0074] In some embodiments, the values ​​of the first distances corresponding to different power elements are the same, that is, the spacing between the signal pins 101 corresponding to the first MOS tube M1 is the same as the first distance A1 and the spacing between the signal pins 101 corresponding to the second MOS tube M2 is the same as the first distance A2. In some embodiments, the values ​​of the first distances corresponding to different power elements are different, that is, the spacing between the signal pins 101 corresponding to the first MOS tube M1 is the same as the first distance A1 and the spacing between the signal pins 101 corresponding to the second MOS tube M2 is different as the first distance A2. Whether the values ​​of the first distances corresponding to different power elements are the same can be set based on whether the power elements are the same, for example, the values ​​of the first distances corresponding to different types of power elements are different, and the values ​​of the first distances corresponding to the same type of power elements are the same.

[0075] Generally, the current flowing through the power pin 102 is greater than the current flowing through the signal pin 101, and the current carrying capacity of the power pin 102 needs to be greater than the current carrying capacity of the signal pin 101. Therefore, in some embodiments, the width of the power pin 102 can be set to be greater than the width of the signal pin 101.

[0076] If there is no difference in current carrying capacity between the signal pin 101 and the power pin 102 , in some other embodiments, the width of the power pin 102 may be set to be equal to the width of the signal pin 101 .

[0077] In some embodiments, the widths of all power pins 102 may be the same size, the widths of all signal pins 101 may be the same size, or the widths of the power pins 102 and the widths of the signal pins 101 may be different sizes.

[0078] Since the width of the pin can be set in relation to the current carrying capacity of the pin, in some embodiments, the widths of different power pins 102 are different; accordingly, the widths of different signal pins 101 may also be different.

[0079] The embodiments of the present disclosure do not specifically limit the specific width of each pin, for example, it can be selected according to the flow capacity of the actual application scenario. In addition, the embodiments of the present disclosure do not specifically limit the spacing between pins, and the spacing between pins can be set according to the specific scenario.

[0080] refer to Figure 4 and Figure 5 , Figure 4 A schematic diagram of the circuit structure of a power circuit with a detection function provided in this embodiment, Figure 5 The corresponding Figure 4 Schematic diagram of the packaging structure of a semiconductor device with detection function.

[0081] Since the semiconductor device 100 generates heat when working, it is necessary to detect the temperature of the semiconductor device 100 for the safety of the semiconductor device 100. In some embodiments, the semiconductor device 100 further includes a detection element, which is disposed on the substrate.

[0082] In some embodiments, the detection element can be configured as a temperature sensor, for example, a thermistor is used to implement temperature detection. Specifically, the semiconductor device 100 further includes a thermistor, which is soldered on the substrate.

[0083] In some embodiments, the thermistor NTC can be soldered on the DBC substrate.

[0084] It should be noted that if the semiconductor device 100 includes a detection element, the package body 103 also packages the detection element.

[0085] In some embodiments, the signal pin 101 includes a control pin 111 and a detection pin 121. The detection pin 121 is connected to the detection element, that is, the detection pin 121 is connected to the terminal of the thermistor, and the control pin 111 is used to receive a driving signal corresponding to the power circuit, that is, the signal pin 101 mentioned in the above content.

[0086] The detection pin 121 and the power pin 102 are arranged on the same side, and / or the detection pin 121 and the control pin 111 are arranged on the same side.

[0087] In one example, the detection pin 121 can be set on the same side as the power pin 102; in another example, the detection pin 121 can be set on the same side as the control pin 111; in yet another example, the detection pin 121 can be partially set on the same side as the power pin 102 and partially set on the same side as the control pin 111.

[0088] Specifically, the detection pin 121 is used to detect the performance parameters of the semiconductor device 100 for external adjustment of corresponding control parameters, thereby ensuring that the semiconductor device 100 is in a normal working state.

[0089] In some embodiments, the detection pins 121 include first-type detection pins T1 and second-type detection pins T2 , the first-type detection pins T1 and the control pins 111 are arranged on the same side, and the second-type detection pins T2 and the power pins 102 are arranged on the same side.

[0090] For the thermistor, one end of the thermistor is connected to the first type detection pin T1, the other end of the thermistor is connected to the second type detection pin T2, and the other end of the thermistor is connected to the power pin P1 or P2.

[0091] It should be noted that Figure 4The example is illustrated by taking the other end of the thermistor connected to the power pin P2 as an example, which does not constitute a limitation of this embodiment. In other embodiments, if the other end of the thermistor is connected to the power pin P, the thermistor is connected above the power pin P1.

[0092] Figure 5 and Figure 2 The difference is that Figure 5 A thermistor is added, and the thermistor generally has a negative temperature coefficient (NTC). By detecting a signal of a detection pin 121 corresponding to the thermistor, the resistance parameter of the thermistor is obtained, thereby obtaining the temperature of the semiconductor device 100 .

[0093] Based on the foregoing, it can be known that the width of the pin can be set in relation to the current carrying capacity of the pin. In some embodiments, the width of the first type of detection pin T1 is less than or equal to the width of the control pin 111. For example, the width of the first type of detection pin T1 is less than the width of the control pin 111; for another example, the width of the first type of detection pin T1 is equal to the width of the control pin 111. In some embodiments, the width of the second type of detection pin T2 is less than or equal to the width of the first type of detection pin T1. For example, the width of the second type of detection pin T2 is less than the width of the first type of detection pin T1; for another example, the width of the second type of detection pin T2 is equal to the width of the first type of detection pin T1. Specifically, because the power pin 102 is relatively large in width, the second type of detection pin T2 is set smaller to reduce the impact on the layout of the power pin 102, such as not affecting the layout of multiple power pins 102 within a limited size, and considering the creepage distance between the power pins 102.

[0094] In some embodiments, the distance between the detection pin 121 and the power pin 102 is less than or equal to the distance between the detection pin 121 and the control pin 111 .

[0095] In one example, refer to Figure 5 , the pin width of the control pin 111 corresponding to the same power tube is F, and the pin spacing is A; the pin width of the first type detection pin T1 is F, and the pin width of the second type detection pin T2 is H. The first type detection pin T1 and some control pins 111 are arranged in the same group, and the spacing between control pins in different groups is L, L = A + B + F, where B is greater than A. The pin width of the power pin 102 is G, and the pin spacing between different power pins 102 is C. The minimum spacing between the second type detection pin T2 and the power pin 102 is D, and the maximum spacing is E, where C = D + E + H, and E is greater than D.

[0096] For the above example, in some embodiments, B>C>E>A>D, G>F>H can be set. The built-in temperature sensor of the semiconductor device 100 can monitor the temperature of the internal power device in real time for temperature sampling and protection; and the distance between the two groups of signal pins 101 is increased to reduce the mutual interference of signals between different power tubes; and the problem of difficult wiring on the signal pin 101 side due to the large number of pins is avoided.

[0097] In some embodiments, the signal pins may further include support pins, which may be disposed on the side of the substrate where there are fewer pins. The support pins are used to play a certain supporting and reinforcing role to improve the connection strength of the semiconductor device 100 and its force bearing capacity.

[0098] It should be noted that if the semiconductor device 100 provided in the above embodiment is large enough, in addition to the temperature sensor integrated inside, other detection elements, such as current detection elements, may also be integrated to achieve overcurrent protection for the semiconductor device 100. The embodiments of the present disclosure do not specifically limit other detection elements that may be integrated inside the semiconductor device 100, and may be set according to the size of the entire chip.

[0099] The power pin 102 and the signal pin 101 provided in this embodiment include at least one of the following: a small outline package, a J-type pin small outline package, a quad flat package, a plastic chip carrier with leads, or a plug-in pin.

[0100] Specifically, Small outline Package (SOP): There are legs on both sides of the part, and the legs are splayed outward; generally called gull-wing pins. Small outline J-lead Package (SOJ): There are legs on both sides of the part, and the legs are bent toward the bottom of the part, that is, J-type pins. Quad Flat Package (QFP): There are legs on the four sides of the part, and the legs of the part are splayed outward. Plastic Leadless Chip Carrier (PLCC): There are legs on the four sides of the part, and the legs of the part are bent toward the bottom of the part.

[0101] In some embodiments, at least some of the power pins 102 have different packaging styles and / or at least some of the signal pins 101 have different packaging styles.

[0102] In some embodiments, the packaging form of all signal pins 101 is the same, the packaging form of all power pins 102 is the same, and the packaging form of all detection pins 121 is the same; the packaging form of the signal pins 101, the power pins 102 and the detection pins 121 can be set to the same packaging form or to different packaging forms.

[0103] In some embodiments, in order to make the packaging form of the semiconductor device 100 more flexible, the form of at least some of the power pins 102 is different from the packaging form of at least some of the signal pins 101. All the power pins 102 and all the signal pins 101 can be in different packaging forms, or some of the power pins 102 and all the signal pins 101 can be in the same form, or some of the power pins 102 and some of the signal pins 101 can be in the same form and some can be different.

[0104] In addition, this embodiment also provides a pin design, referring to Figure 6 and Figure 7 , Figure 6 A schematic diagram of pin lengths provided for this embodiment, Figure 7 This is a schematic diagram of the pin angles provided for this embodiment.

[0105] Specifically, the power pin 102 and the signal pin 101 include: a first connection portion, the first end of which is connected to the power circuit on the substrate, and the second end of which is extended outside the substrate; a bending portion, the first end of which is connected to the second end of the first connection portion, the second end of which is connected to the first end of the second connection portion, and the bending portion is at a first angle to the first connection portion and at a second angle to the second connection portion. The second end of the second connection portion is used to connect to a circuit board carrying a semiconductor device.

[0106] In some embodiments, the first angle and the second angle are set in the range of 120° to 150°, and the second angle is greater than the first angle. The package flatness of the semiconductor device 100 is ensured by setting specific pin length and pin angle.

[0107] Specifically, assuming that the angle between the pin and the circuit board is θ, the first angle is α, and the second angle is β, then β=α+θ; in specific applications, the first angle and the second angle can be actually set according to the angle between the pin and the circuit board. In one example, the first angle is 135°, the second angle is 137°, and the angle between the pin and the circuit board is 2°; in another example, the first angle is 139°, the second angle is 140°, and the angle between the pin and the circuit board is 1°.

[0108] In some embodiments, the first connecting portion is a first length L1, the bending portion is a second length L2, and the second connecting portion is a third length L3; wherein, the first length L1 is greater than the third length L3, and the third length L3 is greater than the second length L2. By reasonably setting the lengths of the first connecting portion, the second connecting portion and the third connecting portion, the flatness of the package of the semiconductor device 100 is ensured while increasing the strength of the pins.

[0109] In summary, the embodiments of the present disclosure separate the power routing and signal routing in the semiconductor device in practical applications by setting the signal pin and the power pin on different sides of the substrate and distributing the power pin and the signal pin on different sides of the semiconductor device, thereby avoiding cross routing and mutual interference between the power routing and the signal routing, and avoiding the problem of difficulty in wiring on the signal pin 101 side due to the large number of pins.

[0110] Another embodiment of the present disclosure further provides an on-board charger, wherein a circuit structure of the on-board charger includes the semiconductor device 100 described above.

[0111] Specifically, the on-board charger may include a power converter, wherein the power converter may include a rectifier circuit and a DC / DC circuit, wherein the rectifier circuit may include the semiconductor device 100 introduced in the above embodiment, and the DC / DC circuit may also include the semiconductor device 100 introduced in the above embodiment.

[0112] In addition, the embodiments of the present disclosure do not specifically limit the implementation form of the rectifier circuit, and the rectifier circuit may be a half-bridge circuit or a full-bridge circuit.

[0113] When the rectifier circuit is a half-bridge circuit, the semiconductor device 100 corresponding to the half-bridge circuit introduced in the above embodiment can be used; if it is a full-bridge circuit, the semiconductor device 100 corresponding to the half-bridge circuit introduced in the above embodiment can also be used, but the full-bridge circuit requires more than one semiconductor device 100 corresponding to the half-bridge circuit.

[0114] Since the on-board charger provided by the embodiment of the present disclosure includes the semiconductor device 100 provided by the above embodiment, the semiconductor device 100 has a flexible packaging form; therefore, the on-board charger formed based on the semiconductor device 100 has simple circuit wiring and circuit board design.

[0115] Another embodiment of the present disclosure provides a vehicle, including the semiconductor device or the on-board charger. The vehicle provided by the present disclosure can realize bidirectional power transmission without adapting more driving circuits, thereby reducing circuit area and system complexity.

[0116] The exclusive right of the vehicle has all the beneficial effects of the above-mentioned minimum protection subject, which will not be described in detail in this disclosure. The vehicle can be a fuel vehicle, a plug-in hybrid vehicle or a new energy vehicle, etc., which is not specifically limited in this disclosure.

[0117] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the detailed description of other embodiments above, and will not be repeated here.

[0118] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only for example and does not constitute a limitation of the present disclosure. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements and corrections to the present disclosure. Such modifications, improvements and corrections are suggested in the present disclosure, so such modifications, improvements and corrections still belong to the spirit and scope of the exemplary embodiments of the present disclosure.

[0119] The semiconductor device, vehicle charger and vehicle provided by the embodiments of the present disclosure are introduced in detail above. The principles and implementation methods of the present disclosure are explained in this article using specific examples. The description of the above embodiments is only used to help understand the method and core idea of ​​the present disclosure. At the same time, for those skilled in the art, according to the idea of ​​the present disclosure, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present disclosure.

Claims

1. A semiconductor device (100), characterized in that: include: A substrate, a power circuit, a power pin (102) and a signal pin (101); The power circuit is arranged on the substrate; The power pin (102) and the signal pin (101) are connected to the power circuit; The signal pins (101) arranged on the same side of the substrate are arranged in groups, and the spacing between the signal pins (101) in different groups is greater than the spacing between the power pins (102).

2. The semiconductor device (100) according to claim 1, characterized in that The spacing between the signal pins (101) in the same group is smaller than the spacing between the power pins (102).

3. The semiconductor device (100) according to claim 1, characterized in that The power pins (102) are arranged on a first side of the substrate, and at least part of the signal pins (101) are arranged on a second side of the substrate, and the first side and the second side are different sides of the substrate.

4. The semiconductor device (100) according to claim 3, characterized in that: The first side edge and the second side edge are opposite sides of the substrate.

5. The semiconductor device (100) according to claim 3 or 4, characterized in that: The signal pins (101) arranged on the second side are arranged in groups, and the spacing between the signal pins (101) in different groups is greater than the spacing between the power pins (102).

6. The semiconductor device (100) according to any one of claims 1 to 4, characterized in that: The power circuit comprises at least two power elements, and the signal pins (101) corresponding to different power elements are arranged in different groups.

7. The semiconductor device (100) according to claim 1, characterized in that The width of the power pin (102) is greater than the width of the signal pin (101).

8. The semiconductor device (100) according to claim 7, characterized in that: The widths of the different power pins (102) are different.

9. The semiconductor device (100) according to any one of claims 1 to 4, characterized in that: The semiconductor device (100) further comprises a detection element, and the signal pin (101) comprises a control pin (111) and a detection pin (121); The detection pin (121) is connected to the detection element, and the control pin (111) is used to receive a drive signal corresponding to the power circuit; The detection pin (121) and the power pin (102) are arranged on the same side, and / or the detection pin (121) and the control pin (111) are arranged on the same side.

10. The semiconductor device (100) according to claim 9, characterized in that The detection pins (121) include: a first type of detection pins and a second type of detection pins; The first type of detection pin and the control pin (111) are arranged on the same side; The second type detection pin and the power pin (102) are arranged on the same side.

11. The semiconductor device (100) according to claim 9, characterized in that The width of the second type pin (201) is less than or equal to the width of the control pin (111).

12. The semiconductor device (100) according to claim 10, characterized in that The width of the second type of detection pins is less than or equal to the width of the first type of detection pins.

13. The semiconductor device (100) according to claim 9, characterized in that The distance between the detection pin (121) and the power pin (102) is less than or equal to the distance between the detection pin (121) and the control pin (111).

14. The semiconductor device (100) according to any one of claims 1 to 4, characterized in that: The packaging form of the signal pin (101) and the power pin (102) includes at least one of the following: a small outline package, a J-shaped pin small outline package, a square flat package, a plastic chip carrier with leads, or a direct-insert pin package.

15. The semiconductor device (100) according to claim 14, characterized in that At least some of the signal pins (101) and / or the power pins (102) are packaged in different forms.

16. The semiconductor device (100) according to any one of claims 1 to 4, characterized in that: The signal pin (101) and / or the power pin (102) comprises: A first connecting portion, wherein a first end is connected to the power circuit on the substrate, and a second end is extended out of the substrate; A bending portion, wherein a first end is connected to the second end of the first connecting portion, a second end is connected to the first end of the second connecting portion, and the bending portion forms a first angle with the first connecting portion and a second angle with the second connecting portion; The second end of the second connecting portion is used to connect to a circuit board carrying the semiconductor device (100).

17. The semiconductor device (100) according to claim 16, characterized in that The first angle and the second angle are set in the range of 120° to 150°, and the second angle is greater than the first angle.

18. The semiconductor device (100) according to claim 16, characterized in that The first connecting portion has a first length, the bending portion has a second length, and the second connecting portion has a third length; wherein the first length is greater than the third length, and the third length is greater than the second length.

19. A vehicle-mounted charger, characterized in that: The components of the on-vehicle charger include the semiconductor device (100) according to any one of claims 1 to 18.

20. A means of transport, characterized in that: The invention comprises the semiconductor device according to any one of claims 1 to 18, or comprises the on-vehicle charger according to claim 19.

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