Memory element and manufacturing method thereof

Abstract

A memory element includes a substrate, a first word line structure, a first dielectric layer, a dielectric liner and a bit line structure. The first word line structure is in the substrate and includes a first bottom conductive material and a first top conductive material, where a top surface of the first bottom conductive material is wider than a bottom surface of the first top conductive material. The first dielectric layer is over the first word line structure. The dielectric liner is lined on the first word line structure. The bit line structure is located on the substrate. Capacitance between a word line structure and a bit line structure can be reduced, and electric leakage between the bit line structure and a substrate can be further improved.

Description

Technical Field

[0001] The present disclosure relates to a memory device and a method for manufacturing the same. Background Art

[0002] Semiconductor devices (such as memory devices, dynamic random access memory (DRAM) or other devices for storing information) are now widely used in many applications. Dynamic random access memory includes a plurality of dynamic random access memory cells, each of which includes a capacitor (for storing information) and a transistor coupled to the capacitor (for controlling the timing of charging and discharging the capacitor). In a read operation, the word line (WL) is asserted to enable the transistor. The enabled transistor allows the sense amplifier to access the voltage across the capacitor through the bit line (BL). In a write operation, the data to be written is provided to the bit line when the word line is asserted. Summary of the invention

[0003] An embodiment of the present disclosure provides a memory element, comprising a substrate, a first word line structure, a first dielectric layer, a dielectric liner, and a bit line structure. The first word line structure is in the substrate and comprises a first bottom conductive material and a first top conductive material located on the first bottom conductive material, wherein a top surface of the first bottom conductive material is wider than a bottom surface of the first top conductive material. The first dielectric layer is located on the first word line structure. The dielectric liner is located on the first word line structure. The bit line structure is located on the substrate.

[0004] In some embodiments, the first dielectric layer is in contact with the first bottom conductive material.

[0005] In some embodiments, the first top conductive material has a first spacer and a second spacer opposite to the first spacer, the first spacer contacts the first dielectric layer, and the second spacer contacts the dielectric liner.

[0006] In some embodiments, a bottom surface of the first dielectric layer is smaller than a top surface of the first top conductive material.

[0007] In some embodiments, the capacitor is electrically coupled to the doped region of the substrate.

[0008] In some embodiments, a top surface of a portion of the first bottom conductive material is not covered by the first top conductive material.

[0009] In some embodiments, the first dielectric layer contacts a top surface of the first top conductive material and sidewalls of the first top conductive material.

[0010] In some embodiments, it also includes: an insulating structure located in the substrate; and a second word line structure located in the insulating structure, including: a second bottom conductive material; and a second top conductive material located above the second bottom conductive material, wherein the top surface of the second bottom conductive material and the bottom surface of the second top conductive material have equal widths.

[0011] In some embodiments, the second top conductive material is wider than the first top conductive material.

[0012] In some embodiments, a second dielectric layer is further included on the second top conductive material, wherein the first dielectric material contacts a portion of the first bottom conductive material, and the second dielectric layer is spaced apart from the second bottom conductive material.

[0013] An embodiment of the present disclosure provides a method for manufacturing a memory element, comprising: forming a first trench in a substrate; forming a first dielectric liner and lining the first trench; forming a first bottom conductive material on the first dielectric liner; forming a first top conductive material on the first bottom conductive material; removing a portion of the first top conductive material to expose a portion of the first bottom conductive material; forming a first dielectric layer on the remaining portion of the first top conductive material; and forming a bit line structure on the substrate.

[0014] In some embodiments, a material of the first top conductive material is different from a material of the first bottom conductive material.

[0015] In some embodiments, forming the bit line structure further includes: forming a groove in the substrate; depositing a first conductive layer to fill the groove; depositing a second conductive layer on the first conductive layer; and patterning the second conductive layer and the first conductive layer.

[0016] In some embodiments, removing a portion of the first top conductive material includes: forming a patterned mask on the substrate, wherein the patterned mask exposes a portion of the first top conductive material and covers other portions of the first top conductive material; etching a portion of the first top conductive material through the patterned mask; and removing the patterned mask.

[0017] In some embodiments, the method further includes etching back the first top conductive material before removing the portion of the first top conductive material.

[0018] In some embodiments, the first dielectric layer contacts a top surface of the remaining portion of the first top conductive material and a sidewall of the remaining portion of the first top conductive material.

[0019] In some embodiments, the remaining portion of the first top conductive material includes a first spacer and a second spacer opposite to the first spacer, the first spacer contacts the first dielectric layer, and the second spacer contacts the first dielectric liner.

[0020] In some embodiments, it also includes: forming an insulating structure in the substrate; forming a second groove in the insulating structure; forming a second dielectric liner lining the second groove; forming a second bottom conductive material on the second dielectric liner; and forming a second top conductive material on the second bottom conductive material, wherein after removing part of the first top conductive material, the remaining part of the first top conductive material is narrower than the second top conductive material.

[0021] In some embodiments, the method further includes forming a second dielectric layer on the second top conductive material, wherein the second dielectric layer is separated from the second bottom conductive material by the second top conductive material.

[0022] In some embodiments, removing a portion of the first top conductive material includes: forming a patterned mask on the substrate, wherein the patterned mask exposes a portion of the first top conductive material and covers the second top conductive material; etching a portion of the first top conductive material through the patterned mask, wherein during the process of etching the portion of the first top conductive material, the second top conductive material is protected by the patterned mask; and removing the patterned mask.

[0023] It is to be understood that both the foregoing general description and the following detailed description are exemplary and are intended to provide further explanation of the present invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The various embodiments of the present disclosure may be understood by reading the following detailed description in conjunction with the corresponding drawings.

[0025] Figure 1 is a circuit diagram of a memory cell of a memory device according to some embodiments of the present disclosure.

[0026] Figure 2 is a cross-sectional view of a memory device according to some embodiments of the present disclosure.

[0027] Figures 3 to 14 are cross-sectional views of various stages in forming a memory device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0028] Reference will now be made in detail to the present embodiments of the present disclosure, examples of which will be illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used in the drawings and description to indicate the same or similar parts.

[0029] Figure 11 is a circuit diagram of a memory cell of a memory device according to some embodiments of the present disclosure. Shown is a memory device 100, which includes at least one memory cell 102. In some embodiments, the memory device 100 is a dynamic random access memory. The memory cell 102 of the memory device 100 includes a transistor 100T and a capacitor 100C as the main structure. One end of the capacitor 100C is coupled to the drain region of the transistor 100T, and the other end of the capacitor 100C is grounded. The memory device 100 also includes a word line 100W (coupled to the gate of the transistor 100T) and a bit line 100B (coupled to the source of the transistor 100T). The operation of the device can be achieved by using the word line 100W and the bit line 100B, and the storage of data can be achieved by controlling the charge in the capacitor 100C. The transmission of charge on the capacitor 100C can be determined by controlling the transistor 100T, which can be manipulated by the bit line 100B and the word line 100W to represent the reading and writing of signals.

[0030] Figure 2 2 is a cross-sectional view of a memory device according to some embodiments of the present disclosure. Memory device 200 is shown here. In some embodiments, the cross-sectional view of memory device 200 may be as shown in FIG. Figure 1 An example of the memory device 100 described in .

[0031] Memory device 200 includes substrate 201. In some embodiments, substrate 201 may be a suitable semiconductor material, such as silicon, silicon carbide, gallium arsenide, gallium phosphide, germanium, indium antimonide, indium phosphide, indium arsenide, or the like. Substrate 201 may also be doped with a suitable dopant. For example, substrate 201 may be doped with a p-type dopant, such as boron (B), gallium (Ga), indium (In), aluminum (Al), or the like. In other embodiments, substrate 201 may be doped with an n-type dopant, such as phosphorus (P), arsenic (As), or antimony (Sb), or the like.

[0032] The insulating structure 202 is disposed in the substrate 201. The insulating structure 202 may be a suitable insulating structure, such as a shallow trench isolation (STI) structure. Figure 2 In the cross-sectional view of FIG. 2 , two insulating structures 202 are shown, which define an active region 201A (on which at least one transistor is formed). In some embodiments, the insulating structures 202 can be made of a suitable material, such as silicon oxide, silicon nitride, or the like.

[0033] The memory device 200 further includes a plurality of word line structures 216A and 216B. Figure 2In the cross-sectional view of , the word line structure 216A is encapsulated in the active region 201A of the substrate 201 , while the word line structure 216B is encapsulated in the insulating structure 202 .

[0034] The memory device 200 further includes a dielectric layer 206A disposed above the respective word line structures 216A, and a dielectric liner 203A lining the respective word line structures 216A and the dielectric layer 206A. In some embodiments, the dielectric layer 206A may include a suitable dielectric material, such as silicon oxide, silicon nitride, or the like. In some embodiments, the dielectric liner 203A may include a suitable dielectric material, such as silicon oxide, silicon nitride, or the like.

[0035] Likewise, the memory device 200 further includes a dielectric layer 206B on each word line structure 216B, and a dielectric liner 203B lining the word line structure 216B and the dielectric layer 206B, respectively. The materials of the dielectric layer 206B and the dielectric liner 203B are similar to those described for the dielectric layer 206A and the dielectric liner 203A, and thus the related details are not discussed again for the sake of brevity.

[0036] In some embodiments, each word line structure 216A includes a bottom conductive material 204A and a top conductive material 205A (located on the bottom conductive material 204A). In some embodiments, the bottom conductive material 204A and the top conductive material 205A are made of different materials. In some embodiments, the bottom conductive material 204A may include a suitable conductive material, such as cobalt, nickel, titanium, titanium nitride, tungsten, tungsten nitride, the like, or a combination thereof. For example, in some embodiments, a combination of titanium nitride and tungsten is used as the bottom conductive material 204A. In some embodiments, the top conductive material 205A may be a suitable material to reduce the band bending between the active region 201A and the dielectric liner 203A. The top conductive material 205A may be a semiconductor material or a conductive material. In some embodiments, polysilicon is used for the top conductive material 205A. In other embodiments, doped polysilicon is used for the top conductive material 205A.

[0037] The top surface of the bottom conductive material 204A has a width L1, and the bottom surface of the top conductive material 205A has a width L2. In some embodiments, the width L1 is greater than the width L2. That is, at least a portion of the top surface of the bottom conductive material 204A is not covered by the top conductive material 205A. Therefore, at least a portion of the top surface of the bottom conductive material 204A is in contact with the dielectric layer 206A. In some embodiments, the dielectric layer 206A may be in contact with the sidewalls of the top conductive material 205A and the top surface of the top conductive material 205A. In some embodiments, the top conductive material 205A has a first sidewall and a second sidewall opposite to each other, wherein the first sidewall is in contact with the dielectric liner 203A and the second sidewall is in contact with the dielectric layer 206A. In some embodiments, the bottom surface of the dielectric layer 206A is lower than the top surface of the top conductive material 205A. Although the top conductive material 205A is shown as having a square cross-section, the present disclosure is not intended to be limited thereto. In other embodiments, the cross-section of the top conductive material 205A may also be semicircular, triangular, trapezoidal, inverted trapezoidal, or irregular.

[0038] With respect to the word line structures 216B, each word line structure 216B includes a bottom conductive material 204B and a top conductive material 205B (located on the bottom conductive material 204B). The materials of the bottom conductive material 204B and the materials of the top conductive material 205B may be similar to those described for the bottom conductive material 204A and the materials of the top conductive material 205A, and thus the related details are not discussed again for the sake of brevity.

[0039] The word line structure 216B differs from the word line structure 216A in that the top surface of the bottom conductive material 204B has a width L3, the bottom surface of the top conductive material 205B has a width L4, and the width L3 is substantially equal to the width L4. In other words, the top surface of the bottom conductive material 204B is completely covered by the top conductive material 205B. Therefore, the bottom conductive material 204B is completely vertically separated from the dielectric layer 206B by the top conductive material 205B. In some embodiments, the top conductive material 205B can be wider than the top conductive material 205A, and the width L4 can be greater than the width L2.

[0040] The memory device 200 further includes a doped region 201D in the active region 201A of the substrate 201, wherein a pair of doped regions are disposed on opposite sides of the word line structure 216A. In some embodiments, the doped region 201D may include an opposite conductivity type to the substrate 201. For example, when the substrate 201 is a p-type substrate, the doped region 201D may be an n-type doped region. Similarly, when the substrate 201 is an n-type substrate, the doped region 201D may be a p-type doped region.

[0041] Here, the word line structure 216A, the dielectric liner 203A, the pair of doped regions 201D on opposite sides of the word line structure 216A, and the active region 201A of the substrate 201 can be used together as a transistor of the memory device 200 (eg Figure 1 In more detail, the word line structure 216A may serve as a gate of the transistor, the dielectric liner 203A may serve as a gate dielectric of the transistor, the active region 201A of the substrate 201 may serve as a channel region of the transistor, and the doped region 201D may serve as a source / drain region of the transistor.

[0042] The memory device 200 further includes a bit line structure 217 (located on the substrate 201) and electrically coupled to a doped region 201D. In some embodiments, the bit line structure 217 may include a buried contact 212A and a bit line 211A (located on the buried contact 212A). In some embodiments, a portion of the buried contact 212A is encapsulated in the substrate 201 and a portion protrudes from the substrate 201. In some embodiments, the material of the buried contact 212A may be doped silicon or polysilicon. In some embodiments, the material of the bit line 211A may be a suitable conductive material, such as tungsten, tungsten nitride, titanium nitride, the like, or a combination thereof.

[0043] The memory device 200 further includes a capacitor contact structure 218 (located on the substrate 201) and electrically coupled to the doped region 201D. In some embodiments, each capacitor contact structure 218 may include a buried contact 212B and a metal contact 211B (located on the buried contact 212B). In some embodiments, a portion of the buried contact 212B is encapsulated in the substrate 201 and a portion protrudes from the substrate 201. In some embodiments, the materials of the buried contact 212B and the materials of the metal contact 211B may be similar to those described in the structures of the buried contact 212A and the bit line 211A, and thus the relevant details are not discussed again for brevity.

[0044] The memory device 200 further includes capacitor structures 215 (respectively located on the capacitor contact structures 218). In some embodiments, each capacitor structure 215 includes a lower electrode 208, an intermediate dielectric 209, and an upper electrode 210, wherein the intermediate dielectric 209 is disposed between the upper electrode 210 and the lower electrode 208. In some embodiments, the lower electrode 208 and the intermediate dielectric 209 may include a U-shaped cross-section.

[0045] The memory device 200 further includes a dielectric layer 207 (located on the substrate 201 and laterally surrounding the bit line structure 217), a capacitor contact structure 218, and a capacitor structure 215. In some embodiments, the dielectric layer 207 can be made of silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric material, the like, or a combination thereof.

[0046] The disclosed embodiments provide a memory device in which a portion of the top conductive material 205A of the word line structure 216A is removed. This will result in a thicker portion of the upper dielectric layer 206A between the word line structure 216A and the bit line structure 217, which can reduce the capacitance between the word line structure 216A and the bit line structure 217. In addition, the thicker dielectric layer 206A at the boundary of the word line structure 216A can also reduce the electric field (when the word line structure 216A is in an open state) and further improve the leakage between the bit line structure 217 and the substrate 201.

[0047] Figures 3 to 14 1 is a cross-sectional view of a memory device at various stages of formation according to some embodiments of the present disclosure. In more detail, Figures 3 to 14 A method for forming a memory element 200 (eg, Figure 2 Therefore, similar components will have the same reference numerals and the relevant details will not be repeated for the sake of brevity.

[0048] refer to Figure 3 , a substrate 201 is provided. An insulating structure 202 is formed in the substrate 201 to define an active region 201A. For example, a series of deposition processes may be performed to deposit a pad oxide layer (not shown) and a pad nitride layer (not shown) on the substrate 201. A photolithography process may be performed to define the position of the insulating structure 202. After the photolithography process, an etching process (such as an anisotropic etching process) may be performed to form a groove through the pad oxide layer, the pad nitride layer and the substrate 201. In some embodiments, a cleaning process may be performed by a suitable cleaning method, such as wet cleaning. An insulating material may be deposited into the trench, and a planarization process (such as chemical mechanical polishing) may then be performed to remove excess fill material until the substrate 201 is exposed. After the insulating structure 202 is formed, a doped region 201D may be formed in the active region 201A of the substrate 201 by an implantation process.

[0049] refer to Figure 4, trench 401A and trench 401B are formed in substrate 201 and insulating structure 202, respectively. In some embodiments, a patterned mask (e.g., a photoresist) is formed on substrate 201, wherein the patterned mask may include an opening (defining the location of trench 401A and trench 401B). Thereafter, an etching process may be performed from the opening of the patterned mask to remove portions of substrate 201 and insulating structure 202, thereby forming trench 401A and trench 401B. In some embodiments, the etching process may be a suitable etching process, such as wet etching or dry etching. In some embodiments, an anisotropic etching process may be performed, such as reactive ion etching (RIE), deep reactive ion etching (DRIE), or the like. In some embodiments, the aspect ratio of trench 401A may be different (or the same) as the aspect ratio of trench 401B.

[0050] refer to Figure 5 , dielectric liner 203A and word line structure 216A are formed in trench 401A, and dielectric liner 203B and word line structure 216B are formed in trench 401B, respectively. Word line structure 216A includes bottom conductive material 204A and top conductive material 205A (located above bottom conductive material 204A). Word line structure 216B includes bottom conductive material 204B and top conductive material 205B (located above bottom conductive material 204B).

[0051] In some embodiments, a first deposition process may be performed to form the material of the dielectric liner 203A and the material of the dielectric liner 203B on the substrate 201 and line the sidewalls of the trench 401A and the sidewalls of the trench 401B. In some embodiments, the first deposition process may be a suitable deposition process, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), ultra-high vacuum chemical vapor deposition (UHVCVD), atomic layer deposition (ALD), or the like.

[0052] Afterwards, a second deposition process may be performed to form the material of the bottom conductive material 204A and the material of the bottom conductive material 204B on the substrate 201 and fill the trench 401A and the trench 401B. Next, an etch-back process is performed to lower the top surface of the material of the bottom conductive material 204A and the top surface of the material of the bottom conductive material 204B.

[0053] Next, a third deposition process is performed to form the material of the top conductive material 205A and the material of the top conductive material 205B to overfill the trench 401A and the trench 401B.

[0054] After the third deposition process, a planarization process (such as chemical mechanical polishing) may be performed on the material of the top conductive material 205A and the material of the top conductive material 205B until the substrate 201 is exposed. Therefore, the top surface of the substrate 201, the top surface of the top conductive material 205A, the top surface of the top conductive material 205B, and the top surface of the insulating structure 202 are substantially coplanar. In some embodiments, a cleaning process may be performed after the planarization process.

[0055] refer to Figure 6 An etch-back process may be performed to lower the top surface of the top conductive material 205A and the top surface of the top conductive material 205B to form the trench 601A and the trench 601B of the word line structure 216A and the word line structure 216B, respectively.

[0056] refer to Figure 7 , a patterned mask 701 may be formed on the substrate 201 and fill the trench 601B and a portion of the trench 601A. The patterned mask 701 may include an opening 703 (exposing a portion of the top conductive material 205A of the word line structure 216A). In some embodiments, the patterned mask 701 may cover the top conductive material 205B, the surface of the substrate 201, the surface of the insulating structure 202, and the top conductive material 205A. In some embodiments, a portion of the top conductive material 205A may be covered by the patterned mask 701 and another portion of the top conductive material 205A may be exposed through the opening 703. In some embodiments, the patterned mask 701 may include a photoresist, a hard mask, or the like.

[0057] refer to Figure 8, an etching process is performed to etch and expose a portion of the top conductive material, so that a portion of the bottom conductive material 204A below is exposed. In some embodiments, the etching process can be performed with a suitable etching method, such as wet etching, dry etching, or a combination thereof. In some embodiments, the wet etching can be performed with a suitable wet etchant, such as hydrofluoric acid, phosphoric acid, sulfuric acid, nitric acid, acetic acid, the like, or a combination thereof. In some embodiments, an additive can be provided with the wet etchant, such as ammonia, hydrogen peroxide, the like, or a combination thereof. In some embodiments, the etching process can be performed with a suitable dry etching method, such as reactive ion etching, deep reactive ion etching, neutral beam etching (NBE). In some embodiments, the anisotropic dry etching method can be performed with a suitable etching gas, such as fluorine, chlorine, bromine, methyl fluoride, methyl chloride, methyl bromide, hydrogen halide, the like, or a combination thereof. In some embodiments, a gas additive can be provided with the etching gas, such as sulfur oxide, sulfur fluoride, boron chloride, hydrocarbons, oxygen, hydrogen, the like, or a combination thereof. After the etching process, recesses 901 are formed on the top conductive material 205A, respectively.

[0058] refer to Fig. 9 After the etching process, a removal process may be performed to remove the patterned mask 701. In some embodiments, the removal process of the patterned mask 701 may be performed using a suitable removal method, such as a wet cleaning process using a suitable solution or organic solvent. In some embodiments, the removal process may be performed using a plasma cleaning method, such as an ashing method.

[0059] refer to Fig.10 , dielectric layer 206A and dielectric layer 206B are formed on word line structure 216A and word line structure 216B, respectively. In some embodiments, a deposition process may be performed to form a dielectric material on substrate 201 and cover word line structure 216A and word line structure 216B. Next, a planarization process may be performed to remove excess dielectric material until substrate 201 is exposed. In some embodiments, the planarization process may be performed to make the top surface of dielectric layer 206A and the top surface of dielectric layer 206B coplanar with the surface of substrate 201.

[0060] refer to Fig.11, recess 111A and recess 111B are formed in doped region 201D of substrate 201. In some embodiments, the bottom of recess 111A and the bottom of recess 111B may be higher than the top surface of top conductive material 205A. In some embodiments, a patterned mask (not shown) is formed on substrate 201, and an etching process is performed to remove exposed portions of substrate 201 (via the patterned mask) to form recess 111A and recess 111B. In some embodiments, a cleaning process may be performed after the etching process. In some embodiments, recess 111A may be formed between adjacent dielectric layers 206A. In some embodiments, recess 111B may be formed between adjacent dielectric layers 206A and 206B.

[0061] refer to Fig.12 , a first conductive layer 121 is formed on the substrate 201, and a second conductive layer 123 is formed on the first conductive layer 121. In some embodiments, the first conductive layer 121 may fill the grooves 111A and 111B, and may contact the doped region 201D. In some embodiments, the first conductive layer 121 and the second conductive layer 123 may be formed by a suitable deposition process.

[0062] refer to Fig.13 , the first conductive layer 121 and the second conductive layer 123 are patterned to form a bit line structure 217 and a capacitor contact structure 218. In some embodiments, the bit line structure 217 includes a buried contact 212A and a bit line 211A (on the buried contact 212A), wherein the buried contact 212A is the remaining portion of the first conductive layer 121, and the bit line 211A is the remaining portion of the second conductive layer 123. On the other hand, the capacitor contact structure 218 includes a buried contact 212B and a metal contact 211B (on the buried contact 212B), wherein the buried contact 212B is the remaining portion of the first conductive layer 121, and the metal contact 211B is the remaining portion of the second conductive layer 123.

[0063] refer to Fig.14 , a dielectric layer 207 is formed on the substrate 201 and covers the bit line structure 217 and the capacitor contact structure 218. Then, the capacitor structure 215 is formed in the dielectric layer 207 and contacts the capacitor contact structure 218 respectively. In some embodiments, the dielectric layer 207 can be formed using a suitable deposition process. In some embodiments, the formation of the capacitor structure 215 can be by, for example, patterning the dielectric layer 207 to form an opening to expose the capacitor contact structure 218, depositing the lower electrode 208, the middle dielectric 209 and the upper electrode 210 in the opening, and then performing a planarization process until the dielectric layer 207 is exposed.

[0064] In some embodiments, additional processes and steps may be implemented to complete the fabrication process of the memory device. In some embodiments, additional back end of line (BEOL) processes may be implemented on the memory device 200 .

[0065] Although the present invention has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0066] It is obvious to those skilled in the art that various modifications and changes can be made to the structure of the present disclosure without departing from the scope or spirit of the present disclosure. In view of the foregoing, the present disclosure is intended to cover modifications and changes of the present disclosure as long as they fall within the scope of the appended claims.

[0067]

Explanation of symbols

[0068] 100: memory element

[0069] 100B: bit line

[0070] 100C:Capacitance

[0071] 100T: Transistor

[0072] 100W: Character Line

[0073] 200: memory element

[0074] 201:Substrate

[0075] 201A: Active Area

[0076] 201D: Doping area

[0077] 202: Insulation structure

[0078] 203A: Dielectric liner

[0079] 203B: Dielectric liner

[0080] 204A: Bottom conductive material

[0081] 204B: Bottom conductive material

[0082] 205A: Top conductive material

[0083] 205B: Top conductive material

[0084] 206A: Dielectric layer

[0085] 206B: Dielectric layer

[0086] 207: Dielectric layer

[0087] 208: Lower electrode

[0088] 209:Intermediate dielectric

[0089] 210: Upper electrode

[0090] 211A: Bit line

[0091] 211B: Metal contact

[0092] 212A:Buried Contact

[0093] 212B: Buried Contact

[0094] 215: Capacitor structure

[0095] 216A: Character line structure

[0096] 216B: Character line structure

[0097] 217: Bit Line Structure

[0098] 218: Capacitor contact structure

[0099] 401A: Groove

[0100] 401B: Groove

[0101] 601A: Groove

[0102] 601B: Groove

[0103] 701: Mask

[0104] 703: Opening

[0105] 901: Groove

[0106] 111A: Groove

[0107] 111B: Groove

[0108] 121: Conductive layer

[0109] 123: Conductive layer

[0110] L1: Width

[0111] L2: Width

[0112] L3: Width

[0113] L4: Width.

Claims

1. A memory element, characterized in that: Include: substrate; The first word line structure, located in the substrate, comprises: a first bottom conductive material; and a first top conductive material disposed on the first bottom conductive material, wherein a top surface of the first bottom conductive material is wider than a bottom surface of the first top conductive material; A first dielectric layer is located on the first word line structure; A dielectric liner lining the first word line structure; as well as The bit line structure is located on the substrate. 2 . The memory device according to claim 1 , wherein the first dielectric layer contacts the first bottom conductive material. 3 . The memory device according to claim 1 , wherein the first top conductive material has a first spacer and a second spacer opposite to the first spacer, the first spacer contacts the first dielectric layer, and the second spacer contacts the dielectric liner. 4 . The memory device of claim 1 , wherein a bottom surface of the first dielectric layer is smaller than a top surface of the first top conductive material.

5. The memory element according to claim 1, wherein: A capacitor is also included that is electrically coupled to the doped region of the substrate. 6 . The memory element of claim 1 , wherein a portion of the top surface of the first bottom conductive material is not covered by the first top conductive material. 7 . The memory device according to claim 1 , wherein the first dielectric layer contacts a top surface of the first top conductive material and a sidewall of the first top conductive material.

8. The memory element according to claim 1, wherein: Also includes: an insulating structure disposed in the substrate; and The second word line structure, located in the insulating structure, comprises: a second bottom conductive material; and A second top conductive material is disposed on the second bottom conductive material, wherein a top surface of the second bottom conductive material and a bottom surface of the second top conductive material have equal widths. 9 . The memory device of claim 8 , wherein the second top conductive material is wider than the first top conductive material.

10. The memory element according to claim 8, wherein: A second dielectric layer is also included on the second top conductive material, wherein the first dielectric material contacts a portion of the first bottom conductive material, and the second dielectric layer is spaced apart from the second bottom conductive material.

11. A method for manufacturing a memory element, characterized in that: Include: forming a first trench in the substrate; forming a first dielectric liner lining the first trench; forming a first bottom conductive material on the first dielectric liner; forming a first top conductive material on the first bottom conductive material; removing a portion of the first top conductive material to expose a portion of the first bottom conductive material; forming a first dielectric layer on the remaining portion of the first top conductive material; as well as A bit line structure is formed on the substrate. 12 . The method of claim 11 , wherein a material of the first top conductive material is different from a material of the first bottom conductive material.

13. The method of claim 11 , wherein forming the bit line structure further comprises: forming a groove in the substrate; depositing a first conductive layer to fill the groove; depositing a second conductive layer on the first conductive layer; and The second conductive layer and the first conductive layer are patterned.

14. The method of claim 11 , wherein removing the portion of the first top conductive material comprises: forming a patterned mask on the substrate, wherein the patterned mask exposes the portion of the first top conductive material and covers other portions of the first top conductive material; etching the portion of the first top conductive material through the patterned mask; and Remove the patterned mask.

15. The method according to claim 11, wherein: Also included is etching back the first top conductive material before removing the portion of the first top conductive material. 16 . The method according to claim 11 , wherein the first dielectric layer contacts a top surface of the remaining portion of the first top conductive material and a sidewall of the remaining portion of the first top conductive material. 17 . The method according to claim 11 , wherein the remaining portion of the first top conductive material comprises a first spacer and a second spacer opposite to the first spacer, the first spacer contacts the first dielectric layer, and the second spacer contacts the first dielectric liner.

18. The method according to claim 11, wherein: Also includes: forming an insulating structure in the substrate; forming a second trench in the insulating structure; forming a second dielectric liner lining the second trench; forming a second bottom conductive material on the second dielectric liner; as well as A second top conductive material is formed on the second bottom conductive material, wherein after removing the portion of the first top conductive material, the remaining portion of the first top conductive material is narrower than the second top conductive material.

19. The method according to claim 18, wherein: The method further includes forming a second dielectric layer on the second top conductive material, wherein the second dielectric layer is separated from the second bottom conductive material by the second top conductive material.

20. The method of claim 18, wherein removing the portion of the first top conductive material comprises: forming a patterned mask on the substrate, wherein the patterned mask exposes the portion of the first top conductive material and covers the second top conductive material; etching the portion of the first top conductive material through the patterned mask, wherein the second top conductive material is protected by the patterned mask during etching of the portion of the first top conductive material; and Remove the patterned mask.

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