Semiconductor Structure and Method for Preparing the Same

Abstract

A semiconductor structure and a method for manufacturing the same. The method for manufacturing the semiconductor structure includes: forming a stacked structure on a substrate; forming a first isolation structure, a sacrificial structure, and a filling layer in the stacked structure, patterning a first semiconductor layer to form an initial active pattern arranged in an array, the first isolation structure including a first isolation portion and a second isolation portion, the size of the first isolation portion along a second direction being greater than the size of the second isolation portion along the second direction, and adjacent first isolation portions in the second direction being in contact; removing a part of the filling layer and forming an initial word line layer; removing the sacrificial structure to respectively form a bit line groove and a capacitor groove, patterning the initial active pattern into an active structure, and patterning the initial word line layer into a word line structure; forming a bit line structure and a capacitor structure in the bit line groove and the capacitor groove respectively, the bit line structure and the capacitor structure being alternately arranged in a first direction and alternately arranged in a second direction. The method for manufacturing the above semiconductor structure simplifies the manufacturing process difficulty of the word line structure.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] The development of dynamic random access memory (DRAM) pursues performance indicators such as high speed, high integration density, and low power consumption. With the miniaturization of the structure size of semiconductor devices, the technical barriers encountered by existing structures are becoming more and more obvious. Therefore, on the basis of existing structures, developing more novel structures is an effective means to break through the existing technical barriers.

[0003] The emergence of three-dimensional dynamic random access memory (3D DRAM), especially 3D DRAM including multilayer horizontal cells (MHC), which usually includes a plurality of transistors stacked on a substrate, meets the above requirements.

[0004] However, since the transistors are suspended on the substrate, the manufacturing process of the horizontal word lines is difficult, and word line open circuits or short circuits between adjacent word lines are likely to occur, affecting the performance of the semiconductor structure. Summary of the Invention

[0005] According to a first aspect of embodiments of the present disclosure, a method for manufacturing a semiconductor structure is provided, including: forming a stacked structure on a substrate, the stacked structure including a first semiconductor layer and a second semiconductor layer alternately stacked in a vertical direction; forming a first isolation structure, a sacrificial structure, and a filling layer in the stacked structure, and patterning the first semiconductor layer to form an initial active pattern arranged in an array, the first isolation structure being arranged in an array in a first direction and a second direction, the first isolation structure including a first isolation portion located in the layer where the initial active pattern is located and a second isolation portion located in the layer where the second semiconductor layer is located, the size of the first isolation portion in the second direction being greater than the size of the second isolation portion in the second direction and the first isolation portions adjacent in the second direction being in contact with each other, the sacrificial structure being located between the first isolation structures adjacent in the second direction, the filling layer being located in the layer where the second semiconductor layer is located; removing a part of the filling layer and forming an initial word line layer; removing the sacrificial structure and at least a part of the filling layer to form a bit line groove and a capacitor groove respectively, and patterning the initial active pattern into an active structure, and patterning the initial word line layer into a word line structure extending in the first direction; forming a bit line structure and a capacitor structure in the bit line groove and the capacitor groove respectively, the bit line structure and the capacitor structure being alternately arranged in the first direction and alternately arranged in the second direction.

[0006] In some embodiments, forming a first isolation structure, a sacrificial structure, and a filling layer in a stacked structure, and patterning a first semiconductor layer to form an initially active pattern arranged in an array includes: etching the stacked structure to form a plurality of rectangular grooves, the rectangular grooves exposing a partial surface of the substrate, the plurality of rectangular grooves being arranged in an array along a first direction and a second direction, the pitch between adjacent rectangular grooves along the first direction being greater than the pitch between adjacent rectangular grooves along the second direction; removing a portion of the first semiconductor layer along the rectangular grooves to form an initially active pattern arranged in an array and isolation grooves; forming a first isolation structure filling the isolation grooves.

[0007] In some embodiments, after forming the plurality of rectangular grooves, further included are: filling an initial isolation structure in the rectangular grooves; etching the stacked structure to form a plurality of cylindrical grooves, the cylindrical grooves exposing a partial surface of the substrate, the cylindrical grooves being located between adjacent initial isolation structures along the second direction; removing a second semiconductor layer along the cylindrical grooves to form an interlayer gap between the first semiconductor layers; filling a first dielectric layer, a second dielectric layer, and a third dielectric layer in the cylindrical grooves and the interlayer gap to form a sacrificial structure located in the cylindrical grooves and a filling layer located in the interlayer gap; removing a portion of the first semiconductor layer along the rectangular grooves to form an initially active pattern arranged in an array and isolation grooves, including: removing at least a portion of the initial isolation structure to expose the rectangular grooves; removing the exposed portion of the first semiconductor layer along the rectangular grooves to form isolation grooves, the isolation grooves including a first isolation groove portion located in the layer where the first semiconductor layer is located, the first isolation groove portions being connected in the second direction and disconnecting the initially active pattern in the first direction.

[0008] In some embodiments, the first dielectric layer covers the surface of the initially active pattern, the second dielectric layer covers the surface of the second dielectric layer and fills the interlayer gap, removing a portion of the filling layer, and forming an initial word line layer includes: removing a portion of the first dielectric layer to form an initial word line groove; forming an initial word line layer in the initial word line groove.

[0009] In some embodiments, the initial word line layer includes a gate oxide material layer and a conductive material layer; forming the initial word line layer in the initial word line groove includes: forming a gate oxide material layer covering the surface of the initially active pattern in the initial word line groove; forming a conductive material layer covering the surface of the gate oxide material layer and filling the initial word line groove.

[0010] In some embodiments, the sacrificial structure includes a first sacrificial structure and a second sacrificial structure, and the first sacrificial structure and the second sacrificial structure are alternately arranged in a first direction and alternately arranged in a second direction; the sacrificial structure and at least a part of the filling layer are removed to form a bit line groove and a capacitor groove respectively, and the initial active pattern is patterned into an active structure, and the initial word line layer is patterned into a word line structure extending in the first direction, including: removing the first sacrificial structure to expose the capacitor vertical groove, and removing a part of the initial active pattern along the capacitor vertical groove to form a capacitor horizontal groove, and the capacitor vertical groove and the capacitor horizontal groove form a capacitor groove; filling a third sacrificial structure in the capacitor groove; removing the second sacrificial structure to expose the bit line vertical groove, and removing a part of the initial active pattern along the bit line vertical groove to form a bit line horizontal groove, and the bit line vertical groove and the bit line horizontal groove form a bit line groove, and the remaining initial active pattern serves as the active structure.

[0011] In some embodiments, after removing the second sacrificial structure to expose the bit line vertical groove and before removing a part of the initial active pattern along the capacitor vertical groove, it further includes: removing a part of the initial word line layer along the bit line vertical groove, and the remaining initial word line layer serves as the word line structure; forming a second isolation structure, and the second isolation structure is sandwiched between the word line structure and the bit line vertical groove.

[0012] According to a second aspect of the embodiments of the present disclosure, a semiconductor structure is provided, including: a stacked structure located on a substrate, the stacked structure includes a plurality of storage layers stacked in a vertical direction, and each storage layer includes a plurality of active structures arranged in an array in a first direction and a second direction and a word line structure extending in the first direction; bit line structures and capacitor structures located on both sides of each active structure in the second direction, and the bit line structures and the capacitor structures are alternately arranged in the first direction and alternately arranged in the second direction; a first isolation structure penetrating the stacked structure, and the first isolation structure is arranged in an array in the first direction and the second direction, and the first isolation structure includes a first isolation portion located in the layer where the active structure is located and a second isolation portion located in the layer where the word line structure is located, and the size of the first isolation portion in the second direction is greater than the size of the second isolation portion in the second direction and the first isolation portions adjacent in the second direction are in contact, and the bit line structures and the capacitor structures are located between the first isolation structures adjacent in the second direction.

[0013] In some embodiments, the bit line structure includes a bit line vertical portion and a bit line horizontal portion, the bit line vertical portion penetrates the stacked structure in the vertical direction, the bit line horizontal portions are located on both sides of the bit line vertical portion in the second direction and are spaced apart in the vertical direction, and the bit line horizontal portions are in contact with the active structures.

[0014] In some embodiments, the capacitive structure includes a vertical capacitive portion and a horizontal capacitive portion. The vertical capacitive portion penetrates the stacked structure in the vertical direction. The horizontal capacitive portions are located on both sides of the vertical capacitive portion in the second direction and are arranged at intervals in the vertical direction. The horizontal capacitive portion includes a first electrode portion, a capacitive dielectric layer, and a second electrode portion. The capacitive dielectric layer is sandwiched between the first electrode portion and the second electrode portion. The first electrode portion is in contact with the active structure, and the second electrode portion is in contact with the vertical capacitive portion.

[0015] In some embodiments, the word line structure includes a first word line portion and a second word line portion that are alternately connected in the first direction. The first word line portion at least covers the active structure. The second word line portion is located between adjacent first isolation structures in the second direction. The dimension of the first word line portion in the second direction is greater than the dimension of the second word line portion in the second direction.

[0016] In some embodiments, it further includes: a second isolation structure sandwiched between the first word line portion and the bit line structure; a third isolation structure sandwiched between the first word line portion and the capacitive structure.

[0017] In some embodiments, the first word line portion has arc-shaped sidewalls that face each other in the second direction.

[0018] In some embodiments, the dimension of the active structure in the first direction is non-uniform, and the active structure has a protrusion facing the contact surface between adjacent first isolation structures.

[0019] In the embodiments of the present disclosure, forming the isolation structure and the sacrificial structure in the stacked structure can pre-define and divide the regions for setting each device structure, improve the integration degree between each device structure and effectively improve the isolation effect between the device structures. And by forming a filling layer for occupying positions and then removing the filling layer to form the initial word line layer, the manufacturing process difficulty of the horizontal word line is simplified, and it can ensure that the initial word line layers are arranged at intervals in the vertical direction, avoiding the occurrence of short circuit or open circuit in the word line structure. Description of the Drawings

[0020] Figure 1 is a three-dimensional schematic diagram of a semiconductor structure shown according to an exemplary embodiment;

[0021] Figure 2 is a flowchart of a preparation method of a semiconductor structure shown according to an exemplary embodiment;

[0022] Figure 3A and Figures 3B to 19A and Figure 19B are semiconductor structure schematic diagrams of a preparation process of a semiconductor structure shown according to the embodiments of the present disclosure, wherein, Figure 3A 、 Figure 4A 、 Figure 5A 、Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A and Figure 19A are schematic vertical cross-sectional views of the semiconductor structure during the manufacturing process, Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B and Figure 19B are schematic horizontal cross-sectional views of the semiconductor structure during the manufacturing process. Detailed implementation manners

[0023] The technical solutions of the present disclosure will be further elaborated in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation manners described herein. On the contrary, these implementation manners are provided to enable a more thorough understanding of the present disclosure and to be able to fully convey the scope of the present disclosure to those skilled in the art.

[0024] The present disclosure will be described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the present disclosure will be clearer according to the following description and the claims. It should be noted that the drawings are all in a very simplified form and use non-precise scales, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.

[0025] It can be understood that the meanings of "on...", "above...", and "over..." in the present disclosure should be interpreted in the broadest manner, so that "on..." not only means "on" something without any intervening features or layers therebetween (i.e., directly on something), but also includes the meaning of having intervening features or layers on something.

[0026] In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects and do not necessarily describe a specific order or sequence.

[0027] In the embodiments of the present disclosure, the term "layer" refers to a portion of a material that includes a region having a thickness. The layer may extend over the entirety of a structure below or above, or may have a scope that is less than the scope of the structure below or above. Additionally, the layer may be a region of a homogeneous or inhomogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure, or the layer may be between any horizontal planes at the top and bottom surfaces of the continuous structure. The layer may extend horizontally, vertically, and / or along an inclined surface. The layer may include a plurality of sub-layers.

[0028] It should be noted that the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0029] Figure 1 is a three-dimensional schematic diagram of a semiconductor structure 10 shown according to an embodiment of the present disclosure; Figure 2 is a flowchart of a method for manufacturing a semiconductor structure shown according to an embodiment of the present disclosure; Figure 3A and Figures 3B to 19A and Figure 19B is a schematic diagram of a manufacturing process of a semiconductor structure shown according to an embodiment of the present disclosure, where Figures 3A to 19A is a schematic diagram of a vertical cross-section of the semiconductor structure during the manufacturing process, Figures 3B to 19B is a schematic diagram of a horizontal cross-section of the semiconductor structure during the manufacturing process. Figure 1 and Figures 3A to 19B In, the first direction D1 and the second direction D2 are horizontal directions parallel to the plane of the substrate 100, and the first direction D1 intersects the second direction D2. For example, the first direction D1 may be perpendicular to the second direction D2, and the vertical direction D3 is a direction intersecting the plane of the substrate 100. For example, the vertical direction D3 is perpendicular to the plane of the substrate 100.

[0030] Next, a method for manufacturing a semiconductor structure provided in the embodiments of the present disclosure will be described in detail with reference to Figure 2 As shown, the manufacturing method at least includes the following steps:

[0031] S210: Form a stacked structure on the substrate, the stacked structure including a first semiconductor layer and a second semiconductor layer alternately stacked in the vertical direction;

[0032] S220: Form a first isolation structure, a sacrificial structure, and a filling layer in the stacked structure, and pattern the first semiconductor layer to form an array of initial active patterns;

[0033] S230: Remove part of the filling layer and form an initial word line layer;

[0034] S240: Remove the sacrificial structure and at least part of the filling layer to form a bit line groove and a capacitor groove respectively, pattern the initial active pattern into an active structure, and pattern the initial word line layer into a word line structure extending in the first direction;

[0035] S250: Form a bit line structure and a capacitor structure in the bit line groove and the capacitor groove respectively. The bit line structure and the capacitor structure are alternately arranged in the first direction and alternately arranged in the second direction.

[0036] It should be understood that Figure 2 the steps shown in Figure 2 are not exclusive, and other steps may be performed before, after, or between any of the steps shown;

[0037] In the method for manufacturing a semiconductor structure provided by the present disclosure, on the one hand, by forming an isolation structure and a sacrificial structure in a stacked structure before forming each device structure (such as a transistor, a bit line, and a capacitor), the regions where each device structure is to be arranged can be defined and divided in advance, the integration degree between each device structure can be improved, and the isolation effect between device structures can be effectively improved. On the other hand, a filling layer is formed for occupying positions, and then the filling layer is removed to form an initial word line layer, which simplifies the manufacturing process difficulty of the horizontal word line, can ensure that the initial word line layers are arranged at intervals in the vertical direction, and avoid the occurrence of short circuits in the vertical direction of the word line structure. On the third hand, after forming the initial active pattern and the initial word line layer, the initial active pattern is patterned into an active structure by using the bit line groove and the capacitor groove, and the initial word line layer is patterned into a horizontally extending word line structure by using the bit line groove and the capacitor groove, which can accurately control the morphology of the active structure and the word line structure, avoid the occurrence of open circuits or short circuits in the horizontal direction of the word line structure, and is beneficial to improving the performance of the semiconductor structure.

[0038] In some embodiments, referring to Figure 3A and Figure 3B shown, wherein, Figure 3A a schematic vertical cross-sectional view, Figure 3B the left figure in Figure 3A is a schematic horizontal cross-sectional view of the first horizontal section H1-H1' in Figure 3B the right figure in Figure 3ASchematic diagram of the horizontal section of the second horizontal section H2-H2'. After providing the substrate 100, a stacked structure SG is formed on the substrate 100. The stacked structure SG includes a first semiconductor layer 101 and a second semiconductor layer 102 alternately stacked in the vertical direction D3. The first horizontal section H1-H1' is the section of the layer where the first semiconductor layer 101 is located, and the second horizontal section H2-H2' is the section of the layer where the second semiconductor layer 102 is located. In the figure, the first semiconductor layer 101 is taken as an example of the top layer of the stacked structure SG. In fact, the top layer of the stacked structure SG can also be the second semiconductor layer 102.

[0039] The material of the substrate 100 includes semiconductor materials, such as elemental semiconductor materials (e.g., silicon (Si) or germanium (Ge), etc.), III-V compound semiconductor materials (e.g., gallium nitride (GaN), gallium arsenide (GaAs) or indium phosphide (InP), etc.), II-VI compound semiconductor materials (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS) or cadmium telluride (CdTe), etc.), organic semiconductor materials or other semiconductor materials known in the art.

[0040] The materials of the first semiconductor layer 101 and the second semiconductor layer 102 are different. The materials of the first semiconductor layer 101 and the second semiconductor layer 102 can be single-crystalline silicon, polycrystalline silicon, germanium, silicon germanide or oxide semiconductor materials (e.g., zinc tin oxide (Zn x Sn y O, commonly known as "ZTO"), indium zinc oxide (In x Zn y O, commonly known as "IZO"), zinc oxide (Zn x O), indium gallium zinc oxide (In x Ga y Zn z O, commonly known as "IGZO"), indium gallium silicon oxide (In x Ga y Si z O, commonly known as "IGSO") and one or more of other similar materials). For example, the first semiconductor layer 101 is single-crystalline silicon and the second semiconductor layer 102 is silicon germanide. The first semiconductor layer 101 and the second semiconductor layer 102 can be formed alternately in sequence by an epitaxial growth process or a deposition process. The deposition process can include chemical vapor deposition, atomic layer deposition process, plasma-enhanced physical vapor deposition, plasma-enhanced chemical vapor deposition or low-pressure chemical vapor deposition, etc. The thickness of the first semiconductor layer 101 in the vertical direction is greater than the thickness of the second semiconductor layer 102 in the vertical direction, which is beneficial to improving the material quality of the first semiconductor layer 101.

[0041] In some embodiments, referring to Figure 4A and Figure 4BAs shown, where Figure 4A The left figure in Figure 4B is a schematic vertical section view of the first vertical section V1-V1' in Figure 4A The right figure in Figure 4B is a schematic vertical section view of the second vertical section V2-V2' in Figure 4B The left figure in Figure 4A is a schematic horizontal section view of the first horizontal section H1-H1' in Figure 4B The right figure in Figure 4A is a schematic horizontal section view of the second horizontal section H2-H2' in. The stacked structure SG is etched to form a plurality of rectangular grooves T1. The rectangular grooves T1 expose a partial surface of the substrate 100. The plurality of rectangular grooves T1 are arranged in an array along a first direction D1 and a second direction D2. The spacing between adjacent rectangular grooves T1 along the first direction D1 is greater than the spacing between adjacent rectangular grooves T1 along the second direction D2. The bottom surface of the rectangular groove T1 can be lower than or flush with the top surface of the substrate 100. The shape of the projection of each rectangular groove T1 along the vertical direction D3 is rectangular or rounded rectangular, and the length of each rectangular groove T1 along the second direction D2 is greater than the width of the rectangular groove T1 along the first direction D1. The plurality of rectangular grooves T1 arranged at intervals along the first direction D1 can be defined as a column of rectangular grooves T1, and the plurality of rectangular grooves T1 arranged at intervals along the second direction D2 can be defined as a row of rectangular grooves T1. The two ends of each column of rectangular grooves T1 arranged along the first direction D1 in the second direction D2 are aligned in the second direction D2, that is, the projections of the plurality of rectangular grooves T1 in each column of rectangular grooves T1 along the first direction D1 basically coincide. The two ends of each row of rectangular grooves T1 arranged along the second direction D2 in the first direction D1 are aligned in the first direction D1, that is, the projections of the plurality of rectangular grooves T1 in each row of rectangular grooves T1 along the second direction D2 basically coincide. The first vertical section V1-V1' spans the space between the plurality of rectangular grooves T1 along the second direction D2, and the second vertical section V2-V2' spans the plurality of rectangular grooves T1 along the second direction D2.

[0042] In some embodiments, after a mask layer is formed on the top surface of the stacked structure SG, the mask layer and the stacked structure SG can be patterned. The mask layer can be used to protect the top surface of the stacked structure SG and prevent damage to the first semiconductor layer 101 or the second semiconductor layer 102 located at the top layer in the stacked structure SG during the etching process.

[0043] In some embodiments, referring to Figure 5A and Figure 5B as shown, where Figure 5A The left figure in Figure 5B is a schematic vertical section view of the first vertical section V1-V1' in Figure 5A The right figure in Figure 5B is a schematic vertical section view of the second vertical section V2-V2' inFigure 5B The left figure in the middle is Figure 5A a schematic diagram of a horizontal section of the first horizontal section H1-H1' in the middle, Figure 5B The right figure in the middle is Figure 5A a schematic diagram of a horizontal section of the second horizontal section H2-H2' in the middle. Fill the rectangular groove T1 with the initial isolation structure 110, and perform a planarization process on the initial isolation structure 110. For example, the top surface of the initial isolation structure 110 can be flush with the top surface of the mask layer on the stack structure SG. The initial isolation structure 110 can be a single-layer structure or a multi-layer structure. For example, the initial isolation structure 110 can include a first initial isolation layer 111 that conformally covers the inner wall of the rectangular groove T1 and a second initial isolation layer 112 that fills the inside of the rectangular groove T1. The material of the initial isolation structure 110 includes a dielectric material. For example, silicon oxide, silicon nitride, or silicon oxynitride, etc. The material of the initial isolation structure 110 can also include a sacrificial material, such as aluminum oxide, amorphous carbon, polysilicon, etc. In this example, the first initial isolation layer 111 is silicon nitride, and the second initial isolation layer 112 is polysilicon.

[0044] In some embodiments, referring to Figure 6A and Figure 6B as shown, where Figure 6A The left figure in the middle is Figure 6B a schematic diagram of a vertical section of the first vertical section V1-V1' in the middle, Figure 6A The right figure in the middle is Figure 6B a schematic diagram of a vertical section of the second vertical section V2-V2' in the middle, Figure 6B The left figure in the middle is Figure 6A a schematic diagram of a horizontal section of the first horizontal section H1-H1' in the middle, Figure 6B The right figure in the middle is Figure 6A a schematic diagram of a horizontal section of the second horizontal section H2-H2' in the middle. Etch the stack structure SG to form a plurality of columnar grooves T2. The columnar grooves T2 expose a part of the surface of the substrate 100, and the columnar grooves T2 are located between the initial isolation structures 110 adjacent along the second direction D2. The bottom surface of the columnar groove T2 can be lower than or flush with the top surface of the substrate 100. The shape of the projection of each columnar groove T2 along the vertical direction D3 is circular or elliptical. One columnar groove T2 is formed between every two initial isolation structures 110 adjacent along the second direction D2, and the plurality of columnar grooves T2 are arranged in an array along the first direction D1 and the second direction D2. The two ends of the columnar groove T2 along the first direction D1 are in contact with the initial isolation structure 110.

[0045] In some embodiments, referring to Figure 7A and Figure 7B as shown, where Figure 7A The left figure in the middle is Figure 7B a schematic diagram of a vertical section of the first vertical section V1-V1' in the middle, Figure 7A The right figure in the middle is Figure 7BSchematic diagram of the vertical section of the second vertical section V2-V2' Figure 7B The left figure in Figure 7A Schematic diagram of the horizontal section of the first horizontal section H1-H1' Figure 7B The right figure in Figure 7A Schematic diagram of the horizontal section of the second horizontal section H2-H2'. The second semiconductor layer 102 is removed along the cylindrical groove T2 to form an interlayer gap G1 between the first semiconductor layers 101, and the remaining first semiconductor layers 101 are supported by the initial isolation structure 110. The second semiconductor layer 102 is laterally etched by a wet etching process.

[0046] In some embodiments, referring to Figure 8A and Figure 8B as shown, wherein Figure 8A The left figure in Figure 8B Schematic diagram of the vertical section of the first vertical section V1-V1' Figure 8A The right figure in Figure 8B Schematic diagram of the vertical section of the second vertical section V2-V2' Figure 8B The left figure in Figure 8A Schematic diagram of the horizontal section of the first horizontal section H1-H1' Figure 8B The right figure in Figure 8A Schematic diagram of the horizontal section of the second horizontal section H2-H2'. Through the interlayer gap G1, the remaining first semiconductor layers 101 are thinned to increase the spatial height of the interlayer gap G1 in the vertical direction D3. The thickness of the thinned first semiconductor layers 101 in the vertical direction D3 can be less than the spatial height of the increased interlayer gap G1 in the vertical direction D3, and the thinned first semiconductor layers 101 are used to form device structures, for example, for forming the source, drain, and channel layers of a transistor. By first forming a second semiconductor layer 102 with a smaller thickness and a first semiconductor layer 101 with a larger thickness, and then thinning the first semiconductor layer 101, the quality of the first semiconductor layer 101 can be effectively improved, thereby improving the electrical performance of the subsequent formed device structures.

[0047] In some embodiments, referring to Figure 9A and Figure 9B as shown, wherein Figure 9A The left figure in Figure 9B Schematic diagram of the vertical section of the first vertical section V1-V1' Figure 9A The right figure in Figure 9B Schematic diagram of the vertical section of the second vertical section V2-V2' Figure 9B The left figure in Figure 9A Schematic diagram of the horizontal section of the first horizontal section H1-H1' Figure 9B The right figure in Figure 9ASchematic diagram of the horizontal section of the second horizontal section H2-H2' in [the figure]. The first dielectric layer 121, the second dielectric layer 122, and the third dielectric layer 123 are sequentially formed in the cylindrical groove T2 and the interlayer gap G1 to form a sacrificial structure 120a located in the cylindrical groove T2 and a filling layer 120b located in the interlayer gap G1. Among them, the first dielectric layer 121 covers the exposed surface of the first semiconductor layer 101, and the first dielectric layer 121 also covers the exposed surface of the substrate 100. The second dielectric layer 122 covers the surface of the first dielectric layer 121 and fills the interlayer gap G1 completely. The second dielectric layer 122 also partially locates on the sidewall of the cylindrical groove T2. The third dielectric layer 123 covers the second dielectric layer 122 and fills the cylindrical groove T2 completely. The sacrificial structure 120a includes the third dielectric layer 123 and a part of the second dielectric layer 122, and the filling layer 120b includes the first dielectric layer 121 and a part of the second dielectric layer 122. The materials of the first dielectric layer 121, the second dielectric layer 122, and the third dielectric layer 123 include dielectric materials, such as silicon oxide, silicon nitride, or silicon oxynitride, etc., or sacrificial materials, such as aluminum oxide, amorphous carbon, polysilicon, etc. In one example, the material of the first dielectric layer 121 is silicon nitride, the material of the second dielectric layer 122 is silicon oxide, and the material of the third dielectric layer 123 is polysilicon.

[0048] In some embodiments, the sacrificial structure 120a includes a first sacrificial structure 120a1 and a second sacrificial structure 120a2. The first sacrificial structure 120a1 and the second sacrificial structure 120a2 are alternately arranged in the first direction D1 and alternately arranged in the second direction D2. A part of the sacrificial structure 120a is used as the first sacrificial structure 120a1 for forming a capacitor structure subsequently, and another part of the sacrificial structure 120a is used as the second sacrificial structure 120a2 for forming a bit line structure subsequently.

[0049] In some embodiments, referring to Figure 10A and Figure 10B as shown, where Figure 10A the left figure in [the figure] is Figure 10B the schematic diagram of the vertical section of the first vertical section V1-V1' in [the figure], Figure 10A the right figure in [the figure] is Figure 10B the schematic diagram of the vertical section of the second vertical section V2-V2' in [the figure], Figure 10B the left figure in [the figure] is Figure 10A the schematic diagram of the horizontal section of the first horizontal section H1-H1' in [the figure], Figure 10B the right figure in [the figure] is Figure 10ASchematic diagram of the horizontal section of the third horizontal section H3-H3' in [text]. At least part of the initial isolation structure 110 is removed to expose the rectangular groove T1. For example, dry etching can be used to remove the initial isolation structure 110 with the mask layer as the mask. The exposed part of the sacrificial structure 120a is on the sidewall of the rectangular groove T1. The size of the remaining part of the first semiconductor layer 101 located between adjacent column rectangular grooves T1 is smaller than the size of the remaining part of the first semiconductor layer 101 located between adjacent row rectangular grooves T1.

[0050] In some embodiments, referring to Figure 11A and Figure 11B as shown, wherein, Figure 11A The left figure in [text] is Figure 11B Schematic diagram of the vertical section of the first vertical section V1-V1' in [text], Figure 11A The right figure in [text] is Figure 11B Schematic diagram of the vertical section of the second vertical section V2-V2' in [text], Figure 11B The left figure in [text] is Figure 11A Schematic diagram of the horizontal section of the first horizontal section H1-H1' in [text], Figure 11B The right figure in [text] is Figure 11A Schematic diagram of the horizontal section of the third horizontal section H3-H3' in [text]. Part of the first semiconductor layer 101 is removed along the rectangular groove T1 to form an array of initial active patterns 201 and isolation grooves T3, and a first isolation structure 130 is formed to fill the isolation grooves T3. Among them, removing part of the first semiconductor layer 101 along the rectangular groove T1 to form an array of initial active patterns 201 and isolation grooves T3 includes: referring to Figure 10A and Figure 10B as shown, after removing at least part of the initial isolation structure 110 to expose the rectangular groove T1, the exposed part of the first semiconductor layer 101 along the rectangular groove T1 is removed to form the isolation groove T3. The isolation groove T3 includes a first isolation groove part T3a located in the layer where the original first semiconductor layer 101 is located. The first isolation groove parts T3a of each row of isolation grooves T3 are connected in the second direction D2 and disconnect the initial active patterns 201 in the first direction D1. The isolation groove T3 also includes a second isolation groove part T3b located in the layer of the first dielectric layer 121 on the surface of the first semiconductor layer 101. The size of the first isolation groove part T3a along the second direction D2 is larger than the size of the second isolation groove part T3b along the second direction D2, and the size of the first isolation groove part T3a along the first direction D1 is larger than the size of the second isolation groove part T3b along the first direction D1.

[0051] The initial active patterns 201 arranged in an array are arranged in a four-sided pattern along the first direction D1 and the second direction D2. A plurality of initial active patterns 201 arranged at intervals along the second direction D2 can be defined as a row of initial active patterns 201, and a plurality of initial active patterns 201 arranged at intervals along the first direction D1 can be defined as a column of initial active patterns 201. The two ends of each column of initial active patterns 201 arranged along the first direction D1 are aligned in the second direction D2, that is, the projections of the plurality of initial active patterns 201 in each column of initial active patterns 201 along the first direction D1 basically coincide. The two ends of each row of initial active patterns 201 arranged along the second direction D2 are aligned in the first direction D1, that is, the projections of the plurality of initial active patterns 201 in each row of initial active patterns 201 along the second direction D2 basically coincide.

[0052] In some embodiments, the exposed portion of the first semiconductor layer 101 can be etched transversely along the rectangular groove T1 through a wet etching process. Since the size of the portion of the first semiconductor layer 101 located between adjacent column rectangular grooves T1 is smaller than the size of the portion of the first semiconductor layer 101 located between adjacent row rectangular grooves T1, the portion of the first semiconductor layer 101 located between adjacent column rectangular grooves T1 is basically removed, that is, the portion of the first semiconductor layer 101 located between adjacent rectangular grooves T1 in the second direction D2 is basically removed, while the portion of the first semiconductor layer 101 located between adjacent row rectangular grooves T1 remains. The first semiconductor layer 101 remaining after the wet etching process is used as the initial active pattern 201. Thus, the initial active pattern 201 is disconnected in the first direction D1, that is, the first semiconductor layer 101 is separated into a plurality of initial active patterns 201 arranged at intervals in the first direction D1. The finally formed initial active pattern 201 has a convex portion facing the contact surface between adjacent first isolation structures 130 in the second direction D2. The size of the initial active pattern 201 in the first direction D1 is uneven, and along the second direction D2, the size of the middle of the initial active pattern 201 is larger than the size of both ends of the initial active pattern 201.

[0053] In some embodiments, when removing the exposed portion of the first semiconductor layer 101, it further includes removing a part of the first dielectric layer 121 located in the columnar groove T2 and exposed by the rectangular groove T1, so as to expose a part of the second dielectric layer 122 in the sacrificial structure 120a.

[0054] In some embodiments, the first isolation structure 130 is arranged in an array along a first direction D1 and a second direction D2. The first isolation structure 130 includes a first isolation portion 130a located in the layer where the initial active pattern 201 is located and a second isolation portion 130b located in the layer where the second semiconductor layer 102 is located. The dimension of the first isolation portion 130a along the second direction D2 is greater than the dimension of the second isolation portion 130b along the second direction D2, and the adjacent first isolation portions 130a in the second direction D2 are in contact with each other.

[0055] In some embodiments, the first isolation structure 130 can be a single-layer structure or a multi-layer structure. For example, the first isolation structure 130 can include a first isolation layer 131 that conformally covers the inner wall of the rectangular groove T1, a second isolation layer 132, and a third isolation layer 133 that fills the inside of the rectangular groove T1. In this example, the first isolation structure 130 is an ONO (Oxide-Nitride-Oxide) structure, the first isolation layer 131 is silicon oxide, the second isolation layer 132 is silicon nitride, and the third isolation layer 133 is silicon oxide. The first isolation layer 131 can fill the portion between adjacent rectangular grooves T1 in the second direction D2.

[0056] In some embodiments, referring to Figure 12A and Figure 12B as shown, wherein, Figure 12A the left figure in Figure 12B is a schematic vertical cross-sectional view of the first vertical cross-section V1-V1' in Figure 12A and the right figure in Figure 12B is a schematic vertical cross-sectional view of the second vertical cross-section V2-V2' in Figure 12B the left figure in Figure 12A is a schematic horizontal cross-sectional view of the first horizontal cross-section H1-H1' in Figure 12B and the right figure in Figure 12A is a schematic horizontal cross-sectional view of the third horizontal cross-section H3-H3' in

[0057] In some embodiments, referring to Figure 13A and Figure 13B as shown, wherein,Figure 13A The left figure in the middle is Figure 13B a schematic vertical cross-sectional view of the first vertical cross-section V1-V1' in the middle, Figure 13A The right figure in the middle is Figure 13B a schematic vertical cross-sectional view of the second vertical cross-section V2-V2' in the middle, Figure 13B The left figure in the middle is Figure 13A a schematic horizontal cross-sectional view of the first horizontal cross-section H1-H1' in the middle, Figure 13B The right figure in the middle is Figure 13A a schematic horizontal cross-sectional view of the third horizontal cross-section H3-H3' in the middle. Along the capacitor vertical groove T21, part of the first dielectric layer 121 is etched transversely using a wet etching process, and the sidewalls of the initial active pattern 201 are exposed. Along the capacitor vertical groove T21, part of the initial active pattern 201 is further removed to form a capacitor horizontal groove T22. The capacitor vertical groove T21 and the capacitor horizontal groove T22 form a capacitor groove CAt. The size of the space formed by the part of the first dielectric layer 121 removed transversely in the second direction D2 is greater than the size of the space formed by the part of the initial active pattern 201 removed transversely in the second direction D2, that is, the etched initial active pattern 201 protrudes in the second direction D2 from the etched first dielectric layer 121. During the process of removing part of the initial active pattern 201, the third dielectric layer 123 remaining at the bottom of the cylindrical groove T2 can be removed, and the first dielectric layer 121 and the second dielectric layer 122 at the bottom of the cylindrical groove T2 can protect the substrate 100 from etching damage and prevent leakage problems in the subsequent formed device structure.

[0058] In some embodiments, referring to Figure 14A and Figure 14B as shown, wherein, Figure 14A The left figure in the middle is Figure 14B a schematic vertical cross-sectional view of the first vertical cross-section V1-V1' in the middle, Figure 14A The right figure in the middle is Figure 14B a schematic vertical cross-sectional view of the second vertical cross-section V2-V2' in the middle, Figure 14B The left figure in the middle is Figure 14A a schematic horizontal cross-sectional view of the first horizontal cross-section H1-H1' in the middle, Figure 14B The right figure in the middle is Figure 14ASchematic diagram of the horizontal section of the third horizontal section H3-H3' in [description]. The third sacrificial structure 140 is filled in the capacitor trench CAt. The third sacrificial structure 140 can be a single-layer structure or a multi-layer structure. For example, the third sacrificial structure 140 can include a first sacrificial layer 141 filling the capacitor horizontal trench T22 and a second sacrificial layer 142 filling the capacitor vertical trench T21. The material of the first sacrificial layer 141 can include dielectric materials, such as silicon oxide, silicon nitride, or silicon oxynitride, etc. The material of the second sacrificial layer 142 can include sacrificial materials, such as alumina, amorphous carbon, polysilicon, etc. In one example, the first sacrificial layer 141 includes a silicon oxide layer and a silicon nitride layer, and the second sacrificial layer 142 includes polysilicon.

[0059] In some embodiments, referring to Figure 15A and Figure 15B as shown, wherein, Figure 15A the left figure in [description] is Figure 15B the schematic diagram of the vertical section of the first vertical section V1-V1' in [description], Figure 15A the right figure in [description] is Figure 15B the schematic diagram of the vertical section of the second vertical section V2-V2' in [description], Figure 15B the left figure in [description] is Figure 15A the schematic diagram of the horizontal section of the first horizontal section H1-H1' in [description], Figure 15B the right figure in [description] is Figure 15A the schematic diagram of the horizontal section of the third horizontal section H3-H3' in [description]. The second sacrificial structure 120a2 is removed to expose the bit line vertical trench T23. A part of the filling layer 120b is removed, and an initial word line layer is formed, including: removing the remaining first dielectric layer 121 along the bit line vertical trench T23 to form an initial word line groove G0.

[0060] In some embodiments, referring to Figure 16A and Figure 16B as shown, wherein, Figure 16A the left figure in [description] is Figure 16B the schematic diagram of the vertical section of the first vertical section V1-V1' in [description], Figure 16A the right figure in [description] is Figure 16B the schematic diagram of the vertical section of the second vertical section V2-V2' in [description], Figure 16B the left figure in [description] is Figure 16A the schematic diagram of the horizontal section of the first horizontal section H1-H1' in [description], Figure 16B the right figure in [description] is Figure 16ASchematic diagram of the horizontal section of the third horizontal section H3-H3' in []. An initial word line layer 202 is formed in the initial word line groove G0. The initial word line layer 202 includes a gate oxide material layer 202a and a conductive material layer 202b; forming the initial word line layer 202 in the initial word line groove G0 includes: forming a gate oxide material layer 202a covering the surface of the initial active pattern 201 in the initial word line groove G0; forming a conductive material layer 202b covering the surface of the gate oxide material layer 202a and filling the initial word line groove G0.

[0061] An in-situ steam generation (ISSG) process or a rapid thermal oxidation (RTO) process can be used to form the gate oxide material layer 202a on the surface of the initial active pattern 201. The gate oxide material layer 202a can only cover the surface of the initial active pattern 201. An atomic layer deposition process or a plasma vapor deposition process can also be used to form the gate oxide material layer 202a. The gate oxide material layer 202a can also cover the surface of the second dielectric layer 122.

[0062] In some embodiments, the conductive material layer 202b is formed by a deposition process, such as depositing a conductive material along the bit line vertical groove T23, filling the initial word line groove G0 and the bit line vertical groove T23 with the conductive material, and then removing the conductive material located in the bit line vertical groove T23 by a dry etching process. The material of the conductive material layer 202b is a conductive material. The conductive material can include one or more of the following: metals (such as tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), cobalt (Co), nickel (Ni)); alloys (such as Co-based alloys, Ti-based alloys, Co and Ni-based alloys, Fe and Co-based alloys); conductive metal-containing materials (such as conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides); and conductive doped semiconductor materials (such as conductive doped polysilicon, conductive doped germanosilicon). For example, the material of the conductive material layer 202b can be titanium nitride.

[0063] In some embodiments, referring to Figure 17A and Figure 17B shown, where Figure 17A the left figure in [] is Figure 17B the schematic diagram of the vertical section of the first vertical section V1-V1' in [], Figure 17A the right figure in [] is Figure 17B the schematic diagram of the vertical section of the second vertical section V2-V2' in [], Figure 17B the left figure in [] is Figure 17A the schematic diagram of the horizontal section of the first horizontal section H1-H1' in [],Figure 17B The right middle figure is Figure 17A A schematic diagram of a horizontal section of the third horizontal section H3-H3' in the middle. Along the bit line vertical groove T23, a part of the initial word line layer 202 is removed, so that the initial word line layer 202 is patterned into a word line structure 220 extending along the first direction D1. Part of the conductive material layer 202b can be removed only, or part of the gate oxide material layer 202a and part of the conductive material layer 202b can be removed. After removing part of the initial word line layer 202, it further includes filling the space where the initial word line layer 202 is removed to form a second isolation structure 203. The material of the second isolation structure 203 can be a low dielectric constant material, such as: silicon oxide, silicon nitride, silicon carbide, silicon carbonitride or silicon oxynitride. After forming the second isolation structure 203, the initial active pattern 201 is patterned into an active structure 210, including: removing part of the initial active pattern 201 along the bit line vertical groove T23 to form a bit line horizontal groove T24, and the bit line vertical groove T23 and the bit line horizontal groove T24 form a bit line groove BLt, and the remaining initial active pattern 201 serves as the active structure 210. The etched conductive layer in the word line structure 220 is indented at both ends in the second direction with respect to the two ends of the active structure 210. The etched gate oxide layer in the word line structure 220 can be indented at both ends in the second direction with respect to the two ends of the active structure 210, or one end of the gate oxide layer can be indented at one end of the active structure 210 while the other end of the gate oxide layer is flush with the other end of the active structure 210. The word line structure 220 and the active structure 210 are used to form a transistor structure.

[0064] In some embodiments, the patterned word line structure 220 includes a first word line portion 221 and a second word line portion 222 that are alternately connected along the first direction D1. The first word line portion 221 at least covers the active structure 210, and the second word line portion 222 is located between the second isolation portions 130b of the first isolation structure 130 adjacent in the second direction D2. The dimension of the first word line portion 221 in the second direction D2 is greater than the dimension of the second word line portion 222 in the second direction D2. By setting the first word line portion 221 with a larger dimension, the channel length can be increased, the short channel effect of the transistor can be reduced, and by setting the second word line portion 222 with a smaller dimension, the coupling between adjacent word line structures 220 can be reduced.

[0065] In some embodiments, referring to Figure 18A and Figure 18B shown, wherein Figure 18A The left middle figure is Figure 18B A schematic diagram of a vertical section of the first vertical section V1-V1' in the middle, Figure 18A The right middle figure is Figure 18B A schematic diagram of a vertical section of the second vertical section V2-V2' in the middle, Figure 18B The left middle figure is Figure 18A A schematic diagram of a horizontal section of the first horizontal section H1-H1' in the middle,Figure 18B The right middle figure is Figure 18A a schematic cross-sectional view of the third horizontal section H3-H3' in the middle. A bit line structure 300 is formed in the bit line slot BLt. The bit line structure 300 includes a bit line vertical portion 310 and a bit line horizontal portion 320. The bit line vertical portion 310 refers to the part of the bit line structure 300 located in the bit line vertical slot T23, and the bit line horizontal portion 320 refers to the part of the bit line structure 300 located in the bit line horizontal slot T24. Among them, the bit line horizontal portion 320 protrudes from both sides of the bit line vertical portion 310 along the second direction D2. A plurality of bit line horizontal portions 320 are arranged on the same layer as the active structure 210 and are spaced apart in the vertical direction D3. The bit line horizontal portion 320 is in contact connection with the active structure 210. The material of the bit line structure 300 is a conductive material, and the bit line structure 300 can be a single-layer structure or a multi-layer structure. For example, the bit line structure 300 includes a conductive doped polysilicon layer and a titanium nitride layer.

[0066] In some embodiments, referring to Figure 19A and Figure 19B as shown, among which, Figure 19A the left middle figure is Figure 19B a schematic cross-sectional view of the first vertical section V1-V1' in the middle, Figure 19A the right middle figure is Figure 19B a schematic cross-sectional view of the second vertical section V2-V2' in the middle, Figure 19B the left middle figure is Figure 19A a schematic cross-sectional view of the first horizontal section H1-H1' in the middle, Figure 19B the right middle figure is Figure 19A a schematic cross-sectional view of the third horizontal section H3-H3' in the middle. At least a part of the third sacrificial structure 140 in the capacitor slot CAt can be removed to expose the capacitor slot CAt, and the first sacrificial layer 141 located on one side of the conductive layer in the word line structure 220 is retained as the third isolation structure 204. In other examples, all of the third sacrificial structure 140 in the capacitor slot CAt can also be removed, and the third isolation structure 204 on one side of the conductive layer in the word line structure 220 is formed by filling.

[0067] A capacitor structure 400 is formed in the exposed capacitor trench CAt. The capacitor structure 400 includes a capacitor vertical portion 410 and a capacitor horizontal portion 420. The capacitor vertical portion 410 refers to the part of the capacitor structure 400 located in the capacitor vertical trench T21, and the capacitor horizontal portion 420 refers to the part of the capacitor structure 400 located in the capacitor horizontal trench T22. Among them, the capacitor horizontal portion 420 protrudes from both sides of the capacitor vertical portion 410 along the second direction D2. A plurality of capacitor horizontal portions 420 are arranged on the same layer as the active structure 210 and are arranged at intervals in the vertical direction D3. The capacitor horizontal portion 420 is in contact connection with the active structure 210. The capacitor horizontal portion 420 can be a double-sided capacitor structure, a columnar capacitor structure or a cylindrical capacitor structure, and the capacitor vertical portion 410 can serve as a common upper electrode for a plurality of capacitor horizontal portions 420 arranged at intervals in the vertical direction D3.

[0068] Each capacitor structure 400 and a transistor electrically connected thereto form a storage cell MC, and a plurality of storage cells MC located on the same layer form a storage layer ML. A plurality of storage layers ML are stacked in the vertical direction D3 to form a stacked structure MG. The stacked structure MG has a high integration degree, and each device structure in the stacked structure MG has a good isolation effect.

[0069] In other examples, the bit line structure 300 can be formed first, and then the capacitor structure 400 can be formed.

[0070] In some embodiments, the bit line structure 300 and the capacitor structure 400 are respectively formed in the bit line trench BLt and the capacitor trench CAt. The bit line structure 300 and the capacitor structure 400 are alternately arranged in the first direction D1 and alternately arranged in the second direction D2. The bit line structure 300 is arranged in a staggered manner. Compared with the symmetric arrangement method, this structural layout can effectively increase the spacing between the bit line structures 300, thereby reducing the coupling between the bit line structures 300, and thus improving the sensing margin of the semiconductor structure.

[0071] Based on the above preparation method of the semiconductor structure, the embodiments of the present disclosure also provide a semiconductor structure 10. Figure 1 is a three-dimensional schematic diagram of a semiconductor structure 10 shown according to an embodiment of the present disclosure, Figure 19A is a vertical cross-sectional schematic diagram of a semiconductor structure 10 shown according to an embodiment of the present disclosure and Figure 19B is a horizontal cross-sectional schematic diagram of a semiconductor structure 10 shown according to an embodiment of the present disclosure.

[0072] Referring to Figure 19A and Figure 19B shown and in combination with Figure 1As shown, the semiconductor structure 10 includes: a stacked structure MG located on a substrate 100, the stacked structure MG including a plurality of memory layers ML stacked in a vertical direction D3, each memory layer ML including a plurality of active structures 210 arranged in an array in a first direction D1 and a second direction D2 and a word line structure 220 extending in the first direction D1; bit line structures 300 and capacitor structures 400 located on both sides of each active structure 210 in the second direction D2, the bit line structures 300 and the capacitor structures 400 being alternately arranged in the first direction D1 and alternately arranged in the second direction D2; a first isolation structure 130 penetrating the stacked structure MG, the first isolation structure 130 being arranged in an array in the first direction D1 and the second direction D2, the first isolation structure 130 including a first isolation portion 130a located in the layer where the active structure 210 is located and a second isolation portion 130b located in the layer where the word line structure 220 is located, the size of the first isolation portion 130a in the second direction D2 being larger than the size of the second isolation portion 130b in the second direction D2 and the adjacent first isolation portions 130a in the second direction D2 being in contact with each other, and the bit line structures 300 and the capacitor structures 400 being located between the adjacent first isolation structures 130 in the second direction D2.

[0073] In the semiconductor structure provided by the present disclosure, in a first aspect, by arranging the bit line structures and the capacitor structures alternately in the first direction and the second direction, the pitch between the bit line structures can be increased, thereby reducing the coupling between the bit line structures, and thus improving the sensing margin of the semiconductor structure. In a second aspect, by providing an integrated first isolation structure between the device structures, and the first isolation structure having a first isolation portion and a second isolation portion that are alternately wide and narrow in the vertical direction, the isolation effect between the word line structures can be effectively improved, the morphology of the word line structures can be accurately defined, and the situation of open circuit or short circuit of the word line structures in the horizontal direction can be avoided, which is beneficial to improving the performance of the semiconductor structure.

[0074] In some embodiments, the bit line structure 300 includes a bit line vertical portion 310 and a bit line horizontal portion 320, the bit line vertical portion 310 penetrating the stacked structure MG in the vertical direction D3, the bit line horizontal portions 320 being located on both sides of the bit line vertical portion 310 in the second direction D2 and being spaced apart in the vertical direction D3, and the bit line horizontal portions 320 being in contact with the active structures 210. The material of the bit line structure 300 is a conductive material, and the bit line structure 300 can be a single-layer structure or a multi-layer structure. For example, the bit line structure 300 includes a conductive doped polysilicon layer and a titanium nitride layer. The transistors of the memory cells on both sides of the bit line structure 300 in the second direction D2 share one bit line structure 300, which can improve the integration degree of the semiconductor structure.

[0075] In some embodiments, the capacitive structure 400 includes a capacitive vertical portion 410 and a capacitive horizontal portion 420. The capacitive vertical portion 410 penetrates the stacked structure along the vertical direction D3. The capacitive horizontal portions 420 are located on both sides of the capacitive vertical portion 410 along the second direction D2 and are arranged at intervals in the vertical direction D3. The capacitive horizontal portion 420 includes a first electrode portion 421, a capacitive dielectric layer 422, and a second electrode portion 423. The capacitive dielectric layer 422 is sandwiched between the first electrode portion 421 and the second electrode portion 423. The first electrode portion 421 is in contact with the active structure 210, and the second electrode portion 423 is in contact with the capacitive vertical portion 410. The capacitive vertical portion 410 can serve as a common upper electrode for a plurality of capacitive horizontal portions 420 arranged at intervals in the vertical direction D3, and can further improve the integration degree of the semiconductor structure. The materials of the first electrode portion 421, the second electrode portion 423, and the capacitive vertical portion 410 are conductive materials. For example, the materials of the first electrode portion 421 and the second electrode portion 423 are titanium nitride, and the material of the capacitive vertical portion 410 is tungsten. The material of the capacitive dielectric layer 422 includes high-k materials, such as hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, etc.

[0076] In some embodiments, the word line structure 220 includes a first word line portion 221 and a second word line portion 222 that are alternately connected along the first direction D1. The first word line portion 221 at least covers the active structure 210. The second word line portion 222 is located between adjacent first isolation structures 130 along the second direction D2. The dimension of the first word line portion 221 along the second direction D2 is greater than the dimension of the second word line portion 222 along the second direction D2. The active structure 210 includes a channel portion 211 and a first source / drain portion 212 and a second source / drain portion 213 located on both sides of the channel portion 211. The first source / drain portion 212 is electrically connected to the capacitive structure 400, and the second source / drain portion 213 is electrically connected to the bit line structure 300. The first word line portion 221 at least covers the channel portion 211 in the active structure 210, that is, the projection of the first word line portion 221 on the substrate 100 intersects with the projection of the active structure 210 on the substrate 100, and the projection of the first word line portion 221 on the substrate 100 covers the projection of the channel portion 211 on the substrate 100. By providing the first word line portion 221 with a larger dimension, the channel length can be increased, the short-channel effect of the transistor can be reduced, and by providing the second word line portion 222 with a smaller dimension, the coupling between adjacent word line structures 220 can be reduced.

[0077] In some embodiments, the first isolation structure 130 formed by the first isolation portion 130a and the second isolation portion 130b is an integrally formed structure. The first isolation structure 130 may be a single-layer structure or a multi-layer structure. For example, the first isolation structure 130 may include a first isolation layer 131, a second isolation layer 132, and a third isolation layer 133. In this example, the first isolation structure 130 is an ONO (Oxide-Nitride-Oxide) structure, the first isolation layer 131 is silicon oxide, the second isolation layer 132 is silicon nitride, and the third isolation layer 133 is silicon oxide. The first isolation structure 130 has excellent isolation performance, can prevent signal crosstalk between the word line structures 220, and can improve the structural stability of the storage layer ML, thereby improving the reliability of the semiconductor structure 10.

[0078] In some embodiments, the semiconductor structure further includes a second isolation structure 203 interposed between the first word line portion 221 and the bit line structure 300; and a third isolation structure 204 interposed between the first word line portion 221 and the capacitor structure 400. The materials of the second isolation structure 203 and the third isolation structure 204 may include low dielectric constant materials, such as: silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, or silicon oxynitride, thereby reducing the coupling between the word line structure 220 and the bit line structure 300 and the capacitor structure 400.

[0079] In some embodiments, the first word line portion 221 has arc-shaped sidewalls that are opposite to each other in the second direction D2. The arc-shaped sidewalls of the first word line portion 221 are in contact with the second isolation structure 203 and the third isolation structure 204. The opposite arc-shaped sidewalls mean that the two arc-shaped sidewalls protrude towards each other, and the two arc-shaped sidewalls may not be completely symmetrical. For example, the curvature of the arc-shaped sidewall in contact with the second isolation structure 203 is less than the curvature of the arc-shaped sidewall in contact with the third isolation structure 204.

[0080] In some embodiments, the size of the active structure 210 is non-uniform in the first direction D1, and the active structure 210 has a protruding portion 210a facing the contact surface between adjacent first isolation structures 130. The portion of the active structure 210 having the protruding portion 210a is located in the middle of the active structure 210 and is used as the channel portion 211. That is, the size of the channel portion 211 in the first direction D1 is greater than the size of the first source / drain portion 212 and the second source / drain portion 213 in the first direction D1, which can reduce the short channel effect of the transistor.

[0081] In some embodiments, the semiconductor structure 10 includes: a memory, which may be a dynamic random access memory, specifically a three-dimensional dynamic random access memory, and the memory may also be a memory known in the art, for example, ferroelectric random access memory (FRAM), phase change memory (PCM), magnetic random access memory (MRAM), or resistive random access memory (RRAM), etc.

[0082] The various semiconductor structures shown in this specific embodiment can be used in electronic devices with a storage function. The electronic device can be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or can also be a personal computer (PC), a server, a workstation, etc. The storage function in the electronic device can be realized by a memory including the above semiconductor structure.

[0083] As described above, only the specific embodiments of the present disclosure are provided, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: forming a stacked structure on a substrate, the stacked structure comprising first semiconductor layers and second semiconductor layers alternately stacked in a vertical direction; A first isolation structure, a sacrificial structure and a filling layer are formed in the stacked structure, and the first semiconductor layer is patterned to form an initial active pattern arranged in an array, wherein the first isolation structure is arranged in an array along a first direction and a second direction, the first isolation structure comprises a first isolation portion located in a layer where the initial active pattern is located and a second isolation portion located in a layer where the second semiconductor layer is located, the size of the first isolation portion along the second direction is greater than the size of the second isolation portion along the second direction, and the first isolation portions adjacent to each other along the second direction are in contact, the sacrificial structure is located between the first isolation structures adjacent to each other along the first direction, and the filling layer is located in the layer where the second semiconductor layer is located; removing part of the filling layer and forming an initial word line layer; Removing the sacrificial structure and at least a portion of the filling layer to form a bit line trench and a capacitor trench respectively, and patterning the initial active pattern into an active structure, and patterning the initial word line layer into a word line structure extending along a first direction; A bit line structure and a capacitor structure are formed in the bit line trench and the capacitor trench, respectively. The bit line structure and the capacitor structure are alternately arranged in the first direction and alternately arranged in the second direction.

2. The preparation method according to claim 1, characterized in that: The forming of a first isolation structure, a sacrificial structure and a filling layer in the stacked structure, and patterning the first semiconductor layer to form an initial active pattern arranged in an array comprises: Etching the stacked structure to form a plurality of rectangular grooves, wherein the rectangular grooves expose a portion of the surface of the substrate, the plurality of rectangular grooves are arranged in an array along a first direction and a second direction, and a spacing between adjacent rectangular grooves along the first direction is greater than a spacing between adjacent rectangular grooves along the second direction; Removing a portion of the first semiconductor layer along the rectangular grooves to form an initial active pattern and isolation grooves arranged in an array; A first isolation structure filling the isolation trench is formed.

3. The preparation method according to claim 2, characterized in that: After forming a plurality of rectangular grooves, the method further comprises: filling an initial isolation structure in the rectangular groove; Etching the stacked structure to form a plurality of columnar grooves, wherein the columnar grooves expose a portion of the surface of the substrate, and the columnar grooves are located between the initial isolation structures adjacent to each other along the second direction; removing the second semiconductor layer along the columnar grooves to form interlayer gaps between the first semiconductor layers; Filling the first dielectric layer, the second dielectric layer and the third dielectric layer in the columnar groove and the interlayer gap to form a sacrificial structure in the columnar groove and a filling layer in the interlayer gap; Removing a portion of the first semiconductor layer along the rectangular groove to form an initial active pattern and isolation grooves arranged in an array, comprising: removing at least a portion of the initial isolation structure to expose the rectangular groove; The exposed portion of the first semiconductor layer is removed along the rectangular groove to form an isolation groove, wherein the isolation groove includes a first isolation groove portion located at the layer where the first semiconductor layer is located, the first isolation groove portions are connected in the second direction and disconnect the initial active pattern in the first direction.

4. The preparation method according to claim 3, characterized in that: The first dielectric layer covers the surface of the initial active pattern, the second dielectric layer covers the surface of the second dielectric layer and fills the interlayer gap, a portion of the filling layer is removed, and an initial word line layer is formed, including: removing a portion of the first dielectric layer to form an initial word line trench; An initial word line layer is formed in the initial word line groove.

5. The preparation method according to claim 4, characterized in that: The initial word line layer includes a gate oxide material layer and a conductive material layer; Forming an initial word line layer in the initial word line groove comprises: forming a gate oxide material layer in the initial word line groove to cover the surface of the initial active pattern; A conductive material layer is formed to cover the surface of the gate oxide material layer and fill the initial word line groove.

6. The preparation method according to claim 1, characterized in that: The sacrificial structure comprises a first sacrificial structure and a second sacrificial structure, wherein the first sacrificial structure and the second sacrificial structure are alternately arranged in the first direction and alternately arranged in the second direction; The sacrificial structure and at least a portion of the filling layer are removed to form a bit line groove and a capacitor groove respectively, and the initial active pattern is patterned into an active structure, and the initial word line layer is patterned into a word line structure extending along a first direction, comprising: Removing the first sacrificial structure to expose the capacitor vertical groove, removing a portion of the initial active pattern along the capacitor vertical groove to form a capacitor horizontal groove, wherein the capacitor vertical groove and the capacitor horizontal groove constitute a capacitor groove; Filling a third sacrificial structure in the capacitor groove; The second sacrificial structure is removed to expose the bit line vertical groove, and a portion of the initial active pattern is removed along the bit line vertical groove to form a bit line horizontal groove, wherein the bit line vertical groove and the bit line horizontal groove constitute a bit line groove, and the remaining initial active pattern serves as an active structure.

7. The preparation method according to claim 6, characterized in that: After removing the second sacrificial structure to expose the bit line vertical groove and before removing a portion of the initial active pattern along the capacitor vertical groove, the method further includes: removing a portion of the initial word line layer along the bit line vertical groove, and using the remaining initial word line layer as a word line structure; A second isolation structure is formed, wherein the second isolation structure is sandwiched between the word line structure and the bit line vertical trench.

8. A semiconductor structure, characterized in that: include: A stacked structure located on a substrate, the stacked structure comprising a plurality of storage layers stacked in a vertical direction, each of the storage layers comprising a plurality of active structures arrayed in a first direction and a second direction and a word line structure extending in the first direction; bit line structures and capacitor structures located on both sides of each of the active structures along the second direction, the bit line structures and the capacitor structures are alternately arranged in the first direction and alternately arranged in the second direction; A first isolation structure runs through the stacked structure, the first isolation structure is arranged in an array along a first direction and a second direction, the first isolation structure includes a first isolation portion located at a layer where the active structure is located and a second isolation portion located at a layer where a word line structure is located, a size of the first isolation portion along the second direction is greater than a size of the second isolation portion along the second direction, and first isolation portions adjacent to each other along the second direction are in contact, and the bit line structure and the capacitor structure are located between first isolation structures adjacent to each other along the second direction.

9. The semiconductor structure according to claim 8, characterized in that: The bit line structure includes a bit line vertical portion and a bit line horizontal portion, the bit line vertical portion penetrates the stacking structure along the vertical direction, the bit line horizontal portion is located on both sides of the bit line vertical portion along the second direction and is arranged at intervals in the vertical direction, and the bit line horizontal portion contacts the active structure.

10. The semiconductor structure according to claim 8, characterized in that The capacitor structure includes a vertical capacitor portion and a horizontal capacitor portion, the vertical capacitor portion penetrates the stacked structure along the vertical direction, the horizontal capacitor portion is located on both sides of the vertical capacitor portion along the second direction and is arranged at intervals in the vertical direction, the horizontal capacitor portion includes a first electrode portion, a capacitor dielectric layer and a second electrode portion, the capacitor dielectric layer is sandwiched between the first electrode portion and the second electrode portion, the first electrode portion is in contact with the active structure, and the second electrode portion is in contact with the vertical capacitor portion.

11. The semiconductor structure according to claim 8, characterized in that: The word line structure includes a first word line portion and a second word line portion alternately connected along the first direction, the first word line portion at least covers the active structure, the second word line portion is located between adjacent first isolation structures along the second direction, and the size of the first word line portion along the second direction is greater than the size of the second word line portion along the second direction.

12. The semiconductor structure according to claim 11, characterized in that: Also includes: a second isolation structure, the second isolation structure being sandwiched between the first word line portion and the bit line structure; A third isolation structure is sandwiched between the first word line portion and the capacitor structure.

13. The semiconductor structure according to claim 11, characterized in that: The first word line portion has arc-shaped side walls opposite to each other along the second direction.

14. The semiconductor structure according to claim 8, characterized in that The active structure has a non-uniform size in the first direction, and has a protruding portion facing a contact surface between adjacent first isolation structures.

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