Three-dimensional memory device with stepped structure

Abstract

The invention relates to a three-dimensional memory device with a stepped structure. A three-dimensional memory device includes: first and second isolation patterns extending in a first direction and adjacent to each other in a second direction crossing the first direction; a laminate disposed between the first isolation pattern and the second isolation pattern, and including a connection region including a plurality of electrode layers and a plurality of interlayer insulating layers alternately stacked in a vertical direction, and an insulating region surrounded by the connection region; and a plurality of stepped recessed portions disposed in the insulating region and the connecting region, and arranged in the first direction, wherein at least one of the plurality of stepped recesses includes a first stepped structure connected to the first isolation pattern, a second stepped structure connected to the second isolation pattern, and a sidewall connecting the first stepped structure and the second stepped structure and disposed in the insulating region.

Description

Technical Field

[0001] Various embodiments relate generally to semiconductor technology and, more particularly, to three-dimensional memory devices and methods of fabricating the same. Background Art

[0002] Semiconductor memory devices with two-dimensional or planar structures have been developed to store more data in the same area using fine patterning processes. However, as circuit line widths narrow due to the demand for higher integration, interference between memory cells increases, causing various limitations and problems such as performance degradation. In addition to these structural limitations, an increase in manufacturing costs is inevitable because expensive equipment is required to pattern the increasingly narrow lines.

[0003] To overcome this limitation of two-dimensional semiconductor memory devices, three-dimensional semiconductor memory devices have been proposed. The advantage of three-dimensional memory devices is that they can achieve a larger capacity within the same area by stacking memory cells vertically, thereby increasing the number of stacked layers and providing higher performance and excellent power efficiency. Summary of the Invention

[0004] Various embodiments of the disclosed technology are directed to three-dimensional memory devices with improved integration and reliability, and methods of manufacturing such devices.

[0005] In an embodiment, a three-dimensional memory device may include: a first isolation pattern and a second isolation pattern, which extend in a first direction and are adjacent to each other in a second direction intersecting the first direction; a stack, which is arranged between the first isolation pattern and the second isolation pattern, the stack including a connection area and an insulating area surrounded by the connection area, the connection area including a plurality of electrode layers and a plurality of interlayer insulating layers alternately stacked in a vertical direction; and a plurality of stepped recesses, which are configured in the insulating area and the connection area and arranged along the first direction, wherein at least one of the plurality of stepped recesses includes: a first stepped structure connected to the first isolation pattern, a second stepped structure connected to the second isolation pattern, and a sidewall connecting the first stepped structure and the second stepped structure and arranged in the insulating area.

[0006] In an embodiment, a three-dimensional memory device may include: a first semiconductor structure including a peripheral circuit; and a second semiconductor structure disposed on the first semiconductor structure, the second semiconductor structure including: a source plate disposed on the first semiconductor structure; a first isolation pattern and a second isolation pattern disposed on the source plate, extending in a first direction, and adjacent to each other in a second direction intersecting the first direction; a stack disposed between the first isolation pattern and the second isolation pattern and including a connection region and an insulating region surrounded by the connection region, the connection region including a plurality of electrode layers and a plurality of interlayer insulating layers alternately stacked in a vertical direction; and a plurality of stepped recesses configured in the insulating region and the connection region and arranged along the first direction, wherein at least one of the plurality of stepped recesses includes: a first stepped structure connected to the first isolation pattern, a second stepped structure connected to the second isolation pattern, and a sidewall connecting the first stepped structure and the second stepped structure and disposed in the insulating region.

[0007] In an embodiment, a three-dimensional memory device may include: a first semiconductor structure having a peripheral circuit and a first bonding layer, the first bonding layer including a plurality of first bonding pads connected to the peripheral circuit; and a second semiconductor structure bonded to the first semiconductor structure, the second semiconductor structure including: a second bonding layer including a plurality of second bonding pads bonded to the plurality of first bonding pads; a first isolation pattern and a second isolation pattern, which are arranged on the second bonding layer, extend in a first direction, and are adjacent to each other in a second direction intersecting the first direction; a stack, which is arranged between the first isolation pattern and the second isolation pattern and includes a connection region and an insulating region surrounded by the connection region, the connection region including a plurality of electrode layers and a plurality of interlayer insulating layers alternately stacked in a vertical direction; and a plurality of stepped recesses, which are configured in the insulating region and the connection region and arranged along the first direction, wherein at least one of the plurality of stepped recesses includes: a first stepped structure connected to the first isolation pattern, a second stepped structure connected to the second isolation pattern, and a sidewall connecting the first stepped structure and the second stepped structure and arranged in the insulating region.

[0008] According to embodiments of the disclosed technology, a three-dimensional memory device with improved integration and reliability may be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a layout diagram of a three-dimensional memory device according to an embodiment of the present disclosure.

[0010] Figure 2 This is an example Figure 1 A three-dimensional view of the first stepped recess and the second stepped recess.

[0011] Figure 3 It is along Figure 1 A cross-sectional view taken along line A.

[0012] Figure 4 It is along Figure 1 A cross-sectional view taken along line B.

[0013] Figure 5 It is along Figure 1 A cross-sectional view taken along line C.

[0014] Figure 6 It is along Figure 1 A cross-sectional view taken along line D.

[0015] Figure 7 It is along Figure 1 A cross-sectional view taken along line E.

[0016] Figure 8 and Figure 9 is a layout diagram of a three-dimensional memory device according to an embodiment of the present disclosure.

[0017] Figure 10 It is along Figure 9 A cross-sectional view taken along line F.

[0018] Figure 11 is a layout diagram of a three-dimensional memory device according to an embodiment of the present disclosure.

[0019] Figure 12 and Figure 13 is a cross-sectional view of a three-dimensional memory device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, although elements are shown in different drawings, identical elements will be indicated by identical reference numerals. In addition, in the following description of the present disclosure, when a detailed description of the known functions and configurations incorporated herein may make the subject matter of the present disclosure unclear, the detailed description will be omitted. It should be noted that the terms "comprise", "have", "include" etc. used in the specification and claims should not be interpreted as being limited to the means listed thereafter, unless otherwise expressly stated. When an indefinite article or definite article (e.g., "one", "an" and "the") is used when referring to a singular noun, this may include the plural form of the noun, unless otherwise expressly stated.

[0021] In addition, when describing the components of the present disclosure, terms such as first, second, A, B, (a), and (b) may be used. These are only for the purpose of distinguishing one component from another, but do not limit the essence, sequence, order, or number of the components.

[0022] In the description of the positional relationship of components, when describing that at least two components are “connected,” “coupled,” or “linked,” it is to be understood that the at least two components may be directly “connected,” “coupled,” or “linked,” but may be indirectly “connected,” “coupled,” or “linked” with another component interposed therebetween. Here, the other component may be included in at least one of the at least two components that are “connected,” “coupled,” or “linked” to each other.

[0023] In the description of the time flow relationship of components, operating methods or manufacturing methods, when describing the temporal context or process context by, for example, "after", "subsequently", "next" or "before", discontinuities may be included unless "immediately" or "directly" is used.

[0024] When referring to a numerical value of a component or its corresponding information, even without separate explicit description, the numerical value or its corresponding information can be interpreted as including an error range that may be caused by various factors (e.g., process variables, internal or external shocks, noise, etc.).

[0025] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the accompanying drawings, a direction perpendicularly projected from the top surface of the substrate is defined as a vertical direction VD, and two directions parallel to the top surface of the substrate and intersecting each other are defined as a first direction FD and a second direction SD, respectively. The first direction FD and the second direction SD may intersect substantially perpendicularly with each other. In the accompanying drawings, a direction indicated by an arrow and a direction opposite thereto represent the same direction.

[0026] Figure 1 is a layout diagram of a three-dimensional memory device according to an embodiment of the present disclosure.

[0027] Reference Figure 1 , a three-dimensional memory device according to an embodiment of the present disclosure may include first and second isolation patterns DP1 and DP2 , a stack STA, and first and second stepped recesses R1 and R2 .

[0028] The first isolation pattern DP1 and the second isolation pattern DP2 may extend in a first direction FD and may be adjacent to or spaced apart from each other in a second direction SD intersecting the first direction FD. The first direction FD and the second direction SD may intersect each other perpendicularly. The first direction FD may be an extending direction of a word line, and the second direction SD may be an extending direction of a bit line.

[0029] The first isolation pattern DP1 and the second isolation pattern DP2 may include an insulating layer. As another example, at least a portion of the first isolation pattern DP1 and the second isolation pattern DP2 may function as a common source line. In this case, although not shown, at least a portion of the first isolation pattern DP1 and the second isolation pattern DP2 may include a conductive layer functioning as the common source line. An insulating layer may be disposed between the conductive layer and the stack STA to isolate the conductive layer from the stack STA.

[0030] The stack STA may be disposed between the first isolation pattern DP1 and the second isolation pattern DP2. The first isolation pattern DP1 and the second isolation pattern DP2 may be disposed on both sides of the stack STA in the second direction SD, respectively. The stack STA may configure one memory block.

[0031] Although only two isolation patterns DP1 and DP2 and one stack STA are shown in the drawing, a plurality of stacks may be arranged in the second direction SD, and an isolation pattern may be provided between two stacks adjacent to or spaced apart from each other.

[0032] The stack STA may include a cell array region CAR, a connection region CNR extending from the cell array region CAR in the first direction FD, and an insulating region ISR surrounded by the connection region CNR.

[0033] As will be referred to later Figure 2 and Figure 3 As described, the cell array region CAR and the connection region CNR may include a plurality of electrode layers stacked in the vertical direction VD. The plurality of electrode layers may include a plurality of word line layers and a plurality of select line layers. The plurality of select line layers may include, for example, at least one top select line layer disposed above the plurality of word line layers and at least one bottom select line layer disposed below the plurality of word line layers.

[0034] When viewed from the top, the insulating region ISR may have a linear shape that crosses the center portion of the stack STA in the first direction FD. The insulating region ISR may be arranged in a row in the stack STA. Although the present disclosure illustrates a case where one insulating region ISR is arranged in one stack STA, the present disclosure is not limited thereto. Multiple insulating regions may be arranged in a row along the first direction FD at the center portion of the stack STA.

[0035] The connection region CNR may include bridges BP disposed on both sides of the insulating region ISR in the second direction SD. The bridges BP have a reduced width due to the presence of the insulating region ISR. In the embodiment of the present disclosure, since the insulating region ISR is disposed in a single row within the single stack STA, the bridges BP may be disposed in two rows.

[0036] A barrier structure BA surrounding the insulating region ISR may be disposed between the insulating region ISR and the connection region CNR to isolate the insulating region ISR from the connection region CNR. The insulating region ISR may be defined by the barrier structure BA.

[0037] A plurality of support members SP may be disposed in the connection region CNR of the stack STA. The plurality of support members SP may be disposed in the bridge portion BP of the connection region CNR. The support members SP may pass through the connection region CNR of the stack STA in the vertical direction VD. The support members SP may be used to support the stack STA to prevent the stack STA from collapsing or bending during the manufacturing process.

[0038] A third isolation pattern DP3 , a top selection line cut DLC, and a bottom selection line cut SLC may be configured in the stack STA.

[0039] When viewed from the top, the third isolation pattern DP3 may extend in the first direction FD on both sides of the insulating region ISR. The third isolation pattern DP3 may be spaced apart from the insulating region ISR.

[0040] Although not shown, the third isolation pattern DP3 may vertically penetrate the stack STA. Each word line layer may include a connection portion in a region where the third isolation pattern DP3 and the insulating region ISR are spaced apart from each other. Each word line layer may include two word line fingers distinguished by the third isolation pattern DP3 and the insulating region ISR. The two word line fingers may be connected to each other via the connection portion. The word line layers may configure word lines.

[0041] When viewed from the top, the top selection line cutout DLC may be disposed between the first and third isolation patterns DP1 and DP3 and between the second and third isolation patterns DP2 and DP3 , may extend in the first direction FD, and may be arranged along the second direction SD.

[0042] Although not shown, a top selection line cutout DLC may vertically penetrate the top selection line layer. The top selection line layer may be divided into a plurality of top selection lines, for example, eight top selection lines, through the third isolation pattern DP3 and the top selection line cutout DLC. The top selection lines may be configured as drain selection lines.

[0043] When viewed from the top, the bottom select line cutout SLC may be connected between the third isolation pattern DP3 and the insulating region ISR. Although not shown, the bottom select line cutout SLC may vertically pass through the bottom select line layer. The bottom select line layer may be divided into two bottom select lines by the third isolation pattern DP3, the bottom select line cutout SLC, and the insulating region ISR. The bottom select lines may be configured as source select lines.

[0044] The first stepped recess R1 and the second stepped recess R2 may be disposed in the insulating region ISR and the connection region CNR. The first stepped recess R1 and the second stepped recess R2 may be arranged along the first direction FD. Although two stepped recesses are illustrated in this embodiment, the present disclosure is not limited thereto. Multiple stepped recesses may be disposed in the insulating region ISR and the connection region CNR along the first direction FD.

[0045] A plurality of row connection contacts XCT connected to the electrode layer may be provided in the connection region CNR of the stack STA. The row connection contacts XCT may extend vertically from the connection region CNR of the stack STA. The row connection contacts XCT may be arranged in the connection region CNR of the stack STA along the first direction FD. In an embodiment of the present disclosure, the row connection contacts XCT may be provided in a plurality of rows along the second direction SD.

[0046] A plurality of through-contacts TCT1 and TCT2 may be disposed in the insulating region ISR of the stack STA. The through-contacts TCT1 and TCT2 may penetrate the insulating region ISR of the stack STA in the vertical direction VD. The through-contacts TCT1 and TCT2 may provide vertical interconnects through the three-dimensional memory cell array in the vertical direction VD, thereby helping to reduce the number of metal layers and the die size.

[0047] The through-contacts TCT1 and TCT2 may be arranged in a plurality of rows in the second direction SD. The embodiment of the present disclosure illustrates a case where the through-contacts TCT1 and TCT2 are arranged in two rows, but the present disclosure is not limited thereto. Hereinafter, for ease of explanation, the through-contacts TCT1 in the first row will be defined as first through-contacts, and the through-contacts TCT2 in the second row will be defined as second through-contacts.

[0048] A plurality of cell plugs CP may be arranged in the cell array region CAR. The plurality of cell plugs CP may penetrate the cell array region CAR in the vertical direction VD. The plurality of cell plugs CP may be arranged in a plurality of rows along the second direction SD. The cell plugs CP in odd-numbered rows and the cell plugs CP in even-numbered rows may be offset relative to each other in the first direction FD due to a zigzag pattern. Due to this fact, a larger number of cell plugs CP may be arranged within the same area to achieve a higher degree of integration.

[0049] According to an embodiment of the present disclosure, since the insulating region ISR is configured as a row in one stack STA and the bridge portions BP of the connection region CNR are configured as two rows, the number of barrier structures BA and support members SP arranged in the same row in the second direction SD can be minimized. Since the number of components arranged in the same row in the second direction SD is small, the pitch of the memory blocks in the second direction SD can be configured to have a smaller size.

[0050] Figure 2 This is an example Figure 1 A three-dimensional view of the first stepped recess and the second stepped recess.

[0051] Reference Figure 2 The connection region CNR may include a plurality of electrode layers 11 and a plurality of first interlayer insulating layers 12 alternately stacked in the vertical direction VD. The insulating region ISR may include a plurality of horizontal insulating layers 21 and a plurality of second interlayer insulating layers 22 alternately stacked in the vertical direction VD.

[0052] The first stepped recess R1 may include first and second stepped structures ST1 and ST2 arranged in the second direction SD, and a sidewall CSW connecting the first and second stepped structures ST1 and ST2 .

[0053] Each of the first stepped structure ST1 and the second stepped structure ST2 may include a plurality of steps. When viewed from the top, the steps included in each of the first stepped structure ST1 and the second stepped structure ST2 may be arranged in a row along the first direction FD. When viewed from the top, the first stepped structure ST1 and the second stepped structure ST2 may be adjacent to each other in the second direction SD.

[0054] The first stepped structure ST1 and the second stepped structure ST2 may be located at different height levels and may be connected to each other by a sidewall CSW. The sidewall CSW may be provided in the insulating region ISR.

[0055] like Figure 2 As shown in the X-section, a triple point may be generated at the boundary between the sidewall CSW and the second stepped structure ST2. Each triple point represents a point where the horizontal surface of the second stepped structure ST2, the vertical surface of the second stepped structure ST2, and the sidewall CSW intersect. During the etching process used to form the second stepped structure ST2, etching residue may accumulate around the triple point. In subsequent processes, the etching residue may be replaced with conductive material to produce conductive foreign matter.

[0056] Unlike the present disclosure, when the sidewall CSW is provided in the connection region CNR, a defect may occur in which the upper electrode layer 11 and the lower electrode layer 11 are short-circuited due to conductive foreign matter generated around the triple point. In the embodiment of the present disclosure, the sidewall CSW is provided in the insulating region ISR so that the triple point is located in the insulating region ISR. Therefore, the upper electrode layer 11 and the lower electrode layer 11 can be prevented from being short-circuited by the conductive foreign matter generated around the triple point.

[0057] The second stepped recess R2 may include a third stepped structure ST3. The third stepped structure ST3 may include a plurality of steps. When viewed from the top, the steps of the third stepped structure ST3 may be arranged in a row along the first direction FD.

[0058] Figure 3 It is along Figure 1 A cross-sectional view taken along line A, Figure 4 It is along Figure 1 A cross-sectional view taken along line B of Figure 5 It is along Figure 1 A cross-sectional view taken along line C of Figure 6 It is along Figure 1 A cross-sectional view taken along line D of Figure 7 It is along Figure 1 A cross-sectional view taken along line E.

[0059] To simplify the diagram, Figure 3 and Figure 6 The support member SP is omitted (see Figure 1 ) icon.

[0060] Reference Figures 3 to 7 The cell array region CAR and the connection region CNR may include a plurality of electrode layers 11 and a plurality of first interlayer insulating layers 12 alternately stacked on the source plate 30 in the vertical direction VD. The electrode layer 11 may include at least one selected from a semiconductor (e.g., doped silicon), a metal (e.g., tungsten, copper, or aluminum), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), and a transition metal (e.g., titanium or tantalum). The first interlayer insulating layer 12 may include silicon oxide.

[0061] As described above, the electrode layer 11 may include a plurality of word lines, top selection lines, and bottom selection lines. The plurality of word lines may include main word lines connected to main cells for storing data and dummy word lines connected to dummy cells not for storing data.

[0062] Although not shown, the source plate 30 may include a plurality of source layers. An isolation layer may be provided between adjacent source layers to isolate the plurality of source layers.

[0063] The source plate 30 may be configured to overlap the cell array region CAR and the connection region CNR in the vertical direction VD and not overlap at least a portion of the insulating region ISR in the vertical direction VD. The insulating pattern 40 may be provided below the insulating region ISR that does not overlap with the source plate 30 in the vertical direction VD.

[0064] A plurality of cell plugs CP may penetrate the cell array region CAR in the vertical direction VD.

[0065] Although not shown, the cell plug CP may include a channel layer and a gate dielectric layer. The channel layer may include polycrystalline silicon or single crystal silicon and may include P-type impurities such as boron (B) in some regions thereof. The gate dielectric layer may have a shape surrounding the outer wall of the channel layer. The gate dielectric layer may include a tunnel insulating layer, a charge storage layer, and a blocking layer stacked in sequence from the outer wall of the channel layer. In some embodiments, the gate dielectric layer may have an ONO (oxide-nitride-oxide) stacked structure in which an oxide layer, a nitride layer, and an oxide layer are stacked in sequence.

[0066] The main cell may be configured in a portion or region where the main word line surrounds the cell plug CP, and the dummy cell may be configured in a portion or region where the dummy word line surrounds the cell plug CP. The bottom selection transistor may be configured in a portion or region where the bottom selection line surrounds the cell plug CP, and the top selection transistor may be configured in a portion or region where the top selection line surrounds the cell plug CP.

[0067] The first stepped structure ST1 and the second stepped structure ST2 in the first stepped recess R1 may be disposed between the first isolation pattern DP1 and the second isolation pattern DP2 in the second direction SD. The first stepped structure ST1 may be connected to the first isolation pattern DP1, and the second stepped structure ST2 may be connected to the second isolation pattern DP2. Figure 2 As described, the first stepped structure ST1 and the second stepped structure ST2 may be disposed at different height levels in the vertical direction VD and may be connected to each other through the sidewall CSW disposed in the insulating region ISR.

[0068] The third stepped structure ST3 in the second stepped recess R2 may be disposed between the first and second isolation patterns DP1 and DP2 and may be connected to the first and second isolation patterns DP1 and DP2.

[0069] The third stepped structure ST3 can be produced using an etching process known as an X-slim process. The X-slim process may include forming a mask pattern having linear openings extending in the second direction SD, etching the portion exposed by the openings to a thickness corresponding to the vertical pitch of the horizontal insulating layer 21, thinning the mask pattern to increase the width of the openings, and alternately repeating the etching and thinning processes. The vertical pitch of the horizontal insulating layer 21 may correspond to the sum of the thickness of one horizontal insulating layer 21 and the thickness of one second interlayer insulating layer 22.

[0070] The first stepped structure ST1 may be produced using an etching process called an X-slim process and a Z-slim process. After the stepped structure is formed by the X-slim process, the first stepped structure ST1 may be produced as the stepped structure produced by the X-slim process is transferred downward through the Z-slim process.

[0071] The Z-slim process may include forming a mask pattern that exposes a region including the stepped structure generated by the X-slim process, and etching the region exposed by the mask pattern to a first depth. The first depth may correspond to k (k is an integer equal to or greater than 2) times the vertical pitch of the horizontal insulating layer 21. For example, the present disclosure illustrates a case where k is 3.

[0072] The second stepped structure ST2 may be produced using etching processes such as an X-slim process, a Z-slim process, and a Y-slim (Y-thinning) process. After the first stepped structure ST1 is produced through the X-slim process and the Z-slim process, the second stepped structure ST2 may be produced as the portion of the first stepped structure ST1 in contact with the second isolation pattern DP2 is transferred downward through the Y-slim process.

[0073] The Y-slim process may include forming a mask pattern that exposes a region including a portion of the first stepped structure ST1 that contacts the second isolation pattern DP2, and etching the region exposed by the mask pattern to a second depth. The second depth may correspond to m (m is an integer equal to or greater than 2) times the vertical pitch of the horizontal insulating layer 21. Thus, the second stepped structure ST2 may be located at a second depth lower than the first stepped structure ST1. For example, the present disclosure illustrates a case where m is 3.

[0074] The sidewall CSW connecting the first stepped structure ST1 and the second stepped structure ST2 may be formed by a Y-slim process. The height of the sidewall CSW may be the same as the etching depth (i.e., the second depth) of the Y-slim process. The Y-slim process may be performed to form the sidewall CSW in the insulating region ISR.

[0075] Each of the first to third stepped structures ST1 to ST3 may include a pair of stepped portions. The pair of stepped portions included in each of the first to third stepped structures ST1 to ST3 may be disposed facing each other in the first direction FD. The pad region LP of the electrode layer 11 may be disposed in any one of the pair of stepped portions included in each of the first to third stepped structures ST1 to ST3, and the dummy pad region DP of the electrode layer 11 may be disposed in the other of the pair of stepped portions.

[0076] The row connection contacts XCT may be respectively connected to the pad regions LP of the electrode layer 11. The row connection contact XCT is not connected to each of the dummy pad regions DP.

[0077] Although the present embodiment illustrates a case where the slope of the step portion including the dummy pad region DP is the same as the slope of the step portion including the pad region LP, the present disclosure is not limited thereto. The step portion including the dummy pad region DP may be configured to have a steeper slope than the step portion including the pad region LP.

[0078] The pad region LP should have a width of at least a predetermined size in order to connect to the row connection contact XCT, but the dummy pad region DP can have a smaller width because it is not connected to the row connection contact. By configuring the dummy pad region DP to have a smaller width than the pad region LP in the first direction FD, the stepped portion including the dummy pad region DP can have a steeper slope than the stepped portion including the pad region LP. Due to this fact, the width of the first stepped structure ST1 to the third stepped structure ST3 in the first direction FD can be reduced.

[0079] The barrier structure BA may vertically penetrate the stack STA between the insulating region ISR and the connection region CNR. A lower end of the barrier structure BA may be connected to the source plate 30.

[0080] In an embodiment of the present disclosure, multiple horizontal insulating layers and multiple interlayer insulating layers are alternately stacked in the vertical direction VD. The horizontal insulating layers of the cell array region CAR and the connection region CNR are then removed, and a conductive material is filled in the spaces where the horizontal insulating layers have been removed to create electrode layers. The barrier structure BA can serve as an etching barrier, preventing the horizontal insulating layers of the insulating region ISR from being removed or lost during the process of removing the horizontal insulating layers of the cell array region CAR and the connection region CNR. Furthermore, the barrier structure BA can also serve to support the stack STA to prevent the stack STA from collapsing or bending during the manufacturing process.

[0081] The barrier structure BA may be composed of an insulating material having an etch selectivity different from that of the horizontal insulating layer 21. For example, the horizontal insulating layer 21 may be composed of nitride, and the barrier structure BA may be composed of oxide.

[0082] A plurality of through-contacts TCT1 and TCT2 may pass through the insulating region ISR in a vertical direction VD. Lower ends of the through-contacts TCT1 and TCT2 may be connected to the insulating pattern 40. A plurality of conductive contact plugs DCC vertically passing through the insulating pattern 40 may be defined below the through-contacts TCT1 and TCT2 to be connected to the through-contacts TCT1 and TCT2, respectively.

[0083] The through contacts TCT1 and TCT2 can be made of a conductive material. For example, the through contacts TCT1 and TCT2 can be made of tungsten (W) with excellent step coverage. Since the through contacts TCT1 and TCT2 pass through the insulating region ISR, the through contacts TCT1 and TCT2 may not include insulating spacers. Since the through contacts TCT1 and TCT2 do not include insulating spacers, the manufacturing cost can be reduced by omitting the processing steps for forming insulating spacers. In addition, since the cross-sectional area of ​​the conductors constituting the through contacts TCT1 and TCT2 is not reduced due to the presence of insulating spacers, low resistance of the through contacts TCT1 and TCT2 can be achieved.

[0084] As will be referred to later Figure 12 and Figure 13 As described, the three-dimensional memory device may include a peripheral circuit and a plurality of external connection pads. Power and signals may be provided to the three-dimensional memory device from an external device via the external connection pads. The first through-contact TCT1 may connect the external connection pads and the peripheral circuit, and may transmit power and signals provided from the external device to the peripheral circuit via the external connection pads.

[0085] Each second through-contact TCT2 may be connected to a row connection contact XCT through an interconnection pattern not shown herein and may be connected to the electrode layer 11 through the row connection contact XCT. The second through-contact TCT2 may be connected to a peripheral circuit and may be used to transmit an operating voltage from the peripheral circuit to the electrode layer 11.

[0086] Figure 8 is a layout diagram of a three-dimensional memory device according to an embodiment of the present disclosure.

[0087] Reference Figure 8 , the first through-contact TCT1 and the second through-contact TCT2 may be offset with respect to each other in the first direction FD. The first through-contact TCT1 and the second through-contact TCT2 may not overlap each other in the second direction SD.

[0088] During the manufacturing process of the memory device, conductive foreign matter may be generated along the vertical surfaces of the steps defined in the first stepped recess R1 and the second stepped recess R2 due to process defects. When the first through-contacts TCT1 and the second through-contacts TCT2 are arranged in the same row in the second direction SD, a defect may occur in which the first through-contacts TCT1 and the second through-contacts TCT2 are short-circuited by the conductive foreign matter.

[0089] According to the present embodiment, by disposing the first and second through-contacts TCT1 and TCT2 disposed in different rows to be offset relative to each other in the first direction FD, short circuiting of the first and second through-contacts TCT1 and TCT2 can be suppressed or prevented.

[0090] Figure 9 is a layout diagram of a three-dimensional memory device according to an embodiment of the present disclosure, and Figure 10 It is along Figure 9 A cross-sectional view taken along line F.

[0091] Reference Figure 9 The insulating region ISR may include a line portion LPP and a protrusion PP protruding from the line portion LPP toward the first isolation pattern DP1 and the second isolation pattern DP2. Although the present disclosure illustrates a case where the insulating region ISR includes the protrusion PP protruding in the second direction SD toward the first isolation pattern DP1 and the second isolation pattern DP2, the present disclosure is not limited thereto. The insulating region ISR may include at least one protrusion PP protruding from the line portion LPP toward at least one of the first isolation pattern DP1 and the second isolation pattern DP2.

[0092] The first through-contact TCT1 may pass through the protrusion portion PP, and the second through-contact TCT2 may pass through the line portion LPP. The first through-contact TCT1 and the second through-contact TCT2 may be offset with respect to each other in the first direction FD.

[0093] Reference Figure 9 and Figure 10 The protrusion PP may be disposed in a region including the non-recessed region NR between the first stepped recess R1 and the second stepped recess R2. Since the protrusion PP, through which the first through-contact TCT1 passes, is disposed in a region including the non-recessed region NR, the conditions of the contact hole etching process for forming the first through-contact TCT1 may be uniform, thereby reducing process defects that may occur during the etching process.

[0094] Figure 11 is a layout diagram of a three-dimensional memory device according to an embodiment of the present disclosure.

[0095] Reference Figure 11 , the second through-contact TCT2 may include a main through-contact TCT2A and a dummy through-contact TCT2B.

[0096] As described above, the word lines may include a main word line connected to the main cell and a dummy word line connected to the dummy cell. The main through-contact TCT2A may be used to electrically connect the main word line and the peripheral circuit. The dummy through-contact TCT2B may be used to electrically connect the dummy word line and the peripheral circuit. As described above, the first through-contact TCT1 may transmit power and signals provided from an external device to the peripheral circuit.

[0097] The main through-contact TCT2A may be disposed in a region separated from the region A where the first through-contact TCT1 is disposed in a diagonal direction crossing the first direction FD and the second direction SD. The dummy through-contact TCT2B may be disposed in a region adjacent to the region A where the first through-contact TCT1 is disposed in the second direction SD.

[0098] Due to coupling between the first through-contact TCT1 and the main through-contact TCT2A, a voltage of the main through-contact TCT2A may change under the influence of a voltage of the first through-contact TCT1 , and thus an error may occur in a data read or write operation.

[0099] According to the present embodiment, when the main through-contact TCT2A is provided in a region diagonally separated from the region A in which the first through-contact TCT1 is provided, the distance between the main through-contact TCT2A and the first through-contact TCT1 can be increased, and the coupling can be reduced. Therefore, since the influence exerted by the voltage of the first through-contact TCT1 on the voltage of the main through-contact TCT2A is reduced, errors in data storage and / or reading operations can be reduced.

[0100] The dummy through-contact TCT2B can be disposed in a region adjacent to the region A in which the first through-contact TCT1 is disposed along the second direction SD. Since the dummy through-contact TCT2B is used to transmit an operating voltage to a dummy word line that is unrelated to stored data, even if the voltage of the dummy through-contact TCT2B changes due to the coupling between the dummy through-contact TCT2B and the first through-contact TCT1, errors in data storage and / or read operations will not occur. Therefore, by disposing the dummy through-contact TCT2B in a region adjacent to the region A in which the first through-contact TCT1 is disposed along the second direction SD, area utilization efficiency can be improved.

[0101] The three-dimensional memory device according to the embodiment of the present disclosure may be provided in a periphery-under-cell (PUC) structure or a periphery-on-cell (POC) structure.

[0102] Figure 12 and Figure 13 is a cross-sectional view of a three-dimensional memory device according to an embodiment of the present disclosure.

[0103] Reference Figure 12 The three-dimensional memory device according to the embodiment of the present disclosure may have a PUC structure. In detail, the three-dimensional memory device may include a first semiconductor structure 100 and a second semiconductor structure 200 built on the first semiconductor structure 100. That is, after the first semiconductor structure 100 is first formed, the second semiconductor structure 200 may be formed on the first semiconductor structure 100.

[0104] The second semiconductor structure 200 may include a memory cell array, and the first semiconductor structure 100 may include peripheral circuits that control the operation of the memory cell array. For example, the peripheral circuits may include, but are not limited to, a row decoder, a page buffer circuit, a voltage generator, and a control circuit.

[0105] The first semiconductor structure 100 may include a substrate 110 , a peripheral circuit 120 , an insulating layer 130 , a plurality of bottom interconnection layers UM1 to UM3 , and a plurality of bottom contacts UMC.

[0106] The substrate 110 may include at least one selected from the group consisting of a single crystal silicon layer, SOI (Silicon On Insulator), a silicon layer formed on a silicon germanium (SiGe) layer, a single crystal silicon layer formed on an insulating layer, and a polysilicon layer formed on an insulating layer.

[0107] The peripheral circuit 120 may include a transistor TR. The transistor TR may include a gate dielectric layer GI defined on the substrate 110, a gate electrode GE defined on the gate dielectric layer GI, and junction regions Jn1 and Jn2 formed by implanting impurity ions into active regions on both sides of the gate electrode GE. One of the junction regions Jn1 and Jn2 may serve as a source region of the transistor TR, and the other of the junction regions Jn1 and Jn2 may serve as a drain region of the transistor TR.

[0108] An insulating layer 130 may be disposed on the substrate 110 to cover the transistor TR.

[0109] The bottom interconnection layers UM1 to UM3 may be provided in the insulating layer 130. For example, the bottom interconnection layers UM1 to UM3 may include a first bottom interconnection layer UM1, a second bottom interconnection layer UM2 above the first bottom interconnection layer UM1, and a third bottom interconnection layer UM3 above the second bottom interconnection layer UM2. Figure 12The case where three bottom interconnection layers UM1 to UM3 are included is illustrated, but it should be noted that the present disclosure is not limited thereto. The number of bottom interconnection layers may be two or at least four.

[0110] A plurality of interconnect patterns may be provided in each of the bottom interconnect layers UM1 to UM3. The interconnect patterns of the bottom interconnect layers UM1 to UM3 may be configured to have characteristics that do not exhibit process defects (e.g., hillocks) at the highest temperature (hereinafter, referred to as the "process critical temperature") during the process of forming the memory cell array. In other words, as a material for the interconnect patterns of the bottom interconnect layers UM1 to UM3, a conductive material having heat-resistant characteristics at the process critical temperature may be used. For example, the interconnect patterns of the bottom interconnect layers UM1 to UM3 may include a material having a melting point higher than the process critical temperature, such as tungsten (W). Since the bottom interconnect layers UM1 to UM3 are formed before the memory cell array is formed, the interconnect patterns of the bottom interconnect layers UM1 to UM3 may be formed using a conductive material having a high resistivity but a high melting point.

[0111] The peripheral circuit 120 and the interconnection patterns of the bottom interconnection layers UM1 to UM3 may be connected to each other through bottom contacts UMC.

[0112] The second semiconductor structure 200 may be disposed on the insulating layer 130 of the first semiconductor structure 100. The second semiconductor structure 200 may include the above-mentioned Figures 1 to 11 A three-dimensional memory device is described.

[0113] The conductive contact plug DCC may pass through the insulating pattern 40 and the insulating layer 130 and may be connected to the interconnection pattern of the bottom interconnection layer UM3. The conductive contact plug DCC may be connected to the bottom of the second through-contact TCT2 and may connect the second through-contact TCT2 and the interconnection pattern of the bottom interconnection layer UM3.

[0114] Although not shown, a top interconnection may be defined on the second through-contact TCT2 and may be connected to the second through-contact TCT2. The second through-contact TCT2 may be connected to the row connection contact ( Figure 7 XCT) and can be connected to the row connection contacts ( Figure 7 The electrode layer 11 is connected to the XCT).

[0115] Reference Figure 13 , the three-dimensional memory device according to the embodiment of the present disclosure may have a POC structure. In other words, the first semiconductor structure 100A and the second semiconductor structure 200A may be manufactured on different wafers and then connected by bonding to each other.

[0116] Reference Figure 13 ,and Figure 12 Compared with the first semiconductor structure 100A, the first semiconductor structure 100A may further include a first bonding layer BNL1.

[0117] In detail, the first semiconductor structure 100A may include a substrate 110 , a peripheral circuit 120 defined on the substrate 110 , a first bonding layer BNL1 , and a plurality of bottom interconnection layers UM1 to UM3 disposed between the substrate 110 and the first bonding layer BNL1 .

[0118] An insulating layer 130 may be defined on the substrate 110 to cover the peripheral circuit 120. A plurality of bottom interconnection layers UM1 to UM3 may be provided in the insulating layer 130.

[0119] The interconnection patterns of the bottom interconnect layers UM1 to UM3 can include, for example, at least one of aluminum (Al) and copper (Cu). Because the interconnection patterns of the bottom interconnect layers UM1 to UM3 are formed on a wafer separate from the memory cell array, the material configuring the interconnection patterns of the bottom interconnect layers UM1 to UM3 can be selected without considering the thermal budget of the process used for the memory cell array. As the material configuring the interconnection patterns of the bottom interconnect layers UM1 to UM3, aluminum (Al), copper (Cu), or the like having low resistivity can be selected. This fact reduces the resistance of the interconnection patterns of the bottom interconnect layers UM1 to UM3.

[0120] The first bonding layer BNL1 may include a plurality of first bonding pads PBD and a first bonding insulation pattern 140 insulating the first bonding pads PBD from each other. A first bonding contact PBC may be defined between the first bonding layer BNL1 and the third bottom interconnection layer UM3 to connect the first bonding pads PBD and the interconnection pattern of the third bottom interconnection layer UM3.

[0121] and Figure 12 Compared with the second semiconductor structure 200A, the second semiconductor structure 200A may further include a second bonding layer BNL2, an insulating layer 50, and first and second top interconnection layers M1 and M2.

[0122] The second bonding layer BNL2 may include a plurality of second bonding pads CBD and a second bonding insulation pattern 210 insulating the second bonding pads CBD from each other.

[0123] The second bonding layer BNL2 of the second semiconductor structure 200A can be bonded to the first bonding layer BNL1 of the first semiconductor structure 100A in a face-to-face manner at a bonding interface BS. As a result of hybrid bonding (also known as direct bonding), the bonding interface BS can be configured between the first bonding layer BNL1 and the second bonding layer BNL2, and can simultaneously configure metal-metal bonding and dielectric-dielectric bonding. At the bonding interface BS, a plurality of first bonding pads PBD and a plurality of second bonding pads CBD can be bonded to each other to form a plurality of conductive bonds, and the first bonding insulation pattern 140 and the second bonding insulation pattern 210 can be bonded to each other to form an insulating bond.

[0124] The first top interconnect layer M1 may be disposed between the second bonding layer BNL2 and the stack STA. Although this embodiment illustrates a case where one top interconnect layer is disposed between the second bonding layer BNL2 and the stack STA, the present disclosure is not limited thereto. The number of top interconnect layers disposed between the second bonding layer BNL2 and the stack STA may be at least one. The second bonding pad CBD may be connected to the interconnect pattern of the first top interconnect layer M1 via a second bonding contact CBC.

[0125] An insulating layer 50 may be disposed on the source plate 30 and the insulating pattern 40. A second top interconnection layer M2 may be disposed in the insulating layer 50. A conductive contact plug DCC may pass through the insulating pattern 40 and the insulating layer 50 and may be connected to an interconnection pattern 60 of the second top interconnection layer M2.

[0126] Although not shown, external connection pads may be provided on the second top interconnect layer M2. The external connection pads may be connected to the first through-contact TCT1 via the interconnection pattern 60 and the conductive contact plug DCC of the second top interconnect layer M2, and may be connected to the peripheral circuit 120 via the interconnection pattern of the first top interconnect layer M1 connected to the first through-contact TCT1, the second bonding contact CBC, the second bonding pad CBD, the first bonding pad PBD, the first bonding contact PBC, the interconnection patterns of the bottom interconnect layers UM1 to UM3, and the bottom contact UMC. The first through-contact TCT1 may form an electrical path connecting the peripheral circuit 120 of the first semiconductor structure 100A and the external connection pads.

[0127] Although the exemplary embodiments of the present disclosure have been described for illustrative purposes, those skilled in the art will recognize that various modifications, additions, and substitutions are possible without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed above and in the accompanying drawings should be considered to be merely illustrative and not intended to limit the scope of the technology. The scope of the technology of the present disclosure is not limited by the embodiments and the accompanying drawings.

[0128] CROSS-REFERENCE TO RELATED APPLICATIONS

[0129] This application claims priority from Korean Patent Application No. 10-2023-0132335 filed on October 5, 2023, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A three-dimensional memory device, comprising: a first isolation pattern and a second isolation pattern, the first isolation pattern and the second isolation pattern extending in a first direction and adjacent to each other in a second direction crossing the first direction; a stack disposed between the first isolation pattern and the second isolation pattern, the stack including a connection region and an insulating region surrounded by the connection region, the connection region including a plurality of electrode layers and a plurality of interlayer insulating layers alternately stacked in a vertical direction; as well as a plurality of stepped recessed portions, the plurality of stepped recessed portions being configured in the insulating region and the connecting region and arranged along the first direction, At least one of the plurality of stepped recesses includes a first stepped structure connected to the first isolation pattern, a second stepped structure connected to the second isolation pattern, and a sidewall connecting the first stepped structure and the second stepped structure and disposed in the insulating region.

2. The three-dimensional memory device according to claim 1, wherein: The insulating regions are arranged in a single row in the stack.

3. The three-dimensional memory device according to claim 1, wherein: When viewed from the top, the insulating region has a line shape extending in the first direction.

4. The three-dimensional memory device according to claim 1, further comprising: A plurality of through contacts pass through the insulating region in the vertical direction and are arranged in at least two rows in the second direction.

5. The three-dimensional memory device according to claim 4, wherein: The through-contacts arranged in different rows are offset relative to each other in the first direction.

6. The three-dimensional memory device according to claim 1, wherein: The insulating area includes: a line portion extending in the first direction when viewed from the top; and A protrusion extending from the line portion toward at least one of the first isolation pattern and the second isolation pattern.

7. The three-dimensional memory device according to claim 6, wherein: The protrusion is provided in a region including a non-recessed region.

8. The three-dimensional memory device according to claim 6, wherein: The side wall is provided in the line portion.

9. The three-dimensional memory device according to claim 6, further comprising: a first through-contact, the first through-contact passing through the protrusion in the vertical direction; as well as A second through-contact passes through the line portion in the vertical direction.

10. The three-dimensional memory device according to claim 9, wherein: The first through-contact and the second through-contact are offset relative to each other in the first direction.

11. A three-dimensional memory device, the three-dimensional memory device comprising: a first semiconductor structure, the first semiconductor structure comprising a peripheral circuit; as well as a second semiconductor structure, the second semiconductor structure being disposed on the first semiconductor structure, The second semiconductor structure comprises: A source plate, the source plate being disposed on the first semiconductor structure; a first isolation pattern and a second isolation pattern, the first isolation pattern and the second isolation pattern being disposed on the source plate, extending in a first direction, and adjacent to each other in a second direction intersecting the first direction; a stack disposed between the first isolation pattern and the second isolation pattern and including a connection region and an insulating region surrounded by the connection region, the connection region including a plurality of electrode layers and a plurality of interlayer insulating layers alternately stacked in a vertical direction; and a plurality of stepped recessed portions, the plurality of stepped recessed portions being configured in the insulating region and the connecting region and arranged along the first direction, At least one of the plurality of stepped recesses includes a first stepped structure connected to the first isolation pattern, a second stepped structure connected to the second isolation pattern, and a sidewall connecting the first stepped structure and the second stepped structure and disposed in the insulating region.

12. The three-dimensional memory device according to claim 11, further comprising: a plurality of through-contacts, the plurality of through-contacts passing through the insulating region in the vertical direction, Wherein, the plurality of through contacts are arranged in at least two rows in the second direction.

13. The three-dimensional memory device according to claim 12, wherein: The through-contacts arranged in different rows are offset relative to each other in the first direction.

14. The three-dimensional memory device according to claim 12, in, The second semiconductor structure further comprises a plurality of external connection pads, Wherein, the plurality of through-contacts include: a plurality of first through-contacts connecting the plurality of external connection pads with the peripheral circuit; and a plurality of second through-contacts connecting the plurality of electrode layers and the peripheral circuit, and Wherein, the plurality of first through-contacts and the plurality of second through-contacts are arranged in different rows.

15. The three-dimensional memory device according to claim 14, wherein: The plurality of electrode layers include a main word line and a dummy word line, The plurality of second through-contacts include a main through-contact connected to the main word line, and The main through-contact is disposed in a region diagonally adjacent to a region in which the plurality of first through-contacts are disposed.

16. The three-dimensional memory device according to claim 15, wherein: The plurality of second through-contacts further include a dummy through-contact connected to the dummy word line, and The dummy through-contact is disposed in a region adjacent to a region in which the plurality of first through-contacts are disposed along the second direction.

17. A three-dimensional memory device, the three-dimensional memory device comprising: a first semiconductor structure having a peripheral circuit and a first bonding layer, the first bonding layer comprising a plurality of first bonding pads connected to the peripheral circuit; as well as a second semiconductor structure bonded to the first semiconductor structure, The second semiconductor structure comprises: a second bonding layer including a plurality of second bonding pads bonded to the plurality of first bonding pads; a first isolation pattern and a second isolation pattern, the first isolation pattern and the second isolation pattern being disposed on the second bonding layer, extending in a first direction, and adjacent to each other in a second direction crossing the first direction; a stack disposed between the first isolation pattern and the second isolation pattern and including a connection region and an insulating region surrounded by the connection region, the connection region including a plurality of electrode layers and a plurality of interlayer insulating layers alternately stacked in a vertical direction; and a plurality of stepped recessed portions, the plurality of stepped recessed portions being configured in the insulating region and the connecting region and arranged along the first direction, At least one of the plurality of stepped recesses includes a first stepped structure connected to the first isolation pattern, a second stepped structure connected to the second isolation pattern, and a sidewall connecting the first stepped structure and the second stepped structure and disposed in the insulating region.

18. The three-dimensional memory device according to claim 17, further comprising: a plurality of through-contacts, the plurality of through-contacts passing through the insulating region in the vertical direction, Wherein, the plurality of through contacts are arranged in at least two rows in the second direction.

19. The three-dimensional memory device according to claim 18, wherein: The through-contacts arranged in different rows are offset relative to each other in the first direction.

20. The three-dimensional memory device according to claim 18, wherein: The second semiconductor structure further includes an external connection pad, and At least one of the plurality of through-contacts connects the external connection pad and the peripheral circuit.

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