Transistors comprising two-dimensional materials and related microelectronic devices, memory devices and electronic systems

Abstract

The present application relates to transistors comprising two-dimensional materials, and to related microelectronic devices, memory devices, and electronic systems. The transistor includes a 2D material structure and a gate structure. The 2D material structure extends conformally on and between a surface of a dielectric fin structure extending in parallel in a first horizontal direction, and includes a source region, a drain region, and a channel region positioned between the source region and the drain region in the first horizontal direction. The gate structure covers the channel region of the 2D material structure and extends in a second horizontal direction orthogonal to the first horizontal direction. The gate structure is within a horizontal boundary of the channel region of the 2D material structure in the first horizontal direction.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the Chinese invention patent application with application number 202010836620.4, application date August 19, 2020, and invention name “Transistors containing two-dimensional materials and related microelectronic devices, memory devices and electronic systems”.

[0003] Priority claim

[0004] This application claims priority to U.S. patent application serial number 16 / 549,519, filed on August 23, 2019, entitled "Transistors comprising two-dimensional materials and related microelectronic devices, memory devices, and electronic systems." Technical Field

[0005] In various embodiments, the present disclosure relates generally to the field of microelectronic device design and fabrication. More specifically, the present disclosure relates to transistors containing two-dimensional (2D) materials, and to related microelectronic devices, memory devices, and electronic systems. Background Art

[0006] An ongoing goal of the microelectronics industry is to increase the memory density (e.g., the number of memory cells per memory die) of memory devices, such as nonvolatile memory devices (e.g., NAND flash memory devices). One way to increase memory density in nonvolatile memory devices is to utilize a vertical memory array (also referred to as a "three-dimensional (3D) memory array") architecture. Conventional vertical memory arrays include vertical memory strings that extend through openings in a layer of a conductive structure (e.g., a word line plate) and a dielectric material at each junction of the vertical memory string with the conductive structure. Such configurations allow a greater number of switching devices (e.g., transistors) to be located in a unit die area (i.e., the length and width of the active surface consumed) compared to structures with conventional planar (e.g., two-dimensional) arrangements of transistors by building the array upward (e.g., longitudinally, vertically) on the die.

[0007] Conventional vertical memory arrays include electrical connections between conductive structures and access lines (e.g., word lines) so that memory cells in the vertical memory array can be uniquely selected for write, read, or erase operations. One method of forming such electrical connections includes forming a so-called at least one "staircase" (or "rung") structure at an edge (e.g., a horizontal end) of a conductive structure layer. The staircase structure includes individual "steps" that define contact regions of the conductive structure, on which a conductive contact structure can be positioned to provide an electrical path to the conductive structure.

[0008] As vertical memory array technology has advanced, additional memory densities have been provided by forming vertical memory arrays to include additional layers of conductive structures, and thus additional stair structures and / or additional steps in individual stair structures associated therewith. However, increasing the number of layers of conductive structures of a stacked structure (and thus the number of stair structures and / or the number of steps in individual stair structures) without undesirably increasing the overall width (e.g., lateral footprint) of the stacked structure can result in complex and crowded routing paths to electrically connect the conductive structures to additional components of the memory device (e.g., string drivers). Such complex and crowded routing paths can impede (or even prevent) desired connection paths from and between other components of the memory device. Additionally, as the number of layers of conductive structures continues to increase, conventional locations and configurations of additional components of the memory device have become unable to support the increased number of additional components.

[0009] In view of the foregoing, there remains a need for new device (e.g., microelectronic devices, memory devices) configurations that facilitate increased memory density while alleviating problems (e.g., routing congestion, connectivity barriers) of conventional device configurations, and new electronic systems incorporating new device configurations. Summary of the invention

[0010] In some embodiments, the transistor includes a 2D material structure and a gate structure. The 2D material structure extends conformally on and between a surface of a dielectric fin structure extending in parallel in a first horizontal direction, and includes a source region, a drain region, and a channel region positioned between the source region and the drain region in the first horizontal direction. The gate structure covers the channel region of the 2D material structure and extends in a second horizontal direction orthogonal to the first horizontal direction. The gate structure is within a horizontal boundary of the channel region of the 2D material structure in the first horizontal direction.

[0011] In an additional embodiment, the microelectronic device includes a discrete dielectric structure, a non-planar 2D material structure, a gate structure, a conductive structure, a contact structure, and at least one additional contact structure. The discrete dielectric structure covers the isolation structure and is separated from each other by the filled trench. The non-planar 2D material structure extends above the surface of the isolation structure and the discrete dielectric structure inside and outside the filled trench, and includes a conductive doped region and a channel region between the conductive doped regions. The gate structure covers the channel region of the non-planar 2D material structure and is substantially aligned with it. The conductive structure extends from the gate structure into the trench. The contact structure is coupled to some of the conductive doped regions and extends into the isolation structure. The at least one additional contact structure is coupled to at least another of the conductive doped regions and extends away from the isolation structure.

[0012] In a further embodiment, a memory device includes a stacked structure, a ladder structure, a string driver transistor, at least one additional conductive structure, and a memory cell string. The stacked structure includes vertically alternating conductive structures and insulating structures arranged in layers. The ladder structure is at a horizontal end of the stacked structure. The ladder structure has a step including an edge of a layer. The string driver transistor vertically covers the ladder structure and includes a channel region, the channel region including at least one 2D material. The at least one additional conductive structure extends from and between the string driver transistor and one of the steps of the ladder structure. The memory cell string extends vertically through the stacked structure.

[0013] In yet another additional embodiment, an electronic system includes an input device, an output device, a processor device operably coupled to the input device and the output device, and a memory device operably coupled to the processor device. The memory device includes a stacked structure, a contact structure, a microelectronic device, and a vertically extending string of memory cells. The stacked structure has a layer including a conductive structure and an insulating structure vertically adjacent to the conductive structure, and includes a step region and a memory array region. The step region includes a step structure having a step, the step including a horizontal end of the layer. The memory array region is horizontally adjacent to the step region. The contact structure is on the step of the step structure. The microelectronic device is electrically coupled to the contact structure and includes a transistor vertically overlying and within a horizontal boundary of the step region of the stacked structure. Each of the transistors includes: a channel region including a 2D material; a conductive doped region adjacent to a relative horizontal boundary of the channel region and including the 2D material doped with at least one conductive dopant; and a gate structure vertically overlying and at least partially horizontally aligned with the channel region. The vertically extending string of memory cells is within the memory array region of the stacked structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1A is a simplified partial top view of a microelectronic device according to an embodiment of the present disclosure.

[0015] Figure 1B yes Figure 1A The microelectronic device shown in Figure 2A Simplified partial cross-sectional view of line AA depicted in .

[0016] Figure 1C yes Figure 1A The microelectronic device shown in Figure 2A Simplified partial cross-sectional view of line BB depicted in FIG.

[0017] Figure 2A According to an embodiment of the present disclosure, Figures 1A to 1C 0036] A simplified partial top view of a memory device of a microelectronic device shown in FIG.

[0018] Figure 2B yes Figure 2A The memory device shown in Figure 2A Simplified partial cross-sectional view of line AA depicted in .

[0019] Figure 2C yes Figure 2A The memory device shown in Figure 2A Simplified partial cross-sectional view of line BB depicted in FIG.

[0020] Figure 3 is a schematic block diagram illustrating an electronic system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] The following description provides specific details, such as material composition, shape and size, in order to provide a comprehensive description of the embodiments of the present disclosure. However, it will be understood by those skilled in the art that the embodiments of the present disclosure can be practiced without adopting these specific details. In fact, the embodiments of the present disclosure can be practiced in conjunction with conventional microelectronic device manufacturing techniques used in industry. In addition, the description provided below does not form a complete process flow for manufacturing microelectronic devices. The structure described below does not form a complete microelectronic device. Only those process actions and structures necessary for understanding the embodiments of the present disclosure are described in detail below. Additional actions to form a complete microelectronic device can be performed by conventional manufacturing techniques from the structure.

[0022] The drawings presented herein are for illustrative purposes only and are not meant to be actual views of any particular material, component, structure, device, or system. Changes in the shapes depicted in the drawings due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, the embodiments described herein should not be interpreted as being limited to the specific shapes or zones shown, but rather include shape deviations, for example, caused by manufacturing. For example, a box-shaped zone may have rough and / or nonlinear features, and a circular zone may include some rough and / or linear features. In addition, the acute angles shown may be rounded, and vice versa. Therefore, the zones shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the zones, and do not limit the scope of the present claims. The drawings do not have to be drawn to scale. In addition, elements shared between the drawings may retain the same numerical designations.

[0023] As used herein, "memory device" refers to and includes a microelectronic device that exhibits, but is not limited to, memory functionality.

[0024] As used herein, the terms "vertical", "longitudinal", "horizontal", and "transverse" are referenced to a principal plane of a structure and are not necessarily defined by the Earth's gravitational field. A "horizontal" or "transverse" direction is a direction substantially parallel to a principal plane of a structure, while a "vertical" or "longitudinal" direction is a direction substantially perpendicular to a principal plane of a structure. A principal plane of a structure is defined by a surface of the structure having a relatively large area compared to other surfaces of the structure.

[0025] As used herein, "vertically adjacent" or "longitudinally adjacent" features (e.g., regions, structures, devices) refer to and include features that are vertically closest (e.g., vertically closest) to each other. Additionally, as used herein, "horizontally adjacent" or "horizontally adjacent" features (e.g., regions, structures, devices) refer to and include features that are horizontally closest (e.g., horizontally closest) to each other.

[0026] As used herein, the term "pitch" refers to the distance between the same points in two adjacent features.

[0027] As used herein, spatially relative terms, such as "beneath," "below," "lower," "bottom," "above," "upper," "top," "front," "rear," "left," "right," and the like, may be used to describe the relationship of one element or feature to another, as shown in the figures. Unless otherwise indicated, spatially relative terms are intended to encompass different orientations of the material in addition to the orientation depicted in the figures. For example, if the material in the accompanying drawings is inverted, an element described as being "below" or "below" or "at the bottom" of other elements or features will be oriented as being "above" or "at the top" of the other elements or features. Thus, the term "below" may encompass both above and below orientations, depending on the context in which the term is used, as will be apparent to one of ordinary skill in the art. The material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatially relative descriptors used herein are interpreted accordingly.

[0028] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0029] As used herein, "and / or" includes any and all combinations of one or more of the associated listed items.

[0030] As used herein, the term "configured" refers to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device that facilitates operation of the one or more of the structure and the device in a predetermined manner.

[0031] As used herein, the phrase "coupled to" refers to structures that are operatively connected to each other, such as by a direct ohmic connection or electrically connected by an indirect connection (eg, through another structure).

[0032] As used herein, the term "substantially" refers to a given parameter, property, or condition and includes to the extent that one of ordinary skill in the art will understand that a given parameter, property, or condition satisfies a certain degree of variance, such as within an acceptable tolerance. For example, depending on the particular parameter, property, or condition that is substantially satisfied, the parameter, property, or condition may be satisfied by at least 90.0%, satisfied by at least 95.0%, satisfied by at least 99.0%, satisfied by at least 99.9%, or even satisfied by at least 100.0%.

[0033] As used herein, "about" or "approximately" a numerical value with respect to a particular parameter includes the numerical value, and the degree of deviation from the numerical value that will be understood by a person of ordinary skill in the art is within an acceptable tolerance for the particular parameter. For example, "about" or "approximately" a reference to a numerical value may include additional values ​​within the range of 90.0% to 110.0% of the numerical value, such as within the range of 95.0% to 105.0% of the numerical value, within the range of 97.5% to 102.5% of the numerical value, within the range of 99.0% to 101.0% of the numerical value, within the range of 99.5% to 100.5% of the numerical value, or within the range of 99.9% to 100.1% of the numerical value.

[0034] As used herein, the term "two-dimensional material" or "2D material" refers to and includes a crystalline material formed of and including a single (e.g., only one) monolayer or multiple (e.g., greater than or equal to two (2) layers) units (e.g., atoms, molecules) that are bound together by intramolecular forces (e.g., covalent bonds). In other words, a 2D material can be characterized as a crystalline material comprising about one or more monolayers bound together by intramolecular forces.

[0035] As used herein, the term "NMOS" transistor refers to and includes a so-called metal oxide transistor having a P-type channel region, an N-type channel region, or an I-type channel region. The gate of an NMOS transistor may include a conductive metal, another conductive material such as polysilicon, or a combination thereof. As used herein, the term "PMOS" transistor refers to and includes a so-called metal oxide transistor having a P-type channel region, an N-type channel region, or an I-type channel region. The gate of a PMOS transistor may include a conductive metal, another conductive material such as polysilicon, or a combination thereof. Therefore, the gate structure of such transistors may include a conductive material that is not necessarily a metal.

[0036] Figure 1A is a simplified partial top view of a microelectronic device 100 according to an embodiment of the present disclosure. Figure 1B yes Figure 1A A portion of the microelectronic device 100 shown in Figure 1A Simplified partial cross-sectional view of line AA depicted in . Figure 1C yes Figure 1A A portion of the microelectronic device 100 shown in Figure 1A BB is a simplified partial cross-sectional view of the line BB depicted in FIG. For clarity and ease of understanding of the drawings and the related description, not in Figures 1A to 1C All components (e.g., features, structures, devices) of the microelectronic device 100 depicted in one of the Figures 1A to 1C For example, some components of the microelectronic device 100 vertically overlap other components of the microelectronic device 100 that are not vertically overlapped. Figure 1A , in order to provide a clearer top view of the other components.

[0037] refer to Figure 1A , the microelectronic device 100 may include: a dielectric structure 104 covering the isolation structure 102; a 2D material structure 106 extending above and between the dielectric structure 104; a gate structure 118 covering a region (e.g., a channel region) of the 2D material structure 106; and a local contact structure 114 and a global contact structure 116 coupled to additional regions (e.g., a source region, a drain region) of the 2D material structure 106. As described in further detail below, the microelectronic device 100 may include in addition to Figure 1A Additional components (e.g., features, structures, regions, devices) beyond those depicted in .

[0038] The isolation structure 102 (eg, an interlayer dielectric (ILD) structure) may be formed of and include one or more dielectric materials, such as at least one dielectric oxide material (eg, silicon oxide (SiO x), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, aluminum oxide (AlO x ), hafnium oxide (HfO x ), niobium oxide (NbO x ), titanium oxide (TiO x ), zirconium oxide (ZrO x ), tantalum oxide (TaO x ) and magnesium oxide (MgO x ), at least one dielectric nitride material (e.g., silicon nitride (SiN y )), at least one dielectric oxynitride material (e.g., silicon oxynitride (SiO x N y )) and at least one dielectric carbonitride material (e.g., silicon carbonitride (SiO x C z N y )). A formula herein containing one or more of "x", "y", and "z" (e.g., SiO x 、AlO x , HfO x 、NbO x 、TiO x 、SiN y 、SiO x N y 、SiO x C z N y) represents a material containing an average ratio of "x" atoms of one element, "y" atoms of another element, and "z" atoms of an additional element (if any) for each atom of another element (e.g., Si, Al, Hf, Nb, Ti). Since the formula represents relative atomic ratios rather than strict chemical structures, the isolation structure 102 may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of "x", "y", and "z" (if any) may be integers or may be non-integers. As used herein, the term "non-stoichiometric compound" refers to and includes compounds having elemental compositions that cannot be represented by a ratio of clear natural numbers and violates definite proportional laws. The isolation structure 102 includes a substantially uniform distribution or a substantially non-uniform distribution of at least one dielectric material. As used herein, the term "uniform distribution" means that the relative amount of a material does not vary in different parts of the structure (e.g., different horizontal parts, different vertical parts). In contrast, as used herein, the term "non-uniform distribution" means that the relative amount of a material varies in different parts of the structure. In some embodiments, the isolation structure 102 presents a substantially uniform distribution of dielectric material. In further embodiments, isolation structure 102 exhibits a substantially non-uniform distribution of at least one dielectric material. Isolation structure 102 may, for example, be formed of and include a stack (e.g., a laminate) of at least two different dielectric materials. In some embodiments, isolation structure 102 is formed of and includes silicon dioxide (SiO2).

[0039] The dielectric structure 104 may present a first horizontal direction (eg, Figure 1A The term "parallel" as used herein means substantially parallel. In some embodiments, each dielectric structure 104 exhibits substantially the same size (e.g., in the X direction ( Figure 1A and 1C ) with substantially the same width W1 in the Y direction ( Figure 1A ) and the length L1 in the Z direction ( Figure 1C ) with substantially the same height H1), shape and spacing (e.g., in the X direction ( Figure 1A and 1C) on the 2D material structure 106. In additional embodiments, at least one dielectric structure 104 exhibits one or more of at least one different size (e.g., different length, different width, different height) and a different shape than one or more other dielectric structures 104, and / or the distance between at least one pair of horizontally adjacent dielectric structures 104 is different from the distance between at least another pair of horizontally adjacent dielectric structures 104. The size, shape, and spacing of the dielectric structures 104 can be selected to provide the 2D material structure 106 with a desired size and shape, as described in further detail below. As a non-limiting example, the dielectric structures 104 can each individually exhibit an aspect ratio (e.g., height H1 ( Figure 1C ) and width W1( Figure 1A and 1C ), and the ratio between the width W1 of each dielectric structure 104 and the distance D1 (e.g., spacing) between horizontally adjacent dielectric structures 104 may be in the range of about 0.1:1 to about 10:1. In some embodiments, each of the dielectric structures 104 exhibits a width W1 ( Figure 1A and 1C ), a height H1 in the range of about 10 nm to about 500 nm ( Figure 1C ) and the distance D1 between horizontally adjacent dielectric structures 104 ( Figure 1A and 1C ) is in the range of about 10 nm to about 100 nm.

[0040] The dielectric structure 104 may be formed of and include at least one dielectric material, such as at least one dielectric oxide material (e.g., SiO x , phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x 、NbO x 、TiO x 、ZrO x 、TaO x and MgO x one or more of the above), at least one dielectric nitride material (e.g., SiN y ), at least one dielectric oxynitride material (e.g., SiO x N y ) and at least one dielectric carbonitride material (e.g., SiO x C z N y). Each of the dielectric structures 104 may individually include a substantially uniform distribution or a substantially non-uniform distribution of at least one dielectric material. In some embodiments, each of the dielectric structures 104 presents a substantially uniform distribution of the dielectric material. In further embodiments, at least one of the dielectric structures 104 presents a substantially non-uniform distribution of at least one dielectric material. One or more dielectric structures 104 may, for example, be formed of and include a stack (e.g., a laminate) of at least two different dielectric materials. In some embodiments, each of the dielectric structures 104 is formed of and includes aluminum oxide (Al2O3). For example, each of the dielectric structures 104 may include crystalline Al2O3 having a hexagonal crystal structure or a rhombohedral crystal structure.

[0041] Common Reference Figure 1A and 1C , the 2D material structure 106 may be formed on or above the surface (eg, upper surface, side surface) of the isolation structure 102 and the dielectric structure 104. Figure 1C As shown in , the 2D material structure 106 may be at least partially (e.g., substantially) conformal to a topography defined by a surface (e.g., upper surface, side surface) on which the 2D material structure 106 is formed. The 2D material structure 106 may extend (e.g., continuously extend) above the surfaces (e.g., upper surface, side surface) of the isolation structure 102 and the dielectric structure 104. The 2D material structure 106 partially (e.g., less than completely) fills a trench (e.g., an opening) horizontally sandwiched between the dielectric structures 104 (e.g., in the X direction). The 2D material structure 106 may be formed to a desired thickness T1, at least partially depending on the horizontal distance between horizontally adjacent dielectric structures 104 (e.g., in the X direction). For example, the 2D material structure 106 may exhibit a thickness T1 of less than or equal to about 10 nanometers (nm), such as less than or equal to about 8 nm, less than or equal to about 6 nm, or less than or equal to about 4 nm. In some embodiments, the thickness T1 of the 2D material structure 106 is in a range from about 1 nm to about 4 nm.

[0042] The 2D material structure 106 may be formed of and include one or more of a transition metal dichalcogenide (TMDC) having a general chemical formula MX2, where M is a transition metal (e.g., molybdenum (Mo), tungsten (W), niobium (Nb), zirconium (Zr), hafnium (Hf), rhenium (Re), platinum (Pt), titanium (Ti), tantalum (Ta), vanadium (V), cobalt (Co), cadmium (Cd), chromium (Cr)) and X is a chalcogen element (e.g., sulfur (S), selenium (Se), tellurium (Te)); a carbide or carbonitride having a general chemical formula M n+1 X n (also referred to as "MXene") and comprising oxygen (-O), hydroxyl (-OH) or fluorine (-F) surface terminations, wherein M is a transition metal from Group IV or V of the Periodic Table (e.g., Ti, Hf, Zr, V, Nb, Ta), and X is selected from carbon (C) and nitrogen (N); graphene; graphene oxide; stanene; phosphine; hexagonal boron nitride (h-BN); borographene; silicene; graphene; germanene; germanane; 2D supercrystals; and monolayers of semiconductor materials. In some embodiments, the 2D material structure 106 includes one or more TMDC monolayers, such as one or more monolayers of one or more of tungsten sulfide (WS2), tungsten selenide (WSe2), tungsten telluride (WTe2), molybdenum sulfide (MoS2), molybdenum selenide (MoSe2), molybdenum telluride (MoTe2), niobium sulfide (NbS2), niobium selenide (NbSe2), niobium telluride (NbTe2), zirconium sulfide (ZrS2), zirconium selenide (ZrSe2), zirconium telluride (ZrTe2), hafnium sulfide (HfS2), hafnium selenide (HfSe2), hafnium telluride (ZrTe2), rhenium sulfide (ReS2), rhenium selenide (ReSe2), and rhenium telluride (ReTe2). In some embodiments, the 2D material structure 106 has an electron mobility of about 10 square centimeters per volt second (cm2). 2 / V·s) to about 400cm 2 / V·s range (for example, within about 150cm 2 / V·s to about 400cm 2 / V·s, for example, about 150cm 2 / V·s to about 200cm 2 / V·s), and a band gap in the range of about 1.2 electron volts (eV) to about 2.5 eV (e.g., in the range of about 1.8 eV to about 2.5 eV). As non-limiting examples, the 2D material structure 106 may include one or more of WS2, WSe2, MoS2, and MoSe2. In some embodiments, the 2D material structure 106 is WSe2. In additional embodiments, the 2D material structure 106 is WS2. In further embodiments, the 2D material structure 106 is MoSe2.

[0043] refer to Figure 1B , the 2D material structure 106 can be formed to include a channel region 108, a first conductive doping region 110, and a second conductive doping region 112. Each of the channel regions 106 of the 2D material structure 108 can be individually (e.g., in the Y direction) horizontally sandwiched between a pair of (e.g., two (2)) first conductive doping regions 110, and each pair of first conductive doping regions 110 can be individually (e.g., in the Y direction) horizontally sandwiched between a pair of (e.g., two (2)) second conductive doping regions 112. As described in further detail below, the first conductive doping region 110 can be used as an offset region (e.g., a lateral double diffusion (LDD) offset region) to horizontally offset the first conductive doping region 110 from the gate structure 118, and the second conductive doping region 112 can be used as a source region and a drain region of a transistor (e.g., a driver transistor such as a string driver transistor) that includes the gate structure 118, the channel region 108, the first conductive doping region 110, and the second conductive doping region 112. As a non-limiting example, as Figure 1B , the second conductive doping region 112 may include a source region 112A and a drain region 112B. Each source region 112A may be horizontally separated from a drain region 112B that is closest thereto (e.g., in the Y direction) by two (2) first conductive doping regions 110 and one of the channel regions 108 between the two (2) first conductive doping regions 110. A single (e.g., only one) source region 112A may be shared by two (2) horizontally adjacent transistors of the microelectronic device 100.

[0044] The first conductive doping region 110 and the second conductive doping region 112 (e.g., source region 112A, drain region 112B) of the 2D material structure 106 may be doped with any desired dopant. In some embodiments, the first conductive doping region 110 and the second conductive doping region 112 are doped with at least one N-type dopant (e.g., one or more of phosphorus, arsenic, antimony, and bismuth), and the first conductive doping region 110 is doped to present relatively fewer free electrons than the second conductive doping region 112. For example, the first conductive doping region 110 may include N - region, and the second conductive doping region 112 may include N + In some such embodiments, the channel region 108 is doped with at least one P-type dopant (e.g., one or more of boron, aluminum, and gallium). In additional embodiments, the first conductive doping region 110 and the second conductive doping region 112 are doped with at least one P-type dopant (e.g., one or more of boron, aluminum, and gallium), and the first conductive doping region 110 is doped to exhibit a relatively less valence electron deficiency (commonly referred to as "holes") than the second conductive doping region 112. For example, the first conductive doping region 110 may include a P- region, and the second conductive doping region 112 may include P + In some such embodiments, the channel region 108 is doped with at least one N-type dopant (e.g., one or more of phosphorus, arsenic, antimony, and bismuth). In further embodiments, one or more of the first conductive doping region 110 and the second conductive doping region 112 of the 2D material structure 106 are substantially undoped. For example, the characteristics of the 2D material structure 106 (e.g., 2D material composition) may allow one or more of the first conductive doping region 110 and the second conductive doping region 112 to include an I-type region.

[0045] Continue to refer Figure 1B , the local contact structure 114 and the global contact structure 116 can contact (e.g., electrically contact, physically contact) the second conductive doping region 112 of the 2D material structure 106. For example, the local contact structure 114 can physically contact the drain region 112B of the 2D material structure 106, and the global contact structure 116 can physically contact the source region 112A of the 2D material structure 106. The local contact structure 114 can be formed to extend vertically downward from the drain region 112B of the 2D material structure 106 (e.g., in the negative Z direction) and through the isolation structure 102 below the 2D material structure 106; the global contact structure 116 can be formed to extend vertically upward from the source region 112A of the 2D material structure 106 (e.g., in the positive Z direction). As Figure 1B, in some embodiments, the local contact structure 114 is formed to extend vertically downward from an upper boundary of the drain region 112B of the 2D material structure 106, such that the local contact structure 114 extends vertically through the drain region 112B of the 2D material structure 106; and the global contact structure 116 is formed to extend vertically upward from an upper boundary of the source region 112A of the 2D material structure 106. In additional embodiments, the local contact structure 114 is formed to extend vertically downward from a lower boundary of the drain region 112B of the 2D material structure 106, such that the local contact structure 114 does not extend vertically through the drain region 112B of the 2D material structure 106; and / or the global contact structure 116 is formed to extend vertically upward from a lower boundary of the source region 112A of the 2D material structure 106, such that the global contact structure 116 extends vertically through the source region 112A of the 2D material structure 106. As described in further detail below, the local contact structure 114 can electrically connect the 2D material structure 106 of the microelectronic device 100 to additional structures (e.g., additional conductive structures, such as conductive line structures and / or additional conductive contact structures) and / or devices vertically located below the microelectronic device 100; and the global contact structure 116 can electrically connect the 2D material structure 106 of the microelectronic device 100 to additional structures and / or devices vertically covering the microelectronic device 100. In additional embodiments, the local contact structure 114 and / or the global contact structure 116 physically contacts the first conductive doping region 110 of the 2D material structure 106 but not the second conductive doping region 112. In further embodiments, the local contact structure 114 and / or the global contact structure 116 physically contacts the first conductive doping region 110 and the second conductive doping region 112 of the 2D material structure 106.

[0046] The local contact structure 114 and the global contact structure 116 may each be individually formed of and include at least one conductive material, such as at least one metal (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)); at least one alloy (e.g., C The local contact structure 114 and the global contact structure 116 may include one or more of an electrically conductive material (e.g., an electrically conductive metal nitride, an electrically conductive metal silicide, an electrically conductive metal carbide, an electrically conductive metal oxide) and an electrically conductive material (e.g., an electrically conductive metal nitride, an electrically conductive metal silicide, an electrically conductive metal carbide, an electrically conductive metal oxide). The local contact structure 114 and the global contact structure 116 may include a substantially uniform distribution of the electrically conductive material, or may include a substantially non-uniform distribution of the electrically conductive material. If one or more of the local contact structures 114 and the global contact structures 116 present a substantially non-uniform distribution of the conductive material, the amount of the conductive material may change stepwise (e.g., abruptly) throughout different portions of the one or more of the local contact structures 114 and the global contact structures 116, or may change continuously (e.g., gradually, such as linearly, parabolically). In some embodiments, the local contact structures 114 and the global contact structures 116 each individually present a substantially uniform distribution of the conductive material. In additional embodiments, at least one of the local contact structures 114 and at least one of the global contact structures 116 present a substantially non-uniform distribution of at least one conductive material. For example, at least one of the local contact structures 114 and at least one of the global contact structures 116 may be formed of and include a stack of at least two different conductive materials.

[0047] Common Reference Figure 1A and 1B , the gate structure 118 may vertically cover (eg, in the Z direction) the channel region 108 of the 2D material structure 106 ( Figure 1B ), and may be present in the dielectric structure 104 ( Figure 1A ) extending in a first horizontal direction (eg, the Y direction) orthogonal to a second horizontal direction (eg, the X direction ( Figure 1A)) in a horizontally elongated shape (e.g., an elliptical shape, a rectangular shape) extending parallel to the 2D material structure 106. The gate structure 118 can be substantially horizontally aligned with the channel region 108 of the 2D material structure 106 (e.g., in the Y direction). Each of the gate structures 118 can be individually horizontally sandwiched (e.g., in the Y direction) between one of the source regions 112A of the 2D material structure 106 and one of the drain regions 112B of the 2D material structure 106 that is most horizontally close (e.g., in the Y direction) to one of the source regions 112A. The gate structures 118 can each present substantially the same size as each other (e.g., a width W2 in the Y direction ( Figure 1A and 1B ), length in the X direction ( Figure 1A ) and the height H2 in the Z direction ( Figure 1B and 1C )) and shape. In some embodiments, each of the gate structures 118 has a width W2 of about 18.5 micrometers (μm), and a distance D2 ( Figure 1A and 1B ) is about 30.5μm.

[0048] The gate structure 118 may be formed of and include at least one conductive material, such as one or more of at least one metal (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al), at least one alloy (e.g., Co-based alloy, Fe-based alloy, Ni-based alloy, Fe and Ni-based alloy, Co and Ni-based alloy, Fe and Co-based alloy, Co- and Ni- and Fe-based alloy, Al-based alloy, Cu-based alloy, magnesium (Mg)-based alloy, Ti-based alloy, steel, mild steel, stainless steel), at least one conductive doped semiconductor material (e.g., conductive doped polysilicon, conductive doped Ge, conductive doped SiGe), and at least one conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). The gate structure 118 may include a substantially uniform distribution of the conductive material, or may include a substantially non-uniform distribution of the conductive material. If the gate structures 118 present a substantially non-uniform distribution of the conductive material, the amount of the conductive material may vary stepwise (e.g., abruptly) throughout different portions of the gate structures 118, or may vary continuously (e.g., gradually, e.g., linearly, parabolically). In some embodiments, each gate structure 118 presents a substantially uniform distribution of the conductive material. In additional embodiments, one or more (e.g., each) gate structures 118 present a substantially non-uniform distribution of at least one conductive material. One or more of the gate structures 118 may, for example, be formed of and include a stack of at least two different conductive materials.

[0049] refer to Figure 1C , the microelectronic device 100 may further include a conductive structure 120 extending vertically (e.g., in the Z direction) from the gate structure 118 toward the channel region 108 of the 2D material structure 106. The conductive structure 120 can effectively serve as a protrusion or extension of the gate structure 118 to accommodate the non-planar structure of the 2D material structure 106 achieved by the combined topography of the dielectric structure 104 and the isolation structure 102. The conductive structure 120 can be horizontally sandwiched (e.g., in the X direction) between horizontally adjacent dielectric structures 104. The conductive structure 120 partially (e.g., less than completely fills) a portion of a trench (e.g., an opening) horizontally sandwiched between the dielectric structures 104 (e.g., a portion of the trench not occupied by the 2D material structure 106) (e.g., in the X direction). The conductive structure 120 can be formed to any desired size, depending at least in part on the size of the dielectric structure 104 (e.g., the Y direction ( Figure 1A ) in width, size (e.g., X direction ( Figure 1C) width, Z direction ( Figure 1C )) and spacing (e.g., X direction ( Figure 1C )) and the size (eg, thickness) of the 2D material structure 106. The conductive structures 120 may each be individually Figure 1A ) shows a difference with the gate structure 118 in the Y direction ( Figure 1A ) have substantially the same width in the Z direction ( Figure 1C ) shows a height H3 and in the X direction ( Figure 1C ) presents a thickness T2, thereby allowing all portions of the conductive structure 120 that are proximate to the 2D material structure 106 in the X-direction and the Z-direction to be substantially equally offset (e.g., spaced apart).

[0050] The conductive structure 120 may be formed of and include at least one conductive material, such as at least one metal (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al), at least one alloy (e.g., Co-based alloy, Fe-based alloy, Ni-based alloy, Fe and Ni-based alloy, Co and Ni-based alloy, Fe and Co-based alloy, Co- and Ni- and Fe-based alloy, Al-based alloy, Cu-based alloy, magnesium (Mg)-based alloy, Ti-based alloy, steel, low carbon steel, stainless steel), at least one conductive doped semiconductor material (e.g., conductive doped polysilicon, conductive doped Ge, conductive doped SiGe), and at least one conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). The conductive structure 120 may include a substantially uniform distribution of the conductive material, or may include a substantially non-uniform distribution of the conductive material. If the conductive structures 120 present a substantially non-uniform distribution of the conductive material, the amount of the conductive material may vary stepwise (e.g., abruptly) in different portions of the conductive structures 120, or may vary continuously (e.g., gradually, e.g., linearly, parabolically). In some embodiments, each conductive structure 120 presents a substantially uniform distribution of the conductive material. In additional embodiments, one or more (e.g., each) conductive structures 120 present a substantially non-uniform distribution of at least one conductive material. One or more of the conductive structures 120 may, for example, be formed by and include a stack of at least two different conductive materials. The material composition of the conductive structures 120 may be substantially the same as the material composition of the gate structure 118, or the material composition of the conductive structures 120 may be different from the material composition of the gate structure 118. In some embodiments, the material composition of the conductive structures 120 is substantially the same as the material composition of the gate structure 118.

[0051] Continue to refer Figure 1C , the microelectronic device 100 may further include a gate dielectric material 122 positioned between the 2D material structure 106 and the gate structure 118 and the conductive structure 120 (e.g., horizontally located therebetween, vertically located therebetween). The gate dielectric material 122 may extend from a boundary (e.g., horizontal boundary, vertical boundary) of the 2D material structure 106 to an opposing boundary (e.g., horizontal boundary, vertical boundary) of the gate structure 118 and the conductive structure 120. The gate dielectric material 122 may fill the remaining portion of the trench (e.g., opening) horizontally sandwiched between the dielectric structures 104 (e.g., the portion of the trench not occupied by the 2D material structure 106 and the conductive structure 120) (e.g., in the X direction). The gate dielectric material 122 may be formed to a desired thickness T3, which depends at least in part on the size of the gate structure 118 (e.g., the width W2 ( Figure 1A )); the size of the conductive structure 120 (eg, width W2 ( Figure 1A )、Height H3( Figure 1C )); the size of the dielectric structure 104 (eg, width W1 ( Figure 1C )、Height H2( Figure 1C )) and spacing (e.g., distance D1 ( Figure 1C )); the size of the 2D material structure 106 (e.g., thickness T1 ( Figure 1C )); and the distance between the upper surface of the dielectric structure 104 and the lower surface of the gate structure 118 (eg, in the Z direction ( Figure 1C )). As a non-limiting example, the gate dielectric material 122 can be formed to have a thickness T3 of less than or equal to about 15 nm, such as less than or equal to about 10 nm, less than or equal to about 8 nm, or less than or equal to about 5 nm. In some embodiments, the gate dielectric material 122 has a thickness T3 in the range of about 5 nm to about 10 nm.

[0052] The gate dielectric material 122 may be formed of and include at least one dielectric material, such as at least one oxide dielectric material (eg, SiO x 、AlO x , one or more of phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass), at least one nitride dielectric material (e.g., SiN y ) and at least one low-K dielectric material (e.g., silicon oxycarbide (SiO x C y ), silicon oxynitride (SiO x N y ), hydrogenated silicon oxycarbide (SiC x O y Hz ) and silicon oxycarbide (SiO x C z N y ). The gate dielectric material 122 may include a substantially uniform distribution or a substantially non-uniform distribution of at least one dielectric material. In some embodiments, the gate dielectric material 122 exhibits a substantially uniform distribution of the dielectric material. In further embodiments, the gate dielectric material 122 exhibits a substantially non-uniform distribution of at least one dielectric material. In some embodiments, the gate dielectric material 122 is formed of and includes SiO2.

[0053] refer to Figure 1B , the gate structure 118, the gate dielectric material 122, and the channel region 108 of the 2D material structure 106 and the first conductive doped region 110 (including the source region 112A and the drain region 112B) and the channel region 108 can form a transistor 124 (e.g., a driver transistor such as a string driver transistor) of the microelectronic device 100. Each of the transistors 124 can include one of the gate structures 118, the gate dielectric material 122, one of the channel region 108 of the 2D material structure 106, one of the drain region 112B of the 2D material structure 106, and one of the source region 112A of the 2D material structure 106. Each of the transistors 124 also includes a conductive structure 120 ( Figure 1C ). In some embodiments, transistor 124 includes a high voltage (HV) transistor (e.g., an HVNMOS transistor, an HVPMOS transistor). The HV transistor operates at a voltage higher than a non-HV transistor (e.g., an NMOS transistor, a PMOS transistor). For example, the HV transistor may have a threshold voltage greater than a threshold voltage range of a non-HV transistor (e.g., about +0.5V to about +0.7V), such as a threshold voltage greater than or equal to about +3V higher than the threshold voltage range of the non-HV transistor. For example, if the first conductive doped region 110 of the 2D material structure 106 is doped with at least one N-type dopant, transistor 124 includes a HVNMOS transistor. As another example, if the first conductive doped region 110 of the 2D material structure 106 is doped with at least one P-type dopant, transistor 124 includes a HVPMOS transistor.

[0054] The non-planar topography of the 2D material structure 106 (eg, the isolation structure 102 and the dielectric structure 104 on which the 2D material structure 106 is formed) Figure 1A and 1C) surface definition) provides a so-called "folded channel" configuration for transistor 124. The folded channel configuration of transistor 124 can provide transistor 124 with a larger effective channel width than a conventional transistor that does not exhibit the folded channel structure of the present disclosure (e.g., a conventional transistor that exhibits a substantially planar channel configuration). In addition, the material composition of the 2D material structure 106 can provide the channel region 108 of transistor 124 with a higher bandgap and comparable (or greater) electron mobility than a conventional transistor that employs a semiconductor material such as silicon and polysilicon as its channel region. Therefore, the 2D material structure 106 can promote more favorable electrical characteristics (e.g., a relatively high on-state current (I on ), relatively low shutdown current (I off ), relatively faster switching speed, improved off-state voltage (BV), relatively lower operating voltage, relatively reduced current leakage, relatively less scattering at the interface between the channel region 108 and the gate dielectric material 122). In addition, the 2D material structure 106 can be formed at a relatively low temperature (e.g., a temperature less than or equal to about 600° C., such as a temperature in the range of about 400° C. to about 600° C., or less than or equal to about 400° C.) to reduce or eliminate temperature incompatibility with other structures and / or devices below the microelectronic device 100.

[0055] Therefore, according to an embodiment of the present disclosure, a transistor includes a 2D material structure and a gate structure. The 2D material structure extends conformally on and between the surfaces of the dielectric fin structure extending in parallel in a first horizontal direction, and includes a source region, a drain region, and a channel region positioned between the source region and the drain region in the first horizontal direction. The gate structure covers the channel region of the 2D material structure and extends in a second horizontal direction orthogonal to the first horizontal direction. The gate structure is within the horizontal boundary of the channel region of the 2D material structure in the first horizontal direction.

[0056] In addition, according to additional embodiments of the present disclosure, a microelectronic device includes a discrete dielectric structure, a non-planar 2D material structure, a gate structure, a conductive structure, a contact structure, and at least one additional contact structure. The discrete dielectric structure covers the isolation structure and is separated from each other by the filled trench. The non-planar 2D material structure extends above the surface of the isolation structure and the discrete dielectric structure inside and outside the filled trench, and includes a conductive doped region and a channel region between the conductive doped regions. The gate structure covers the channel region of the non-planar 2D material structure and is substantially aligned with it. The conductive structure extends from the gate structure into the trench. The contact structure is coupled to some of the conductive doped regions and extends into the isolation structure. The at least one additional contact structure is coupled to at least another of the conductive doped regions and extends away from the isolation structure.

[0057] In additional embodiments, the 2D material structure 106 can be formed to be substantially planar (e.g., substantially horizontally planar) such that a transistor including the 2D material structure 106 exhibits a substantially planar (e.g., non-folded) channel configuration. In such embodiments, the dielectric structure 104 ( Figure 1A and 1C ), so that the 2D material structure 106 extends substantially continuously horizontally on the substantially planar upper surface of the isolation structure 102 (the 2D material structure 106 formed thereby is also substantially planar); the conductive structure 120 ( Figure 1C ) may also be omitted. Although such planar configurations of the channel region of the transistor may present a smaller effective channel width than the channel region 108 of the transistor 124, the material composition of the 2D material structure 106 may still impart improved electrical characteristics to the transistor compared to conventional transistors using semiconductor materials such as silicon and polysilicon for their channel regions.

[0058] and Figures 1A to 1C The microelectronic device 100 is depicted as including a single (eg, only one) 2D material structure 106 and two (2) transistors 124 ( Figure 1B ); the microelectronic device 100 may include an additional 2D material structure 106 and an additional transistor 124 including a portion of the additional 2D material structure 106. For example, the microelectronic device 100 may include a plurality of (e.g., more than one) 2D material structures 106 that are substantially similar to each other and spaced apart from each other on the isolation structure 102. Each of the plurality of 2D material structures 106 may individually form a portion of a transistor 124 of the microelectronic device 100 (e.g., a channel region 108, a source region 112A, a drain region 112B), and the source region 112A ( Figure 1B ) and the drain region 112B ( Figure 1B In addition, the microelectronic device 100 may include additional local contact structures 114 and additional global contact structures 116, which are similar to those previously described with reference to Figures 1A to 1C Substantially the same manner as described is operably associated with additional 2D material structures 106 and additional transistors 124. The number, configuration, and arrangement of additional 2D material structures 106, additional transistors 124, additional local contact structures 114, and additional global contact structures 116 of the microelectronic device 100 can depend on the number, configuration, and arrangement of additional structures and / or devices operably associated with the microelectronic device 100, as described in further detail below.

[0059] According to the microelectronic device of the embodiment of the present disclosure (for example, the previously referenced Figures 1A to 1C The microelectronic device 100 described above can be used in embodiments of the memory device of the present disclosure. For example, Figure 2A is a simplified partial top view of a memory device 200 (eg, a 3D NAND flash memory device) that includes the previously referenced Figures 1A to 1C One or more embodiments of a microelectronic device 100 are described. Figure 2B yes Figure 2A A portion of the memory device 200 shown in FIG. Figure 2A Simplified partial cross-sectional view of line AA depicted in FIG. Figure 2C yes Figure 2A A portion of the memory device 200 shown in FIG. Figure 2A BB is a simplified partial cross-sectional view of the line BB depicted in FIG. For clarity and ease of understanding of the drawings and related descriptions, not Figures 2A to 2C All components (e.g., features, structures, devices) of the memory device 200 depicted in one of the Figures 2A to 2C For example, some components of memory device 200 vertically overlap other components of memory device 200 that are not depicted in FIG. Figure 2A , in order to provide a clearer top view of the other components.

[0060] like Figure 2B and 2C As shown in FIG. 1 , the microelectronic device 100 of the memory device 200 (including the previously referenced Figures 1A to 1C The stacked structure 202 includes a vertically alternating (e.g., in the Z direction) sequence of conductive structures 204 (e.g., access line plates, word line plates) and insulating structures 206 arranged in a layer 208. In addition, as shown in FIG. Figure 2A and 2C, the stacked structure 202 includes a memory array region 202A and a staircase region 202B horizontally adjacent (e.g., in the X direction) to a first horizontal boundary of the memory array region 202A. As described in further detail below, the memory device 200 further includes additional components (e.g., features, structures, devices) within the horizontal boundaries of different regions (e.g., the memory array region 202A and the staircase region 202B) of the stacked structure 202.

[0061] Common Reference Figure 2B and 2C , the layers 208 of the stacked structure 202 of the memory device 200 may each individually include at least one of the conductive structures 204 vertically adjacent to at least one of the insulating structures 206. The stacked structure 202 may include a desired number of layers 208. For example, the stacked structure 202 may include greater than or equal to ten (10) layers 208, greater than or equal to twenty-five (25) layers 208, greater than or equal to fifty (50) layers 208, greater than or equal to one hundred (100) layers 208, greater than or equal to one hundred and fifty (150) layers 208, or greater than or equal to two hundred (200) layers 208 of conductive structures 204 and insulating structures 206.

[0062] The conductive structure 204 of the layer 208 of the stacked structure 202 may be formed of and include at least one conductive material, such as one or more of at least one metal (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al), at least one alloy (e.g., Co-based alloys, Fe-based alloys, Ni-based alloys, Fe and Ni-based alloys, Co and Ni-based alloys, Fe and Co-based alloys, Co-, Ni- and Fe-based alloys, Al-based alloys, Cu-based alloys, magnesium (Mg)-based alloys, Ti-based alloys, steel, low carbon steel, stainless steel), at least one conductive doped semiconductor material (e.g., conductive doped polysilicon, conductive doped Ge, conductive doped SiGe), and at least one conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, the conductive structures 204 are formed of and include a metallic material (e.g., a metal such as W; an alloy). In additional embodiments, the conductive structures 204 are formed of and include conductively doped polysilicon. Each of the conductive structures 204 may individually include a substantially uniform distribution of at least one conductive material, or a substantially non-uniform distribution of at least one conductive material. In some embodiments, each of the conductive structures 204 of each of the layers 208 of the stacked structure 202 presents a substantially uniform distribution of the conductive material. In additional embodiments, at least one of the conductive structures 204 of at least one of the layers 208 of the stacked structure 202 presents a substantially non-uniform distribution of at least one conductive material. The conductive structures 204 may, for example, be formed of and include a stack of at least two different conductive materials. The conductive structures 204 of each of the layers 208 of the stacked structure 202 may each be substantially planar, and may each present a desired thickness.

[0063] The insulating structure 206 of the layer 208 of the stacked structure 202 may be formed of and include at least one dielectric material, such as at least one dielectric oxide material (eg, SiO x , phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x 、NbO x 、TiO x 、ZrO x 、TaO x and MgO x one or more of the above), at least one dielectric nitride material (e.g., SiN y), at least one dielectric oxynitride material (e.g., SiO x N y ) and at least one dielectric carbonitride material (e.g., SiO x C z N y ). In some embodiments, the insulating structure 206 is formed of and includes SiO2. Each of the insulating structures 206 may individually include a substantially uniform distribution of at least one insulating material, or a substantially non-uniform distribution of at least one insulating material. In some embodiments, each of the insulating structures 206 of each of the layers 208 of the stacked structure 202 presents a substantially uniform distribution of the insulating material. In additional embodiments, at least one of the insulating structures 206 of at least one of the layers 208 of the stacked structure 202 presents a substantially non-uniform distribution of at least one insulating material. The insulating structure 206 may, for example, be formed of and include a stack (e.g., a laminate) of at least two different insulating materials. The insulating structures 206 of each of the layers 208 of the stacked structure 202 may each be substantially planar and may each individually present a desired thickness.

[0064] At least one lower conductive structure 204 of the stacked structure 202 may be used as at least one lower select gate (e.g., at least one source-side select gate (SGS)) of the memory device 200. In some embodiments, a single (e.g., only one) conductive structure 204 of the vertically lowermost layer 208 of the stacked structure 202 is used as a lower select gate (e.g., SGS) of the memory device 200. In addition, the upper conductive structure 202 of the stacked structure 204 may be used as an upper select gate (e.g., drain-side select gate (SGD)) of the memory device 200. In some embodiments, the horizontally adjacent conductive structures 204 of the vertically uppermost layer 208 of the stacked structure 202 are used as upper select gates (e.g., SGD) of the memory device 200.

[0065] refer to Figure 2A and 2B , the stacked structures 202 can be separated by the filled slots 210 in the Y direction. The filled slots 210 can, for example, extend vertically (eg, in the Z direction ( Figure 2B ) completely through the stacked structure 202. The filled slots 210 may divide the stacked structure 202 into a plurality of blocks 212 (eg, in the Y direction). Figure 2B As shown in FIG. 2 , the filled trenches 210 may each be individually filled with at least one dielectric structure 214. The dielectric structure 214 may be formed of at least one dielectric material and include at least one dielectric material, such as at least one dielectric oxide material (e.g., SiOx , phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x 、NbO x 、TiO x 、ZrO x 、TaO x and MgO x one or more of the above), at least one dielectric nitride material (e.g., SiN y ), at least one dielectric oxynitride material (e.g., SiO x N y ) and at least one dielectric carbonitride material (e.g., SiO x C z N y ) In some embodiments, the dielectric structure 214 includes SiO2. Before being filled with the dielectric structure 214 to become the filled trench 210, for example, a preliminary trench may be used to form the conductive structure 204 ( ) of the stacked structure 202 by a so-called "replacement gate" or "last gate" processing action. Figure 1A ). For example, a preliminary stacked structure comprising a vertically alternating sequence of sacrificial structures and preliminary insulating structures may be formed by conventional material deposition processes; a preliminary trench may be formed through at least the preliminary stacked structure by one or more conventional material removal processes to form modified sacrificial structures and insulating structures 206 ( Figure 2B ); at least a portion of each of the modified sacrificial structures may be selectively removed by one or more additional conventional material removal processes to form a recessed region; then, the recessed region may be at least partially (e.g., substantially) filled with a conductive material to form a conductive structure 204 ( Figure 2B ).

[0066] like Figure 2A As shown in FIG. 1 , each of the blocks 212 can exhibit substantially the same width W3 (e.g., horizontal dimension in the Y direction) as one another. Additionally, each of the blocks 212 can be spaced apart from one another (e.g., in the X direction) by substantially the same distance D3 (e.g., corresponding to the width of each of the filled slots 210 ( Figure 2B )), so that the blocks 212 are substantially uniformly spaced apart from each other. Thus, throughout the stacked structure 202, the spacing P1 ( Figure 2A ) can be basically unified.

[0067] For clarity and ease of understanding of the drawings and related descriptions, Figure 2A and 2BThe stacked structure 202 of the memory device 200 is shown to include three (3) blocks 212 and two (2) slots 210. However, the stacked structure 202 may include a different number (e.g., amount, number) of blocks 212 (e.g., greater than three (3) blocks 212, less than three (3) blocks 212) and slots 210 (e.g., greater than two (2) slots 210, less than two (2) slots 210) and / or may include a different distribution of blocks 212 (and, therefore, slots 210). The number of blocks 212 and slots 210 included in the stacked structure 202 depends at least in part on the number, size, and arrangement of additional structures included in the memory device 200, as described in further detail below.

[0068] refer to Figure 2A , within the horizontal boundaries of the memory array region 202A of the stacked structure 202 (e.g., in the X direction and the Y direction), the memory device 200 may include vertically extending pillar structures 216. Each of the vertically extending pillar structures 216 may include a semiconductor pillar (e.g., a polysilicon pillar, a silicon-germanium pillar) at least partially surrounded by one or more charge storage structures (e.g., a charge trapping structure, such as a charge trapping structure including an oxide-nitride-oxide ("ONO") material; a floating gate structure). The vertically extending pillar structures 216 are aligned with the stacked structure 202 ( Figure 2B and 2C ) of layer 208( Figure 2B and 2C ) of the conductive structure 204 ( Figure 2B and 2C) can define vertically extending memory cell strings 218 that are coupled in series with each other within the memory array region 202A of the stacked structure 202. In some embodiments, the memory cells 218 formed at the intersections of the conductive structures 204 and the vertically extending pillar structures 216 within each layer 208 of the stacked structure 202 include so-called "MONOS" (metal oxide-nitride-oxide-semiconductor) memory cells. In additional embodiments, the memory cells 218 include so-called "TANOS" (tantalum nitride-aluminum oxide-nitride-oxide-semiconductor) memory cells, or so-called "BETANOS" (band / barrier engineered TANOS) memory cells, each of which is a subset of MONOS memory cells. In further embodiments, the memory cells 218 include so-called "floating gate" memory cells that include a floating gate (e.g., a metal floating gate) as a charge storage structure. The floating gate can be horizontally sandwiched between the central structure of the vertically extending pillar structures 216 and the conductive structures 204 of the different layers 208 of the stacked structure 202. The memory device 200 may include any desired number and distribution of vertically extending pillar structures 216 within the memory array region 202A of the stacked structure 202 .

[0069] Common Reference Figures 2A to 2C , the memory device 200 may further include a digit line 220 vertically covering the stack structure 202 ( Figure 2A and 2C ) (eg, data line, bit line), and vertically covers at least one source structure 222 ( Figure 2B and 2C) (eg, source line, source plate). The vertically extending pillar structure 216 may extend substantially vertically between the digit line 220 and the source structure 222 . The digit line 220 and the source structure 222 may each individually be formed of and include at least one conductive material, such as one or more of at least one metal (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al), at least one alloy (e.g., Co-based alloys, Fe-based alloys, Ni-based alloys, Fe and Ni-based alloys, Co and Ni-based alloys, Fe and Co-based alloys, Co-, Ni- and Fe-based alloys, Al-based alloys, Cu-based alloys, magnesium (Mg)-based alloys, Ti-based alloys, steel, mild steel, stainless steel), at least one conductively doped semiconductor material (e.g., conductively doped polysilicon, conductively doped Ge, conductively doped SiGe), and at least one conductive metal-containing material (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides). Digit line 220 and source structure 222 may include a substantially uniform distribution of conductive material, or may include a substantially non-uniform distribution of conductive material. If one or more of digit line 220 and source structure 222 present a substantially non-uniform distribution of conductive material, the amount of conductive material may change stepwise (e.g., abruptly) in different portions of one or more of digit line 220 and source structure 222, or may change continuously (e.g., gradually, such as linearly, parabolically). In some embodiments, digit line 220 and source structure 222 each individually present a substantially uniform distribution of conductive material. In additional embodiments, one or more of at least one of digit line 220 and source structure 222 present a substantially non-uniform distribution of at least one conductive material. For example, one or more of at least one of digit line 220 and source structure 222 may be formed of and include a stack of at least two different conductive materials.

[0070] Continue to refer Figure 2A and 2C , within the horizontal boundary of the stepped region 202B of the stacked structure 202 (e.g., in the X direction), each of the blocks 212 of the stacked structure 202 may include a stepped structure 224 at its horizontal end (e.g., in the X direction). The stepped structure 224 of each of the blocks 212 of the stacked structure 202 includes a step 226 that is at least partially defined by the horizontal end (e.g., in the X direction) of the layer 208. The steps 226 of the stepped structure 224 may be used as contact areas to connect the layer 208 ( Figure 2C ) of the conductive structure 204 ( Figure 2C) is electrically coupled to other components (e.g., features, structures, devices) of the memory device 200, as described in further detail below. Each of the stepped structures 224 within the stepped region 202B of the stacked structure 202 may individually include a desired number of steps 226. In addition, as Figure 2C , in some embodiments, the steps 226 of each of the step structures 224 are arranged in sequence, such that the steps 226 that are directly horizontally adjacent to each other (e.g., in the X direction) correspond to the layers 208 of the stacked structure 202 that are directly vertically adjacent to each other (e.g., in the Z direction). In additional embodiments, the steps 226 of one or more of the step structures 224 are not arranged in sequence, such that at least some of the steps 226 of the step structures 224 that are directly horizontally adjacent to each other (e.g., in the X direction) correspond to the layers 208 of the stacked structure 202 that are not directly vertically adjacent to each other (e.g., in the Z direction).

[0071] Still reference Figure 2A and 2C , the memory device 200 may further include a conductive contact structure 228 that physically and electrically contacts at least some (e.g., each) of the steps 226 of the step structure 224 of the stack structure 202 to provide electrical access to the conductive structure 204 of the stack structure 202. The conductive contact structure 228 may be coupled to the conductive structure 204 of the layer 208 of the stack structure 202 at the steps 226 of the step structure 224. Figure 2C , the conductive contact structure 228 may physically contact and extend vertically upward (e.g., in the positive Z direction) from the conductive structure 204 of the layer 208 of the stacked structure 202 at the step 226 of the step structure 224. Each step structure 224 of each block 212 of the stacked structure 202 may include at least one conductive contact structure 228 that physically contacts each step 226 thereof; or one or more step structures 224 of one or more blocks 212 of the stacked structure 202 may not have at least one conductive contact structure 228 that physically contacts at least one step 226 thereof.

[0072] In some embodiments, each of the conductive contact structures 228 individually presents a primary columnar shape (e.g., a circular columnar shape, a rectangular columnar shape, an oval columnar shape, a columnar shape), and is sized and positioned to be in physical contact with a single (e.g., only one) step 226 of a single (e.g., only one) step structure 224 of the stacked structure 202 (e.g., the step structure 224 of a single block 212). In additional embodiments, one or more of the conductive contact structures 228 present a different shape, a different size, and / or a different position.

[0073] The conductive contact structure 228 may be formed of and include at least one conductive material, such as a metal (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al), an alloy (e.g., Co-based alloys, Fe-based alloys, Ni-based alloys, Fe and Ni-based alloys, Co and Ni-based alloys, Fe and Co-based alloys, Co- and Ni- and Fe-based alloys, Al-based alloys, Cu-based alloys, Mg-based alloys, Ti-based alloys, steel, low carbon steel, stainless steel), a conductive metal-containing material (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides), a conductive doped semiconductor material (e.g., conductive doped Si, conductive doped Ge, conductive doped SiGe). The conductive contact structure 228 may include a substantially uniform distribution of the conductive material, or may include a substantially non-uniform distribution of the conductive material. If the conductive contact structures 228 present a substantially non-uniform distribution of the conductive material, the amount of the conductive material may vary stepwise (e.g., abruptly) throughout different portions of the conductive contact structures 228, or may vary continuously (e.g., gradually, e.g., linearly, parabolically). In some embodiments, each conductive contact structure 228 presents a substantially uniform distribution of the conductive material. In additional embodiments, one or more (e.g., each) conductive contact structures 228 present a substantially non-uniform distribution of at least one conductive material. One or more of the conductive contact structures 228 may, for example, be formed of and include a stack of at least two different conductive materials.

[0074] Common Reference Figure 2B and 2C Optionally, the memory device 200 may further include conductive structures 230 that physically contact at least some of the conductive contact structures 228 of the memory device 200. For example, the conductive structures 230 may be individually sized, shaped, and positioned to physically contact (e.g., in the X direction, in the Y direction) and horizontally extend beyond the horizontal boundaries of the conductive contact structures 228 located on the steps 226 of the stacked structure 202. In some such embodiments, each of the conductive structures 230 individually physically contacts and horizontally extends beyond the horizontal boundary of one of the conductive contact structures 228 located on one of the steps 226 of the stacked structure 202. In additional embodiments, at least some (e.g., all) of the conductive structures 230 are omitted.

[0075] Conductive structure 230, if present, may be formed of and include at least one conductive material, such as a metal (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al), an alloy (e.g., Co-based alloys, Fe-based alloys, Ni-based alloys, Fe and Ni-based alloys, Co and Ni-based alloys, Fe and Co-based alloys, Co- and Ni- and Fe-based alloys, Al-based alloys, Cu-based alloys, Mg-based alloys, Ti-based alloys, steel, low carbon steel, stainless steel), a conductive metal-containing material (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides), a conductive doped semiconductor material (e.g., conductive doped Si, conductive doped Ge, conductive doped SiGe). Conductive structure 230 may include a substantially uniform distribution of the conductive material, or may include a substantially non-uniform distribution of the conductive material. If the conductive structures 230 present a substantially non-uniform distribution of the conductive material, the amount of the conductive material may vary stepwise (e.g., abruptly) throughout different portions of the conductive structures 230, or may vary continuously (e.g., gradually, e.g., linearly, parabolically). In some embodiments, each conductive structure 230 presents a substantially uniform distribution of the conductive material. In additional embodiments, one or more (e.g., each) conductive contact structure 228 presents a substantially non-uniform distribution of at least one conductive material. One or more of the conductive structures 230 may, for example, be formed of and include a stack of at least two different conductive materials.

[0076] Continue to refer Figure 2B and 2C , the memory device 200 may further include an isolation material 232 on or above the stacked structure 202. The isolation material 232 may be vertically sandwiched (eg, in the Z direction) between the stacked structure 202 and the isolation structure 102. Figure 2C , the isolation material 232 may substantially cover the step structure 224 within the step region 202B of the stacked structure 202, and may substantially surround the side surfaces (e.g., sidewalls) of the conductive contact structure 228 on the steps 226 of the step structure 224. The isolation material 232 may present a substantially planar upper vertical boundary, and a substantially non-planar lower vertical boundary that is at least complementary to the topography of the underlying stacked structure 202 (including its step structure 224).

[0077] The isolation material 232 may be formed of and include at least one dielectric material, such as at least one dielectric oxide material (eg, SiO x, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x 、NbO x 、TiO x 、ZrO x 、TaO x and MgO x one or more of the above), at least one dielectric nitride material (e.g., SiN y ), at least one dielectric oxynitride material (e.g., SiO x N y ) and at least one dielectric carbonitride material (e.g., SiO x C z N y ). Isolation material 232 may include a substantially uniform distribution or a substantially non-uniform distribution of at least one dielectric material. In some embodiments, isolation material 232 exhibits a substantially uniform distribution of dielectric material. In further embodiments, isolation material 232 exhibits a substantially non-uniform distribution of at least one dielectric material. Isolation material 232 may, for example, be formed of and include a stack (e.g., a laminate) of at least two different dielectric materials. In some embodiments, isolation material 232 is formed of and includes SiO2.

[0078] Common Reference Figures 2A to 2C The microelectronic device 100 according to an embodiment of the present disclosure may be vertically located above the step region 202B of the stacked structure 202 (eg, at Figure 2B and 2B ) and is at least partially (eg, substantially) located within a horizontal boundary of the step region 202B of the stacked structure 202 (eg, in the Z direction shown in FIG. 2 ). Figure 2A ). The microelectronic device 100 can be used as a string driver assembly (e.g., an HV string driver assembly) of the memory device 200. As described in further detail below, the transistor 124 ( Figure 2B ) (eg, a driver transistor such as a string driver transistor) can be connected via the local contact structure 114, the conductive contact structure 228 ( Figure 2A and 2C ), and, if present, conductive structure 230 ( Figure 2B and 2C ) is electrically coupled to the conductive structure 204 of the stacked structure 202.

[0079] like Figure 2A and 2CAs shown in FIG. 1 , the plurality of 2D material structures 106 of the microelectronic device 100 may vertically cover (e.g., Figure 2C 2 (in the Z direction shown in FIG. 2 ). For example, different 2D material structures 106 of the microelectronic device 100 may individually vertically cover and at least partially (e.g., substantially) be located within the horizontal boundaries (e.g., X direction) of the steps 226 of the step structure 224 within the step region 202B of the stacked structure 202. Figure 2A As shown in FIG. 1 , different 2D material structures 106 of the microelectronic device 100 can individually extend horizontally in the Y direction across different steps 226 of the stacked structure 202 and be horizontally adjacent to each other in the Y direction, and can be substantially confined within the horizontal boundaries of different horizontally adjacent steps 226 in the X direction. As a non-limiting example, Figure 2A , three (3) 2D material structures 106 of the microelectronic device 100 can be operably associated with three (3) groups of steps 226 of the stacked structure 202, wherein each of the three (3) 2D material structures 106 individually vertically covers and is located within a horizontal boundary (e.g., in the X direction) of one of the three (3) groups of steps 226, and each group of the steps 226 individually includes a different step 226 of the stacked structure 202 that is adjacent to each other in the horizontal direction (e.g., in the Y direction) and is located at substantially the same vertical position (e.g., in the Z direction) as each other in the stacked structure 202. The spacing P2 between the 2D material structures 106 of the microelectronic device 100 that are horizontally adjacent to each other in the X direction can be substantially equal to (e.g., substantially the same as) the spacing between the steps 226 of the stacked structure 202 that are horizontally adjacent to each other in the X direction.

[0080] Continue to refer Figure 2A and 2C , the gate structure 118 of the microelectronic device 100 may vertically overlap and be positioned at a horizontal boundary (eg, in the Y direction) of the block 212 of the stacked structure 202. Figure 2A , the gate structures 118 of the microelectronic device 100 may extend in a horizontal direction (e.g., an X direction) substantially the same as the blocks 212 of the stacked structure 202, and may be located within the horizontal boundaries of the blocks 212 of the stacked structure 202 in another horizontal direction (e.g., a Y direction) orthogonal to the horizontal direction in which the gate structures 118 and the blocks 212 extend. In some embodiments, the centerline of the gate structure 118 in the Y direction is substantially aligned with the centerline of the blocks 212 in the Y direction. The spacing between horizontally adjacent gate structures 118 of the microelectronic device 100 (e.g., in the Y direction) may be substantially equal to (e.g., substantially the same as) the spacing P1 (e.g., between horizontally adjacent blocks 212 of the stacked structure 202 (e.g., in the Y direction) Figure 2A).

[0081] Next reference Figure 2B and 2C , the local contact structure 114 of the microelectronic device 100 can extend vertically (eg, in the Z direction) from the 2D material structure 106 of the microelectronic device 100 to the conductive structure 230. For example, Figure 2B As shown in FIG. 1 , the local contact structure 114 can extend vertically from some of the second conductive doping regions 112 (e.g., the drain region 112B) of the 2D material structure 106 to the conductive structure 230. The local contact structure 114 can contact (e.g., physically contact, electrically contact) the conductive structure 230. Therefore, the local contact structure 114, the conductive structure 230, and the conductive contact structure 228 can electrically connect the transistor 124 (e.g., a driver transistor such as a string driver transistor) of the microelectronic device 100 to the conductive structure 204 of the layer 208 of the stacked structure 202. Figure 2B and 2C As shown in FIG. 1 , the local contact structure 114 may be located within the horizontal boundary of the conductive structure 230 (eg, in the Y direction ( Figure 2B ) and X direction ( Figure 2C )). In some embodiments, at least some (eg, all, less than all) of the local contact structures 114 are disposed in the X direction ( Figure 2C ) is offset from the centerline in the X direction of the conductive structures 230 that at least some of the local contact structures 114 contact (e.g., physically contact, electrically contact). In additional embodiments, the centerlines in the X direction of at least some (e.g., all, less than all) of the local contact structures 114 are substantially aligned with the centerlines in the X direction of the conductive structures 230 that at least some of the local contact structures 114 contact (e.g., physically contact, electrically contact).

[0082] In additional embodiments, such as embodiments in which the conductive structure 230 is omitted, the local contact structure 114 of the microelectronic device 100 can extend vertically (e.g., in the Z direction) from the 2D material structure 106 to the conductive contact structure 228. In such embodiments, the local contact structure 114 is at least partially (e.g., substantially) located within the horizontal boundaries of the conductive contact structure 228 (e.g., in the Y direction ( Figure 2B ) and in the X direction ( Figure 2C )). Therefore, the local contact structure 114 and the conductive contact structure 228 can electrically connect the transistor 124 of the microelectronic device 100 to the conductive structure 204 of the layer 208 of the stacked structure 202.

[0083] In additional embodiments, one or more of the local contact structures 114 of the microelectronic device 100 can extend vertically (e.g., in the Z direction) from the 2D material structure 106 to the step 226 of the stacked structure 202. As a non-limiting example, the conductive contact structure 228 and the conductive structure 230 can be omitted, and each of the local contact structures 114 can individually contact one of the steps 226 of the stacked structure 202. Thus, the local contact structures 114 can directly electrically connect the transistor 124 of the microelectronic device 100 to the conductive structure 204 of the layer 208 of the stacked structure 202.

[0084] although Figures 2A to 2C The microelectronic device 100 of the memory device 200 is depicted as being located within a horizontal boundary (e.g., in the X direction, in the Y direction) of a stepped region 202B of a stacked structure 202 of the memory device 200, and one or more portions of the microelectronic device 100 may be located outside the horizontal boundary of the stepped region 202B of the stacked structure 202 of the memory device 200. For example, one or more portions (e.g., all, less than all) of one or more transistors 124 of the microelectronic device 100 may be located outside the horizontal boundary of the stepped region 202B of the stacked structure 202. In such embodiments, the geometric configuration of one or more of the local contact structure 114, the conductive structure 230, and the conductive contact structure 228 connected (e.g., physically connected, electrically connected) to the one or more portions of the one or more transistors 124 may be relative to Figures 2A to 2C 2B may be modified to facilitate electrical connection between the one or more transistors 124 and one or more of the conductive structures 204 of the stacked structure 202. As a non-limiting example, the routing (e.g., path) of the one or more conductive structures 230 electrically connected to the one or more transistors 124 may be shaped to extend outside of the horizontal boundaries of the stepped region 202B of the stacked structure 202 and to a local contact structure 114 in contact with the one or more transistors 124.

[0085] Therefore, according to an additional embodiment of the present disclosure, a memory device includes a stacked structure, a ladder structure, a string driver transistor, at least one additional conductive structure, and a memory cell string. The stacked structure includes vertically alternating conductive structures and insulating structures arranged in layers. The ladder structure is at a horizontal end of the stacked structure. The ladder structure has a step including an edge of a layer. The string driver transistor vertically covers the ladder structure and includes a channel region, and the channel region includes at least one 2D material. The at least one additional conductive structure extends from and between the string driver transistor and one of the steps of the ladder structure. The memory cell string extends vertically through the stacked structure.

[0086] According to the microelectronic device of the embodiment of the present disclosure (for example, the previously referenced Figures 1A to 1C The microelectronic device 100 described above) and the memory device (eg, previously described with reference to Figures 2A to 2C The memory device 200 described above can be used in embodiments of the electronic system of the present disclosure. For example, Figure 3 is a block diagram of an illustrative electronic system 300 according to an embodiment of the present disclosure. The electronic system 300 may include, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular enabled tablet, for example or Tablets, electronic books, navigation devices, etc. Electronic system 300 includes at least one memory device 302. Memory device 302 may include, for example, a microelectronic device previously described herein (e.g., previously referenced Figures 1A to 1C The microelectronic device 100 described above) and the memory device (eg, previously described with reference to Figures 2A to 2C The electronic system 300 may further include at least one electronic signal processor device 304 (commonly referred to as a "microprocessor"). The electronic signal processor device 304 may optionally include a microelectronic device previously described herein (e.g., previously described with reference to Figures 1A to 1C The microelectronic device 100 described above) and the memory device (eg, previously described with reference to Figures 2A to 2C One or more embodiments of the memory device 200 described herein. Figure 3 300 as two (2) separate devices, but in additional embodiments, a single (e.g., only one) memory / processor device having the functionality of memory device 302 and electronic signal processor device 304 is included in electronic system 300. In such embodiments, the memory / processor device may include a microelectronic device previously described herein (e.g., previously described with reference to FIG. Figures 1A to 1C The microelectronic device 100 described above) and the memory device (eg, previously described with reference to Figures 2A to 2CThe electronic system 300 may further include one or more input devices 306 for inputting information into the electronic system 300 by a user, such as a mouse or other pointing device, a keyboard, a touch pad, a button, or a control panel. The electronic system 300 may further include one or more output devices 308 for outputting information (e.g., visual or audio output) to the user, such as a monitor, a display, a printer, an audio output jack, a speaker, etc. In some embodiments, the input device 306 and the output device 308 may include a single touch screen device, which can be used to input information to the electronic system 300 and output visual information to the user. The input device 306 and the output device 308 may be in electrical communication with one or more of the memory device 302 and the electronic signal processor device 304.

[0087] Therefore, according to an embodiment of the present disclosure, an electronic system includes an input device, an output device, a processor device operably coupled to the input device and the output device, and a memory device operably coupled to the processor device. The memory device includes a stacked structure, a contact structure, a microelectronic device, and a vertically extending memory cell string. The stacked structure has a layer including a conductive structure and an insulating structure vertically adjacent to the conductive structure, and includes a step region and a memory array region. The step region includes a step structure having a step, and the step includes a horizontal end of the layer. The memory array region is horizontally adjacent to the step region. The contact structure is on the step of the step structure. The microelectronic device is electrically coupled to the contact structure and includes a transistor vertically covering and within a horizontal boundary of the step region of the stacked structure. Each of the transistors includes: a channel region including a 2D material; a conductive doped region adjacent to a relative horizontal boundary of the channel region and including the 2D material doped with at least one conductive dopant; and a gate structure vertically covering and at least partially aligned horizontally with the channel region. The vertically extending memory cell string is within the memory array region of the stacked structure.

[0088] Compared to conventional structures, conventional devices, and conventional systems, the structures, devices, and systems of the present disclosure advantageously facilitate one or more of improved simplicity, greater packaging density, and increased component miniaturization. For example, compared to conventional microelectronic devices and conventional memory devices, the configuration of the microelectronic device (e.g., microelectronic device 100) of the present disclosure facilitates a robust memory device (e.g., memory device 200) architecture that exhibits more components, less component congestion, and / or smaller horizontal dimensions. Compared to conventional structures, conventional devices, and conventional systems, the structures, devices, and systems of the present disclosure can increase performance, scalability, efficiency, reliability, and simplicity.

[0089] Additional non-limiting example embodiments of the present disclosure are described below.

[0090] Embodiment 1: A transistor, comprising: a 2D material structure, which conformally extends on and between a surface of a dielectric fin structure extending in parallel in a first horizontal direction, the 2D material structure comprising: a source region; a drain region; and a channel region, which is positioned between the source region and the drain region in the first horizontal direction; and a gate structure, which covers the channel region of the 2D material structure and extends in a second horizontal direction orthogonal to the first horizontal direction, the gate structure being within a horizontal boundary of the channel region of the 2D material structure in the first horizontal direction.

[0091] Embodiment 2: The transistor according to embodiment 1, wherein the 2D material structure comprises one or more of WS2, WSe2, MoS2 and MoSe2.

[0092] Embodiment 3: The transistor according to one of embodiments 1 and 2, wherein the source region and the drain region of the 2D material structure are doped with at least one N-type dopant.

[0093] Embodiment 4: The transistor according to one of embodiments 1 and 2, wherein the source region and the drain region of the 2D material structure are doped with at least one P-type dopant.

[0094] Embodiment 5: The transistor according to any one of Embodiments 1 and 2, wherein the source region and the drain region of the 2D material structure are substantially undoped.

[0095] Embodiment 6: The transistor according to any one of Embodiments 1 to 5, wherein the 2D material structure further comprises a lateral double diffusion region positioned between the channel region and each of the source region and the drain region in the first horizontal direction.

[0096] Embodiment 7: A transistor according to any one of embodiments 1 to 6, wherein: the dielectric fin structures each individually present an aspect ratio in the range of about 0.1:1 to about 10:1; and the ratio of the width of each of the dielectric fin structures to the distance between horizontally adjacent dielectric structures is in the range of about 0.1:1 to about 10:1.

[0097] Embodiment 8: The transistor according to any one of Embodiments 1 to 7, further comprising a conductive structure extending vertically from the gate structure toward the channel region of the 2D material structure, the conductive structure being sandwiched between the dielectric fin structures in the second horizontal direction.

[0098] Embodiment 9: The transistor of Embodiment 8, further comprising a gate dielectric material interposed between the 2D material structure and each of the gate structure and conductor.

[0099] Embodiment 10: A microelectronic device comprising: discrete dielectric structures covering isolation structures and separated from each other by filled trenches; non-planar 2D material structures extending above the surfaces of the isolation structures and the discrete dielectric structures inside and outside the filled trenches, the non-planar 2D material structures comprising: conductive doped regions; and channel regions between the conductive doped regions; a gate structure covering the channel regions of the non-planar 2D material structure and being substantially aligned therewith; a conductive structure extending from the gate structure into the trenches; a contact structure coupled to some of the conductive doped regions and extending into the isolation structure; and at least one additional contact structure coupled to at least another of the conductive doped regions and extending away from the isolation structure.

[0100] Embodiment 11: The microelectronic device of Embodiment 10, wherein the non-planar 2D material structure physically contacts and conforms to surfaces of the isolation structure and the discrete dielectric structure inside and outside the filled trench.

[0101] Embodiment 12: A microelectronic device according to one of embodiments 10 and 11, wherein the non-planar 2D material structure further includes an additional conductive doping region between the channel region and the conductive doping region, and the additional conductive doping region includes a relatively smaller amount of conductive dopant than the conductive doping region.

[0102] Embodiment 13: The microelectronic device according to embodiment 12, wherein: the conductive doped region of the non-planar 2D material structure comprises N + Region; The additional conductive doping region of the non-planar 2D material structure includes N - district.

[0103] Embodiment 14: A microelectronic device according to one of embodiments 12 and 13, wherein the contact structure and the at least one additional contact structure physically contact one or more of the conductive doped regions and the additional conductive doped regions of the non-planar 2D material structure.

[0104] Embodiment 15: A microelectronic device according to any one of embodiments 10 to 14, wherein: the conductive doped region of the non-planar 2D material includes at least one source region and at least two drain regions; the contact structure includes at least two local contact structures coupled to the at least two drain regions; and the at least one additional contact structure includes at least one global contact structure coupled to the at least one source region.

[0105] Embodiment 16: A memory device comprising: a stacked structure including vertically alternating conductive structures and insulating structures arranged in layers; a stepped structure having steps including edges of the layers at a horizontal end of the stacked structure; a string driver transistor vertically covering the stepped structure and including a channel region including at least one 2D material; at least one additional conductive structure extending from and between the string driver transistor and one of the steps of the stepped structure; and a memory cell string extending vertically through the stacked structure.

[0106] Embodiment 17: The memory device of Embodiment 16, wherein the at least one 2D material has a bandgap in a range of about 1.2 eV to about 2.5 eV and has a bandgap of about 10 cm 2 / V·s to about 400cm 2 / V·s range of electron mobility.

[0107] Embodiment 18: A memory device according to one of Embodiments 16 and 17, wherein the string driver transistor further comprises: a lateral double diffusion region horizontally adjacent to the channel region and comprising the at least one 2D material; and a source region and a drain region horizontally adjacent to the lateral double diffusion region and comprising the at least one 2D material.

[0108] Embodiment 19: The memory device of any one of Embodiments 16 to 18, wherein the at least one 2D material has a substantially non-planar shape that conforms to the combined topography of a dielectric fin structure and an insulating structure vertically underlying the at least one 2D material.

[0109] Embodiment 20: The memory device of any one of Embodiments 16-18, wherein the at least one 2D material has a substantially horizontally planar shape.

[0110] Embodiment 21: A memory device according to any one of Embodiments 16 to 20, wherein the at least one additional conductive structure includes: a vertical contact structure, which is on one of the steps of the stepped structure; and a local contact structure, which extends vertically downward from the string driver transistor and is electrically coupled to the vertical contact structure.

[0111] Embodiment 22: The memory device of Embodiment 21, wherein the at least one additional conductive structure further comprises another conductive structure vertically located between and in physical contact with the vertical contact structure and the local contact structure.

[0112] Embodiment 23: The memory device of one of Embodiments 21 and 22, further comprising a global contact structure extending vertically upward from the string driver transistor.

[0113] Embodiment 24: An electronic system comprising: an input device; an output device; a processor device operably coupled to the input device and the output device; and a memory device operably coupled to the processor device and comprising: a stacked structure having a layer including a conductive structure and an insulating structure vertically adjacent to the conductive structure, the stacked structure comprising: a step region including a step structure having steps including horizontal ends of the layer; a memory array region horizontally adjacent to the step region; a contact structure on the step of the step structure; a microelectronic device electrically coupled to the contact structure and comprising transistors vertically covering and within a horizontal boundary of the step region of the stacked structure, each of the transistors comprising: a channel region including a 2D material; a conductive doped region adjacent to a relative horizontal boundary of the channel region and including the 2D material doped with at least one conductive dopant; and a gate structure vertically covering and at least partially horizontally aligned with the channel region; and a memory cell string extending vertically within the memory array region of the stacked structure.

[0114] Embodiment 25: The electronic system of Embodiment 24, wherein the memory device comprises a 3D NAND flash memory device.

[0115] Although the present disclosure is susceptible to various modifications and alternative forms, its details show specific embodiments by way of example and are described in detail herein. However, the present disclosure is not limited to the specific forms disclosed. On the contrary, the present disclosure will cover all modifications, equivalents and substitutions that fall within the scope of the attached claims and their legal equivalents.

Claims

1. A string driver assembly, comprising: a dielectric fin structure extending horizontally and in parallel in a first direction; a two-dimensional (2D) material extending horizontally over and between the dielectric fin structures in a second direction orthogonal to the first direction; a gate electrode vertically covering the 2D material and extending horizontally in parallel in the second direction; and A gate dielectric material is vertically sandwiched between the 2D material and the gate electrode.

2. The string driver assembly of claim 1, wherein the 2D material comprises: a conductive doped region; and A channel region is horizontally sandwiched between the conductive doping regions in the first direction, and the channel region horizontally overlaps with the gate electrode in the first direction.

3. A string driver assembly according to claim 2, wherein the 2D material also includes a conductive doped offset region horizontally sandwiched between the conductive doped region and the channel region in the first direction, the conductive doped offset region having a lower concentration of one or more conductivity enhancing dopants than the conductive doped region.

4. The string driver assembly of claim 2, further comprising: a conductive contact extending horizontally in the second direction and vertically overlapping the gate electrode, the conductive contact coupled to one of the conductive doped regions of the 2D material; and An additional conductive contact extending horizontally in the second direction and vertically below the gate electrode and the conductive contact, the additional conductive contact coupled to an additional conductive doped region in the conductive doped region of the 2D material.

5. The string driver assembly of claim 1, wherein the 2D material comprises one or more of transition metal dichalcogenides, carbides, carbonitrides, graphene, graphene oxide, stanene, phosphine, hexagonal boron nitride, borophene, silicene, graphene, germanene, germanane, 2D supercrystals, and monolayers of semiconductor materials.

6. A string driver assembly according to claim 1, wherein the 2D material comprises a transition metal dichalcogenide having a general chemical formula MX2, wherein M is selected from Mo, W, Nb, Zr, Hf, Re, Pt, Ti, Ta, V, Co, Cd, Cr, and wherein X is selected from S, Se and Te.

7. The string driver assembly of claim 1, wherein the 2D material structure comprises a structure having a general chemical formula M n+1 X n A carbide or carbonitride of wherein M is selected from Ti, Hf, Zr, V, Nb, Ta, and wherein X is selected from C and N.

8. The string driver assembly of claim 1, wherein: In the second direction, a first distance between adjacent ones of the dielectric fin structures is in a range from about 10 nanometers (nm) to about 100 nm; and In the first direction, a second distance between adjacent ones of the gate electrodes is greater than the first distance.

9. A memory device comprising: blocks extending horizontally in parallel in a first direction, and each block comprising layers, the layers individually comprising a conductive material and an insulating material vertically adjacent to the conductive material, the blocks respectively comprising: an array region; and a step region, which is adjacent to the array region in the first direction and includes a step structure having steps, The steps include edges of at least some of the layers; microelectronic devices vertically covering the blocks and individually extending horizontally over two of the blocks in a second direction perpendicular to the first direction, the microelectronic devices respectively comprising: a dielectric fin structure extending horizontally and in parallel in the second direction; a two-dimensional (2D) material that conformally extends substantially over and between the dielectric fin structures; a dielectric material on the 2D material; and a gate electrode extending on the dielectric material and in parallel in the first direction; and Conductive contacts couple corresponding ones of the microelectronic devices to the conductive material of corresponding ones of the layers of the two ones of the blocks horizontally overlapping the corresponding ones of the microelectronic devices in the second direction.

10. The memory device of claim 9, wherein the corresponding one of the microelectronic devices is positioned horizontally in the first direction within the step region of each of the two of the blocks horizontally overlapping the corresponding one of the microelectronic devices in the second direction.

11. The memory device of claim 9, wherein for the respective one of the microelectronic devices, the 2D material comprises: a first channel region horizontally overlapping each of a first block of the two blocks of the blocks and a first gate electrode of the gate electrodes in the second direction; and A second channel region horizontally overlaps each of a second block of the two blocks of the blocks and a second gate electrode of the gate electrodes in the second direction.

12. The memory device of claim 11 , wherein for the respective one of the microelectronic devices, the 2D material further comprises: a first conductive doped region horizontally overlapping the first of the two of the blocks in the second direction; a second conductive doped region horizontally overlapping the second one of the two ones of the blocks in the second direction; and A third conductive doped region horizontally overlaps with a dielectric trench structure in the second direction, the dielectric trench structure being sandwiched between the first block and the second block of the two blocks in the blocks in the second direction.

13. The memory device of claim 12, wherein for the corresponding one of the microelectronic devices, the conductive contacts comprise: a first local conductive contact coupled to the first conductive doped region of the 2D material and extending vertically downward from the first conductive doped region of the 2D material; a second local conductive contact coupled to the second conductively doped region of the 2D material and extending vertically downward from the second conductively doped region of the 2D material; A global conductive contact is coupled to the third conductive doped region of the 2D material and extends vertically upward from the third conductive doped region of the 2D material.

14. The memory device of claim 13, wherein for the corresponding one of the microelectronic devices, the conductive contacts further comprise: a first word line contact coupled to the first local conductive contact and physically contacting the conductive material of one of the layers of the first block at one of the steps of the stepped structure of the first block; as well as A second word line contact is coupled to the second local conductive contact and physically contacts the conductive material of one of the layers of the second block at one of the steps of the stepped structure of the second block.

15. The memory device according to claim 12, wherein: For the corresponding one of the microelectronic devices, the 2D material further comprises: a first lateral double-diffused LDD offset region horizontally sandwiched between the first conductive doping region and the first channel region in the second direction; a second LDD offset region horizontally sandwiched between the first channel region and the third conductive doping region in the second direction; a third LDD offset region horizontally sandwiched between the third conductive doping region and the second channel region in the second direction; and A fourth LDD offset region is horizontally sandwiched between the second channel region and the second conductive doping region in the second direction.

16. The memory device of claim 9, further comprising memory cell strings extending vertically within the array region of corresponding ones of the blocks.

17. A 3D NAND flash memory device comprising: two blocks extending horizontally and in parallel in a first direction, each of the two blocks comprising layers, the layers respectively comprising a conductive material and an insulating material vertically adjacent to the conductive material; a trench structure horizontally sandwiched between the two blocks in a second direction orthogonal to the first direction; a memory cell string located within the horizontal regions of the two blocks and extending vertically through the two blocks; a string driver assembly vertically covering the two blocks and the trench structure in the second direction and individually overlapping the two blocks and the trench structure horizontally, the string driver assembly respectively comprising: a dielectric fin structure extending horizontally and in parallel in the second direction; a two-dimensional (2D) material extending conformally substantially over and between the dielectric fin structures; a gate dielectric material on the 2D material; and two gate electrodes located on the gate dielectric material and horizontally overlapping the two blocks in the second direction, the two gate electrodes extending horizontally and in parallel in the first direction; and Conductive contacts couple corresponding ones of the string driver assemblies with the conductive material of corresponding ones of the layers of each of the two blocks.

18. The 3D NAND flash memory device of claim 17, wherein the string driver assemblies further include conductive protrusions extending vertically from the two gate electrodes and vertically overlapping the dielectric fin structures, respectively, the conductive protrusions being horizontally sandwiched between the dielectric fin structures in the second direction.

19. The 3D NAND flash memory device of claim 17, wherein: For the respective one of the string driver assemblies, the 2D material comprises: a first channel region horizontally overlapping with a first block of the two blocks and each of a first gate electrode of the two gate electrodes in the second direction; a first drain region horizontally overlapping the first of the two blocks in the second direction; a source region horizontally overlapping the trench structure in the second direction; a second channel region horizontally overlapping with a second block of the two blocks and each of a second gate electrode of the two gate electrodes in the second direction; and A second drain region horizontally overlaps the second block of the two blocks in the second direction.

20. The 3D NAND flash memory device of claim 17, wherein: For the respective ones of the string driver assemblies, the 2D material includes one or more of WS2, WSe2, MoS2, and MoSe2.

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