Transistors including two-dimensional materials and related microelectronic devices, memory devices, and electronic systems

Abstract

The present application relates to transistors comprising a two-dimensional material, and to related microelectronic devices, memory devices, and electronic systems. A transistor comprises a 2D material structure and a gate structure. The 2D material structure extends conformally over and between surfaces of dielectric fin structures extending in a first horizontal direction, and comprises a source region, a drain region, and a channel region positioned between the source region and the drain region in the first horizontal direction. The gate structure covers the channel region of the 2D material structure, and extends in a second horizontal direction orthogonal to the first horizontal direction. The gate structure is within horizontal bounds of the channel region of the 2D material structure in the first horizontal direction.

Description

[0001] Information related to divisional application

[0002] This application is a divisional application of Chinese Patent Application No. 202010836620.4, filed on August 19, 2020, entitled "Transistor comprising two-dimensional material and related microelectronic devices, memory devices and electronic systems".

[0003] Priority requirements

[0004] This application claims priority to U.S. Patent Application Serial No. 16 / 549,519, filed on August 23, 2019, entitled "Transistors comprising two-dimensional materials and associated microelectronic devices, memory devices and electronic systems". Technical Field

[0005] In various embodiments, this disclosure generally relates to the field of microelectronic device design and fabrication. More specifically, this disclosure relates to transistors comprising two-dimensional (2D) materials, and to related microelectronic devices, memory devices, and electronic systems. Background Technology

[0006] A continuous goal of the microelectronics industry is to increase the memory density (e.g., the number of memory cells per memory die) of memory devices, such as non-volatile memory devices (e.g., NAND flash memory devices). One way to increase memory density in non-volatile memory devices is to utilize vertical memory array (also known as “three-dimensional (3D) memory array”) architectures. Conventional vertical memory arrays comprise vertical memory strings that extend through openings in layers of conductive structures (e.g., word line boards) and dielectric material at each junction of the vertical memory strings with the conductive structures. Compared to conventional planar (e.g., two-dimensional) arrangements with transistors, these configurations allow for a greater number of switching devices (e.g., transistors) to be located within the cell die area (i.e., the length and width of the active surface consumed) by constructing the array upwards (e.g., longitudinally, vertically) on the die.

[0007] Conventional vertical memory arrays include electrical connections between conductive structures and access lines (e.g., word lines), allowing memory cells in the vertical memory array to be uniquely selected for write, read, or erase operations. One method of forming these electrical connections involves forming at least one so-called "step" (or "step") structure at the edge (e.g., horizontal end) of the conductive structure layer. The step structure includes individual "steps" defining contact areas of the conductive structure, on which conductive contact structures can be positioned to provide electrical pathways to the conductive structure.

[0008] With advancements in vertical memory array technology, additional memory density has been provided by forming vertical memory arrays to include conductive structures of additional layers, and thus additional staircase structures and / or additional steps in individual staircase structures associated therewith. However, increasing the number of conductive layers in the stacked structure (and therefore the number of staircase structures and / or the number of steps in individual staircase structures) without undesirably increasing the total width of the stacked structure (e.g., lateral footprint) can result in complex and congested routing paths to electrically connect the conductive structures to additional components of the memory device (e.g., string drivers). These complex and congested routing paths can obstruct (or even block) desired connection paths from other components of the memory device and between them. Furthermore, as the number of conductive layers continues to increase, the conventional locations and configurations of additional components in the memory device have become insufficient to support the increased number of additional components.

[0009] In view of the foregoing, there is still a need for new device configurations (e.g., microelectronic devices, memory devices) that can help increase memory density while mitigating problems of conventional device configurations (e.g., routing congestion, connectivity barriers), as well as new electronic systems that incorporate these new device configurations. Summary of the Invention

[0010] In some embodiments, the transistor includes a 2D material structure and a gate structure. The 2D material structure extends conformally between and parallel to dielectric fins extending in a first horizontal direction, and includes a source region, a drain region, and a channel region positioned between the source and drain regions in the first horizontal direction. The gate structure covers the channel region of the 2D material structure and extends in a second horizontal direction orthogonal to the first horizontal direction. The gate structure lies within the horizontal boundary of the channel region of the 2D material structure in the first horizontal direction.

[0011] In an additional embodiment, the microelectronic device includes discrete dielectric structures, a non-planar 2D material structure, a gate structure, a conductive structure, a contact structure, and at least one additional contact structure. The discrete dielectric structures cover an isolation structure and are spaced apart from each other by filled trenches. The non-planar 2D material structure extends above the surfaces of the isolation structure and the discrete dielectric structure, both inside and outside the filled trenches, and includes conductive doped regions and channel regions between them. The gate structure covers and is substantially aligned with the channel region of the non-planar 2D material structure. The conductive structure extends from the gate structure into the trenches. The contact structures are coupled to some of the conductive doped regions and extend into the isolation structure. The at least one additional contact structure is coupled to at least one of the conductive doped regions and extends away from the isolation structure.

[0012] In a further embodiment, the memory device includes a stacked structure, a stepped structure, a string driver transistor, at least one additional conductive structure, and a string of memory cells. The stacked structure includes vertically alternating conductive and insulating structures arranged in layers. The stepped structure is located at a horizontal end of the stacked structure. The stepped structure has steps including the edges of the layers. The string driver transistor vertically covers the stepped structure and includes a channel region comprising at least one 2D material. The at least one additional conductive structure extends from the string driver transistor and one of the steps of the stepped structure and extends therebetween. The string of memory cells extends vertically through the stacked structure.

[0013] In another additional embodiment, the electronic system includes input devices, output devices, a processor device operatively coupled to the input devices and output devices, and a memory device operatively coupled to the processor device. The memory device includes a stacked structure, a contact structure, microelectronic devices, and a vertically extending string of memory cells. The stacked structure has layers including conductive structures and insulating structures vertically adjacent to the conductive structures, and includes a stepped region and a memory array region. The stepped region includes a stepped structure with steps, the steps including horizontal ends of the layers. The memory array region is horizontally adjacent to the stepped region. The contact structure is on the steps of the stepped structure. The microelectronic devices are electrically coupled to the contact structure and include transistors vertically covering and within the horizontal boundary of the stepped region of the stacked structure. Each of the transistors includes: a channel region comprising a 2D material; a conductive doped region adjacent to the relative horizontal boundary of the channel region and comprising the 2D material doped with at least one conductive dopant; and a gate structure vertically covering and at least partially aligned horizontally with the channel region. The vertically extending string of memory cells is within the memory array region of the stacked structure. Attached Figure Description

[0014] Figure 1A This is a simplified partial top view of a microelectronic device according to an embodiment of the present disclosure.

[0015] Figure 1B yes Figure 1A The microelectronic device shown in the document is about Figure 2A The simplified partial cross-sectional view of line AA depicted in the figure.

[0016] Figure 1C yes Figure 1A The microelectronic device shown in the document is about Figure 2A The simplified partial cross-sectional view of line BB depicted in the figure.

[0017] Figure 2A It is included according to the embodiments of this disclosure. Figures 1A to 1C A simplified partial top view of the memory device of the microelectronic device shown in the image.

[0018] Figure 2B yes Figure 2A The memory device shown in the document is about Figure 2A The simplified partial cross-sectional view of line AA depicted in the figure.

[0019] Figure 2C yes Figure 2A The memory device shown in the document is about Figure 2A The simplified partial cross-sectional view of line BB depicted in the figure.

[0020] Figure 3 This is a schematic block diagram illustrating an electronic system according to an embodiment of the present disclosure. Detailed Implementation

[0021] The following description provides specific details, such as material composition, shape, and dimensions, to provide a comprehensive description of embodiments of this disclosure. However, those skilled in the art will understand that embodiments of this disclosure can be practiced without these specific details. In practice, embodiments of this disclosure can be practiced in conjunction with conventional microelectronic device manufacturing techniques used in industry. Furthermore, the description provided below does not form a complete process flow for manufacturing microelectronic devices. The structures described below do not form a complete microelectronic device. Only those process actions and structures necessary for understanding embodiments of this disclosure are described in detail below. Additional actions to form a complete microelectronic device can be performed by the structures using conventional manufacturing techniques.

[0022] The accompanying drawings presented herein are for illustrative purposes only and are not intended to be actual views of any particular material, component, structure, device, or system. Variations in the shapes depicted in the drawings can be expected due to, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes or areas shown, but rather include shape deviations, for example, due to manufacturing processes. For example, an area shown or described as box-shaped may have rough and / or non-linear characteristics, and an area shown or described as circular may contain some rough and / or linear characteristics. Furthermore, acute angles shown may be rounded, and vice versa. Therefore, the areas shown in the figures are schematic in nature, and their shapes are not intended to show the precise shape of the areas and do not limit the scope of the claims. The drawings are not necessarily drawn to scale. Additionally, elements common to each other in the drawings may retain the same numerical designations.

[0023] As used herein, “memory device” means and includes microelectronic devices that present, but are not limited to, memory functions.

[0024] As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” refer to the principal plane of the reference structure and are not necessarily defined by the Earth’s gravitational field. A “horizontal” or “lateral” direction is a direction substantially parallel to the principal plane of the structure, while a “vertical” or “longitudinal” direction is a direction substantially perpendicular to the principal plane of the structure. The principal plane of the structure is defined by structural surfaces that have a relatively large area compared to the other surfaces of the structure.

[0025] As used herein, “vertically adjacent” or “longitudinally adjacent” features (e.g., areas, structures, devices) refer to and include features that are most vertically close to each other (e.g., vertically closest). Similarly, as used herein, “horizontally adjacent” or “horizontally adjacent” features (e.g., areas, structures, devices) refer to and include features that are most horizontally close to each other (e.g., horizontally closest).

[0026] As used in this article, the term "spacing" refers to the distance between identical points in two adjacent features.

[0027] As used herein, spatial relative terms such as “beneath,” “below,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “rear,” “left,” “right,” etc., may be used to describe the relationship of one element or feature to another, as illustrated in the figures. Unless otherwise stated, spatial relative terms are intended to cover different orientations of material other than those depicted in the figures. For example, if the material in the figures were inverted, an element described as “below,” “below,” or “at the bottom” of other elements or features would be oriented as “above” or “at the top” of other elements or features. Thus, depending on the context in which the term is used, the term “below” can encompass both above and below orientations, as will be apparent to those skilled in the art. Material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0028] As used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms, unless the context explicitly indicates otherwise.

[0029] As used in this article, "and / or" includes any and all combinations of one or more associated listed items.

[0030] As used herein, the term “configured” refers to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device that facilitates the operation of one or more of the structure and device in a predetermined manner.

[0031] As used herein, the phrase “coupled to” refers to structures that are operatively connected to each other, such as by direct ohmic connection or by indirect connection (e.g., by another structure) electrical connection.

[0032] As used herein, the term "substantially" means with reference to a given parameter, property, or condition and includes, to a certain extent, a degree of variance that a given parameter, property, or condition will be understood by one of ordinary skill in the art to be satisfied, such as within acceptable tolerances. For example, depending on the specific parameter, property, or condition substantially satisfied, the parameter, property, or condition may be satisfied at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or even at least 100.0%.

[0033] As used herein, “about” or “close” to a numerical value for a particular parameter includes the value itself, and those skilled in the art will understand that the deviation from that value is within acceptable tolerances for the particular parameter. For example, “about” or “close” to a reference value may include additional values ​​within the range of 90.0% to 110.0% of the value, such as within the range of 95.0% to 105.0%, 97.5% to 102.5%, 99.0% to 101.0%, 99.5% to 100.5%, or 99.9% to 100.1%.

[0034] As used herein, the term “two-dimensional material” or “2D material” means and comprises crystalline materials formed and contained in a single (e.g., only one) monolayer or multiple (e.g., two (2) layers) of units (e.g., atoms, molecules) bound together by intramolecular forces (e.g., covalent bonds). In other words, a 2D material can be characterized as a crystalline material comprising about one or more monolayers bound together by intramolecular forces.

[0035] As used herein, the term "NMOS" transistor refers to and includes so-called metal-oxide-semiconductor transistors having a P-type channel region, an N-type channel region, or an I-type channel region. The gate of an NMOS transistor may include a conductive metal, such as another conductive material, such as polysilicon, or a combination thereof. As used herein, the term "PMOS" transistor refers to and includes so-called metal-oxide-semiconductor transistors having a P-type channel region, an N-type channel region, or an I-type channel region. The gate of a PMOS transistor may include a conductive metal, such as another conductive material, such as polysilicon, or a combination thereof. Therefore, the gate structure of these transistors may include a conductive material that is not necessarily metallic.

[0036] Figure 1A This is a simplified partial top view of a microelectronic device 100 according to an embodiment of the present disclosure. Figure 1B yes Figure 1A Part of the microelectronic device 100 shown in the document is about Figure 1A The simplified partial cross-sectional view of line AA depicted in the figure. Figure 1C yes Figure 1A Part of the microelectronic device 100 shown in the document is about Figure 1A The figure depicts a simplified partial cross-sectional view of line BB. This is for clarity and ease of understanding of the accompanying drawings and related descriptions, and is not intended to obscure the true meaning of the figures. Figures 1A to 1C All components (e.g., features, structures, devices) of a microelectronic device 100 depicted in one of the diagrams are in Figures 1A to 1C They are depicted in relation to each other. For example, some components of the microelectronic device 100 vertically cover other components of the microelectronic device 100 that are not in the same position. Figure 1A This is displayed to provide a clearer top view of other components.

[0037] refer to Figure 1A The microelectronic device 100 may include: a dielectric structure 104 covering an isolation structure 102; a 2D material structure 106 extending above and between the dielectric structure 104; a gate structure 118 covering a region (e.g., a channel region) of the 2D material structure 106; and local contact structures 114 and global contact structures 116 coupled to additional regions (e.g., source regions, drain regions) of the 2D material structure 106. As described in further detail below, the microelectronic device 100 may include, in addition to Figure 1A Additional components (e.g., features, structures, areas, devices) beyond those described in the text.

[0038] The isolation structure 102 (e.g., an interlayer dielectric (ILD) structure) may be formed of one or more dielectric materials and may contain one or more dielectric materials, such as at least one dielectric oxide material (e.g., silicon oxide (SiO2)). xPhosphorus silicate glass, borosilicate glass, borosilicate-phosphorus silicate glass, fluorosilicate glass, alumina (AlO) x ), Hafnium oxide (HfO) x ), niobium oxide (NbO) x Titanium oxide (TiO) x Zirconium oxide (ZrO) x ), tantalum oxide (TaO) x ) and magnesium oxide (MgO) x One or more of the following), at least one dielectric nitride material (e.g., silicon nitride (SiN) y ()), at least one dielectric oxynitride material (e.g., silicon oxynitride (SiO2) x N y and at least one dielectric carbonitride material (e.g., silicon carbonitride (SiO2)). x C z N y One or more of the following. This document contains one or more of the formulas containing "x", "y", and "z" (e.g., SiO2). x AlO x HfO x NbO x TiO x SiN y SiO x N y SiO x C z N yThe formula represents the average ratio of "x" atoms of one element, "y" atoms of another element, and "z" atoms of an additional element (if any) for each atom of another element (e.g., Si, Al, Hf, Nb, Ti). Because the formula represents relative atomic ratios rather than strict chemical structures, the isolation structure 102 can include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of "x", "y", and "z" (if any) can be integers or non-integers. As used herein, the term "non-stoichiometric compound" refers to and comprises compounds having elements that cannot be expressed by a definite natural number ratio and violate definite proportionality laws. The isolation structure 102 contains at least one dielectric material in a substantially uniform or substantially non-uniform distribution. As used herein, the term "uniform distribution" means that the relative amount of material does not vary in different parts of the structure (e.g., different horizontal parts, different vertical parts). Conversely, as used herein, the term "non-uniform distribution" means that the relative amount of material varies in different parts of the structure. In some embodiments, the isolation structure 102 exhibits a substantially uniform distribution of dielectric material. In a further embodiment, the isolation structure 102 exhibits a substantially non-uniform distribution of at least one dielectric material. The isolation structure 102 may be formed, for example, by a stack (e.g., a lamination) of at least two different dielectric materials and may contain a stack (e.g., a lamination) of at least two different dielectric materials. In some embodiments, the isolation structure 102 is formed of silicon dioxide (SiO2) and contains silicon dioxide (SiO2).

[0039] The dielectric structure 104 can be presented in a first horizontal direction (e.g., Figure 1A The horizontally elongated shapes (e.g., fin shapes, sheet shapes, elliptical shapes) extending parallel to each other in the Y direction (as shown herein). The term "parallel" as used herein means substantially parallel. In some embodiments, each dielectric structure 104 exhibits substantially the same dimensions (e.g., in the X direction (…)). Figure 1A and 1C The width W1 is basically the same in the X direction and in the Y direction orthogonal to the X direction. Figure 1A The length L1 is basically the same in the Z direction and in the Z direction ( Figure 1C (The height H1 is essentially the same in both directions, as is the shape and spacing in the X direction.) Figure 1A and 1CThe distance D1 is substantially the same on both sides. In additional embodiments, at least one dielectric structure 104 presents one or more of a different size (e.g., different length, different width, different height) and a different shape from one or more other dielectric structures 104, and / or the distance between at least one pair of horizontally adjacent dielectric structures 104 is different from the distance between at least another pair of horizontally adjacent dielectric structures 104. The size, shape, and spacing of the dielectric structures 104 can be selected to provide the desired size and shape to the 2D material structure 106, as described in further detail below. As a non-limiting example, the dielectric structures 104 may each individually present an aspect ratio (e.g., height H1) in the range of about 2:1 to about 5:1 (e.g., about 2:1 to about 3:1). Figure 1C ) and width W1 ( Figure 1A and 1C The ratio of the width W1 of each dielectric structure 104 to the distance D1 (e.g., spacing) between horizontally adjacent dielectric structures 104 can range from about 0.1:1 to about 10:1. In some embodiments, each of the dielectric structures 104 exhibits a width W1 of about 100 nm. Figure 1A and 1C ), and height H1 in the range of approximately 10 nm to approximately 500 nm. Figure 1C ) and the distance D1 between horizontally adjacent dielectric structures 104 Figure 1A and 1C (Approximately 10 nm to approximately 100 nm)

[0040] The dielectric structure 104 may be formed of at least one dielectric material and may contain at least one dielectric material, such as at least one dielectric oxide material (e.g., SiO2). x Phosphorosilicate glass, borosilicate glass, borosilicate-phosphorosilicate glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x TaO x and MgO x One or more of the following), at least one dielectric nitride material (e.g., SiN). y ), and at least one dielectric oxide nitride material (e.g., SiO2). x N y ) and at least one dielectric carbonitride material (e.g., SiO2) x C z N yOne or more of the dielectric structures 104. Each of the dielectric structures 104 may individually comprise a substantially uniform or substantially non-uniform distribution of at least one dielectric material. In some embodiments, each of the dielectric structures 104 exhibits a substantially uniform distribution of dielectric material. In a further embodiment, at least one of the dielectric structures 104 exhibits a substantially non-uniform distribution of at least one dielectric material. One or more dielectric structures 104 may be formed, for example, by and comprise a stack (e.g., a lamination) of at least two different dielectric materials. In some embodiments, each of the dielectric structures 104 is formed of and comprises aluminum oxide (Al2O3). For example, each of the dielectric structures 104 may comprise crystalline Al2O3 having a hexagonal or rhombic crystal structure.

[0041] Common Reference Figure 1A and 1C The 2D material structure 106 can be formed on or above the surfaces (e.g., upper surface, side surface) of the isolation structure 102 and the dielectric structure 104. Figure 1C As shown, the 2D material structure 106 can be at least partially (e.g., substantially) conformable to the morphology defined by the surface (e.g., upper surface, side surface) on which the 2D material structure 106 is formed. The 2D material structure 106 can extend (e.g., continuously) over the surfaces (e.g., upper surface, side surface) of the insulating structure 102 and the dielectric structure 104. The 2D material structure 106 partially (e.g., less than completely) fills the trenches (e.g., openings) horizontally sandwiched between the dielectric structures 104 (e.g., in the X direction). The 2D material structure 106 can be formed with a desired thickness T1, at least in part depending on the horizontal distance (e.g., in the X direction) between horizontally adjacent dielectric structures 104. For example, the 2D material structure 106 can exhibit a thickness T1 of less than or equal to about 10 nanometers (nm), such as less than or equal to about 8 nm, less than or equal to about 6 nm, or less than or equal to about 4 nm. In some embodiments, the thickness T1 of the 2D material structure 106 is in the range of about 1 nm to about 4 nm.

[0042] The 2D material structure 106 may be formed from one or more transition metal dichalcogenides (TMDCs) having the general chemical formula Mx = 2 and may contain a transition metal dichalcogenide (TMDC), wherein M is a transition metal (e.g., molybdenum (Mo), tungsten (W), niobium (Nb), zirconium (Zr), hafnium (Hf), rhenium (Re), platinum (Pt), titanium (Ti), tantalum (Ta), vanadium (V), cobalt (Co), cadmium (Cd), chromium (Cr)) and X is a chalcogenide (e.g., sulfur (S), selenium (Se), tellurium (Te)); a carbide or carbonitride having the general chemical formula Mx = 2. n+1 X n (Also known as "MXene") and contains oxygen (-O), hydroxyl (-OH) or fluorine (-F) surface terminals, where M is a transition metal of group IV or V of the periodic table (e.g., Ti, Hf, Zr, V, Nb, Ta), and X is selected from carbon (C) and nitrogen (N); graphene; graphene oxide; stanene; phosphine; hexagonal boron nitride (h-BN); borographene; silicene; graphene; germanene; germanane; 2D supercrystals; and monolayers of semiconductor materials. In some embodiments, the 2D material structure 106 comprises one or more TMDC monolayers, such as one or more monolayers of tungsten sulfide (WS2), tungsten selenide (WSe2), tungsten telluride (WTe2), molybdenum sulfide (MoS2), molybdenum selenide (MoSe2), molybdenum telluride (MoTe2), niobium sulfide (NbS2), niobium selenide (NbSe2), niobium telluride (NbTe2), zirconium sulfide (ZrS2), zirconium selenide (ZrSe2), zirconium telluride (ZrTe2), hafnium sulfide (HfS2), hafnium selenide (HfSe2), hafnium telluride (ZrTe2), rhenium sulfide (ReS2), rhenium selenide (ReSe2), and rhenium telluride (ReTe2). In some embodiments, the electron mobility of the 2D material structure 106 is approximately 10 square centimeters per volt-second (cm). 2 / V·s) to approximately 400cm 2 Within the range of / V·s (e.g., at approximately 150cm) 2 / V·s to approximately 400cm 2 Within the range of / V·s, for example, approximately 150cm 2 / V·s to approximately 200cm 2 The band gap is in the range of about 1.2 electron volts (eV) to about 2.5 eV (e.g., in the range of about 1.8 eV to about 2.5 eV). As a non-limiting example, the 2D material structure 106 may include one or more of WS2, WSe2, MoS2, and MoSe2. In some embodiments, the 2D material structure 106 is WSe2. In additional embodiments, the 2D material structure 106 is WS2. In further embodiments, the 2D material structure 106 is MoSe2.

[0043] refer to Figure 1B The 2D material structure 106 can be formed to include a channel region 108, a first conductive doped region 110, and a second conductive doped region 112. Each of the channel regions 106 of the 2D material structure 108 can be individually (e.g., in the Y direction) horizontally sandwiched between a pair (e.g., two (2)) of first conductive doped regions 110, and each pair of first conductive doped regions 110 can be individually horizontally (e.g., in the Y direction) sandwiched between a pair (e.g., two (2)) of second conductive doped regions 112. As described in further detail below, the first conductive doped region 110 can be used as an offset region (e.g., a lateral double diffusion (LDD) offset region) to horizontally offset the first conductive doped region 110 from the gate structure 118, and the second conductive doped region 112 can be used as the source and drain regions of a transistor (e.g., a driver transistor of a string driver transistor) including the gate structure 118, the channel region 108, the first conductive doped region 110, and the second conductive doped region 112. As a non-limiting example, Figure 1B As shown, the second conductive doped region 112 may include a source region 112A and a drain region 112B. Each source region 112A may be horizontally separated from its closest horizontally adjacent drain region 112B (e.g., in the Y direction) by one of the channel regions 108 between the two (2) first conductive doped regions 110 and the two (2) first conductive doped regions 110. A single (e.g., only one) source region 112A may be shared by two (2) horizontally adjacent transistors of the microelectronic device 100.

[0044] The first conductive doped region 110 and the second conductive doped region 112 (e.g., source region 112A, drain region 112B) of the 2D material structure 106 can be doped with any desired dopant. In some embodiments, the first conductive doped region 110 and the second conductive doped region 112 are doped with at least one N-type dopant (e.g., one or more of phosphorus, arsenic, antimony, and bismuth), and the first conductive doped region 110 is doped to exhibit relatively fewer free electrons than the second conductive doped region 112. For example, the first conductive doped region 110 may include N... - The second conductive doped region 112 may include N + In some such embodiments, the channel region 108 is doped with at least one p-type dopant (e.g., one or more of boron, aluminum, and gallium). In additional embodiments, the first conductive doped region 110 and the second conductive doped region 112 are doped with at least one p-type dopant (e.g., one or more of boron, aluminum, and gallium), and the first conductive doped region 110 is doped to exhibit a relatively smaller valence electron deficiency (often referred to as "holes") than the second conductive doped region 112. For example, the first conductive doped region 110 may include p-type dopant.- The second conductive doped region 112 may include P + In some such embodiments, the channel region 108 is doped with at least one N-type dopant (e.g., one or more of phosphorus, arsenic, antimony, and bismuth). In further embodiments, one or more of the first conductive doped region 110 and the second conductive doped region 112 of the 2D material structure 106 are substantially undoped. For example, the characteristics of the 2D material structure 106 (e.g., the 2D material composition) may allow one or more of the first conductive doped region 110 and the second conductive doped region 112 to include an I-type region.

[0045] Continue to refer to Figure 1B The local contact structure 114 and the global contact structure 116 can contact (e.g., electrical contact, physical contact) the second conductive doped region 112 of the 2D material structure 106. For example, the local contact structure 114 can physically contact the drain region 112B of the 2D material structure 106, and the global contact structure 116 can physically contact the source region 112A of the 2D material structure 106. The local contact structure 114 can be formed to extend vertically downward from the drain region 112B of the 2D material structure 106 (e.g., in the negative Z direction) and through the isolation structure 102 below the 2D material structure 106; the global contact structure 116 can be formed to extend vertically upward from the source region 112A of the 2D material structure 106 (e.g., in the positive Z direction). Figure 1BAs shown, in some embodiments, the local contact structure 114 is formed to extend vertically downward from the upper boundary of the drain region 112B of the 2D material structure 106, such that the local contact structure 114 extends vertically through the drain region 112B of the 2D material structure 106; and the global contact structure 116 is formed to extend vertically upward from the upper boundary of the source region 112A of the 2D material structure 106. In an additional embodiment, the local contact structure 114 is formed to extend vertically downward from the lower boundary of the drain region 112B of the 2D material structure 106, such that the local contact structure 114 does not extend vertically through the drain region 112B of the 2D material structure 106; and / or the global contact structure 116 is formed to extend vertically upward from the lower boundary of the source region 112A of the 2D material structure 106, such that the global contact structure 116 extends vertically through the source region 112A of the 2D material structure 106. As described in further detail below, local contact structure 114 can electrically connect the 2D material structure 106 of microelectronic device 100 to additional structures (e.g., additional conductive structures, such as conductive line structures and / or additional conductive contact structures) and / or devices vertically located below microelectronic device 100; and global contact structure 116 can electrically connect the 2D material structure 106 of microelectronic device 100 to additional structures and / or devices vertically covering microelectronic device 100. In an additional embodiment, local contact structure 114 and / or global contact structure 116 physically contact a first conductive doped region 110 of 2D material structure 106 instead of a second conductive doped region 112. In a further embodiment, local contact structure 114 and / or global contact structure 116 physically contact both the first conductive doped region 110 and the second conductive doped region 112 of 2D material structure 106.

[0046] The local contact structure 114 and the global contact structure 116 may each be individually formed of at least one conductive material and contain at least one conductive material, such as at least one metal (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)); at least one alloy (e.g., C The materials selected include: Al-based alloys, Cu-based alloys, magnesium (Mg)-based alloys, Ti-based alloys, steel, low-carbon steel, and stainless steel; at least one conductive doped semiconductor material (e.g., conductive doped polycrystalline silicon, conductive doped germanium (Ge), conductive doped silicon-germanium (SiGe)); and at least one conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). The local contact structure 114 and the global contact structure 116 may contain a substantially uniform distribution of conductive material, or may contain a substantially non-uniform distribution of conductive material. If one or more of the local contact structures 114 and global contact structures 116 exhibit a substantially non-uniform distribution of conductive material, the amount of conductive material may vary gradually (e.g., abruptly) or continuously (e.g., gradually, such as linearly or parabolically) throughout the different portions of one or more of the local contact structures 114 and global contact structures 116. In some embodiments, the local contact structures 114 and global contact structures 116 each individually exhibit a substantially uniform distribution of conductive material. In additional embodiments, at least one of the local contact structures 114 and at least one of the global contact structures 116 exhibits a substantially non-uniform distribution of at least one conductive material. For example, at least one of the local contact structures 114 and at least one of the global contact structures 116 may be formed by and comprise a stack of at least two different conductive materials.

[0047] Common Reference Figure 1A and 1B The gate structure 118 can vertically cover (e.g., in the Z direction) the channel region 108 of the 2D material structure 106. Figure 1B ), and can be presented in the dielectric structure 104 ( Figure 1A The first horizontal direction (e.g., the Y direction) extends orthogonally to the second horizontal direction (e.g., the X direction). Figure 1AThe gate structure 118 may be a horizontally elongated shape (e.g., elliptical or rectangular) extending parallel to the channel region 108 of the 2D material structure 106. Each of the gate structures 118 may be individually horizontally sandwiched between one of the source regions 112A of the 2D material structure 106 and one of the drain regions 112B of the 2D material structure 106 that is most horizontally close (e.g., in the Y direction) to one of the source regions 112A. The gate structures 118 may each exhibit substantially the same dimensions as each other (e.g., width W2 in the Y direction). Figure 1A and 1B ), length in the X direction ( Figure 1A ) and the height H2 in the Z direction ( Figure 1B and 1C )) and shape. In some embodiments, each of the gate structures 118 exhibits a width W2 of approximately 18.5 micrometers (μm), and the distance D2 between some horizontally adjacent gate structures is ( Figure 1A and 1B It is approximately 30.5 μm.

[0048] The gate structure 118 may be formed of and contain at least one conductive material, such as at least one metal (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al), at least one alloy (e.g., Co-based alloy, Fe-based alloy, Ni-based alloy, Fe and Ni-based alloy, Co and Ni-based alloy, Fe and Co-based alloy, Co- and Ni- and Fe-based alloy, Al-based alloy, Cu-based alloy, magnesium (Mg)-based alloy, Ti-based alloy, steel, low-carbon steel, stainless steel), at least one conductive doped semiconductor material (e.g., conductive doped polysilicon, conductive doped Ge, conductive doped SiGe), and at least one conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). The gate structure 118 may contain a substantially uniform distribution of the conductive material or may contain a substantially non-uniform distribution of the conductive material. If the gate structure 118 exhibits a substantially non-uniform distribution of conductive material, the amount of conductive material can vary gradually (e.g., abruptly) or continuously (e.g., gradually, such as linearly or parabolically) throughout different portions of the gate structure 118. In some embodiments, each gate structure 118 exhibits a substantially uniform distribution of conductive material. In additional embodiments, one or more (e.g., each) gate structures 118 exhibit a substantially non-uniform distribution of at least one conductive material. One or more of the gate structures 118 may, for example, be formed by and comprise a stack of at least two different conductive materials.

[0049] refer to Figure 1C The microelectronic device 100 may further include a conductive structure 120 extending vertically (e.g., in the Z direction) from the gate structure 118 to the channel region 108 of the 2D material structure 106. The conductive structure 120 can effectively serve as a protrusion or extension of the gate structure 118 to accommodate a non-planar structure of the 2D material structure 106 realized by a combination of the dielectric structure 104 and the isolation structure 102. The conductive structure 120 may be horizontally sandwiched (e.g., in the X direction) between horizontally adjacent dielectric structures 104. The conductive structure 120 is partially (e.g., less than fully filled) horizontally sandwiched in portions of trenches (e.g., openings) between dielectric structures 104 (e.g., portions of trenches not occupied by the 2D material structure 106) (e.g., in the X direction). The conductive structure 120 can be formed to any desired size, at least in part depending on the size of the dielectric structure 104 (e.g., the Y direction of the gate structure 118). Figure 1A Width, dimensions (e.g., X direction) on the surface ( Figure 1CWidth in the Z direction, Z direction Figure 1C Height on the x-axis and spacing (e.g., in the x-direction) Figure 1C The dimensions (e.g., thickness) of the 2D material structure 106. The conductive structures 120 can each be individually positioned in the Y direction ( Figure 1A The gate structure 118 is similar to the gate structure 118 in the Y direction. Figure 1A The widths are basically equal in the Z direction and can be in the Z direction. Figure 1C It exhibits a height of H3 and in the X direction ( Figure 1C The conductive structure 120 exhibits a thickness T2, thereby allowing all portions of the conductive structure 120 that are close to the 2D material structure 106 in the X and Z directions to be offset substantially equally (e.g., spaced apart).

[0050] The conductive structure 120 may be formed of and contain at least one conductive material, such as at least one metal (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al), at least one alloy (e.g., Co-based alloy, Fe-based alloy, Ni-based alloy, Fe and Ni-based alloy, Co and Ni-based alloy, Fe and Co-based alloy, Co- and Ni- and Fe-based alloy, Al-based alloy, Cu-based alloy, magnesium (Mg)-based alloy, Ti-based alloy, steel, low-carbon steel, stainless steel), at least one conductive doped semiconductor material (e.g., conductive doped polycrystalline silicon, conductive doped Ge, conductive doped SiGe), and at least one conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). The conductive structure 120 may contain a substantially uniform distribution of the conductive material, or it may contain a substantially non-uniform distribution of the conductive material. If the conductive structure 120 exhibits a substantially non-uniform distribution of conductive material, the amount of conductive material can vary gradually (e.g., abruptly) or continuously (e.g., gradually, such as linearly or parabolically) in different portions of the conductive structure 120. In some embodiments, each conductive structure 120 exhibits a substantially uniform distribution of conductive material. In additional embodiments, one or more (e.g., each) conductive structures 120 exhibit a substantially non-uniform distribution of at least one conductive material. One or more of the conductive structures 120 may, for example, be formed by and comprise a stack of at least two different conductive materials. The material composition of the conductive structure 120 may be substantially the same as the material composition of the gate structure 118, or the material composition of the conductive structure 120 may be different from the material composition of the gate structure 118. In some embodiments, the material composition of the conductive structure 120 is substantially the same as the material composition of the gate structure 118.

[0051] Continue to refer to Figure 1C The microelectronic device 100 may further include a gate dielectric material 122 positioned between (e.g., horizontally or vertically) the 2D material structure 106 and the gate structure 118 and conductive structure 120. The gate dielectric material 122 may extend from the boundary (e.g., horizontal or vertical) of the 2D material structure 106 to the relative boundary (e.g., horizontal or vertical) of the gate structure 118 and conductive structure 120. The gate dielectric material 122 may fill the remaining portion of a trench (e.g., an opening) horizontally sandwiched between the dielectric structures 104 (e.g., trench portions not occupied by the 2D material structure 106 and conductive structure 120) (e.g., in the X direction). The gate dielectric material 122 may be formed to a desired thickness T3, at least in part depending on the dimensions of the gate structure 118 (e.g., width W2). Figure 1A The dimensions of the conductive structure 120 (e.g., width W2) Figure 1A ), height H3 ( Figure 1C ); The dimensions of dielectric structure 104 (e.g., width W1) Figure 1C ), height H2 ( Figure 1C )) and interval (e.g., distance D1) Figure 1C ); Dimensions of the 2D material structure 106 (e.g., thickness T1) Figure 1C )); and the distance between the upper surface of the dielectric structure 104 and the lower surface of the gate structure 118 (e.g., in the Z direction ( Figure 1C As a non-limiting example, the gate dielectric material 122 may be formed to have a thickness T3 of less than or equal to about 15 nm, for example, less than or equal to about 10 nm, less than or equal to about 8 nm, or less than or equal to about 5 nm. In some embodiments, the gate dielectric material 122 has a thickness T3 in the range of about 5 nm to about 10 nm.

[0052] Gate dielectric material 122 may be formed of at least one dielectric material and may contain at least one dielectric material, such as at least one oxide dielectric material (e.g., SiO2). x AlO x One or more of the following: phosphosilicate glass, borosilicate glass, borophosphosilicate glass, and fluorosilicate glass; at least one nitride dielectric material (e.g., SiN). y and at least one low-k dielectric material (e.g., silicon dioxide (SiO2)). x C y ), silicon oxynitride (SiO) x N y ), hydrogenated carbon silicon oxide (SiC) x O y Hz ) and silicon dioxide (SiO2) x C z N y One or more of the following. The gate dielectric material 122 may comprise a substantially uniform or substantially non-uniform distribution of at least one dielectric material. In some embodiments, the gate dielectric material 122 exhibits a substantially uniform distribution of dielectric material. In a further embodiment, the gate dielectric material 122 exhibits a substantially non-uniform distribution of at least one dielectric material. In some embodiments, the gate dielectric material 122 is formed of and comprises SiO2.

[0053] refer to Figure 1B The gate structure 118, the gate dielectric material 122, and the channel region 108 and first conductive doped region 110 (including source region 112A and drain region 112B) of the 2D material structure 106 can form a transistor 124 of the microelectronic device 100 (e.g., a drive transistor of a string drive transistor). Each of the transistors 124 may include one of the gate structures 118, one of the gate dielectric material 122, one of the channel regions 108 of the 2D material structure 106, one of the drain regions 112B of the 2D material structure 106, and one of the source regions 112A of the 2D material structure 106. Each of the transistors 124 also includes a conductive structure 120 extending vertically from its gate structure 118. Figure 1C In some embodiments, transistor 124 includes a high-voltage (HV) transistor (e.g., an HVNMOS transistor, an HVPMOS transistor). The HV transistor operates at a voltage higher than that of a non-HV transistor (e.g., an NMOS transistor, a PMOS transistor). For example, an HV transistor may have a threshold voltage greater than the threshold voltage range of a non-HV transistor (e.g., about +0.5V to about +0.7V), such that the threshold voltage is greater than or equal to about +3V, which is higher than the threshold voltage range of a non-HV transistor. For example, if the first conductive doped region 110 of the 2D material structure 106 is doped with at least one N-type dopant, then transistor 124 includes an HVNMOS transistor. As another example, if the first conductive doped region 110 of the 2D material structure 106 is doped with at least one P-type dopant, then transistor 124 includes an HVPMOS transistor.

[0054] The non-planar morphology of the 2D material structure 106 (e.g., formed by the isolation structure 102 and dielectric structure 104 on which the 2D material structure 106 is formed) Figure 1A and 1CThe surface definition of the 2D material structure 106 provides a so-called "folded channel" configuration for transistor 124. Compared to conventional transistors that do not exhibit the folded channel structure of this disclosure (e.g., conventional transistors exhibiting a substantially planar channel configuration), the folded channel configuration of transistor 124 can provide transistor 124 with a larger effective channel width. Additionally, the material composition of the 2D material structure 106 can provide the channel region 108 of transistor 124 with a higher bandgap and comparable (or greater) electron mobility than conventional transistors that use semiconductor materials such as silicon and polysilicon as their channel regions. Therefore, the 2D material structure 106 can promote more favorable electrical characteristics (e.g., relatively higher on-state current (I0)) in transistor 124 of this disclosure compared to conventional transistors. on ), and relatively low turn-off current (I off (One or more of the following: relatively fast switching speed, improved breaking voltage (BV), relatively low operating voltage, relatively reduced current leakage, and relatively less scattering at the interface between the channel region 108 and the gate dielectric material 122). Additionally, the 2D material structure 106 can be formed at a relatively low temperature (e.g., less than or equal to about 600°C, for example, in the range of about 400°C to about 600°C, or less than or equal to about 400°C) to reduce or eliminate temperature incompatibility with other structures and / or devices below the microelectronic device 100.

[0055] Therefore, according to embodiments of this disclosure, a transistor includes a 2D material structure and a gate structure. The 2D material structure extends conformally between and on the surface of dielectric fins extending parallel to each other in a first horizontal direction, and includes a source region, a drain region, and a channel region positioned between the source and drain regions in the first horizontal direction. The gate structure covers the channel region of the 2D material structure and extends in a second horizontal direction orthogonal to the first horizontal direction. The gate structure lies within the horizontal boundary of the channel region of the 2D material structure in the first horizontal direction.

[0056] Furthermore, according to additional embodiments of this disclosure, the microelectronic device includes discrete dielectric structures, a non-planar 2D material structure, a gate structure, a conductive structure, a contact structure, and at least one additional contact structure. The discrete dielectric structures cover an isolation structure and are spaced apart from each other by filled trenches. The non-planar 2D material structure extends above the surfaces of the isolation structure and the discrete dielectric structure, both inside and outside the filled trenches, and includes conductive doped regions and channel regions between the conductive doped regions. The gate structure covers and is substantially aligned with the channel region of the non-planar 2D material structure. The conductive structure extends from the gate structure into the trenches. The contact structures are coupled to some of the conductive doped regions and extend into the isolation structure. The at least one additional contact structure is coupled to at least one of the conductive doped regions and extends away from the isolation structure.

[0057] In additional embodiments, the 2D material structure 106 may be formed substantially planar (e.g., substantially horizontal), such that the transistor including the 2D material structure 106 exhibits a substantially planar (e.g., folded) channel configuration. In these embodiments, the dielectric structure 104 may be omitted (e.g., absent). Figure 1A and 1C This results in the 2D material structure 106 extending substantially continuously and horizontally on the substantially planar upper surface of the isolation structure 102 (the 2D material structure 106 thus formed is also substantially planar); the conductive structure 120 extends vertically from the gate structure 118. Figure 1C () can also be omitted. Although these planar configurations of the channel region of the transistor can present a smaller effective channel width than the channel region 108 of the transistor 124, the material composition of the 2D material structure 106 can still impart improved electrical characteristics to the transistor compared to conventional transistors whose channel regions use semiconductor materials such as silicon and polysilicon.

[0058] and Figures 1A to 1C The microelectronic device 100 is depicted as comprising a single (e.g., only one) 2D material structure 106 and two (2) transistors 124 comprising portions of the 2D material structure 106. Figure 1B The microelectronic device 100 may include additional 2D material structures 106 and additional transistors 124 comprising portions of the additional 2D material structures 106. For example, the microelectronic device 100 may include a plurality (e.g., more than one) of 2D material structures 106 that are substantially similar to each other and spaced apart from each other on the isolation structure 102. Each of the plurality of 2D material structures 106 may individually form portions of the transistor 124 of the microelectronic device 100 (e.g., channel region 108, source region 112A, drain region 112B), and the source region 112A of the transistor 124 of the microelectronic device 100. Figure 1B ) and drain region 112B ( Figure 1B Additionally, the microelectronic device 100 may include additional local contact structures 114 and additional global contact structures 116, which are consistent with those previously referenced. Figures 1A to 1C The substantially similar manner described is operatively associated with the additional 2D material structure 106 and the additional transistor 124. The number, configuration, and arrangement of the additional 2D material structure 106, the additional transistor 124, the additional local contact structure 114, and the additional global contact structure 116 of the microelectronic device 100 may depend on the number, configuration, and arrangement of the additional structures and / or devices operatively associated with the microelectronic device 100, as further described in detail below.

[0059] Microelectronic devices according to embodiments of the present disclosure (e.g., previously referenced) Figures 1A to 1C The described microelectronic device 100 can be used in embodiments of the memory device of this disclosure. For example, Figure 2A This is a simplified partial top view of a memory device 200 (e.g., a 3D NAND flash memory device), which includes the previously referenced... Figures 1A to 1C One or more embodiments of the microelectronic device 100 described. Figure 2B yes Figure 2A A portion of the memory device 200 shown herein is about Figure 2A The simplified partial cross-sectional view of line AA depicted in the figure. Figure 2C yes Figure 2A A portion of the memory device 200 shown herein is about Figure 2A The figure depicts a simplified partial cross-sectional view of line BB. This is for clarity and ease of understanding of the accompanying drawings and related descriptions, and is not intended to be construed as a separate, unrelated statement. Figures 2A to 2C All components (e.g., features, structures, means) of the memory device 200 depicted in one of the diagrams are in Figures 2A to 2C They are depicted in relation to each other. For example, some components of memory device 200 vertically cover other components of memory device 200 that are not in the same position. Figure 2A This is displayed to provide a clearer top view of other components.

[0060] like Figure 2B and 2C As shown, the microelectronic device 100 of the memory device 200 (including the previously referenced) Figures 1A to 1C The components described may be vertically covered (e.g., in the Z direction) and operatively associated with a stacked structure 202 of the memory device 200. The stacked structure 202 includes a vertically alternating (e.g., in the Z direction) sequence of conductive structures 204 (e.g., access lines, word lines) and insulating structures 206 arranged in layer 208. Additionally, as... Figure 2A and 2CAs shown, the stacked structure 202 includes a memory array region 202A and a stepped region 202B that is horizontally adjacent to a first horizontal boundary of the memory array region 202A (e.g., in the X direction). As described in further detail below, the memory device 200 further includes additional components (e.g., features, structures, means) within the horizontal boundaries of the different regions (e.g., memory array region 202A and stepped region 202B) of the stacked structure 202.

[0061] Common Reference Figure 2B and 2C Each layer 208 of the stacked structure 202 of the memory device 200 may individually include at least one of the conductive structures 204 that are vertically adjacent to at least one of the insulating structures 206. The stacked structure 202 may include a desired number of layers 208. For example, the stacked structure 202 may include conductive structures 204 and insulating structures 206 of ten (10), twenty-five (25), fifty (50), one hundred (100), one hundred and fifty (150), or two hundred (200) layers 208 or more.

[0062] The conductive structure 204 of layer 208 of stacked structure 202 may be formed of at least one conductive material and may contain at least one conductive material, such as at least one metal (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al), at least one alloy (e.g., Co-based alloy, Fe-based alloy, Ni-based alloy, Fe and Ni-based alloy, Co and Ni-based alloy, Fe and Co-based alloy, Co- and Ni- and Fe-based alloy, Al-based alloy, Cu-based alloy, magnesium (Mg)-based alloy, Ti-based alloy, steel, low carbon steel, stainless steel), at least one conductive doped semiconductor material (e.g., conductive doped polycrystalline silicon, conductive doped Ge, conductive doped SiGe), and at least one conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide) or more. In some embodiments, the conductive structure 204 is formed of and comprises a metallic material (e.g., a metal of W; an alloy). In additional embodiments, the conductive structure 204 is formed of and comprises conductive-doped polysilicon. Each of the conductive structures 204 may individually comprise a substantially uniform distribution of at least one conductive material, or a substantially non-uniform distribution of at least one conductive material. In some embodiments, each of the conductive structures 204 of each of the layers 208 of the stacked structure 202 exhibits a substantially uniform distribution of conductive material. In additional embodiments, at least one of the conductive structures 204 of at least one of the layers 208 of the stacked structure 202 exhibits a substantially non-uniform distribution of at least one conductive material. The conductive structure 204 may, for example, be formed of and comprise a stack of at least two different conductive materials. The conductive structures 204 of each of the layers 208 of the stacked structure 202 may each be substantially planar and may each exhibit a desired thickness.

[0063] The insulating structure 206 of layer 208 of stacked structure 202 may be formed of at least one dielectric material and contain at least one dielectric material, such as at least one dielectric oxide material (e.g., SiO2). x Phosphorosilicate glass, borosilicate glass, borosilicate-phosphorosilicate glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x TaO x and MgO x One or more of the following), at least one dielectric nitride material (e.g., SiN). y), and at least one dielectric oxide nitride material (e.g., SiO2). x N y and at least one dielectric carbonitride material (e.g., SiO2) x C z N y One or more of the following. In some embodiments, the insulating structure 206 is formed of and contains SiO2. Each of the insulating structures 206 may individually contain a substantially uniform distribution of at least one insulating material, or a substantially non-uniform distribution of at least one insulating material. In some embodiments, each of the insulating structures 206 of each of the layers 208 of the stacked structure 202 exhibits a substantially uniform distribution of insulating material. In additional embodiments, at least one of the insulating structures 206 of at least one of the layers 208 of the stacked structure 202 exhibits a substantially non-uniform distribution of at least one insulating material. The insulating structure 206 may be formed, for example, by and contains a stack of at least two different insulating materials (e.g., a lamination). The insulating structure 206 of each of the layers 208 of the stacked structure 202 may each be substantially planar and may each individually exhibit a desired thickness.

[0064] At least one lower conductive structure 204 of the stacked structure 202 can be used as at least one lower select gate (e.g., at least one source-side select gate (SGS)) of the memory device 200. In some embodiments, a single (e.g., only one) conductive structure 204 of the vertically bottommost layer 208 of the stacked structure 202 is used as a lower select gate (e.g., SGS) of the memory device 200. Additionally, the upper conductive structure 202 of the stacked structure 204 can be used as an upper select gate (e.g., drain-side select gate (SGD)) of the memory device 200. In some embodiments, horizontally adjacent conductive structures 204 of the vertically topmost layer 208 of the stacked structure 202 are used as upper select gates (e.g., SGDs) of the memory device 200.

[0065] refer to Figure 2A and 2B The stacked structure 202 can be divided in the Y direction by filled slots 210. The filled slots 210 can extend vertically, for example (e.g., in the Z direction). Figure 2B The stacked structure 202 is completely traversed by the filled slots 210. The filled slots 210 can divide the stacked structure 202 into multiple blocks 212 (e.g., in the Y direction). Figure 2B As shown, the filled trenches 210 can each be individually filled with at least one dielectric structure 214. The dielectric structure 214 can be formed of and contain at least one dielectric material, such as at least one dielectric oxide material (e.g., SiO2).x Phosphorosilicate glass, borosilicate glass, borosilicate-phosphorosilicate glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x TaO x and MgO x One or more of the following), at least one dielectric nitride material (e.g., SiN). y ), and at least one dielectric oxide nitride material (e.g., SiO2). x N y ) and at least one dielectric carbonitride material (e.g., SiO2) x C z N y One or more of the following. In some embodiments, dielectric structure 214 comprises SiO2. Before filling the trench 210 to become a filled trench with dielectric structure 214, for example, preliminary trenches may be used to form the conductive structure 204 of the stacked structure 202 through a so-called "replacement gate" or "post-gate" processing action. Figure 1A For example, a preliminary stacked structure comprising a vertically alternating sequence of sacrificial and preliminary insulating structures can be formed by conventional material deposition processes; a preliminary trench through at least the preliminary stacked structure can be formed by one or more conventional material removal processes to form a modified sacrificial and insulating structure 206. Figure 2B At least a portion of each of the modified sacrificial structures can be selectively removed by one or more additional conventional material removal processes to form a recessed region; the recessed region can then be at least partially (e.g., substantially) filled with a conductive material to form a conductive structure 204. Figure 2B ).

[0066] like Figure 2A As shown, each of the blocks 212 can have substantially the same width W3 (e.g., a horizontal dimension in the Y direction) as each other. Additionally, each of the blocks 212 can be spaced from each other by substantially the same distance D3 (e.g., the width corresponding to each of the filled slots 210) in the horizontally adjacent blocks 212 (e.g., in the X direction). Figure 2B This arrangement ensures that blocks 212 are spaced substantially uniformly apart from each other. Therefore, throughout the entire stacked structure 202, the spacing P1 between the centerlines of horizontally adjacent blocks 212 is... Figure 2A They can be basically unified.

[0067] For clarity and ease of understanding of the accompanying drawings and related descriptions, Figure 2A and 2BA stacked structure 202 of memory device 200 is shown, comprising three (3) blocks 212 and two (2) slots 210. However, the stacked structure 202 may comprise different numbers (e.g., quantity, number) of blocks 212 (e.g., more than three (3) blocks 212, less than three (3) blocks 212) and slots 210 (e.g., more than two (2) slots 210, less than two (2) slots 210) and / or may comprise blocks 212 (and therefore slots 210) with different distributions. The number of blocks 212 and slots 210 included in the stacked structure 202 depends at least in part on the number, size, and arrangement of additional structures included in memory device 200, as described in further detail below.

[0068] refer to Figure 2A Within the horizontal boundaries (e.g., in the X and Y directions) of the memory array region 202A of the stacked structure 202, the memory device 200 may include vertically extending pillar structures 216. Each of the vertically extending pillar structures 216 may include a semiconductor pillar (e.g., a polysilicon pillar, a silicon-germanium pillar) at least partially surrounded by one or more charge storage structures (e.g., charge trapping structures, such as charge trapping structures comprising oxide-nitride-oxide (“ONO”) materials; floating gate structures). The vertically extending pillar structures 216 and the stacked structure 202 ( Figure 2B and 2C Layer 208 () Figure 2B and 2C The conductive structure 204 () Figure 2B and 2CThe intersections of the conductive structures 204 and the vertically extending pillar structures 216 within each layer 208 of the stacked structure 202 can define vertically extending strings 218 of memory cells coupled in series with each other. In some embodiments, the memory cells 218 formed at the intersections of the conductive structures 204 and the vertically extending pillar structures 216 within each layer 208 of the stacked structure 202 include so-called "MONOS" (metal oxide-nitride-oxide-semiconductor) memory cells. In additional embodiments, the memory cells 218 include so-called "TANOS" (tantalum nitride-aluminum oxide-nitride-oxide-semiconductor) memory cells or so-called "BETANOS" (band / barrier engineered TANOS) memory cells, each of which is a subset of MONOS memory cells. In further embodiments, the memory cells 218 include so-called "floating gate" memory cells, which contain a floating gate (e.g., a metal floating gate) as a charge storage structure. The floating gate can be horizontally sandwiched between the central structure of the vertically extending pillar structure 216 and the conductive structures 204 of the different layers 208 of the stacked structure 202. The memory device 200 can be contained in any desired number and distribution of vertically extending column structures 216 within the memory array region 202A of the stacked structure 202.

[0069] Common Reference Figures 2A to 2C The memory device 200 may further include digital lines 220 vertically covering the stacked structure 202. Figure 2A and 2C (e.g., data lines, bit lines), and vertically covering at least one source structure 222 under the stacked structure 202. Figure 2B and 2C(e.g., source line, source plate). The vertically extending column structure 216 can extend substantially vertically between the digital line 220 and the source structure 222. The digital line 220 and the source structure 222 may each be individually formed of at least one conductive material and contain at least one conductive material, such as at least one metal (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al), at least one alloy (e.g., Co-based alloy, Fe-based alloy, Ni-based alloy, Fe and Ni-based alloy, Co and Ni-based alloy, Fe and Co-based alloy, Co- and Ni- and Fe-based alloy, Al-based alloy, Cu-based alloy, magnesium (Mg)-based alloy, Ti-based alloy, steel, low carbon steel, stainless steel), at least one conductive doped semiconductor material (e.g., conductive doped polycrystalline silicon, conductive doped Ge, conductive doped SiGe), and at least one conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide) or more. Digital lines 220 and source structures 222 may comprise a substantially uniform distribution of conductive material or a substantially non-uniform distribution of conductive material. If one or more of digital lines 220 and source structures 222 exhibit a substantially non-uniform distribution of conductive material, the amount of conductive material may vary gradually (e.g., abruptly) or continuously (e.g., gradually, such as linearly or parabolically) in different portions of one or more of digital lines 220 and source structures 222. In some embodiments, digital lines 220 and source structures 222 each individually exhibit a substantially uniform distribution of conductive material. In additional embodiments, at least one or more of digital lines 220 and source structures 222 exhibit a substantially non-uniform distribution of at least one conductive material. For example, at least one or more of digital lines 220 and source structures 222 may be formed by and comprise a stack of at least two different conductive materials.

[0070] Continue to refer to Figure 2A and 2C Within the horizontal boundary (e.g., in the X direction) of the stepped area 202B of the stacked structure 202, each of the blocks 212 of the stacked structure 202 may include a stepped structure 224 at its horizontal end (e.g., in the X direction). The stepped structure 224 of each of the blocks 212 of the stacked structure 202 includes a step 226, which is at least partially defined by the horizontal end (e.g., in the X direction) of the layer 208. The step 226 of the stepped structure 224 can serve as a contact area to connect the layers 208 of the stacked structure 202. Figure 2C The conductive structure 204 () Figure 2COther components (e.g., features, structures, devices) electrically coupled to the memory device 200, as described in further detail below. Each of the step structures 224 within the step region 202B of the stacked structure 202 may individually contain a desired number of steps 226. Additionally, as Figure 2C As shown, in some embodiments, the steps 226 of each of the stepped structures 224 are arranged sequentially such that steps 226 that are directly horizontally adjacent to each other (e.g., in the X direction) correspond to layers 208 of the stacked structures 202 that are directly vertically adjacent to each other (e.g., in the Z direction). In additional embodiments, one or more steps 226 of the stepped structures 224 are not arranged sequentially such that at least some steps 226 of the stepped structures 224 that are directly horizontally adjacent to each other (e.g., in the X direction) correspond to layers 208 of the stacked structures 202 that are not directly vertically adjacent to each other (e.g., in the Z direction).

[0071] Still referencing Figure 2A and 2C The memory device 200 may further include conductive contact structures 228 that physically and electrically contact at least some (e.g., each) of the steps 226 of the stepped structure 224 of the stacked structure 202 to provide electrical access to the conductive structure 204 of the stacked structure 202. The conductive contact structures 228 may be coupled to the conductive structure 204 of the layer 208 of the stacked structure 202 at the steps 226 of the stepped structure 224. Figure 2C As shown, the conductive contact structure 228 may physically contact the conductive structure 204 of the layer 208 of the stacked structure 202 at the step 226 of the stepped structure 224 and extend vertically upward (e.g., in the positive Z direction). Each step structure 224 of each block 212 of the stacked structure 202 may contain at least one conductive contact structure 228 that physically contacts each of its step 226; or one or more step structures 224 of one or more blocks 212 of the stacked structure 202 may not have at least one conductive contact structure 228 that physically contacts at least one step 226 of its at least one step 226.

[0072] In some embodiments, each of the conductive contact structures 228 individually presents an initial columnar shape (e.g., circular column, rectangular column, oval column, column shape), and its size and position are positioned to physically contact a single (e.g., only one) step 226 of a single (e.g., only one) stepped structure 224 of the stacked structure 202 (e.g., stepped structure 224 of a single block 212). In additional embodiments, one or more of the conductive contact structures 228 present different shapes, different sizes, and / or different positions.

[0073] The conductive contact structure 228 may be formed of and contain at least one conductive material, such as metals (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al), alloys (e.g., Co-based alloys, Fe-based alloys, Ni-based alloys, Fe and Ni-based alloys, Co and Ni-based alloys, Fe and Co-based alloys, Co- and Ni- and Fe-based alloys, Al-based alloys, Cu-based alloys, Mg-based alloys, Ti-based alloys, steel, low-carbon steel, stainless steel), conductive metallic materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides), and conductive doped semiconductor materials (e.g., conductive doped Si, conductive doped Ge, conductive doped SiGe). The conductive contact structure 228 may contain a substantially uniform distribution of the conductive material, or it may contain a substantially non-uniform distribution of the conductive material. If the conductive contact structure 228 exhibits a substantially non-uniform distribution of conductive material, the amount of conductive material can vary gradually (e.g., abruptly) or continuously (e.g., gradually, such as linearly or parabolically) throughout different portions of the conductive contact structure 228. In some embodiments, each conductive contact structure 228 exhibits a substantially uniform distribution of conductive material. In additional embodiments, one or more (e.g., each) conductive contact structures 228 exhibit a substantially non-uniform distribution of at least one conductive material. One or more of the conductive contact structures 228 may, for example, be formed by and comprise a stack of at least two different conductive materials.

[0074] Common Reference Figure 2B and 2C Optionally, the memory device 200 may further include conductive structures 230 that physically contact at least some of the conductive contact structures 228 of the memory device 200. For example, the conductive structures 230 may be individually sized, shaped, and positioned to physically contact (e.g., in the X direction, in the Y direction) and extend horizontally beyond the horizontal boundaries of the conductive contact structures 228 located on the steps 226 of the stacked structure 202. In some such embodiments, each of the conductive structures 230 individually physically contacts and extends horizontally beyond the horizontal boundary of one of the conductive contact structures 228 located on one of the steps 226 of the stacked structure 202. In additional embodiments, at least some (e.g., all) of the conductive structures 230 are omitted.

[0075] The conductive structure 230, if present, may be formed of and contain at least one conductive material, such as metals (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al), alloys (e.g., Co-based alloys, Fe-based alloys, Ni-based alloys, Fe and Ni-based alloys, Co and Ni-based alloys, Fe and Co-based alloys, Co- and Ni- and Fe-based alloys, Al-based alloys, Cu-based alloys, Mg-based alloys, Ti-based alloys, steel, low-carbon steel, stainless steel), conductive metallic materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides), and conductive doped semiconductor materials (e.g., conductive doped Si, conductive doped Ge, conductive doped SiGe). The conductive structure 230 may contain a substantially uniform distribution of the conductive material or may contain a substantially non-uniform distribution of the conductive material. If the conductive structure 230 exhibits a substantially non-uniform distribution of conductive material, the amount of conductive material can vary gradually (e.g., abruptly) or continuously (e.g., gradually, such as linearly or parabolically) throughout different portions of the conductive structure 230. In some embodiments, each conductive structure 230 exhibits a substantially uniform distribution of conductive material. In additional embodiments, one or more (e.g., each) conductive contact structures 228 exhibit a substantially non-uniform distribution of at least one conductive material. One or more of the conductive structures 230 may, for example, be formed by and comprise a stack of at least two different conductive materials.

[0076] Continue to refer to Figure 2B and 2C The memory device 200 may further include an insulating material 232 on or above the stacked structure 202. The insulating material 232 may be vertically sandwiched between the stacked structure 202 and the insulating structure 102 (e.g., in the Z direction). Figure 2C As shown, the insulating material 232 can substantially cover the stepped structure 224 within the stepped region 202B of the stacked structure 202, and can substantially surround the side surface (e.g., sidewall) of the conductive contact structure 228 on the steps 226 of the stepped structure 224. The insulating material 232 can present a substantially planar upper vertical boundary and a substantially non-planar lower vertical boundary that is at least complementary to the morphology of the underlying stacked structure 202 (including its stepped structure 224).

[0077] The insulating material 232 may be formed of at least one dielectric material and may contain at least one dielectric material, such as at least one dielectric oxide material (e.g., SiO2). xPhosphorosilicate glass, borosilicate glass, borosilicate-phosphorosilicate glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x TaO x and MgO x One or more of the following), at least one dielectric nitride material (e.g., SiN). y ), and at least one dielectric oxide nitride material (e.g., SiO2). x N y ) and at least one dielectric carbonitride material (e.g., SiO2) x C z N y The insulating material 232 may comprise one or more of the following: a substantially uniform or substantially non-uniform distribution of at least one dielectric material. In some embodiments, the insulating material 232 exhibits a substantially uniform distribution of dielectric material. In further embodiments, the insulating material 232 exhibits a substantially non-uniform distribution of at least one dielectric material. The insulating material 232 may be formed, for example, by and comprise a stack (e.g., a lamination) of at least two different dielectric materials. In some embodiments, the insulating material 232 is formed of and comprises SiO2.

[0078] Common Reference Figures 2A to 2C According to embodiments of the present disclosure, the microelectronic device 100 can be vertically positioned above the stepped region 202B of the stacked structure 202 (e.g., in...). Figure 2B and 2B (as shown in the Z direction) and at least partially (e.g., substantially) within the horizontal boundary of the stepped region 202B of the stacked structure 202 (e.g., ... Figure 2A The microelectronic device 100 can be used as a string driver assembly (e.g., an HV string driver assembly) of the memory device 200. As described in further detail below, the transistor 124 of the microelectronic device 100 (…) Figure 2B (For example, the driver transistor of a series driver transistor) can be achieved through local contact structure 114 and conductive contact structure 228. Figure 2A and 2C ), and if present, conductive structure 230 ( Figure 2B and 2C Electrically coupled to the conductive structure 204 of the stacked structure 202.

[0079] like Figure 2A and 2CAs shown, multiple 2D material structures 106 of the microelectronic device 100 can be vertically covered (e.g., in...). Figure 2C The stacked structure 202 is shown in the Z direction. For example, different 2D material structures 106 of the microelectronic device 100 may individually vertically overlap and at least partially (e.g., substantially) lie within the horizontal boundaries (e.g., in the X direction) of the steps 226 of the stepped structure 224 within the stepped region 202B of the stacked structure 202. Figure 2A As shown, different 2D material structures 106 of the microelectronic device 100 can extend horizontally individually in the Y direction across different steps 226 of the stacked structure 202 and be horizontally adjacent to each other in the Y direction, and can be substantially confined within the horizontal boundaries of the different horizontally adjacent steps 226 in the X direction. As a non-limiting example, such as Figure 2A As depicted, three (3) 2D material structures 106 of microelectronic device 100 can be operatively associated with three (3) sets of steps 226 of stacked structure 202, wherein each of the three (3) 2D material structures 106 individually vertically covers and lies within the horizontal boundary (e.g., in the X direction) of one of the three (3) sets of steps 226, and each set of steps 226 individually comprises different steps 226 of stacked structure 202 that are adjacent to each other in the horizontal direction (e.g., in the Y direction) and located in substantially the same vertical position (e.g., in the Z direction) within stacked structure 202. The spacing P2 between the 2D material structures 106 of microelectronic device 100 that are horizontally adjacent to each other in the X direction can be substantially equal to (e.g., substantially the same) the spacing between the steps 226 of stacked structure 202 that are horizontally adjacent to each other in the X direction.

[0080] Continue to refer to Figure 2A and 2C The gate structure 118 of the microelectronic device 100 can be vertically covered and positioned at the horizontal boundary (e.g., in the Y direction) of the block 212 of the stacked structure 202. Figure 2A As shown, the gate structure 118 of the microelectronic device 100 can extend in a horizontal direction substantially the same as that of the block 212 of the stacked structure 202 (e.g., the X direction), and can be located within the horizontal boundary of the block 212 of the stacked structure 202 in another horizontal direction orthogonal to the horizontal directions in which the gate structure 118 and the block 212 extend (e.g., the Y direction). In some embodiments, the centerline of the gate structure 118 in the Y direction is substantially aligned with the centerline of the block 212 in the Y direction. The spacing between horizontally adjacent gate structures 118 of the microelectronic device 100 (e.g., in the Y direction) can be substantially equal to (e.g., substantially the same as) the spacing P1 between horizontally adjacent blocks 212 of the stacked structure 202 (e.g., in the Y direction). Figure 2A).

[0081] Next reference Figure 2B and 2C The local contact structure 114 of the microelectronic device 100 can extend vertically (e.g., in the Z direction) from the 2D material structure 106 of the microelectronic device 100 to the conductive structure 230. For example, as Figure 2B As shown, local contact structure 114 can extend vertically from some second conductive doped regions 112 (e.g., drain region 112B) of 2D material structure 106 to conductive structure 230. Local contact structure 114 can contact (e.g., physical contact, electrical contact) conductive structure 230. Therefore, local contact structure 114, conductive structure 230, and conductive contact structure 228 can electrically connect transistor 124 of microelectronic device 100 (e.g., drive transistor of a series drive transistor) to conductive structure 204 of layer 208 of stacked structure 202. Figure 2B and 2C As shown, the local contact structure 114 can be located within the horizontal boundary of the conductive structure 230 (e.g., in the Y direction). Figure 2B ) on and in the X direction ( Figure 2C In some embodiments, at least some (e.g., all or less all) of the local contact structures 114 are in the X direction ( Figure 2C The centerline of the conductive structure 230 that contacts (e.g., physical contact, electrical contact) on the local contact structure 114 is offset from the centerline in the X direction. In an additional embodiment, the centerlines in the X direction of at least some (e.g., all, less than all) of the local contact structures 114 are substantially aligned with the centerlines in the X direction of the conductive structure 230 that contacts (e.g., physical contact, electrical contact) on the local contact structures 114.

[0082] In additional embodiments, such as those omitting the conductive structure 230, the local contact structure 114 of the microelectronic device 100 may extend vertically (e.g., in the Z direction) from the 2D material structure 106 to the conductive contact structure 228. In these embodiments, the local contact structure 114 is at least partially (e.g., substantially) located within the horizontal boundary of the conductive contact structure 228 (e.g., in the Y direction). Figure 2B On and in the X direction ( Figure 2C Therefore, the local contact structure 114 and the conductive contact structure 228 can electrically connect the transistor 124 of the microelectronic device 100 to the conductive structure 204 of the layer 208 of the stacked structure 202.

[0083] In an additional embodiment, one or more of the local contact structures 114 of the microelectronic device 100 may extend vertically (e.g., in the Z direction) from the 2D material structure 106 to the steps 226 of the stacked structure 202. As a non-limiting example, conductive contact structures 228 and 230 may be omitted, and each of the local contact structures 114 may individually contact one of the steps 226 of the stacked structure 202. Thus, the local contact structures 114 can directly electrically connect the transistors 124 of the microelectronic device 100 to the conductive structures 204 of the layer 208 of the stacked structure 202.

[0084] although Figures 2A to 2C A microelectronic device 100 of a memory device 200 is depicted located within the horizontal boundary (e.g., in the X direction, in the Y direction) of a stepped region 202B of a stacked structure 202 of a memory device 200. One or more portions of the microelectronic device 100 may be located outside the horizontal boundary of the stepped region 202B of the stacked structure 202 of the memory device 200. For example, one or more portions (e.g., all or less) of one or more transistors 124 of the microelectronic device 100 may be located outside the horizontal boundary of the stepped region 202B of the stacked structure 202. In these embodiments, the geometric configuration of one or more of the local contact structures 114, conductive structures 230, and conductive contact structures 228 is connected (e.g., physical connection, electrical connection) to one or more portions of one or more transistors 124, which may be relative to... Figures 2A to 2C The geometric configuration depicted is modified to facilitate electrical connections between one or more transistors 124 and one or more conductive structures 204 of the stacked structure 202. As a non-limiting example, routes (e.g., paths) to one or more conductive structures 230 electrically connected to one or more transistors 124 can be shaped to extend outside the horizontal boundary of the stepped region 202B of the stacked structure 202 and to the local contact structure 114 that contacts one or more transistors 124.

[0085] Therefore, according to an additional embodiment of this disclosure, a memory device includes a stacked structure, a stepped structure, a string driver transistor, at least one additional conductive structure, and a string of memory cells. The stacked structure includes vertically alternating conductive and insulating structures arranged in layers. A stepped structure is located at a horizontal end of the stacked structure. The stepped structure has steps including the edges of the layers. The string driver transistor vertically covers the stepped structure and includes a channel region comprising at least one 2D material. The at least one additional conductive structure extends from the string driver transistor and one of the steps of the stepped structure and extends therebetween. The string of memory cells extends vertically through the stacked structure.

[0086] Microelectronic devices according to embodiments of the present disclosure (e.g., previously referenced) Figures 1A to 1C The microelectronic device 100 described herein and the memory device (e.g., previously referenced) Figures 2A to 2C The described memory device 200 can be used in embodiments of the electronic systems disclosed herein. For example, Figure 3 This is a block diagram of an illustrative electronic system 300 according to embodiments of the present disclosure. The electronic system 300 may include, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet, etc. or Tablets, e-books, navigation devices, etc. Electronic system 300 includes at least one memory device 302. Memory device 302 may include, for example, microelectronic devices previously described herein (e.g., previously referenced...). Figures 1A to 1C The microelectronic device 100 described herein and the memory device (e.g., previously referenced) Figures 2A to 2C The electronic system 300 may further include at least one electronic signal processor device 304 (generally referred to as a “microprocessor”). The electronic signal processor device 304 may optionally include the microelectronic devices previously described herein (e.g., previously referenced...). Figures 1A to 1C The microelectronic device 100 described herein and the memory device (e.g., previously referenced) Figures 2A to 2C One or more embodiments of the described memory device 200. Although in Figure 3 The memory device 302 and the electronic signal processor device 304 are depicted as two separate (2) devices, but in additional embodiments, a single (e.g., only one) memory / processor device having the functionality of both the memory device 302 and the electronic signal processor device 304 is included in the electronic system 300. In these embodiments, the memory / processor device may include the microelectronic devices previously described herein (e.g., previously referenced...). Figures 1A to 1C The microelectronic device 100 described herein and the memory device (e.g., previously referenced) Figures 2A to 2CThe electronic system 300 may include one or more embodiments of the memory device 200 described. The electronic system 300 may further include one or more input devices 306 for users to input information into the electronic system 300, such as a mouse or other pointing device, keyboard, touchpad, button, or control panel. The electronic system 300 may further include one or more output devices 308 for outputting information to the user (e.g., visual or audio output), such as a monitor, display, printer, audio output jack, speaker, etc. In some embodiments, the input device 306 and output device 308 may include a single touchscreen device, which can be used to input information into the electronic system 300 and output visual information to the user. The input device 306 and output device 308 may be in electrical communication with one or more of the memory device 302 and the electronic signal processor device 304.

[0087] Therefore, according to embodiments of this disclosure, an electronic system includes an input device, an output device, a processor device operatively coupled to the input and output devices, and a memory device operatively coupled to the processor device. The memory device includes a stacked structure, a contact structure, a microelectronic device, and a vertically extending string of memory cells. The stacked structure has layers including conductive structures and insulating structures vertically adjacent to the conductive structures, and includes a stepped region and a memory array region. The stepped region includes a stepped structure with steps, the steps including horizontal ends of the layers. The memory array region is horizontally adjacent to the stepped region. The contact structure is on the steps of the stepped structure. The microelectronic device is electrically coupled to the contact structure and includes a transistor vertically covering and within the horizontal boundary of the stepped region of the stacked structure. Each of the transistors includes: a channel region comprising a 2D material; a conductive doped region adjacent to the relative horizontal boundary of the channel region and comprising the 2D material doped with at least one conductive dopant; and a gate structure vertically covering and at least partially aligned horizontally with the channel region. The vertically extending string of memory cells is within the memory array region of the stacked structure.

[0088] Compared to conventional structures, devices, and systems, the structures, devices, and systems of this disclosure advantageously promote one or more of improved simplicity, greater package density, and increased component miniaturization. For example, compared to conventional microelectronic devices and conventional memory devices, the configuration of the microelectronic device (e.g., microelectronic device 100) of this disclosure facilitates a robust memory device (e.g., memory device 200) architecture with more components, less component congestion, and / or smaller horizontal dimensions. Compared to conventional structures, devices, and systems, the structures, devices, and systems of this disclosure can increase performance, scalability, efficiency, reliability, and simplicity.

[0089] Additional, non-limiting example embodiments of this disclosure are described below.

[0090] Example 1: A transistor comprising: a 2D material structure extending conformally therebetween on the surface of a dielectric fin structure extending parallel in a first horizontal direction, the 2D material structure comprising: a source region; a drain region; and a channel region positioned between the source region and the drain region in the first horizontal direction; and a gate structure covering the channel region of the 2D material structure and extending in a second horizontal direction orthogonal to the first horizontal direction, the gate structure being within the horizontal boundary of the channel region of the 2D material structure in the first horizontal direction.

[0091] Example 2: The transistor according to Example 1, wherein the 2D material structure includes one or more of WS2, WSe2, MoS2 and MoSe2.

[0092] Example 3: A transistor according to one of Examples 1 and 2, wherein the source region and the drain region of the 2D material structure are doped with at least one N-type dopant.

[0093] Example 4: A transistor according to one of Examples 1 and 2, wherein the source region and the drain region of the 2D material structure are doped with at least one P-type dopant.

[0094] Example 5: A transistor according to any one of Examples 1 and 2, wherein the source region and the drain region of the 2D material structure are substantially undoped.

[0095] Example 6: A transistor according to any one of Examples 1 to 5, wherein the 2D material structure further includes a lateral double diffusion region positioned in the first horizontal direction between the channel region and each of the source region and the drain region.

[0096] Example 7: A transistor according to any one of Examples 1 to 6, wherein: each of the dielectric fin structures individually presents an aspect ratio in the range of about 0.1:1 to about 10:1; and the ratio of the width of each of the dielectric fin structures to the distance between horizontally adjacent dielectric structures is in the range of about 0.1:1 to about 10:1.

[0097] Example 8: The transistor according to any one of Examples 1 to 7 further includes a conductive structure extending vertically from the gate structure toward the channel region of the 2D material structure, the conductive structure being sandwiched between the dielectric fin structures in the second horizontal direction.

[0098] Example 9: The transistor according to Example 8 further includes a gate dielectric material sandwiched between the 2D material structure and each of the gate structure and conductor.

[0099] Example 10: A microelectronic device comprising: discrete dielectric structures covering an isolation structure and spaced apart from each other by filled trenches; a non-planar 2D material structure extending above the surfaces of the isolation structure and the discrete dielectric structure inside and outside the filled trenches, the non-planar 2D material structure comprising: conductive doped regions; and channel regions between the conductive doped regions; a gate structure covering and substantially aligned with the channel regions of the non-planar 2D material structure; a conductive structure extending from the gate structure into the trenches; a contact structure coupled to some of the conductive doped regions and extending into the isolation structure; and at least one additional contact structure coupled to at least one of the conductive doped regions and extending away from the isolation structure.

[0100] Example 11: The microelectronic device according to Example 10, wherein the non-planar 2D material structure physically contacts and conforms to the surfaces of the isolation structure and the discrete dielectric structure inside and outside the filled trench.

[0101] Example 12: A microelectronic device according to one of Examples 10 and 11, wherein the non-planar 2D material structure further includes an additional conductive doped region between the channel region and the conductive doped region, the additional conductive doped region comprising a relatively small amount of conductive dopant compared to the conductive doped region.

[0102] Example 13: A microelectronic device according to Example 12, wherein: the conductive doped region of the non-planar 2D material structure includes N + Region; additional conductive doped regions in non-planar 2D material structures include N - district.

[0103] Example 14: A microelectronic device according to one of Examples 12 and 13, wherein the contact structure and the at least one additional contact structure physically contact one or more of the conductive doped regions and the additional conductive doped regions of the non-planar 2D material structure.

[0104] Example 15: A microelectronic device according to any one of Examples 10 to 14, wherein: the conductive doped region of the non-planar 2D material includes at least one source region and at least two drain regions; the contact structure includes at least two local contact structures coupled to the at least two drain regions; and the at least one additional contact structure includes at least one global contact structure coupled to the at least one source region.

[0105] Example 16: A memory device comprising: a stacked structure including vertically alternating conductive and insulating structures arranged in layers; a stepped structure having steps including the edges of the layers at a horizontal end of the stacked structure; a string driver transistor vertically covering the stepped structure and including a channel region comprising at least one 2D material; at least one additional conductive structure extending from and between the string driver transistor and one of the steps of the stepped structure; and a string of memory cells extending vertically through the stacked structure.

[0106] Example 17: A memory device according to Example 16, wherein the at least one 2D material has a band gap in the range of about 1.2 eV to about 2.5 eV, and has a band gap of about 10 cm⁻¹. 2 / V·s to approximately 400cm 2 Electron mobility in the range of / V·s.

[0107] Example 18: A memory device according to one of Examples 16 and 17, wherein the string driver transistor further comprises: a lateral double-diffusion region horizontally adjacent to the channel region and comprising the at least one 2D material; and a source region and a drain region horizontally adjacent to the lateral double-diffusion region and comprising the at least one 2D material.

[0108] Example 19: A memory device according to any one of Examples 16 to 18, wherein the at least one 2D material has a substantially non-planar shape, the substantially non-planar shape being conformable to a combination morphology of a dielectric fin structure and an insulating structure vertically located below the at least one 2D material.

[0109] Example 20: A memory device according to any one of Examples 16 to 18, wherein the at least one 2D material has a substantially horizontal planar shape.

[0110] Example 21: A memory device according to any one of Examples 16 to 20, wherein the at least one additional conductive structure comprises: a vertical direct contact structure on one of the steps of the stepped structure; and a local contact structure extending vertically downward from the string driver transistor and electrically coupled to the vertical direct contact structure.

[0111] Example 22: The memory device according to Example 21, wherein the at least one additional conductive structure further includes another conductive structure that is vertically located between and in physical contact with the vertical direct contact structure.

[0112] Example 23: A memory device according to one of Examples 21 and 22, further comprising a global contact structure extending vertically upward from the string driver transistor.

[0113] Example 24: An electronic system comprising: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and comprising: a stacked structure having a layer including a conductive structure and an insulating structure vertically adjacent to the conductive structure, the stacked structure comprising: a stepped region including a stepped structure having a step including a horizontal end of the layer; a memory array region horizontally adjacent to the stepped region; a contact structure on the step of the stepped structure; a microelectronic device electrically coupled to the contact structure and comprising transistors vertically covering and within the horizontal boundary of the stepped region of the stacked structure, each of the transistors comprising: a channel region including a 2D material; a conductive doped region adjacent to the relative horizontal boundary of the channel region and comprising the 2D material doped with at least one conductive dopant; and a gate structure vertically covering and at least partially aligned horizontally with the channel region; and a memory cell string extending vertically within the memory array region of the stacked structure.

[0114] Example 25: The electronic system according to Example 24, wherein the memory device includes a 3D NAND flash memory device.

[0115] While this disclosure is open to various modifications and alternatives, its details are illustrated by way of example and are described in detail herein. However, this disclosure is not limited to the specific forms disclosed. Rather, this disclosure is intended to cover all modifications, equivalents, and alternatives falling within the scope of the appended claims and their legal equivalents.

Claims

1. A string driver assembly comprising: Dielectric fin structure, which extends horizontally and parallel in a first direction; An isolation structure is located below the dielectric fin structure; A two-dimensional (2D) material continuously extends above the upper and side surfaces of the dielectric fin structures, above the surface of the insulating structure between the dielectric fin structures, and continuously extends horizontally between the dielectric fin structures in a second direction orthogonal to the first direction, the 2D material comprising: Conductive doped regions; and The channel region is horizontally sandwiched between the conductive doped regions in the first direction; A gate electrode that vertically covers the 2D material and extends horizontally in parallel in the second direction, wherein the channel region of the 2D material horizontally overlaps the gate electrode in the first direction; A conductive structure extending vertically from the gate electrode into the 2D material between the dielectric fin structures; and A gate dielectric material, which is vertically sandwiched between the 2D material, the gate electrode, and the conductive structure.

2. The string driver assembly of claim 1, wherein the 2D material further comprises a conductive doping offset region horizontally sandwiched between the conductive doped region and the channel region in the first direction, the conductive doping offset region having a lower concentration of one or more conductive enhancing dopants than the conductive doped region.

3. The string driver assembly of claim 1, further comprising: A conductive contact that extends horizontally in the second direction and vertically upward from one of the conductive doped regions of the 2D material; and Additional conductive contacts extend horizontally in the second direction and vertically downward from the additional conductive doped region in the conductive doped region of the 2D material.

4. The string driver assembly according to claim 1, wherein the 2D material comprises one or more of the following: transition metal dichalcogenides, carbides or carbonitrides, graphene, graphene oxide, tinene, phosphorene, hexagonal boron nitride, boronene, silylene, graphyne, germanene, germanane, 2D supercrystals, and monolayers of semiconductor materials.

5. The string driver assembly of claim 1, wherein the 2D material comprises a transition metal dichalcogenide having the general chemical formula MX2, wherein M is selected from Mo, W, Nb, Zr, Hf, Re, Pt, Ti, Ta, V, Co, Cd, Cr, and wherein X is selected from S, Se, and Te.

6. The string driver assembly of claim 1, wherein the 2D material comprises materials having a universal chemical formula M n+ 1X n The carbides or carbonitrides, wherein M is selected from Ti, Hf, Zr, V, Nb, Ta, and X is selected from C and combinations of C and N.

7. The serial driver assembly of claim 1, wherein: In the second direction, the first distance between adjacent dielectric fin structures in the dielectric fin structure is in the range of 10 nanometers (nm) to 100 nm; and In the first direction, the second distance between adjacent gate electrodes is greater than the first distance.

8. A memory device comprising: Blocks, extending horizontally in a first direction, and each block comprising a layer, each layer individually comprising a conductive material and an insulating material vertically adjacent to the conductive material, the blocks respectively comprising: Array region; and A stepped area, which is adjacent to the array area in the first direction and includes a stepped structure with steps, the steps including the edges of at least some of the layers; A microelectronic device that vertically covers the block and extends horizontally over two blocks of the block, individually in a second direction perpendicular to the first direction, the microelectronic device comprising: Dielectric fin structure, which extends horizontally and parallel in the second direction; A two-dimensional (2D) material conformally extends on and between the dielectric fin structures, the 2D material including a first channel region and a second channel region; Dielectric material, which is on the 2D material; and A gate electrode, which extends parallel to the dielectric material in the first direction and includes a first gate electrode and a second gate electrode. The first channel region of the 2D material horizontally overlaps with the first of the two blocks in the block and each of the first gate electrode in the second direction; and The second channel region of the 2D material horizontally overlaps with the second block of the two blocks in the block and each of the second gate electrodes in the second direction; and A conductive contact that couples a corresponding microelectronic device in the microelectronic device to the conductive material of a corresponding layer in the layers of two blocks in the block that horizontally overlap with the corresponding microelectronic device in the microelectronic device in the second direction.

9. The memory device of claim 8, wherein the respective microelectronic device in the microelectronic device is horizontally positioned in the first direction within the stepped region of each of two blocks in the block that horizontally overlaps with the respective microelectronic device in the microelectronic device in the second direction.

10. The memory device according to claim 8, wherein, For the corresponding microelectronic device in the aforementioned microelectronic device, the 2D material further includes: A first conductive doped region, which horizontally overlaps with the first block of the two blocks in the second direction; A second conductive doped region, which horizontally overlaps with the second block of the two blocks in the block in the second direction; and A third conductive doped region horizontally overlaps with a dielectric trench structure in the second direction, the dielectric trench structure being sandwiched between the first and second blocks of the two blocks in the second direction.

11. The memory device according to claim 10, wherein, For the corresponding microelectronic device in the aforementioned microelectronic device, the conductive contact includes: A first local conductive contact is coupled to the first conductive doped region of the 2D material and extends vertically downward from the first conductive doped region of the 2D material; A second local conductive contact, coupled to the second conductive doped region of the 2D material and extending vertically downward from the second conductive doped region of the 2D material; and A globally conductive contact that is coupled to the third conductive doped region of the 2D material and extends vertically upward from the third conductive doped region of the 2D material.

12. The memory device according to claim 11, wherein, For the corresponding microelectronic device in the aforementioned microelectronic device, the conductive contact further includes: A first letter contact, coupled to the first local conductive contact and physically contacting the conductive material of one layer of the first block at a step in the stepped structure of the first block; and The second digit contact is coupled to the second local conductive contact and physically contacts the conductive material of one layer of the second block at one step of the stepped structure of the second block.

13. The memory device according to claim 10, wherein, For the corresponding microelectronic device in the aforementioned microelectronic device, the 2D material further includes: A first lateral double-diffused LDD offset region is horizontally sandwiched between the first conductive doped region and the first channel region in the second direction; The second LDD offset region is horizontally sandwiched between the first channel region and the third conductive doped region in the second direction; A third LDD offset region, which is horizontally sandwiched between the third conductive doped region and the second channel region in the second direction; and A fourth LDD offset region is horizontally sandwiched between the second channel region and the second conductive doped region in the second direction.

14. The memory device of claim 8, further comprising a string of memory cells extending vertically within the array region of a respective block in the block.

15. A 3D NAND flash memory device, comprising: Two blocks that extend horizontally parallel to each other in a first direction, each of the two blocks comprising a layer comprising a conductive material and an insulating material vertically adjacent to the conductive material; A groove structure, which is horizontally sandwiched between the two blocks in a second direction orthogonal to the first direction; A string of memory cells, which is located in the horizontal region of the two blocks and extends vertically through the two blocks; A series driver assembly that vertically covers the two blocks and the trench structure in the second direction and individually overlaps the two blocks and the trench structure horizontally, the series driver assembly comprising: Dielectric fin structure, which extends horizontally and parallel in the second direction; A two-dimensional 2D material that conformally extends on and between the dielectric fin structures; Gate dielectric material, which is disposed on the 2D material; and Two gate electrodes, located on the gate dielectric material and horizontally overlapping the two blocks in the second direction, the two gate electrodes extending horizontally parallel in the first direction; and Conductive contacts that couple a respective string driver assembly in the string driver assembly to the conductive material of a respective layer in the layers of each of the two blocks.

16. The 3D NAND flash memory device of claim 15, wherein the string driver assembly further comprises conductive protrusions extending vertically from the two gate electrodes and vertically overlapping the dielectric fin structure, the conductive protrusions being horizontally sandwiched between the dielectric fin structure in the second direction.

17. The 3D NAND flash memory device according to claim 15, wherein, For the respective string driver assembly in the string driver assembly, the 2D material comprises: A first channel region, which horizontally overlaps with each of the first block of the two blocks and the first gate electrode of the two gate electrodes in the second direction; A first drain region, which horizontally overlaps with the first of the two blocks in the second direction; The source region horizontally overlaps with the trench structure in the second direction; A second channel region, which horizontally overlaps in the second direction with each of the second block of the two blocks and the second gate electrode of the two gate electrodes; and The second drain region horizontally overlaps with the second block of the two blocks in the second direction.

18. The 3D NAND flash memory device according to claim 15, wherein, For the respective string driver assembly in the string driver assembly, the 2D material includes one or more of WS2, WSe2, MoS2 and MoSe2.

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