Memory device and manufacturing method thereof

Abstract

The present application relates to a memory device and a manufacturing method thereof. A memory device and a manufacturing method thereof, the memory device comprising: a gate stack formed on a cell region and a transfer transistor region; a plurality of cell plugs extending in a vertical direction in the gate stack of the cell region; a plurality of gate contact structures extending in a vertical direction by passing through the gate stack of the transfer transistor region; and a plurality of transfer transistors connected to a plurality of corresponding gate contact structures. Each of the plurality of transfer transistors has a cylindrical structure.

Description

Technical Field

[0001] The present disclosure relates to electronic devices, and more particularly, to a memory device having a vertical channel structure and a method of manufacturing the same. Background Art

[0002] Memory devices are classified as either volatile memory devices or non-volatile memory devices.

[0003] The writing speed and reading speed of non-volatile memory devices are relatively slow, however, non-volatile memory devices retain their stored data even when their power supply is cut off. Therefore, non-volatile memory devices are used to store data that must be maintained regardless of the power supply. Non-volatile memory devices include read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Flash memory is divided into NOR type and NAND type. Summary of the invention

[0004] According to an embodiment of the present disclosure, a memory device includes: a gate stack formed on a cell region and a transfer transistor region, a plurality of cell plugs extending in a vertical direction in the gate stack of the cell region, a plurality of gate contact structures extending in a vertical direction by passing through the gate stack of the transfer transistor region; and a plurality of transfer transistors connected to the plurality of corresponding gate contact structures, and each of the plurality of transfer transistors has a cylindrical structure.

[0005] According to an embodiment of the present disclosure, a method for manufacturing a memory device includes: forming a groove having a first depth at a boundary between the cell region and the transfer transistor region by etching a first substrate including a cell region and a transfer transistor region and forming a plurality of first holes having a second depth in the transfer transistor region; forming an isolation structure by filling an insulating layer in the groove and forming a gate insulating layer on the sidewalls of the plurality of first holes; forming a channel pattern filling the interior of the plurality of first holes by growing the first substrate via an epitaxial growth method; forming a stack in which a first material layer and a second material layer are alternately stacked on the entire structure including the cell region and the transfer transistor region; forming a plurality of cell plugs extending in a vertical direction in the stack in the cell region; replacing the second material layer with a conductive pattern for a word line; and forming a plurality of gate contact structures connected to the channel pattern through the stack in the transfer transistor region.

[0006] According to an embodiment of the present disclosure, a memory device includes: a gate stack, which includes a plurality of interlayer insulating layers and a plurality of conductive patterns alternately stacked from a first surface to a second surface; a plurality of transfer transistors arranged above the second surface of the gate stack; and a plurality of gate contact structures, which are configured to extend from the first surface of the gate stack to the second surface of the gate stack, and each gate contact structure is configured to connect each transfer transistor to each conductive pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0008] Figure 2A and Figure 2B is a perspective view illustrating an overlapping structure of a peripheral circuit structure and a unit stack according to an embodiment of the present disclosure.

[0009] Figure 3 is a circuit diagram illustrating a memory cell array and a row decoder according to an embodiment of the present disclosure.

[0010] Figure 4 is a cross-sectional view illustrating a memory device including a cell region and a pass transistor region of a cell stack according to an embodiment of the present disclosure.

[0011] Figure 5A , Figure 5B , Figure 6 , Fig. 7A , Figure 7B and Figures 8 to 24 are cross-sectional views and plan views illustrating a method of manufacturing a memory device according to an embodiment of the present disclosure.

[0012] Fig.25 is a block diagram illustrating a configuration of a memory system according to an embodiment of the present disclosure.

[0013] Fig.26 is a block diagram illustrating a configuration of a computing system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0014] The specific structural and functional descriptions of the embodiments of the concepts disclosed in this specification or this application are only exemplified to describe the embodiments of the concepts according to the present disclosure. The embodiments of the concepts according to the present disclosure can be performed in various forms, and the scope of the present disclosure is not limited to the embodiments described in this specification or this application.

[0015] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings in sufficient detail to allow those skilled in the art to implement the technical concept of the present disclosure.

[0016] Embodiments of the present disclosure can improve the process simplification and integration of a memory device by forming a pass transistor connected to a word line using a substrate on which a gate stack is formed. According to the present technology, the process simplification and integration of a memory device can be improved by forming a pass transistor connected to a word line using a substrate on which a gate stack is formed.

[0017] Figure 1 is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0018] Reference Figure 1 , the memory device 50 may include a peripheral circuit 40 and a memory cell array 10 .

[0019] The peripheral circuit 40 may be configured to perform overall operations such as a program operation for storing data in the memory cell array 10, a read operation for outputting data stored in the memory cell array 10, and an erase operation for erasing data stored in the memory cell array 10. As an embodiment, the peripheral circuit 40 may include an input / output circuit 21, a control circuit 23, a voltage generating circuit 31, a row decoder 33, a column decoder 35, a page buffer 37, and a source line driver 39.

[0020] The memory cell array 10 may include a plurality of memory cells in which data is stored. The memory cells may be arranged three-dimensionally. The memory cell array 10 may include one or more cell strings. Each cell string may include one or more drain select transistors, a plurality of memory cells, and one or more source select transistors connected between any one of the bit lines BL and a common source line CSL. One or more drain select transistors may be connected to a drain select line DSL, a plurality of memory cells may be connected to a plurality of word lines WL, and one or more source select transistors may be connected to a source select line SSL.

[0021] The input / output circuit 21 may transmit a command CMD and an address ADD received from an external device (e.g., a memory controller) of the memory device 50 to the control circuit 23. The input / output circuit 21 may transmit data DATA received from the external device to the column decoder 35, or output data DATA received from the column decoder 35 to the external device.

[0022] The control circuit 23 may control the voltage generating circuit 31, the row decoder 33, the column decoder 35, the page buffer 37, and the source line driver 39 to perform a program operation, a read operation, or an erase operation in response to the command CMD and the address ADD received through the input / output circuit 21. For example, the control circuit 23 may generate and output an operation signal OP_S, a row address RADD, a source line control signal SL_S, a page buffer control signal PB_S, and a column address CADD in response to the command CMD and the address ADD.

[0023] The voltage generating circuit 31 may generate various operating voltages Vop for a program operation, a read operation, or an erase operation in response to an operating signal OP_S.

[0024] The row decoder 33 may selectively transfer the operation voltage Vop generated in the voltage generation circuit 31 to the drain selection line DSL, the word line WL, and the source selection line SSL in response to the row address RADD. In addition, the row decoder 33 may selectively discharge the voltages of the drain selection line DSL, the word line WL, and the source selection line SSL.

[0025] The column decoder 35 may transmit data DATA received from the input / output circuit 21 to the page buffer 37 in response to the column address CADD, or transmit data DATA stored in the page buffer 37 to the input / output circuit 21. For example, during a program operation, the column decoder 35 may transmit data DATA received from the input / output circuit 21 through the column line CL to the page buffer 37 in response to the column address CADD. During a read operation, the column decoder 35 may receive data DATA stored in the page buffer 37 through the data line DL and transmit the received data DATA to the input / output circuit 21.

[0026] During a program operation, the page buffer 37 may temporarily store data DATA received from the column decoder 35 and control the potential of the bit line BL based on the temporarily stored data DATA. During a read operation, the page buffer 37 may sense the potential or current amount of the bit line BL and latch the data DATA according to the sensing result. The page buffer 37 may operate in response to a page buffer control signal PB_S.

[0027] The source line driver 39 may control a voltage applied to the common source line CSL in response to the source line control signal SL_S. For example, the source line driver 39 may apply an erase voltage to the common source line CSL during an erase operation.

[0028] In order to improve the integration of the memory device, the cell stack of the memory cell array 10 can overlap with the peripheral circuit 40. For example, after forming the peripheral circuit structure on the substrate, the cell stack can be formed by overlapping the cell stack on the peripheral circuit structure. Alternatively, after forming the cell stack and the peripheral circuit structure on different substrates, the peripheral circuit structure and the cell stack can be overlapped by bonding the peripheral circuit structure and the cell stack to each other in a wafer bonding method, thereby forming the peripheral circuit structure and the cell stack.

[0029] Figure 2A and Figure 2B is a perspective view illustrating an overlapping structure of a peripheral circuit structure and a unit stack according to an embodiment of the present disclosure.

[0030] Reference Figure 2A and Figure 2B , the common source line CSL and the plurality of bit lines BL may overlap on the peripheral circuit structure 45. The cell stack ST[C] may be disposed between the common source line CSL and the plurality of bit lines BL.

[0031] Reference Figure 2A As an embodiment, a common source line CSL may be disposed between the cell stack ST[C] and the peripheral circuit structure 45, and a bit line BL may overlap the common source line CSL with the cell stack ST[C] interposed therebetween.

[0032] Reference Figure 2B As an embodiment, the bit line BL may be disposed between the cell stack ST[C] and the peripheral circuit structure 45, and the common source line CSL may overlap the bit line BL with the cell stack ST[C] interposed therebetween.

[0033] In the above-described embodiment of the present disclosure, the entire unit stack ST[C] overlaps on the peripheral circuit structure 45, but it is possible that only a partial region of the unit stack ST[C] overlaps on the peripheral circuit structure 45. That is, a partial region of the unit stack ST[C] and a partial region of the peripheral circuit structure 45 may overlap each other.

[0034] Figure 3 is a circuit diagram illustrating a memory cell array and a row decoder according to an embodiment of the present disclosure.

[0035] Reference Figure 3 , the memory cell array 10 may include a plurality of cell strings CS respectively connected to a plurality of bit lines BL. The plurality of cell strings CS may be commonly connected to a common source line CSL.

[0036] Each cell string CS may include at least one source select transistor SST disposed between a common source line CSL and a bit line BL, a plurality of memory cells MC, and at least one drain select transistor DST.

[0037] The source select transistor SST may control the electrical connection between the cell string CS and the common source line CSL, and the drain select transistor DST may control the electrical connection between the cell string CS and the bit line BL.

[0038] Between the common source line CSL and the plurality of memory cells MC, one source selection transistor SST may be provided, or two or more source selection transistors connected in series may be provided. Between the bit line BL and the plurality of memory cells MC, one drain selection transistor DST may be provided, or two or more drain selection transistors connected in series may be provided.

[0039] A plurality of memory cells MC may be connected to word lines WL, respectively. Operations of the plurality of memory cells MC may be controlled by cell gate signals applied to the word lines WL. A source select transistor SST may be connected to a source select line SSL. Operations of the source select transistor SST may be controlled by a source gate signal applied to the source select line SSL. A drain select transistor DST may be connected to a drain select line DSL. Operations of the drain select transistor DST may be controlled by a drain gate signal applied to the drain select line DSL.

[0040] The source selection line SSL, the drain selection line DSL, and the word line WL may be connected to the block selection circuit BSC. The block selection circuit BSC may be included in the reference Figure 1 33 described above. As an embodiment, the block selection circuit BSC may include a pass transistor PT connected to a source selection line SSL, a drain selection line DSL, and a word line WL, respectively. The gate of the pass transistor PT may be connected to the block selection line BSEL. The pass transistor PT may be configured to transmit an operating voltage applied to the global lines GSSL, GWL, and GDSL to the source selection line SSL, the drain selection line DSL, and the word line WL in response to a block selection signal applied to the block selection line BSEL.

[0041] The block selection circuit BSC may be connected to the source selection line SSL, the drain selection line DSL, and the word line WL via a gate contact structure GCT.

[0042] Figure 4 is a cross-sectional view illustrating a memory device including a cell region and a pass transistor region of a cell stack according to an embodiment of the present disclosure. Figure 4 Examples of which Figure 1The cell stack of the memory cell array 10 and the peripheral circuit structure of the peripheral circuit 40 overlap.

[0043] Reference Figure 4 , the memory device may be arranged such that the lower structure UC and the upper structure TC are joined to each other.

[0044] The cell region Cell_R of the upper structure TC includes a gate stack GST, a plurality of cell plugs CP passing through the gate stack GST, a bit line 137 disposed under the gate stack GST, and a source line 304 disposed on the gate stack GST.

[0045] The gate stack GST may include first material layers 111 as interlayer insulating layers and word line conductive patterns 129 alternately stacked in a vertical direction. A first insulating layer 103 may be disposed on the gate stack GST.

[0046] Each word line conductive pattern 129 may include various conductive materials, such as a doped silicon layer, a metal layer, a metal silicide layer, and a barrier layer, and may include two or more types of conductive materials. For example, each word line conductive pattern 129 may include tungsten and a titanium nitride (TiN) layer surrounding the surface of the tungsten. Tungsten may be a low resistance metal and may reduce the resistance of the word line conductive pattern 129. The titanium nitride (TiN) layer may be a barrier layer and may prevent direct contact between tungsten and the first material layer 111.

[0047] Among the word line conductive patterns 129, at least one conductive pattern adjacent to the bit line 137 may be used as Figure 3 Among the word line conductive patterns 129, at least one conductive pattern adjacent to the source line 304 may be used as Figure 3 Among the word line conductive patterns 129, the remaining conductive patterns except for the conductive patterns used as drain select lines and the conductive patterns used as source select lines can be used as Figure 3 The word line WL.

[0048] The cell plug CP may pass through the gate stack GST and the first insulating layer 103 in the vertical direction, and one end of the cell plug CP may be formed to protrude compared to the first insulating layer 103. For example, the cell plug CP may extend in the vertical direction in the gate stack GST. The cell plug CP may be formed as a hollow type. The cell plug CP may include a core insulating layer 119 filling the central region, a doped semiconductor layer 121 located at the lower end of the core insulating layer 119, and a channel layer surrounding the surface of the core insulating layer 119 and the doped semiconductor layer 121. The channel layer 117 is used as a channel region of a cell string corresponding thereto. The channel layer 117 may be formed of a semiconductor material. As an embodiment, the channel layer 117 may include a silicon layer. Dopants may be implanted into the portion located at the uppermost portion of the channel layer 117 (i.e., the channel layer portion corresponding to the source select transistor) by an ion implantation process. The channel layer 117 may be formed to protrude compared to the first insulating layer 103 disposed on the gate stack GST. For example, the channel layer 117 may protrude compared to the first insulating layer 103 and extend into the source line 304. Therefore, the channel layer 117 and the source line 304 are in direct contact. The memory layer 115 may be formed to surround the sidewall of the channel layer 117. The memory layer 115 may be disposed between the gate stack GST and the channel layer 117. The memory layer 115 may include a tunnel insulating layer surrounding the channel layer 117, a data storage layer surrounding the tunnel insulating layer, and a blocking insulating layer surrounding the data storage layer. The memory layer 115 may extend in a vertical direction along the sidewall of the channel layer 117, and may extend shorter than the channel layer 117. For example, the memory layer 115 may be formed between the channel layer 117 and the gate stack GST and between the channel layer 117 and the first insulating layer 103, and may have the same height as the first insulating layer 103.

[0049] The source line 304 may be formed to directly contact the channel layer 117 of the cell plug CP protruding more than the gate stack GST. The source line 304 may be configured by including at least one material among a doped polysilicon layer, titanium nitride (TiN), tungsten (W), and copper (Cu).

[0050] The source line 304 may be connected to the line 317 through a source line contact 311 disposed through the sixth insulating layer 307 .

[0051] The bit line 137 may be disposed under the gate stack GST and may be connected to the cell plug CP through a bit line contact 135 passing through the second insulating layer 123 and the third insulating layer 133 .

[0052] The pass transistor region PT_R of the upper structure TC may include a gate stack GST, a plurality of gate contact structures 131 , and a plurality of pass transistors PT.

[0053] The gate stack GST may extend from the cell region Cell_R. For example, an edge portion of the gate stack GST may have a stepped structure. A plurality of gate contact structures 131 may be connected to a plurality of word line conductive patterns 129 of the gate stack GST. In addition, a plurality of gate contact structures 131 may extend by passing through the gate stack GST in a vertical direction. A plurality of transfer transistors PT may be arranged above each gate contact structure 131. For example, the gate stack GST may include a first surface and a second surface facing the first surface. A plurality of transfer transistors PT may be arranged above the first surface of the gate stack GST. A plurality of gate contact structures 131 may extend from the first surface of the gate stack GST to the second surface of the gate stack GST. For example, the transfer transistor region PT_R may be a word line contact region for applying a driving voltage to a plurality of word line conductive patterns 129.

[0054] The gate stack GST may extend to the transfer transistor region PT_R, and the extension lengths of the plurality of word line conductive patterns 129 included in the gate stack GST may be different from each other. For example, the extension length of the word line conductive pattern 129 disposed in the uppermost portion may be the longest, and the extension length of the word line conductive pattern 129 disposed in the lowermost portion may be the shortest, and as the word line conductive pattern 129 is disposed in the upper portion, the extension length may become longer, and thus the word line conductive pattern 129 may have a stepped shape.

[0055] The plurality of gate contact structures 131 may extend and may be disposed in a vertical direction in the transfer transistor region PT_R, and may pass through the plurality of word line conductive patterns 129 extending to the transfer transistor region PT_R. In addition, each of the plurality of gate contact structures 131 may be directly connected to a corresponding one of the plurality of word line conductive patterns 129. The spacer layer 125 may be disposed on a sidewall of each of the plurality of gate contact structures 131, and may be physically and electrically spaced apart from a non-corresponding conductive pattern among the plurality of word line conductive patterns 129 by the spacer layer 125.

[0056] The transfer transistor PT may be disposed on each of the plurality of gate contact structures 131. The transfer transistor PT may have a cylindrical structure. For example, the transfer transistor PT may include a channel pattern 109 having a cylindrical structure, a gate insulating layer 105 surrounding the sidewall of the channel pattern 109, and a first substrate 101 surrounding the sidewall of the gate insulating layer 105 and serving as a gate electrode of the transfer transistor.

[0057] A plurality of transmission transistors PT disposed on each of the plurality of gate contact structures 131 may share the first substrate 101. The first substrate 101 may be a gate electrode of the plurality of transmission transistors PT. The plurality of transmission transistors PT may share a gate electrode. The first substrate 101 may be connected to a transmission transistor contact structure 132, and the transmission transistor contact structure 132 may extend in a vertical direction. A contact 136 passing through the third insulating layer 133 and a contact pad 139 connected to the contact 136 may be disposed below the transmission transistor contact structure 132.

[0058] The plurality of pass transistors PT may be connected to the line 319 via the pass transistor contact 313 disposed through the fifth and sixth insulating layers 301 and 307. The first substrate 101 may be connected to the line 321 through the pass transistor gate contact 315 disposed through the fifth and sixth insulating layers 301 and 307.

[0059] The isolation structure ISO may be disposed between the transfer transistor region PT_R and the cell region Cell_R, and the isolation structure ISO may prevent the first substrate 101 from extending into the cell region Cell_R. The isolation structure ISO may be formed of the same material as the gate insulating layer 105. That is, the isolation structure ISO is disposed at a boundary between the transfer transistor region PT_R and the cell region Cell_R on the gate stack GST, and physically and electrically isolates the source line 304 of the cell region Cell_R from the first substrate 101 of the transfer transistor region PT_R.

[0060] The first connection structure may be formed in the fourth insulating layer 141 covering the bit line 137 and the contact pad 139. The first connection structure may include a contact 143 connected to each of the bit line 137 and the contact pad 139, and a first bonding metal 145 connected to the contact 143 and having a surface exposed to the outside.

[0061] The lower structure UC may include a complementary metal oxide semiconductor (CMOS) circuit structure CMOS including a plurality of transistors 200 formed on a substrate 201 and a second connection structure formed on the CMOS circuit structure CMOS. The plurality of transistors 200 may be spaced apart from each other by an element isolation structure 203.

[0062] The second connection structure may include an insulating structure 211 formed on the substrate 201 and a connection structure 220 formed inside the insulating structure 211. Each connection structure 220 may include various conductive patterns 213, 215, 217, 219, 221, and 223 embedded in the insulating structure 211. The insulating structure 211 may include two or more insulating layers 211A to 211D stacked in sequence. The conductive pattern 223 may be defined as a second bonding metal.

[0063] The upper structure TC and the lower structure UC may have a structure in which the upper structure TC and the lower structure UC are bonded to each other through a bonding process. For example, the exposed first bonding metal 145 of the first connection structure of the upper structure TC and the exposed second bonding metal 223 of the second connection structure of the lower structure UC may be disposed to face each other and may be bonded to each other.

[0064] Figure 5A , Figure 5B , Figure 6 , Fig. 7A , Figure 7B and Figures 8 to 24 are cross-sectional views and plan views illustrating a method of manufacturing a memory device according to an embodiment of the present disclosure.

[0065] Figure 5A , Figure 5B , Figure 6 , Fig. 7A , Figure 7B and Figures 8 to 16 are cross-sectional views and plan views illustrating a method of forming a unit stack and a transfer transistor.

[0066] Reference Figure 5A and Figure 5B , a first insulating layer 103 is formed on a first substrate 101. The first substrate 101 may be a bulk silicon substrate, a silicon germanium substrate, or an epitaxial thin film formed by a selective epitaxial growth method. The first insulating layer 103 may be an oxide layer.

[0067] Thereafter, a trench T is formed by passing through the first insulating layer 103 along the boundary of the cell region Cell_R and the transfer transistor region PT_R and extending into the first substrate 101. In addition, a plurality of first holes H1 are formed by passing through the first insulating layer 103 of the transfer transistor region PT_R and extending into the first substrate 101. The plurality of first holes H1 are formed with Figure 3 The depth of the trench T may be equal to the depth of the plurality of first holes H1, or the depth of the trench T may be formed to be deeper than the depth of the plurality of first holes H1.

[0068] Reference Figure 6, a gate insulating layer 105 is formed on the entire structure. The gate insulating layer 105 may be formed so that the trench T is buried. The gate insulating layer 105 formed in the trench T may be defined as an isolation structure. The gate insulating layer 105 may be formed in a liner shape along the sidewalls and lower surfaces of the plurality of first holes H1. The gate insulating layer 105 may be an oxide layer.

[0069] Thereafter, a first sacrificial layer 107 is formed along an upper surface of the gate insulating layer 105. The first sacrificial layer 107 may be a nitride layer.

[0070] Reference Fig. 7A and Figure 7B , the first sacrificial layer 107 and the gate insulating layer 105 are etched by performing an etch-back process to expose the first substrate 101 through the lower surface of the plurality of first holes H1. Through the etch-back process, the gate insulating layer 105 remains only in the trench T and on the sidewalls of the plurality of first holes H1, and the first sacrificial layer 107 remains only on the sidewalls of the gate insulating layer 105 remaining on the sidewalls of the plurality of first holes H1.

[0071] Reference Figure 8 , remove Fig. 7A The first sacrificial layer 107 is formed by growing the first substrate 101 through an epitaxial growth method to form a channel pattern 109 filling the inside of the plurality of first holes H1. Therefore, the gate insulating layer 105 and the channel pattern 109 for the transfer transistor are disposed inside the plurality of first holes H1. The first substrate 101 may be used as a gate electrode of the transfer transistor, the gate insulating layer 105 may be used as a gate insulating layer of the transfer transistor, and the channel pattern 109 may be used as a channel of the transfer transistor. Therefore, the transfer transistor may be composed of a channel pattern 109 of a cylindrical structure, a gate insulating layer 105 surrounding the sidewall of the channel pattern 109, and the first substrate 101 surrounding the sidewall of the gate insulating layer.

[0072] Reference Fig. 9 The stack ST may be formed on the entire structure of the cell region Cell_R and the transfer transistor region PT_R. The stack ST may include a plurality of first material layers 111 and a plurality of second material layers 113 alternately stacked. For example, the first material layer 111 may be an interlayer insulating layer. The second material layer 113 may be a sacrificial layer.

[0073] The second material layer 113 may include a material having an etching rate different from that of the first material layer 111. For example, the first material layer 111 may include silicon oxide, and the second material layer 113 may include silicon nitride. The following figures list embodiments in which the first material layer 111 is formed as an interlayer insulating layer and the second material layer 113 is formed as a sacrificial layer, but the present disclosure is not limited thereto. The physical properties of the first material layer 111 and the second material layer 113 may be changed in various ways.

[0074] Reference Fig.10 , a plurality of cell plugs CP are formed on the cell region Cell_R. The plurality of cell plugs CP may penetrate the stack ST and the first insulating layer 103 in a vertical direction and extend to a certain depth in the first substrate 101.

[0075] The process of forming the plurality of cell plugs CP is described in more detail as follows.

[0076] The etching process is performed to form a second hole H2 extending to a certain depth in the first substrate 101 by passing through the stack ST and the first insulating layer 103 .

[0077] Thereafter, the memory layer 115 and the channel layer 117 may be formed inside the second hole H2 . A sidewall of the channel layer 117 extending into the first substrate 101 may be surrounded by the memory layer 115 .

[0078] Forming the memory layer 115 may include sequentially stacking a data storage layer and a tunnel insulating layer on the surface of the second hole H2. The memory layer 115 may be formed in a pad shape, and the central area of ​​the second hole H2 may be defined by the memory layer 115. In addition, the memory layer 115 may further include a blocking insulating layer, and the blocking insulating layer may be formed on the surface of the second hole H2 before forming the data storage layer.

[0079] Thereafter, a channel layer 117 may be formed on the surface of the memory layer 115. The channel layer 117 may include a semiconductor layer serving as a channel region. For example, the channel layer 117 may include undoped polysilicon.

[0080] As an embodiment, the channel layer 117 may be formed in a pad shape, and the central area of ​​the second hole H2 may include a portion not filled with the channel layer 17. When the channel layer 117 is formed in a pad shape, it may include: filling the central area of ​​the second hole H2 with the core insulating layer 119, defining a recessed area in a portion of the central area of ​​the second hole H2 by etching the upper end portion of the core insulating layer, and filling the recessed area with the doped semiconductor layer 121. The core insulating layer 119 may include an oxide, and the doped semiconductor layer 121 may include a conductive dopant. The conductive dopant may include an n-type dopant for a junction. The conductive dopant may include a reversely doped p-type dopant.

[0081] As another embodiment, the channel layer 117 may be formed to fill the central region of the second hole H2, and the core insulating layer 119 and the doped semiconductor layer 121 may be omitted. When the core insulating layer 119 and the doped semiconductor layer 121 are omitted, forming the channel layer 117 may further include doping the inner portion of the channel layer with a conductive dopant.

[0082] Reference Fig.11 , the stack structure ST of the transfer transistor region PT_R is etched to form a plurality of stepped structures S1 to S5. Each of the stepped structures S1 to S5 may include one layer of the second material layer 113. In the stepped structure S1 located at the uppermost portion, the first material layer 111 may be disposed at the uppermost portion, and the remaining stepped structures S2 to S5 may be formed such that the upper surface of the second material layer 113 is exposed.

[0083] Reference Fig.12 , a second insulating layer 123 is formed on the entire structure including the plurality of stepped structures S1 to S5. After the second insulating layer 123 is formed, a planarization process may be performed to make the upper surface planar.

[0084] Thereafter, a plurality of third holes H3 are formed to expose the channel pattern 109 by passing through the stack ST of the second insulating layer 123 and the transfer transistor region PT_R. Each of the plurality of third holes H3 may be disposed to pass through the plurality of step structures S1 to S5. The plurality of third holes H3 may extend to a certain depth in the channel pattern 109.

[0085] In addition, a fourth hole H4 exposing the first substrate 101 by passing through the second insulating layer 123 of the transfer transistor region PT_R, the lowermost portion of the first material layer 111 , and the first insulating layer 103 is formed.

[0086] Reference Fig.13 By etching the second insulating layer 123 and the first material layer 111 exposed through the sidewalls of the plurality of third holes H3 to a certain thickness, irregularities can be formed on the sidewalls of the plurality of third holes H3. In addition, the critical dimension can be enlarged by etching the second insulating layer 123, the first material layer 111, and the first insulating layer 103 exposed through the sidewalls of the fourth hole H4 to a certain thickness.

[0087] Thereafter, a spacer 125 is formed along the sidewalls and lower surfaces of the plurality of third holes H3 and the fourth holes H4. The spacer 125 may be an oxide layer. The spacer 125 may be formed to cover the sidewall irregularities of each of the plurality of third holes H3. For example, based on the difference in material properties between the first material layer 111 and the second material layer 113 and the deposition method of the spacer 125, the spacer 125 may be formed to have a non-uniform thickness.

[0088] Thereafter, a support structure 127 is formed in the central region of the plurality of third and fourth holes H3 and H4. The support structure 127 may support the stack ST so that the stack ST does not collapse during a subsequently performed process of removing the second material layer 113. The support structure 127 may be a polysilicon layer.

[0089] Reference Fig.14 , the sidewall of the stack ST is exposed by forming a slit (not shown) passing through the second insulating layer 123 and the stack ST. The slit (not shown) may be formed in a line shape extending from the cell region Cell_R to the transfer transistor region PT_R.

[0090] Thereafter, the laminate ST exposed through the slit (not shown) is removed. Fig.13 The second material layer 113 is formed by forming a word line conductive pattern 129 in a space from which the second material is removed. The word line conductive pattern 129 may be penetrated by the cell plug CP, and each word line conductive pattern 129 is formed to surround the cell plug CP at different heights. The word line conductive pattern 129 may include various conductive materials, such as a doped silicon layer, a metal layer, a metal silicide layer, and a barrier layer, and may include two or more types of conductive materials. For example, each word line conductive pattern 129 may include tungsten and a titanium nitride TiN layer surrounding the surface of the tungsten. Tungsten may be a low resistance metal and may reduce the resistance of the word line conductive pattern 129. The titanium nitride TiN layer may be a barrier layer and may prevent direct contact between tungsten and the interlayer insulating layer.

[0091] Before forming the word line conductive pattern 129, a blocking insulating layer (not shown) may be formed to surround the word line conductive pattern 129 through which the word line conductive pattern 129 is removed. Fig.13 The sidewall of the cell plug CP is exposed by a space of the second material layer 113. The blocking insulating layer may be formed of an aluminum oxide layer AL2O3.

[0092] Reference Fig.15 , remove Fig.14 The support structure 127 is formed by forming a dry etching process to etch a portion of the exposed spacer layer 125 so that a portion of the upper surface of the word line conductive pattern 129 disposed at the uppermost portion among the word line conductive patterns 129 penetrated by each of the plurality of third holes H3 is exposed. In addition, the spacer layer 125 formed on the lower surface of each of the plurality of third holes H3 and the fourth holes H4 is removed to expose the channel pattern 109 and the first substrate 101.

[0093] Reference Fig.16By performing an ion implantation process, ions are implanted into the channel pattern 109 exposed through the plurality of third holes H3 and the inside of the first substrate 101 exposed through the fourth holes H4, and a rapid thermal annealing (RTA) process may be performed.

[0094] The gate contact structure 131 is formed by filling the inside of the plurality of third holes H3 with a conductive material, and the transfer transistor contact structure 132 is formed by filling the inside of the fourth hole H4 with a conductive material. The gate contact structure 131 may be directly connected to the corresponding word line conductive pattern 129 and the corresponding channel pattern 109. In addition, the transfer transistor contact structure 132 may be directly connected to the first substrate 101.

[0095] Thereafter, a third insulating layer 133 is formed on the entire structure, and a bit line contact 135 connected to an upper end portion of the cell plug CP is formed by passing through the third insulating layer 133. In addition, a contact 136 connected to an upper end portion of the transfer transistor contact structure 132 by passing through the third insulating layer 133 is formed.

[0096] Thereafter, a bit line 137 connected to the bit line contact 135 and a contact pad 139 connected to the contact 136 are formed on the third insulating layer 133 .

[0097] Thereafter, after forming a fourth insulating layer 141 on the entire structure, a contact 143 connected to the bit line 137 and the contact pad 139 and a first bonding metal 145 connected to the contact and having a surface exposed to the outside are formed.

[0098] The contact 143 and the first bonding metal 145 connected to the contact 143 and having a surface exposed to the outside may be defined as a first connection structure.

[0099] Fig.17 is a cross-sectional view illustrating a step of forming a CMOS circuit and a second connection structure on a second substrate.

[0100] A plurality of transistors 200 constituting a complementary metal oxide semiconductor (CMOS) circuit may be formed on a second substrate 201 .

[0101] The second substrate 201 may be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial layer formed by a selective epitaxial growth method.

[0102] Each transistor 200 may be formed in an active region of a second substrate 201 separated by an element isolation structure 203. Each transistor 200 may include a gate insulating layer 207 and a gate electrode 209 stacked on an active region corresponding thereto, and junctions 205a and 205b formed in the active region on both sides of the gate electrode 209. The junctions 205a and 205b may include conductive dopants to implement transistors corresponding thereto. The junctions 205a and 205b may include at least one of an n-type dopant or a p-type dopant.

[0103] After forming a plurality of transistors 200 , a second connection structure 220 connected to the transistors 200 constituting the CMOS circuit and a second insulating structure 211 covering the second connection structure 220 and the transistors 200 may be formed.

[0104] The second insulating structure 211 may include two or more insulating layers 211A to 211D. The second connection structures 220 may be buried in the second insulating structure 211. Each second connection structure 220 may include a plurality of conductive patterns 213, 215, 217, 219, 221, and 223. The second insulating structure 211 and the second connection structure 220 are not limited to the examples shown in the drawings, and may be changed in various forms.

[0105] The conductive patterns 213 , 215 , 217 , 219 , 221 , and 223 included in each of the second connection structures 220 may include a second bonding metal 223 having a surface exposed outside the second insulation structure 211 .

[0106] Fig.18 is a cross-sectional view illustrating a step of joining a first connection structure and a second connection structure to each other.

[0107] Reference Fig.18 The first substrate 101 and the second substrate 201 are arranged so that the first bonding metal 145 on the first substrate 101 and the second bonding metal 223 on the second substrate 201 can be bonded to each other. The first bonding metal 145 and the second bonding metal 223 may include various metals, for example, may include copper.

[0108] Thereafter, the first bonding metal 145 and the second bonding metal 223 are bonded to each other. To this end, after applying heat to the first bonding metal 145 and the second bonding metal 223, the first bonding metal 1.45 and the second bonding metal 223 may be hardened. The present disclosure is not limited thereto, and various processes for connecting the first bonding metal 145 and the second bonding metal 223 may be introduced.

[0109] Figures 19 to 24 is a cross-sectional view illustrating a step of forming source lines connected to a plurality of cell plugs and lines connected to pass transistors.

[0110] Reference Fig.19 The first substrate 101 is etched to expose the gate insulating layer 105 and the channel pattern 109 in the trench T. For example, the first substrate is etched to reduce its thickness by performing a chemical mechanical polishing (CMP) process, thereby exposing the gate insulating layer 105 and the channel pattern 109 in the trench T.

[0111] The first substrate 101 of the cell region Cell_R and the first substrate 101 of the transfer transistor region PT_R may be physically and electrically separated from each other by the exposed gate insulating layer 105 in the trench T, and the first substrate 101 of the transfer transistor region PT_R may serve as a gate electrode of the transfer transistor.

[0112] Reference Fig. 20 A fifth insulating layer 301 is formed on the entire structure of the first substrate 101 including the cell region Cell_R and the transfer transistor region PT_R. Thereafter, a first mask pattern 303 in which the cell region Cell_R is opened is formed on the fifth insulating layer 301. The first mask pattern 303 may be a photoresist pattern.

[0113] Thereafter, the fifth insulating layer 301 and the first substrate 101 of the cell region Cell_R opened by the first mask pattern 303 are removed by etching. Thus, the cell plug CP protrudes by passing through the first insulating layer 103.

[0114] Reference Fig.21 , the exposed memory layer 115 of the protruding cell plug CP is etched to expose the channel layer 117 of the protruding cell plug CP. The memory layer 115 may be removed before or after the etching process. Fig. 20 A first mask pattern 303 is formed.

[0115] Reference Fig. 22 , the source line 304 is formed to cover the exposed channel layer 117 of the cell plug CP. The source line 304 may include at least one material among a doped polysilicon layer, titanium nitride (TiN), tungsten W, and copper (Cu).

[0116] Thereafter, a second mask pattern 305 overlapping the cell plug CP and in which the pass transistor region PT_R is opened is formed on the source line 304 , and the source line 304 formed on the pass transistor region PT_R opened by the second mask pattern 305 is removed by etching.

[0117] Reference Fig.23 , remove Fig. 22A second mask pattern 305 is formed, and a sixth insulating layer 307 is formed on the entire structure including the cell region Cell_R and the pass transistor region PT_R. The sixth insulating layer 307 may be an oxide layer.

[0118] Thereafter, a fourth mask pattern 309 is formed in which an area overlapping with the source line 304, an area overlapping with the plurality of channel patterns 109, and an area overlapping with the first substrate 101 are opened, and the sixth insulating layer 307 opened through the fourth mask pattern 309 is etched to form at least one fifth hole H5 exposing the source line 304, a plurality of sixth holes H6 exposing the plurality of channel patterns 109, and a seventh hole H7 through which the first substrate 101 is exposed.

[0119] Reference Fig.24 , a conductive material is buried in at least one fifth hole H5 to form a source line contact 311. Thereafter, a line 317 connected to the source line contact 311 is formed.

[0120] In addition, a conductive material is buried in the plurality of sixth holes H6 to form the transfer transistor contacts 313. Thereafter, a wire 319 connected to the transfer transistor contacts 313 is formed.

[0121] In addition, a conductive material is buried in the seventh hole H7 to form a pass transistor gate contact 315. Thereafter, a line 321 connected to the pass transistor gate contact 315 is formed.

[0122] Fig.25 is a block diagram illustrating a configuration of a memory system 1100 according to an embodiment of the present disclosure.

[0123] Reference Fig.25 , the memory system 1100 includes a memory device 1120 and a memory controller 1110 .

[0124] The memory device 1120 may be a multi-chip package including a plurality of flash memory chips. The memory device 1120 may include a peripheral circuit structure formed on a substrate and a stack formed on the peripheral circuit structure. The stack may include a unit stack. The gate contact structure connected to the gate conductive pattern of the unit stack may be connected to an interconnect structure included in the peripheral circuit structure by passing through the unit stack.

[0125] The memory controller 1110 may be configured to control the memory device 1120, and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 is used as an operation memory of the CPU 1112, the CPU 1112 performs an overall control operation for data exchange of the memory controller 1110, and the host interface 1113 includes a data exchange protocol of a host connected to the memory system 1100. The error correction block 1114 detects and corrects errors included in data read from the memory device 1120. The memory interface 1115 performs an interface with the memory device 1120. The memory controller 1110 may also include a read-only memory (ROM) or the like storing code data for interfacing with the host.

[0126] The above-mentioned memory system 1100 may be a memory card or a solid state drive (SSD) in which the memory device 1120 and the memory controller 1110 are combined. For example, when the memory system 1100 is an SSD, the memory controller 1110 may communicate with the outside (e.g., a host) through one of various interface protocols such as a universal serial bus (USB), a multimedia card (MMC), a peripheral component interconnect express (PCI-E), a serial advanced technology attachment (SATA), a parallel advanced technology attachment (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), and an integrated drive electronics (IDE).

[0127] Fig.26 is a block diagram illustrating a configuration of a computing system 1200 according to an embodiment of the present disclosure.

[0128] Reference Fig.26 The computing system 1200 may include a CPU 1220 electrically connected to a system bus 1260, a random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210. When the computing system 1200 is a mobile device, it may further include a battery for providing an operating voltage to the computing system 1200, and may also include an application chipset, an image processor, a mobile DRAM, and the like.

[0129] The memory system 1210 may include a memory device 1212 and a memory controller 1211. Fig.25 The memory device 1120 described above is configured identically to the memory device 1212. Fig.25 The described memory controller 1110 is identically configured to the memory controller 1211 .

[0130] CROSS-REFERENCE TO RELATED APPLICATIONS

[0131] This application claims the priority of Korean Patent Application No. 10-2023-0131699 filed on October 4, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A memory device, comprising: a gate stack formed on the cell region and the pass transistor region; a plurality of cell plugs extending in a vertical direction in the gate stack of the cell region; a plurality of gate contact structures extending along the vertical direction by passing through the gate stack of the pass transistor region; as well as a plurality of pass transistors connected to corresponding ones of the plurality of gate contact structures, Wherein, each of the plurality of transfer transistors has a cylindrical structure.

2. The memory device according to claim 1, wherein: Each of the plurality of pass transistors comprises: a channel pattern of a cylindrical structure, the channel pattern being connected to any one of the plurality of gate contact structures; a gate insulating layer surrounding a sidewall of the channel pattern; and A gate electrode surrounds a side wall of the gate insulating layer.

3. The memory device according to claim 2, wherein: The plurality of transfer transistors share the gate electrode.

4. The memory device according to claim 2, wherein: The gate electrode is a bulk silicon substrate, a silicon germanium substrate, or an epitaxial thin film formed by a selective epitaxial growth method.

5. The memory device according to claim 4, wherein: The channel pattern is an epitaxial thin film.

6. The memory device according to claim 5, wherein: The channel pattern is a thin film obtained by growing the gate electrode by an epitaxial method.

7. The memory device according to claim 2, further comprising: A transfer transistor contact structure is connected to the gate electrode in the transfer transistor region and extends in the vertical direction.

8. The memory device according to claim 2, further comprising: A source line is formed above the gate stack in the cell region.

9. The memory device according to claim 8, wherein: The plurality of cell plugs extend into the inside of the source line.

10. The memory device according to claim 9, wherein: Each of the plurality of cell plugs includes a channel structure, and wherein the channel structure is directly connected to the source line.

11. The memory device of claim 10, further comprising: an isolation structure, the isolation structure being disposed on the gate stack at a boundary between the cell region and the transfer transistor region, The isolation structure physically and electrically separates the source line from the gate electrode.

12. A method of manufacturing a memory device, the method comprising the steps of: forming a trench having a first depth at a boundary between the cell region and the transfer transistor region by etching a first substrate including the cell region and the transfer transistor region and forming a plurality of first holes having a second depth in the transfer transistor region; forming an isolation structure by filling an insulating layer in the trench and forming a gate insulating layer on sidewalls of the plurality of first holes; forming a channel pattern filling the insides of the plurality of first holes by growing the first substrate through an epitaxial growth method; forming a stack in which first material layers and second material layers are alternately stacked on the entire structure including the cell region and the transfer transistor region; forming a plurality of cell plugs extending in a vertical direction in the stack of the cell regions; replacing the second material layer with a conductive pattern for a word line; as well as A plurality of gate contact structures connected to the channel pattern through the stack of the transfer transistor region are formed.

13. The method according to claim 12, wherein: The step of forming the plurality of gate contact structures comprises the following steps: forming a plurality of second holes exposing the channel patterns by passing through the first material layer and the conductive pattern for word lines, and forming a third hole exposing the first substrate; and The plurality of gate contact structures and the transfer transistor contact structure are formed by filling the plurality of second holes and the third holes with a conductive material.

14. The method according to claim 13, further comprising the steps of: After forming the plurality of second holes and the third holes, ions are implanted into the channel pattern and the first substrate by performing an ion implantation process, and a rapid thermal annealing (RTA) process is performed.

15. The method according to claim 12, wherein: The first depth is equal to or deeper than the second depth.

16. The method according to claim 12, further comprising the steps of: forming a bit line connected to the plurality of cell plugs; forming a conductive first connection structure on the bit line; forming a complementary metal oxide semiconductor (CMOS) circuit on the second substrate; forming a conductive second connection structure connected to the CMOS circuit on the second substrate; as well as The first bonding metal of the first connection structure and the second bonding metal of the second connection structure are bonded to each other so that the first connection structure and the second connection structure are connected to each other.

17. The method according to claim 12, wherein: The step of forming the plurality of unit plugs comprises the following steps: forming a fourth hole extending into the first substrate by penetrating the stack; and The fourth hole is filled with a memory layer and a channel layer.

18. The method according to claim 17, further comprising the steps of: etching the first substrate to expose the channel pattern and the isolation structure; After removing the first substrate on the cell area, exposing the channel layer by removing the exposed memory layer; as well as A source line contacting the channel layer is formed on the cell region.

19. A memory device, the memory device comprising: a gate stack including a plurality of interlayer insulating layers and a plurality of conductive patterns alternately stacked from a first surface to a second surface; a plurality of pass transistors disposed over the second surface of the gate stack; as well as A plurality of gate contact structures extend from the first surface of the gate stack to the second surface of the gate stack, and each of the gate contact structures connects each of the pass transistors with each of the conductive patterns.

20. The memory device of claim 19, wherein: Each of the plurality of pass transistors comprises: a channel pattern connected to a selected gate contact structure of the plurality of gate contact structures; a gate insulating layer surrounding a sidewall of the channel pattern; and A gate electrode surrounds a side wall of the gate insulating layer.

21. The memory device according to claim 19, in, The gate stack includes a memory cell array region and a word line contact region, The plurality of transfer transistors are arranged in the word line contact region.

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