Semiconductor device manufacturing method and semiconductor device

Abstract

The present application discloses a method for manufacturing a semiconductor device and a semiconductor device, belonging to the field of semiconductor technology. The method for manufacturing the semiconductor device includes: forming a first doped region and a second doped region that are laterally spaced apart in a substrate; forming an initial dielectric layer on the substrate; forming an initial conductive layer on the initial dielectric layer; etching the initial conductive layer and the initial dielectric layer to obtain a first dielectric layer and a first conductive layer that are sequentially located on the first doped region and a second dielectric layer and a second conductive layer that are sequentially located on the second doped region, wherein the first doped region constitutes a resistor, and the second doped region, the second dielectric layer and the second conductive layer constitute a capacitor. The present application can simplify the manufacturing process, reduce process costs, and improve the flexibility and applicability of the device.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a method for manufacturing a semiconductor device and a semiconductor device. Background Art

[0002] Semiconductor devices mainly include transistors, resistors and capacitors. Capacitors mainly include MOS capacitors and PIP (Poly-Insulator-Poly, polysilicon-insulator-polysilicon) capacitors. Among them, the dielectric layer in the MOS capacitor is a gate oxide layer. The thickness of the dielectric layer in the MOS capacitor needs to meet the thickness requirement of the gate oxide layer. The thickness of the dielectric layer cannot be adjusted to adjust the capacitance of the MOS capacitor, which affects the flexibility and applicability of the device. For the PIP capacitor, the first polysilicon layer, the insulating layer and the second polysilicon layer are first formed in sequence, and then the second polysilicon layer is etched into the upper plate, and then the first polysilicon layer is etched into the lower plate. The manufacturing process is complicated and the process cost is high. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a method for manufacturing a semiconductor device and a semiconductor device, which can simplify the manufacturing process, reduce the process cost, and improve the flexibility and applicability of the device.

[0004] In a first aspect, the present application provides a method for manufacturing a semiconductor device, comprising:

[0005] forming a first doped region and a second doped region laterally spaced apart in a substrate;

[0006] forming an initial dielectric layer on the substrate;

[0007] forming an initial conductive layer on the initial dielectric layer;

[0008] The initial conductive layer and the initial dielectric layer are etched to obtain a first dielectric layer and a first conductive layer sequentially located on the first doped region and a second dielectric layer and a second conductive layer sequentially located on the second doped region, the first doped region constituting a resistor, and the second doped region, the second dielectric layer and the second conductive layer constituting a capacitor.

[0009] According to the manufacturing method of the semiconductor device of the present application, a first doped region and a second doped region are first formed in a substrate, an initial dielectric layer and an initial conductive layer are sequentially formed on the substrate, and the initial conductive layer and the initial dielectric layer are etched at the same time to form a first dielectric layer on the first doped region as a barrier layer for a resistor (the first doped region constitutes a resistor), and at the same time, a second dielectric layer and a second conductive layer are formed on the second doped region, so that the second doped region, the second dielectric layer and the second conductive layer constitute a capacitor, thereby simplifying the process flow and reducing the process cost. Moreover, by adjusting the thickness of the initial dielectric layer, the thickness of the second dielectric layer can be adjusted, thereby adjusting the capacitance of the capacitor, thereby improving the flexibility and applicability of the device.

[0010] According to an embodiment of the present application, etching the initial conductive layer and the initial dielectric layer includes:

[0011] forming a mask layer on the initial conductive layer, wherein the mask layer corresponds to positions of the first doping region and the second doping region;

[0012] The initial conductive layer and the initial dielectric layer are etched using the mask layer.

[0013] According to an embodiment of the present application, before forming the initial dielectric layer on the substrate, the method further includes:

[0014] A first resistor electrode contact region, a second resistor electrode contact region and a capacitor electrode contact region are formed in the substrate; the first resistor electrode contact region and the second resistor electrode contact region are respectively located on opposite sides of the first doped region in the lateral direction and are respectively connected to the first doped region; the capacitor electrode contact region is located on one side of the second doped region in the lateral direction and is connected to the second doped region.

[0015] According to one embodiment of the present application, the method further includes:

[0016] A first resistor contact structure, a second resistor contact structure, a first capacitor contact structure and a second capacitor contact structure are formed; the first resistor contact structure is located on the first resistor electrode contact area and is connected to the first resistor electrode contact area; the second resistor contact structure is located on the second resistor electrode contact area and is connected to the second resistor electrode contact area; the first capacitor contact structure is located on the capacitor electrode contact area and is connected to the capacitor electrode contact area; the second capacitor contact structure is located on the second conductive layer and is connected to the second conductive layer.

[0017] According to one embodiment of the present application, the method further includes:

[0018] The first conductive layer is removed.

[0019] According to an embodiment of the present application, before forming the first doping region and the second doping region laterally spaced apart in the substrate, the method further includes:

[0020] forming a gate structure on the substrate; the initial dielectric layer also covers the gate structure;

[0021] A source region and a drain region are formed in the substrate, and the source region and the drain region are respectively located on two opposite sides of the gate structure in a lateral direction.

[0022] According to an embodiment of the present application, the initial dielectric layer includes a silicide barrier layer, and the initial conductive layer includes polysilicon or metal.

[0023] In a second aspect, the present application provides a semiconductor device, comprising:

[0024] A substrate including a first doped region and a second doped region that are laterally spaced apart;

[0025] A first dielectric layer, located on the first doped region;

[0026] A second dielectric layer is located on the second doped region, and the first dielectric layer and the second dielectric layer are arranged in the same layer;

[0027] A second conductive layer, located on the second dielectric layer, wherein an orthographic projection of the second conductive layer on the plane where the second dielectric layer is located coincides with the second dielectric layer;

[0028] The first doped region constitutes a resistor, and the second doped region, the second dielectric layer and the second conductive layer constitute a capacitor.

[0029] According to one embodiment of the present application, the semiconductor device further includes:

[0030] The first conductive layer is located on the first dielectric layer, and the first conductive layer and the second conductive layer are arranged on the same layer.

[0031] According to one embodiment of the present application, the substrate further includes a first resistor electrode contact region, a second resistor electrode contact region and a capacitor electrode contact region;

[0032] The first resistor electrode contact region and the second resistor electrode contact region are respectively located on opposite sides of the first doped region in the lateral direction and are respectively connected to the first doped region; the capacitor electrode contact region is located on one side of the second doped region in the lateral direction and is connected to the second doped region.

[0033] According to one embodiment of the present application, the semiconductor device further includes:

[0034] a first resistor contact structure, located on the first resistor electrode contact region and connected to the first resistor electrode contact region;

[0035] a second resistor contact structure, located on the second resistor electrode contact region and connected to the second resistor electrode contact region;

[0036] A first capacitor contact structure, located on the capacitor electrode contact area and connected to the capacitor electrode contact area;

[0037] The second capacitor contact structure is located on the second conductive layer and connected to the second conductive layer.

[0038] According to one embodiment of the present application, the semiconductor device further includes:

[0039] A gate structure, located on the substrate;

[0040] The substrate further includes a source region and a drain region, wherein the source region and the drain region are respectively located on two opposite sides of the gate structure in a lateral direction.

[0041] The above one or more technical solutions in the embodiments of the present application have at least one of the following technical effects:

[0042] First, a first doping region and a second doping region are formed in a substrate, and an initial dielectric layer and an initial conductive layer are sequentially formed on the substrate. The initial conductive layer and the initial dielectric layer are etched at the same time to form a first dielectric layer on the first doping region as a barrier layer for a resistor (the first doping region constitutes a resistor), and at the same time, a second dielectric layer and a second conductive layer are formed on the second doping region, so that the second doping region, the second dielectric layer and the second conductive layer constitute a capacitor, thereby simplifying the process flow and reducing the process cost. Moreover, by adjusting the thickness of the initial dielectric layer, the thickness of the second dielectric layer can be adjusted, thereby adjusting the capacitance of the capacitor, thereby improving the flexibility and applicability of the device.

[0043] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0045] Figure 1 It is a schematic flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0046] Figure 2 It is one of the structural schematic diagrams in the method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0047] Figure 3 This is the second structural schematic diagram of the method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0048] Figure 4 This is the third structural schematic diagram of the method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0049] Figure 5 This is the fourth structural schematic diagram of the method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0050] Figure 6 This is the fifth structural diagram of the method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0051] Figure 7 It is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0052] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0053] The following describes a method for manufacturing a semiconductor device and a semiconductor device provided in an embodiment of the present application with reference to the accompanying drawings.

[0054] Figure 1 A schematic flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application.

[0055] like Figure 1 As shown, the method for manufacturing a semiconductor device provided in an embodiment of the present application includes steps 110 to 140.

[0056] Step 110: forming a first doping region and a second doping region that are laterally spaced apart in a substrate.

[0057] Combination Figure 2 As shown, a substrate 1 is first provided. The substrate 1 may be a silicon substrate or a semiconductor substrate including other elements. The substrate 1 may have N-type doping or P-type doping, which is not specifically limited here.

[0058] Through the ion implantation process, a first doping region 11 and a second doping region 12 are formed in the substrate 1. The first doping region 11 and the second doping region 12 are both arranged close to the upper surface of the substrate 1, and the first doping region 11 and the second doping region 12 are arranged laterally spaced apart. The first doping region 11 can define a resistor region, and the second doping region 12 can define a lower plate region of a capacitor.

[0059] The first doping region 11 may be an N-type doping region or a P-type doping region, and the second doping region 12 may be an N-type doping region or a P-type doping region. The doping types of the first doping region 11 and the second doping region 12 may be the same or different. The doping concentrations of the first doping region 11 and the second doping region 12 may be set according to actual needs and are not specifically limited here.

[0060] Step 120: forming an initial dielectric layer on the substrate.

[0061] like Figure 3 As shown, a thin film deposition process is used to form an initial dielectric layer 2 on one side of the substrate 1 close to the first doping region 11 and the second doping region 12. The initial dielectric layer 2 covers the upper surface of the substrate 1, so that the initial dielectric layer 2 covers the first doping region 11 and the second doping region 12. The thin film deposition process can be physical vapor deposition, chemical vapor deposition, atomic layer deposition, laser assisted deposition, etc.

[0062] In some embodiments, the initial dielectric layer 2 may include a silicide blocking layer (SAB) or the like.

[0063] Step 130: forming an initial conductive layer on the initial dielectric layer.

[0064] like Figure 3 As shown, a thin film deposition process is used to form an initial conductive layer 3 on the side of the initial dielectric layer 2 facing away from the substrate 1. The initial conductive layer 3 covers the upper surface of the initial dielectric layer 2.

[0065] In some embodiments, the initial conductive layer 3 may include polysilicon (poly) or metals such as copper and aluminum.

[0066] Step 140, etching the initial conductive layer and the initial dielectric layer to obtain a first dielectric layer and a first conductive layer sequentially located on the first doped region and a second dielectric layer and a second conductive layer sequentially located on the second doped region, the first doped region constituting a resistor, and the second doped region, the second dielectric layer and the second conductive layer constituting a capacitor.

[0067] Combination Figures 4 to 6 As shown, the initial conductive layer 3 and the initial dielectric layer 2 are etched simultaneously, so as to etch the initial conductive layer 3 into a first conductive layer 31 and a second conductive layer 32 , and to etch the initial dielectric layer 2 into a first dielectric layer 21 and a second dielectric layer 22 .

[0068] The first dielectric layer 21 is located on the first doping region 11, the first conductive layer 31 is located on the first dielectric layer 21, and the first conductive layer 31, the first dielectric layer 21 and the first doping region 11 overlap in the longitudinal direction. The first doping region 11 constitutes a resistor, and the resistance value of the resistor can be adjusted by adjusting the doping concentration of the first doping region 11. The first dielectric layer 21, as a barrier layer of the resistor, can prevent the diffusion of doped ions in the first doping region 11 and protect the resistor.

[0069] The second dielectric layer 22 is located on the second doping region 12, the second conductive layer 32 is located on the second dielectric layer 22, and the second conductive layer 32, the second dielectric layer 22 and the second doping region 12 overlap in the longitudinal direction. The second conductive layer 32, the second dielectric layer 22 and the second doping region 12 form a capacitor, the second doping region 12 is the lower plate of the capacitor, the second conductive layer 32 is the upper plate of the capacitor, and the second dielectric layer 22 is the dielectric layer between the upper plate and the lower plate.

[0070] In some embodiments, etching the initial conductive layer and the initial dielectric layer in step 140 includes:

[0071] forming a mask layer on the initial conductive layer, wherein the mask layer corresponds to positions of the first doping region and the second doping region;

[0072] The initial conductive layer and the initial dielectric layer are etched using the mask layer.

[0073] like Figure 4 As shown, a mask layer 4 is formed on the side of the initial conductive layer 3 away from the initial dielectric layer 2. The mask layer 4 may include a first mask sublayer and a second mask sublayer that are laterally spaced apart. The first mask sublayer corresponds to the position of the first doping region 11, and the orthographic projection of the first mask sublayer on the substrate 1 may coincide with the first doping region 11, that is, the size and shape of the cross section of the first mask sublayer may be the same as the size and shape of the cross section of the first doping region 11. The second mask sublayer corresponds to the position of the second doping region 12, and the orthographic projection of the second mask sublayer on the substrate 1 may coincide with the second doping region 12, that is, the size and shape of the cross section of the second mask sublayer may be the same as the size and shape of the cross section of the second doping region 12.

[0074] like Figure 5 As shown, the initial conductive layer 3 and the initial dielectric layer 2 are etched by an etching process (such as dry etching) and using a mask layer 4, the initial dielectric layer 2 and the initial conductive layer 3 on the first doping region 11 and the second doping region 12 are retained, and the initial dielectric layer 2 and the initial conductive layer 3 on other regions are removed, thereby obtaining a first dielectric layer 21 and a first conductive layer 31 sequentially located on the first doping region 11 and a second dielectric layer 22 and a second conductive layer 32 sequentially located on the second doping region 12.

[0075] like Figure 6 As shown, after the first conductive layer 31, the second conductive layer 32, the first dielectric layer 21 and the second dielectric layer 22 are formed by etching, the mask layer 4 is removed.

[0076] Related technology When preparing a MOS capacitor, a gate oxide layer is formed on a substrate, and the gate oxide layer serves as a dielectric layer of the MOS capacitor. A gate is formed on the gate oxide layer, and the gate serves as an upper plate of the MOS capacitor. A source region and a drain region are doped in the substrate, and the source region, the drain region, and the substrate therebetween serve as a lower plate of the MOS capacitor. The gate oxide layer needs to meet certain thickness requirements, so that the dielectric layer in the MOS capacitor needs to meet certain thickness requirements. The thickness of the dielectric layer in the MOS capacitor cannot be adjusted at will to adjust the capacitance of the MOS capacitor, which affects the flexibility and applicability of the device.

[0077] In the related art, when preparing a PIP capacitor, after forming a barrier layer in the resistance area using a first mask layer, a first polysilicon layer, an insulating layer, and a second polysilicon layer are sequentially stacked in the capacitor area. Then, the first polysilicon layer is etched into the upper plate of the PIP capacitor using a second mask layer, and the second polysilicon layer is etched into the lower plate of the PIP capacitor using a third mask layer. The manufacturing process is complex and the process cost is high.

[0078] In this embodiment, the first doping region 11 and the second doping region 12 are first formed in the substrate, so that the first doping region 11 defines the resistor region, and the second doping region 12 defines the lower plate region of the capacitor. Then, an initial dielectric layer 2 and an initial conductive layer 3 are sequentially formed on the substrate, and the initial conductive layer 3 and the initial dielectric layer 2 are etched simultaneously using a mask layer to form a first dielectric layer 21 on the first doping region 11, and a second dielectric layer 22 and a second conductive layer 23 are formed on the second doping region 12. The first doping region 11 constitutes a resistor, the first dielectric layer 21 is a barrier layer of the resistor, the second doping region 12 constitutes a lower plate, the second conductive layer 23 constitutes an upper plate, and the second doping region 12, the second dielectric layer 22 and the second conductive layer 23 constitute a capacitor, that is, while the mask layer is used to etch the barrier layer of the resistor, the mask layer is used to etch the upper plate of the capacitor, and no additional mask layer is required. Compared with the PIP capacitor, this embodiment can save masks, simplify the process flow, and reduce process costs. In addition, the initial dielectric layer 2 does not need to be used as a gate oxide layer, and there is no specific requirement for the thickness of the initial dielectric layer 2, and the thickness of the initial dielectric layer 2 can be adjusted at will. Compared with the MOS capacitor, this embodiment can adjust the thickness of the second dielectric layer 22 by adjusting the thickness of the initial dielectric layer 2, thereby adjusting the capacitance of the capacitor, thereby improving the flexibility and applicability of the device.

[0079] In some embodiments, the method for manufacturing the semiconductor device further includes:

[0080] The first conductive layer is removed.

[0081] The first conductive layer 31 has no effect on the structure and performance of the resistor and can be removed. In order to avoid complicating the process flow, the first conductive layer 31 can also be retained without being processed.

[0082] In some embodiments, before forming the first doped region and the second doped region spaced apart laterally in the substrate in step 110, the method for manufacturing the semiconductor device further includes:

[0083] forming a gate structure on the substrate; the initial dielectric layer also covers the gate structure;

[0084] A source region and a drain region are formed in the substrate, and the source region and the drain region are respectively located at two opposite sides of the gate structure in the lateral direction.

[0085] Combination Figure 2 As shown, the gate structure 5 may include a gate oxide layer 51 and a gate 52. The gate oxide layer 51 is formed on the substrate 1 by a thin film deposition process. Then, the gate 52 is formed on the gate oxide layer 51 by a thin film deposition process. After the gate structure 5 is formed, an isolation layer may be formed on the periphery of the gate structure 5. The gate oxide layer 51 includes one or more combinations of silicon oxide and silicon nitride. The gate 52 may include polysilicon. The isolation layer may include one or more combinations of silicon oxide and silicon nitride.

[0086] Then, a source region 16 and a drain region 17 are formed in the substrate 1 by an ion implantation process. The source region 16 and the drain region 17 are respectively located on opposite sides of the gate structure 5 in the lateral direction. The source region 16 and the drain region 17 are respectively arranged close to the upper surface of the substrate 1. The source region 16 and the drain region 17 can be an N-type heavily doped region or a P-type heavily doped region. The source region 16, the drain region 17 and the gate structure 5 constitute a MOS transistor.

[0087] After forming the MOS transistor, a first doping region 11 and a second doping region 12 may be formed in the substrate. The source region 16, the drain region 17, the first doping region 11 and the second doping region 12 are arranged laterally spaced apart. Then, an initial dielectric layer 2 and an initial conductive layer 3 are formed in sequence. The initial dielectric layer 2 covers the upper surface of the substrate 1 and the outer surface of the gate structure 5.

[0088] In some embodiments, before forming an initial dielectric layer on the substrate in step 120, the method for manufacturing a semiconductor device further includes:

[0089] A first resistor electrode contact region, a second resistor electrode contact region and a capacitor electrode contact region are formed in the substrate; the first resistor electrode contact region and the second resistor electrode contact region are respectively located on opposite sides of the first doped region in the lateral direction and are respectively connected to the first doped region; the capacitor electrode contact region is located on one side of the second doped region in the lateral direction and is connected to the second doped region.

[0090] like Figure 2 As shown, after forming the first doping region 11, the first resistor electrode contact region 13 and the second resistor electrode contact region 14 can be formed on opposite sides of the first doping region 11 in the lateral direction by an ion implantation process, and the first resistor electrode contact region 13 and the second resistor electrode contact region 14 are respectively connected to the first doping region 11. The first resistor electrode contact region 13 and the second resistor electrode contact region 14 are respectively arranged close to the upper surface of the substrate 1, and the first resistor electrode contact region 13, the second resistor electrode contact region 14, the source region 16 and the drain region 17 are laterally spaced. The first resistor electrode contact region 13 and the second resistor electrode contact region 14 can be N-type heavily doped regions or P-type heavily doped regions, respectively. The first resistor electrode contact region 13 and the second resistor electrode contact region 14 are used to lead out the two electrodes of the resistor.

[0091] After forming the second doping region 12, a capacitor electrode contact region 15 can be formed on any side of the second doping region 12 in the lateral direction by an ion implantation process, and the capacitor electrode contact region 15 is connected to the second doping region 12. The capacitor electrode contact region 15 is arranged close to the upper surface of the substrate 1, and the capacitor electrode contact region 15, the first resistor electrode contact region 13, the second resistor electrode contact region 14, the source region 16 and the drain region 17 are arranged laterally at intervals. The capacitor electrode contact region 15 can be an N-type heavily doped region or a P-type heavily doped region. The capacitor electrode contact region 15 is used to lead out the lower plate of the capacitor.

[0092] In some embodiments, the method for manufacturing the semiconductor device further includes:

[0093] A first resistor contact structure, a second resistor contact structure, a first capacitor contact structure and a second capacitor contact structure are formed; the first resistor contact structure is located on the first resistor electrode contact area and is connected to the first resistor electrode contact area; the second resistor contact structure is located on the second resistor electrode contact area and is connected to the second resistor electrode contact area; the first capacitor contact structure is located on the capacitor electrode contact area and is connected to the capacitor electrode contact area; the second capacitor contact structure is located on the second conductive layer and is connected to the second conductive layer.

[0094] After forming the resistors and capacitors, such as Figure 7As shown, a thin film deposition process can be used to form an insulating layer 6. The insulating layer 6 covers the substrate 1, the first conductive layer 31, the second conductive layer 32 and the gate structure 5, and the upper surface of the insulating layer 6 is a plane. The insulating layer 6 can include one or more combinations of silicon oxide and silicon nitride.

[0095] Then, an etching process is used to form a first resistor contact hole, a second resistor contact hole, a first capacitor contact hole, and a second capacitor contact hole. The first resistor contact hole is located above the first resistor electrode contact area 13, and penetrates the insulating layer 6, exposing a portion of the first resistor electrode contact area 13. The second resistor contact hole is located above the second resistor electrode contact area 14, and penetrates the insulating layer 6, exposing a portion of the second resistor electrode contact area 14. The first capacitor contact hole is located above the capacitor electrode contact area 15, and penetrates the insulating layer 6, exposing a portion of the capacitor electrode contact area 15. The second capacitor contact hole is located above the second conductive layer 32, and penetrates the insulating layer 6, exposing a portion of the second conductive layer 32.

[0096] Then, a first resistor contact structure 71 is formed in the first resistor contact hole, that is, the first resistor contact structure 71 penetrates the insulating layer 6 and contacts the first resistor electrode contact area 13, so that the first resistor contact structure 71 leads out one electrode of the resistor. A second resistor contact structure 72 is formed in the second resistor contact hole, that is, the second resistor contact structure 72 penetrates the insulating layer 6 and contacts the second resistor electrode contact area 14, so that the second resistor contact structure 72 leads out the other electrode of the resistor. A first capacitor contact structure 73 is formed in the first capacitor contact hole, that is, the first capacitor contact structure 73 penetrates the insulating layer 6 and contacts the capacitor electrode contact area 15, so that the first capacitor contact structure 73 leads out the lower plate of the capacitor. A second capacitor contact structure 74 is formed in the second capacitor contact hole, that is, the second capacitor contact structure 74 penetrates the insulating layer 6 and contacts the second conductive layer 32, so that the second capacitor contact structure 74 leads out the upper plate of the capacitor.

[0097] The first resistive contact structure 71 , the second resistive contact structure 72 , the first capacitive contact structure 73 and the second capacitive contact structure 74 may include metals such as copper, aluminum, and tungsten, respectively.

[0098] In the case where the semiconductor device also includes a transistor, a source contact hole, a drain contact hole and a gate contact hole are formed while forming the first resistor contact hole, the second resistor contact hole, the first capacitor contact hole and the second capacitor contact hole. The source contact hole is located above the source region 16 and penetrates the insulating layer 6 to expose a portion of the source region 16. The drain contact hole is located above the drain region 17 and penetrates the insulating layer 6 to expose a portion of the drain region 17. The gate contact hole is located above the gate 52 and penetrates the insulating layer 6 to expose a portion of the gate 52.

[0099] Then, a source contact structure 75 is formed in the source contact hole, that is, the source contact structure 75 penetrates the insulating layer 6 and is connected to the source region 16, so that the source contact structure 75 leads out the source of the transistor. A drain contact structure 76 is formed in the drain contact hole, that is, the drain contact structure 76 penetrates the insulating layer 6 and is connected to the drain region 17, so that the drain contact structure 76 leads out the drain of the transistor. A gate contact structure 77 is formed in the gate contact hole, that is, the gate contact structure 77 penetrates the insulating layer 6 and is connected to the gate 52, so that the gate contact structure 77 leads out the gate of the transistor.

[0100] The source contact structure 75 , the drain contact structure 76 and the gate contact structure 77 may respectively include metals such as copper, aluminum, and tungsten.

[0101] In some embodiments, the method for manufacturing the semiconductor device further includes:

[0102] A wiring layer is formed on a side of the insulating layer facing away from the substrate, and the wiring layer is respectively connected to the first resistive contact structure, the second resistive contact structure, the first capacitive contact structure, and the second contact structure.

[0103] Combination Figure 7 As shown, a thin film deposition process is used to form a wiring layer 8 on the side of the insulating layer 6 facing away from the substrate 1. The wiring layer 8 is respectively connected to the first resistor contact structure 71, the second resistor contact structure 72, the first capacitor contact structure 73 and the second contact structure 74. The wiring layer 8 is also respectively connected to the source contact structure 75, the drain contact structure 76 and the gate contact structure 77. The wiring layer 8 may include metals such as copper and aluminum.

[0104] In summary, according to the method for manufacturing a semiconductor device provided in an embodiment of the present application, a first doped region 11 and a second doped region 12 are first formed in a substrate 1, an initial dielectric layer 2 and an initial conductive layer 3 are sequentially formed on the substrate 1, and the initial conductive layer 2 and the initial dielectric layer 3 are etched at the same time to form a first dielectric layer 21 on the first doped region 11 as a barrier layer for a resistor (the first doped region 11 constitutes a resistor), and at the same time, a second dielectric layer 22 and a second conductive layer 32 are formed on the second doped region 12, so that the second doped region 12, the second dielectric layer 22 and the second conductive layer 32 constitute a capacitor, thereby simplifying the process flow and reducing the process cost. Moreover, by adjusting the thickness of the initial dielectric layer 2, the thickness of the second dielectric layer 22 can be adjusted, thereby adjusting the capacitance of the capacitor, thereby improving the flexibility and applicability of the device.

[0105] Correspondingly, an embodiment of the present application also provides a semiconductor device that can be manufactured using the semiconductor device manufacturing method in the above embodiment.

[0106] like Figure 7As shown, the semiconductor device provided in the embodiment of the present application includes a substrate 1 , a first dielectric layer 21 , a second dielectric layer 22 and a second conductive layer 32 .

[0107] The substrate 1 may be a silicon substrate or a semiconductor substrate including other elements. The substrate 1 includes a first doping region 11 and a second doping region 12 which are arranged laterally and spaced apart. The first doping region 11 and the second doping region 12 are both arranged close to the upper surface of the substrate 1. The first doping region 11 may define a resistor region, and the second doping region 12 may define a lower plate region of a capacitor.

[0108] The first dielectric layer 21 is located on the first doped region 11. The orthographic projection of the first dielectric layer 21 on the substrate 1 coincides with the first doped region 11. The first doped region 11 forms a resistor, and the first dielectric layer 21 is a barrier layer of the resistor. The first dielectric layer 21 may include a silicide barrier layer (SAB) or the like.

[0109] The second dielectric layer 22 is located on the second doped region 12. The orthographic projection of the second dielectric layer 22 on the substrate 1 coincides with the second doped region 12. The first dielectric layer 21 and the second dielectric layer 22 are arranged in the same layer, and the first dielectric layer 21 and the second dielectric layer 22 are formed in the same process. The second dielectric layer 22 may include a silicide barrier layer (SAB) and the like.

[0110] The second conductive layer 32 is located on the second dielectric layer 22. The orthographic projection of the second conductive layer 32 on the plane where the second dielectric layer 22 is located coincides with the second dielectric layer 22. The first dielectric layer 21, the second dielectric layer 22 and the second conductive layer 32 are formed in the same process. The second conductive layer 32 may include polysilicon or metals such as copper and aluminum.

[0111] The second doped region 12, the second dielectric layer 22 and the second conductive layer 32 form a capacitor. The second doped region 12 is the lower plate of the capacitor, the second conductive layer 32 is the upper plate of the capacitor, and the second dielectric layer 22 is the dielectric layer between the upper plate and the lower plate.

[0112] In this embodiment, while forming the barrier layer of the resistor (i.e., the first dielectric layer 21), the dielectric layer of the capacitor (i.e., the second dielectric layer 22) and the upper plate (the second conductive layer 32) are formed, thereby simplifying the manufacturing process and reducing the process cost. In addition, by adjusting the thickness of the second dielectric layer 22, the capacitance of the capacitor is adjusted, thereby improving the flexibility and applicability of the device.

[0113] In some embodiments, the semiconductor device further includes a first conductive layer 31. The first conductive layer 31 is located on the first dielectric layer 21, and the orthographic projection of the first conductive layer 31 on the plane where the first dielectric layer 21 is located coincides with the first dielectric layer 21. The first conductive layer 31 and the second conductive layer 32 are disposed in the same layer. The first dielectric layer 21, the second dielectric layer 22, the first conductive layer 31, and the second conductive layer 32 are formed in the same process.

[0114] In some embodiments, the semiconductor device further includes a gate structure 5, which is located on the substrate 1. The substrate 1 further includes a source region 16 and a drain region 17, which are respectively located on opposite sides of the gate structure 5 in the lateral direction. The source region 16, the drain region 17 and the gate structure 5 constitute a MOS transistor.

[0115] In some embodiments, the gate structure 5 may include a gate oxide layer 51 and a gate 52. The gate oxide layer 51 is located on the substrate 1, and the gate 52 is located on the gate oxide layer 51. The gate oxide layer 51 includes one or more combinations of silicon oxide and silicon nitride. The gate 52 may include polysilicon. The isolation layer may include one or more combinations of silicon oxide and silicon nitride.

[0116] In some embodiments, the substrate 1 further includes a first resistor electrode contact region 13, a second resistor electrode contact region 14, and a capacitor electrode contact region 15. The first resistor electrode contact region 13 and the second resistor electrode contact region 14 are respectively located on opposite sides of the first doping region 11 in the lateral direction, and are respectively connected to the first doping region 11. The capacitor electrode contact region 15 is located on one side of the second doping region 12 in the lateral direction, and is connected to the second doping region 12.

[0117] The first resistor electrode contact region 13 and the second resistor electrode contact region 14 are respectively heavily doped regions, used to lead out two electrodes of the resistor. The capacitor electrode contact region 15 is a heavily doped region, used to lead out the lower plate of the capacitor.

[0118] In some embodiments, the semiconductor device further includes a first resistive contact structure 71, a second resistive contact structure 72, a first capacitive contact structure 73, and a second capacitive contact structure 74. The first resistive contact structure 71 is located on the first resistive electrode contact area 13 and is connected to the first resistive electrode contact area 13. The second resistive contact structure 72 is located on the second resistive electrode contact area 14 and is connected to the second resistive electrode contact area 14. The first capacitive contact structure 73 is located on the capacitive electrode contact area 15 and is connected to the capacitive electrode contact area 15. The second capacitive contact structure 74 is located on the second conductive layer 32 and is connected to the second conductive layer 32.

[0119] The first resistive contact structure 71 , the second resistive contact structure 72 , the first capacitive contact structure 73 and the second capacitive contact structure 74 may include metals such as copper, aluminum, and tungsten, respectively.

[0120] In some embodiments, the semiconductor device further includes a source contact structure 75, a drain contact structure 76, and a gate contact structure 77. The source contact structure 75 is located on the source region 16 and connected to the source region 16. The drain contact structure 76 is located on the drain region 17 and connected to the drain region 17. The gate contact structure 77 is located on the gate 52 and connected to the gate 52.

[0121] The source contact structure 75 , the drain contact structure 76 and the gate contact structure 77 may respectively include metals such as copper, aluminum, and tungsten.

[0122] In some embodiments, the semiconductor device further includes a wiring layer 8. The wiring layer 8 is respectively connected to the first resistive contact structure 71, the second resistive contact structure 72, the first capacitive contact structure 73 and the second contact structure 74. The wiring layer 8 is also respectively connected to the source contact structure 75, the drain contact structure 76 and the gate contact structure 77. The wiring layer 9 may include metals such as copper and aluminum.

[0123] According to the semiconductor device provided by the embodiment of the present application, the first dielectric layer 21 and the second dielectric layer 22 are arranged in the same layer, and the orthographic projection of the second conductive layer 32 on the plane where the second dielectric layer 22 is located coincides with the second dielectric layer 22, that is, the first dielectric layer 21, the second dielectric layer 22, and the second conductive layer 32 are formed in the same process, that is, while forming the barrier layer of the resistor (that is, the first dielectric layer 21), the dielectric layer of the capacitor (that is, the second dielectric layer 22) and the upper plate (the second conductive layer 32) are formed, which simplifies the manufacturing process, reduces the process cost, and adjusts the capacitance of the capacitor by adjusting the thickness of the second dielectric layer 22, thereby improving the flexibility and applicability of the device.

[0124] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more.

[0125] In the description of the present application, “plurality” means two or more.

[0126] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0127] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: forming a first doped region and a second doped region laterally spaced apart in a substrate; forming an initial dielectric layer on the substrate; forming an initial conductive layer on the initial dielectric layer; The initial conductive layer and the initial dielectric layer are etched to obtain a first dielectric layer and a first conductive layer sequentially located on the first doped region and a second dielectric layer and a second conductive layer sequentially located on the second doped region, the first doped region constituting a resistor, and the second doped region, the second dielectric layer and the second conductive layer constituting a capacitor.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The etching of the initial conductive layer and the initial dielectric layer comprises: forming a mask layer on the initial conductive layer, wherein the mask layer corresponds to positions of the first doping region and the second doping region; The initial conductive layer and the initial dielectric layer are etched using the mask layer.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: Before forming the initial dielectric layer on the substrate, the method further comprises: A first resistor electrode contact region, a second resistor electrode contact region and a capacitor electrode contact region are formed in the substrate; the first resistor electrode contact region and the second resistor electrode contact region are respectively located at opposite sides of the first doped region in a lateral direction and are respectively connected to the first doped region; the capacitor electrode contact region is located at one side of the second doped region in a lateral direction and is connected to the second doped region; After etching the initial conductive layer and the initial dielectric layer, the method further includes: A first resistor contact structure, a second resistor contact structure, a first capacitor contact structure and a second capacitor contact structure are formed; the first resistor contact structure is located on the first resistor electrode contact area and is connected to the first resistor electrode contact area; the second resistor contact structure is located on the second resistor electrode contact area and is connected to the second resistor electrode contact area; the first capacitor contact structure is located on the capacitor electrode contact area and is connected to the capacitor electrode contact area; the second capacitor contact structure is located on the second conductive layer and is connected to the second conductive layer.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The method further comprises: The first conductive layer is removed.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: Before forming the first doping region and the second doping region which are laterally spaced apart in the substrate, the method further comprises: forming a gate structure on the substrate; the initial dielectric layer also covers the gate structure; A source region and a drain region are formed in the substrate, and the source region and the drain region are respectively located on opposite sides of the gate structure in a lateral direction.

6. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, characterized in that: The initial dielectric layer includes a silicide barrier layer, and the initial conductive layer includes polysilicon or metal.

7. A semiconductor device, characterized in that: include: A substrate including a first doped region and a second doped region that are laterally spaced apart; A first dielectric layer, located on the first doped region; A second dielectric layer is located on the second doped region, and the first dielectric layer and the second dielectric layer are arranged in the same layer; A second conductive layer, located on the second dielectric layer, wherein an orthographic projection of the second conductive layer on the plane where the second dielectric layer is located coincides with the second dielectric layer; The first doped region constitutes a resistor, and the second doped region, the second dielectric layer and the second conductive layer constitute a capacitor.

8. The semiconductor device according to claim 7, characterized in that The semiconductor device further comprises: The first conductive layer is located on the first dielectric layer, and the first conductive layer and the second conductive layer are arranged on the same layer.

9. The semiconductor device according to claim 7, characterized in that The substrate further comprises a first resistor electrode contact region, a second resistor electrode contact region and a capacitor electrode contact region; The first resistor electrode contact region and the second resistor electrode contact region are respectively located at opposite sides of the first doped region in a lateral direction and are respectively connected to the first doped region; the capacitor electrode contact region is located at one side of the second doped region in a lateral direction and is connected to the second doped region; The semiconductor device further comprises: a first resistor contact structure, located on the first resistor electrode contact region and connected to the first resistor electrode contact region; a second resistor contact structure, located on the second resistor electrode contact region and connected to the second resistor electrode contact region; A first capacitor contact structure, located on the capacitor electrode contact area and connected to the capacitor electrode contact area; The second capacitor contact structure is located on the second conductive layer and connected to the second conductive layer.

10. The semiconductor device according to any one of claims 7 to 9, characterized in that: The semiconductor device further comprises: A gate structure, located on the substrate; The substrate further includes a source region and a drain region, wherein the source region and the drain region are respectively located on two opposite sides of the gate structure in a lateral direction.

Images