Semiconductor device

Abstract

A semiconductor device includes: an active pattern protruding from a substrate and including a plurality of stacked semiconductor patterns; a gate pattern disposed on the active pattern and crossing the active pattern; a gate insulating pattern between the active pattern and the gate pattern; a gate spacer at a side of the gate pattern and on the active pattern; and a cap pattern disposed between the active pattern and the gate spacer and in physical contact with the active pattern, where the cap pattern has a crystal structure.

Description

[0001] This application is a divisional application of a patent application with an application date of April 30, 2020, application number 202010360788.2, and invention name “Method for manufacturing a semiconductor device”. Technical Field

[0002] Embodiments of the inventive concept relate to a semiconductor device, and more particularly, to a semiconductor device including a field effect transistor and a method of manufacturing the semiconductor device. Background Art

[0003] Semiconductor devices are widely used in the electronics industry due to their small size, multifunctional characteristics and / or low manufacturing cost. As the electronics industry develops, semiconductor devices with increasing performance characteristics and improved features are needed. In order to meet these needs, semiconductor devices are highly integrated, and the structure of semiconductor devices becomes more and more complex. Summary of the invention

[0004] Embodiments of the inventive concept may provide a semiconductor device having improved reliability and a method of manufacturing the semiconductor device.

[0005] In some embodiments of the present inventive concept, a method of manufacturing a semiconductor device includes: forming an active pattern on a substrate, the active pattern including a first semiconductor pattern and a second semiconductor pattern alternately stacked; forming a cap pattern on a top surface and a sidewall of the active pattern; performing a deposition process on the cap pattern to form an insulating layer; and forming a sacrificial gate pattern crossing the active pattern on the insulating layer. The cap pattern has a crystalline structure and is in physical contact with the sidewalls of the first semiconductor pattern and the sidewalls of the second semiconductor pattern.

[0006] In some embodiments of the present inventive concept, a method of manufacturing a semiconductor device includes: forming an active pattern protruding from a substrate, the active pattern including a first semiconductor pattern and a second semiconductor pattern alternately stacked; forming a device isolation pattern on the substrate, an upper portion of the active pattern having no device isolation pattern; forming a cap pattern on a top surface and a sidewall of the active pattern, the top surface of the device isolation pattern having no cap pattern; forming an insulating layer on the top surface of the device isolation pattern and the cap pattern; and forming a sacrificial gate pattern crossing the active pattern on the insulating layer. The cap pattern is in physical contact with a first sidewall of the first semiconductor pattern and a second sidewall of the second semiconductor pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The inventive concept will become more apparent from the accompanying drawings and the accompanying detailed description.

[0008] Figure 1 is a top view illustrating a semiconductor device according to some embodiments of the inventive concept.

[0009] Figures 2A to 2L are views illustrating a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0010] Figure 3A and Figure 3B are views illustrating a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0011] FIG. 4A to FIG. 4E are views illustrating a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0012] Figure 4F and Figure 4G are views illustrating a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0013] FIG. 5A to FIG. 5H are views illustrating a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0014] Fig.5I and Figure 5J are views illustrating a method of fabricating a semiconductor device according to some embodiments of the inventive concept. DETAILED DESCRIPTION

[0015] Throughout the specification, the same reference numerals or the same reference designators may denote the same elements or components. Elements or components indicated by the same reference numerals or reference designators may be formed by the same method unless otherwise specified.

[0016] As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items. It will be understood that when an element is referred to as "on" another element, "attached" to another element, "connected" to another element, "coupled" to another element, "contacting" another element, etc., it can be directly on the other element, attached to the other element, connected to the other element, coupled to the other element or contacting the other element, or there may be an intermediate element. In contrast, when an element is referred to as, for example, "directly on" another element, "directly attached" to another element, "directly connected" to another element, "directly coupled" to another element, or "directly contacting" another element, there is no intermediate element. Note that aspects described with respect to one embodiment can be incorporated into different embodiments, although no specific description is made thereon. That is, all embodiments and / or features of any embodiment can be combined in any manner and / or combination. Semiconductor devices and methods for manufacturing the semiconductor devices according to some embodiments of the present invention will be described below.

[0017] Figure 1 is a top view illustrating a semiconductor device according to some embodiments of the inventive concept. Figures 2A to 2L are views illustrating a method of fabricating a semiconductor device according to some embodiments of the inventive concept. FIG. 2A to FIG. 2D and Figure 2F to Figure 2L is along Figure 1 Cross-sectional views taken along lines II' and II-II'. Figure 2E yes Figure 2D Magnified view of region “III”.

[0018] Reference Figure 1 and Figure 2A , the first semiconductor layer 210P and the second semiconductor layer 220P may be stacked on the substrate 100. The substrate 100 may be a semiconductor substrate. For example, the substrate 100 may be a silicon substrate, a silicon germanium substrate, or a silicon on insulator (SOI) substrate. The first semiconductor layer 210P and the second semiconductor layer 220P may be formed by performing an epitaxial growth process using the substrate 100 as a seed layer. For example, the epitaxial growth process may be performed by a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process. The first semiconductor layer 210P and the second semiconductor layer 220P may be continuously formed in the same chamber. That is, the first semiconductor layer 210P and the second semiconductor layer 220P may be formed in situ. The first semiconductor layer 210P and the second semiconductor layer 220P may be conformally grown on the entire surface of the substrate 100, rather than on a partial region of the substrate 100. The first semiconductor layer 210P and the second semiconductor layer 220P may be alternately and repeatedly stacked on the substrate 100. The number of the first semiconductor layer 210P and the number of the second semiconductor layer 220P may be variously changed according to different embodiments of the present invention. The first semiconductor layer 210P may be used as a sacrificial layer or a channel region of a transistor. Each of the first semiconductor layers 210P may be a germanium-containing layer. For example, each of the first semiconductor layers 210P may include at least one of silicon germanium (SiGe) and germanium (Ge). The first semiconductor layer 210P may also include a dopant. For example, the dopant may include at least one of Al, Ga, Sb, As, In, Ge, Zr, Hf, and Ta. For example, each of the first semiconductor layers 210P may be a silicon germanium (SiGe) layer doped with aluminum (Al). Each of the first semiconductor layers 210P may have a uniform composition ratio. Each of the second semiconductor layers 220P may be a silicon-containing layer such as a silicon (Si) layer. For example, the second semiconductor layer 220P may include polycrystalline silicon.

[0019] Reference Figure 1 and Figure 2B, the basic active pattern 110 and the active pattern 200 may be formed on the substrate 100. The formation of the basic active pattern 110 and the active pattern 200 may include patterning the first semiconductor layer 210P, the second semiconductor layer 220P, and the upper portion of the substrate 100 to form the groove 105. The basic active pattern 110 and the active pattern 200 may be defined by the groove 105. Each of the grooves 105 may have a linear shape extending in the first direction D1. The grooves 105 may be spaced apart from each other in the second direction D2. The first direction D1 may be parallel to the bottom surface of the substrate 100. The second direction D2 may be parallel to the bottom surface of the substrate 100 and may be substantially perpendicular to the first direction D1. The active pattern 200 may include a first semiconductor pattern 210 and a second semiconductor pattern 220. The first semiconductor pattern 210 may be formed by patterning the first semiconductor layer 210P. The second semiconductor pattern 220 may be formed by patterning the second semiconductor layer 220P.

[0020] The active pattern 200 may have a linear shape extending in the first direction D1. The first semiconductor pattern 210 and the second semiconductor pattern 220 may be alternately and repeatedly stacked in a direction perpendicular to the bottom surface of the substrate 100. The first semiconductor pattern 210 and the second semiconductor pattern 220 may have a linear shape extending in the first direction D1. The top surface 200a of the active pattern 200 may correspond to the top surface of the uppermost one of the second semiconductor patterns 220. The sidewall 200c of the active pattern 200 may include the sidewall of the first semiconductor pattern 210 and the sidewall of the second semiconductor pattern 220. The basic active pattern 110 may be formed by patterning the upper portion of the substrate 100. The basic active pattern 110 may have a linear shape extending in the first direction D1, and the active pattern 200 may be formed on the top surface of the basic active pattern 110.

[0021] The liner pattern 135 and the device isolation pattern 130 may be formed in the trench 105, respectively. The device isolation pattern 130 may be formed on the substrate 100 at both sides of the base active pattern 110. The device isolation pattern 130 may extend in the first direction D1. In some embodiments, a liner layer may be conformally formed on the sidewalls of the base active pattern 110, and the top surface 200a and the sidewalls 200c of the active pattern 200, as shown by the dotted lines. The formation of the device isolation pattern 130 may include forming an insulating layer at least partially filling the trench 105 on the liner layer as shown by the dotted lines, and recessing the insulating layer to expose the sidewalls 200c of the active pattern 200. Figure 2BAs shown in the cross-sectional view of , the top surface of the device isolation pattern 130 may be lower than the top surface of the base active pattern 110. The liner layer may be recessed to form a liner pattern 135. The liner pattern 135 may expose at least an upper portion of the active pattern 200. The liner pattern 135 may be disposed between the substrate 100 and the device isolation pattern 130 and between the base active pattern 110 and the device isolation pattern 130. The liner pattern 135 may include, for example, silicon nitride. The device isolation pattern 130 may include oxide, nitride and / or oxynitride.

[0022] Reference Figure 1 and Figure 2C , the cap pattern 300 may be formed on the top surface 200a and the sidewall 200c of the active pattern 200. The cap pattern 300 may be in physical contact with the top surface of the uppermost one of the second semiconductor patterns 220, and the sidewalls of the first semiconductor pattern 210 and the sidewalls of the second semiconductor pattern 220. Due to the cap pattern 300, the first semiconductor pattern 210 and the second semiconductor pattern 220 may not be exposed to the external environment. The cap pattern 300 may include a semiconductor material such as silicon. In some embodiments, the cap pattern 300 may not include oxygen. Therefore, the first semiconductor pattern 210 may not be oxidized by the cap pattern 300. The cap pattern 300 may not include nitrogen and germanium. As used herein, when a component is described as not including a certain element, it may not include the element, or it may include a very small amount of the element within the tolerance of one or more processes. For example, the cap pattern 300 may include a material different from that of the first semiconductor pattern 210, and may include the same material as the second semiconductor pattern 220.

[0023] In some embodiments, the cap pattern 300 may include an epitaxial pattern. For example, the formation of the cap pattern 300 may be performed by an epitaxial growth process using the first semiconductor pattern 210 and the second semiconductor pattern 220 as a seed layer. For example, the epitaxial growth process may be performed at a temperature of about 300 degrees Celsius to about 950 degrees Celsius using a silicon-containing gas as a source gas. The silicon-containing gas may include monosilane, disilane, trichlorosilane, and / or tetrachlorosilane.

[0024] In some embodiments, the cap pattern 300 may have a polycrystalline structure. For example, the cap pattern 300 may include polycrystalline silicon. In this case, the formation of the cap pattern 300 may be performed by a deposition process. In some embodiments, the deposition process may include forming a seed layer using, for example, diisopropylaminosilane (DIPAS).

[0025] The capping pattern 300 may have a first thickness T1, and the first thickness T1 may be about to about If the first thickness T1 is greater than It may be difficult to form fine pitches of semiconductor devices.

[0026] Before the formation of the capping pattern 300, a cleaning process may be performed on the active pattern 200. For example, the cleaning process may use NH 4 OH, H 2 O and O 2 mixture (SC1) or sulfuric acid (H 2 SO 4 ) and hydrogen peroxide (H 2 O 2 In another example, the cleaning process may be performed using a mixture of NF 3 、F 2 In another example, the cleaning process may be performed by a low-temperature dry cleaning process using plasma, such as a SiConi cleaning process. When the cleaning process is performed, the formation of interface defects between the cap pattern 300 and the active pattern 200 may be suppressed or prevented.

[0027] Reference Figure 1 , Figure 2D and Figure 2E , an insulating layer 311, a sacrificial gate layer 321, and a mask pattern 330 may be sequentially formed on the cap pattern 300. The insulating layer 311 may be formed by a deposition process. The insulating layer 311 may include a semiconductor oxide such as silicon oxide. The insulating layer 311 may have an oxygen content ratio greater than that of the cap pattern 300. The cap pattern 300 may be exposed in the process of forming the insulating layer 311, and thus, at least a portion of the cap pattern 300 may be oxidized. As a result, after the process of forming the insulating layer 311, the cap pattern 300 may have a second thickness T2 that is less than the first thickness T1.

[0028] If the capping pattern 300 includes germanium, the quality of the insulating layer 311 may be deteriorated. According to some embodiments, the capping pattern 300 may not include germanium, and thus, the quality of the insulating layer 311 may be improved.

[0029] Each of the first semiconductor patterns 210 may include a first portion 211 and a second portion 212. Figure 2EAs shown. The first portion 211 of each of the first semiconductor patterns 210 may be a portion including the sidewall 210c of the first semiconductor pattern 210. The first portion 211 may be in physical contact with the cap pattern 300. The second portion 212 of each of the first semiconductor patterns 210 may be provided between the first portions 211. If the cap pattern 300 is omitted, the first portion 211 of the first semiconductor pattern 210 may be exposed in the process of forming the insulating layer 311, and thus, may be oxidized. However, according to some embodiments, the cap pattern 300 may prevent the first semiconductor pattern 210 from being exposed in the process of forming the insulating layer 311. Therefore, oxidation of the first portion 211 of the first semiconductor pattern 210 may be reduced or prevented. After the process of forming the insulating layer 311, the first portion 211 of the first semiconductor pattern 210 may not include oxygen. The element composition ratio or component composition ratio of the first portion 211 of the first semiconductor pattern 210 may be substantially equal to the element composition ratio or component composition ratio of the second portion 212 of the first semiconductor pattern 210.

[0030] if Figure 2C The first thickness T1 of the cap pattern 300 is less than It may be difficult to prevent the first semiconductor pattern 210 and the second semiconductor pattern 220 from being oxidized in the process of forming the insulating layer 311. However, according to an embodiment, the capping pattern 300 may have or greater first thickness T1.

[0031] The sacrificial gate layer 321 may be formed on the insulating layer 311 to at least partially cover the insulating layer 311. The sacrificial gate layer 321 may include, for example, polysilicon. The mask pattern 330 may be formed on the sacrificial gate layer 321. For example, the mask pattern 330 may include silicon nitride, silicon carbon nitride, and / or silicon oxycarbon nitride.

[0032] Reference Figure 1 and Figure 2F The sacrificial gate layer 321 and the insulating layer 311 may be patterned by an etching process to form a sacrificial gate pattern 320 and an insulating pattern 310. The mask pattern 330 may be used as an etching mask in the etching process. The sacrificial gate pattern 320 and the insulating pattern 310 may extend along the second direction D2 on the substrate 100 and may intersect the active pattern 200, the base active pattern 110, and the device isolation pattern 130.

[0033] The capping pattern 300 may have an etching selectivity with respect to at least the insulating layer 311. In the etching process, an etching rate of the capping pattern 300 may be lower than an etching rate of at least the insulating layer 311. The etching process may be performed until the capping pattern 300 is exposed.

[0034] The gate spacer 350 may be formed on the top surface of the cap pattern 300 at both sides of the sacrificial gate pattern 320. The gate spacer 350 may cover the sidewalls of the insulating pattern 310 and the sidewalls of the sacrificial gate pattern 320. For example, the gate spacer 350 may include silicon nitride, silicon carbon nitride and / or silicon oxycarbon nitride. In some embodiments, a spacer layer may be formed on the substrate 100 to at least partially cover the cap pattern 300, the insulating pattern 310, the sacrificial gate pattern 320 and the mask pattern 330. An etching process may be performed on the spacer layer to form the gate spacer 350. The etching process of the spacer layer may be an anisotropic etching process. In the etching process of the spacer layer, the cap pattern 300 may have an etching selectivity relative to the spacer layer. For example, the etching rate of the cap pattern 300 may be lower than the etching rate of the spacer layer. After the formation of the gate spacer 350, portions of the capping pattern 300 may be provided on the active pattern 200 at both sides of the sacrificial gate pattern 320 and may be exposed by the gate spacer 350 and the mask pattern 330. Figure 2F Differently, in other embodiments of the present inventive concept, portions of the capping pattern 300 exposed by the gate spacer 350 and the mask pattern 330 may also be etched in the etching process of the spacer layer. In this case, the capping pattern 300 may partially remain under the gate spacer 350 and the sacrificial gate pattern 320.

[0035] Reference Figure 1 and Figure 2G , a recessed portion 140 may be formed in the active pattern 200. The formation of the recessed portion 140 may include etching a portion of the active pattern 200 and a portion of the capping pattern 300 using the mask pattern 330 and the gate spacer 350 as an etching mask. The portion of the active pattern 200 may be etched until the top surface of the base active pattern 110 is exposed. Therefore, the recessed portion 140 may be formed on both sides of the sacrificial gate pattern 320, and the top surface of the base active pattern 110 may be exposed. The sidewalls of the first semiconductor pattern 210 and the sidewalls of the second semiconductor pattern 220 may be exposed by the recessed portion 140. Figure 2G Differently, in other embodiments of the present inventive concept, a portion of the basic active pattern 110 may also be etched in the etching process of the portion of the active pattern 200 , and thus, the recess portion 140 may extend into the basic active pattern 110 .

[0036] Portions of the first semiconductor pattern 210 may be laterally recessed to form a recessed region 215. The recessed region 215 may be formed between the second semiconductor patterns 220 and between the lowermost one of the base active pattern 110 and the second semiconductor pattern 220, as shown in FIG. Figure 2GThe formation of the recessed region 215 may include etching the exposed sidewalls of the first semiconductor pattern 210 by using an etching source having a relatively high etching rate with respect to the first semiconductor pattern 210 .

[0037] Reference Figure 1 and Figure 2H , insulating spacers 250 may be formed in the recessed regions 215, respectively. The insulating spacers 250 may at least partially cover the two recessed sidewalls of each first semiconductor pattern 210. The formation of the insulating spacers 250 may include conformally forming a blocking insulating layer (not shown) at least partially filling the recessed regions 215 on the first semiconductor pattern 210 and the second semiconductor pattern 220, and performing an etching process (e.g., an anisotropic etching process) on the blocking insulating layer. For example, the insulating spacers 250 may include silicon nitride and / or silicon oxycarbon nitride.

[0038] The source / drain pattern SD may be formed on the base active pattern 110 at both sides of the sacrificial gate pattern 320. The source / drain pattern SD may be formed by performing a selective epitaxial growth (SEG) process using the second semiconductor pattern 220 and the base active pattern 110 exposed by the recessed portion 140 as a seed layer. The source / drain patterns SD may be provided in the recessed portions 140, respectively. Each of the source / drain patterns SD may be in physical contact with the sidewall of the capping pattern 300, the exposed sidewall of the second semiconductor pattern 220, the insulating spacer 250, and the top surface of the base active pattern 110. The insulating spacer 250 may be disposed between each of the source / drain patterns SD and the first semiconductor pattern 210, respectively. The source / drain pattern SD may be spaced apart from the first semiconductor pattern 210.

[0039] The source / drain pattern SD may include silicon germanium (SiGe), silicon (Si) and / or silicon carbide (SiC). The formation of the source / drain pattern SD may further include doping the source / drain pattern SD with a dopant. The electrical characteristics of the transistor including the source / drain pattern SD may be improved by the incorporation of the dopant. When the transistor is an NMOSFET, the dopant may include, for example, phosphorus (P). When the transistor is a PMOSFET, the dopant may include, for example, boron (B).

[0040] The interlayer insulating layer 400 may be formed on the substrate 100 to at least partially cover the source / drain pattern SD. The formation of the interlayer insulating layer 400 may include forming an initial interlayer insulating layer on the source / drain pattern SD, the gate spacer 350, and the mask pattern 330 on the substrate 100, and planarizing the initial interlayer insulating layer until the sacrificial gate pattern 320 is exposed. The mask pattern 330 may be removed in the planarization process. For example, the interlayer insulating layer 400 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and / or a low-k dielectric layer.

[0041] Reference Figure 1 and Fig.2I , the sacrificial gate pattern 320 and the insulating pattern 310 may be removed to form an opening 500 between the gate spacers 350. The opening 500 may expose the cap pattern 300 between the gate spacers 350. When viewed in a top view, the opening 500 may have a linear shape extending in the second direction D2. The formation of the opening 500 may include etching the sacrificial gate pattern 320 by performing an etching process having an etching selectivity relative to the gate spacer 350, the interlayer insulating layer 400, and the cap pattern 300. The insulating pattern 310 may also be removed in the etching process. In other embodiments, the removal of the insulating pattern 310 may be performed by an etching process different from the etching process of the sacrificial gate pattern 320.

[0042] Reference Figure 1 and Figure 2J , the portion of the cap pattern 300 exposed by the opening 500 may be removed by an etching process. Thus, the opening 500 may expose the active pattern 200 and the device isolation pattern 130 between the gate spacers 350. For example, Figure 2J As shown, the opening 500 may expose a top surface of an uppermost one of the second semiconductor patterns 220 , sidewalls of the second semiconductor patterns 220 , and sidewalls of the first semiconductor patterns 210 .

[0043] According to some embodiments of the present inventive concept, the etching process of the capping pattern 300 may be different from Fig.2I The etching process of the insulating pattern 310 is performed by an anisotropic etching process. In the etching process of the cap pattern 300, the gate spacer 350 may have an etching selectivity with respect to the cap pattern 300. If the cap pattern 300 includes nitrogen, it may be difficult to selectively remove the cap pattern 300. However, according to some embodiments, the cap pattern 300 may not include nitrogen, and thus, the etching process of the cap pattern 300 may be more easily performed.

[0044] The other portion of the capping pattern 300 may not be exposed during the etching process. The other portion of the capping pattern 300 may be disposed under the gate spacer 350. Therefore, after the etching process, the capping pattern 300 may remain between the active pattern 200 and the gate spacer 350. The opening 500 may expose the sidewall 300c of the capping pattern 300.

[0045] Reference Figure 1 and Figure 2K , the first semiconductor pattern 210 exposed by the opening 500 may be removed by an etching process to form an opening region 520. In the etching process, the first semiconductor pattern 210 may have an etching selectivity with respect to the second semiconductor pattern 220. For example, in the etching process, an etching rate of the first semiconductor pattern 210 may be greater than an etching rate of the second semiconductor pattern 220. When the first semiconductor pattern 210 includes silicon germanium (SiGe) and the second semiconductor pattern 220 includes silicon (Si), the etching process of the first semiconductor pattern 210 may be performed by a wet etching process using an etching solution including peracetic acid.

[0046] As mentioned above Figure 2D and Figure 2E As described above, if the first semiconductor pattern 210 is exposed in the process of forming the insulating layer 311, the first portion 211 of the first semiconductor pattern 210 may be oxidized. It may be difficult to etch the oxidized first portion 211 of the first semiconductor pattern 210 in the etching process of the first semiconductor pattern 210. In other words, the difference between the etching rate of the first portion 211 of the first semiconductor pattern 210 and the etching rate of the second semiconductor pattern 220 may be reduced. However, according to some embodiments, the cap pattern 300 may be formed, and therefore, the first semiconductor pattern 210 may not be exposed in the process of forming the insulating layer 311. As a result, in some embodiments, the first portion 211 of the first semiconductor pattern 210 may not be oxidized. The etching rate of the first portion 211 of the first semiconductor pattern 210 may be much higher than the etching rate of the second semiconductor pattern 220. Therefore, the opening region 520 may be more easily formed in the etching process. Here, the opening region 520 may be an empty region.

[0047] The opening region 520 may be formed between the second semiconductor patterns 220 and between the lowermost one of the base active pattern 110 and the second semiconductor pattern 220, as shown in FIG. Figure 2K As described above, the opening region 520 may be an empty region. The opening region 520 may be connected to the opening 500. During the etching process, the source / drain pattern SD may be protected by the interlayer insulating layer 400 and the gate spacer 350.

[0048] After the formation of the open region 520, the active pattern 201 may include second semiconductor patterns 220 spaced apart from each other. The second semiconductor patterns 220 may be spaced apart from each other in a direction perpendicular to the bottom surface of the substrate 100.

[0049] Reference Figure 1 and Figure 2L , a gate insulating pattern 610 and a gate pattern 600 may be formed in the opening 500 and the opening region 520. The formation of the gate insulating pattern 610 and the gate pattern 600 may include forming a gate insulating layer conformally covering the inner surface of the opening 500 and the opening region 520, forming a gate conductive layer at least partially filling the remaining area of ​​the opening 500 and the opening region 520, and performing a planarization process on the gate insulating layer and the gate conductive layer until the interlayer insulating layer 400 is exposed to thereby locally form the gate insulating pattern 610 and the gate pattern 600 in the opening 500 and the opening region 520.

[0050] The gate insulating pattern 610 may at least partially cover the base active pattern 110, the device isolation pattern 130, and the second semiconductor pattern 220. The gate insulating pattern 610 may be provided on the sidewall 300c of the cap pattern 300 and the top surface of the active pattern 201. The gate insulating pattern 610 may contact the sidewall 300c of the cap pattern 300 and the top surface of the active pattern 201. For example, the gate insulating pattern 610 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and / or a high-k dielectric layer. The high-k dielectric layer may include a material having a dielectric constant greater than that of the silicon oxide layer. For example, the high-k dielectric layer may include a hafnium oxide (HfO) layer, an aluminum oxide (AlO) layer, and / or a tantalum oxide (TaO) layer. For example, the gate pattern 600 may include a doped semiconductor material, a conductive metal nitride, and / or a metal. The gate pattern 600 may at least partially fill the opening 500 and the opening region 520. The gate pattern 600 may at least partially cover the gate insulating pattern 610, and may be spaced apart from the second semiconductor pattern 220 and the base active pattern 110. The gate pattern 600 may be spaced apart from the source / drain pattern SD with the gate spacer 350 interposed therebetween.

[0051] The second semiconductor pattern 220 may be used as a channel of a transistor. The second semiconductor pattern 220 may be used as a bridge channel or a nanowire channel connecting the source / drain pattern SD. Each of the source / drain patterns SD may be in physical contact with the second semiconductor pattern 220. The source / drain patterns SD may be spaced apart from each other in the first direction D1 and the second semiconductor pattern 220 may be interposed therebetween. The second semiconductor pattern 220 and the source / drain pattern SD may constitute an active structure AS provided on the base active pattern 110. The active structure AS and the gate pattern 600 may constitute a gate-all-around type field effect transistor.

[0052] The gate capping pattern 630 may be formed on the gate pattern 600. In some embodiments, an upper portion of the gate insulating pattern 610 and an upper portion of the gate pattern 600 may be recessed to form a groove between the gate spacers 350. The gate capping pattern 630 may be formed in the groove. For example, the gate capping pattern 630 may include a silicon oxide layer, a silicon nitride layer, and / or a silicon oxynitride layer.

[0053] An upper insulating layer (not shown) may be formed on the interlayer insulating layer 400. A first contact plug (not shown) may be formed to penetrate the upper insulating layer and the interlayer insulating layer 400, and may be electrically connected to the source / drain pattern SD. A second contact plug (not shown) may be formed to penetrate the upper insulating layer and the gate cap pattern 630, and may be electrically connected to the gate pattern 600. An interconnection line (not shown) may be formed on the upper insulating layer to be connected to the first contact plug and the second contact plug. The first contact plug, the second contact plug and the interconnection line may be formed of a conductive material. The manufacture of the semiconductor device 1 may be completed by the aforementioned embodiments. The semiconductor device 1 may include a transistor.

[0054] Figure 3A and Figure 3B is corresponding to Figure 1 Lines II' and II-II' are cross-sectional views showing methods of manufacturing semiconductor devices according to some embodiments of the present inventive concept. Hereinafter, for ease of explanation, descriptions of the same components and / or features as in the above embodiments will be omitted or briefly mentioned.

[0055] Refer again Figure 1 and Figure 2H , a base active pattern 110, a device isolation pattern 130, an active pattern 200, a capping pattern 300, an insulating pattern 310, a sacrificial gate pattern 320, a gate spacer 350, a source / drain pattern SD, and an interlayer insulating layer 400 may be formed on the substrate 100, as shown in FIG. FIG. 2A to FIG. 2H However, Figure 2G The recessed area 215 and Figure 2HThe insulating spacer 250 described in FIG. 2 may not be formed.

[0056] Reference Figure 1 and Figure 3A , the sacrificial gate pattern 320 may be removed to form an opening 500 between the gate spacers 350. Here, the opening 500 may expose the insulating pattern 310 between the gate spacers 350. The formation of the opening 500 may include etching the sacrificial gate pattern 320 by performing an etching process having an etching selectivity with respect to the gate spacer 350, the interlayer insulating layer 400, and the insulating pattern 310.

[0057] Reference Figure 1 and Figure 3B , a gate pattern 600 may be formed in the opening 500. The formation of the gate pattern 600 may include forming a gate conductive layer filling the opening 500, and performing a planarization process on the gate conductive layer until the interlayer insulating layer 400 is exposed to thereby partially form the gate pattern 600 in the opening 500. The material and plane arrangement of the gate pattern 600 may be the same as those of the reference Figure 2L The gate pattern 600 may be provided on the insulating pattern 310 and may be spaced apart from the first and second semiconductor patterns 210 and 220 and the base active pattern 110. The insulating pattern 310 may be provided under the gate pattern 600 and may serve as a gate insulating layer.

[0058] Each of the source / drain patterns SD may be in physical contact with the first semiconductor pattern 210 and the second semiconductor pattern 220. The source / drain patterns SD may be spaced apart from each other in the first direction D1 with the first semiconductor pattern 210 and the second semiconductor pattern 220 interposed therebetween. The first semiconductor pattern 210 and the second semiconductor pattern 220 may function as channels of transistors.

[0059] If the capping pattern 300 is omitted, the first portion 211 of the first semiconductor pattern 210 may be oxidized, as shown in FIG. Figure 2D and Figure 2EAs described. In this case, the interface characteristics between the insulating pattern 310 and the first portion 211 of the first semiconductor pattern 210 may be degraded. Therefore, the operational reliability of the transistor may be degraded. However, according to some embodiments, the cover pattern 300 may be formed, and therefore, the first portion 211 of the first semiconductor pattern 210 may not include oxygen, but may have a composition ratio substantially the same as the second portion 212, i.e., a composition ratio of elements and / or components. Therefore, the interface characteristics between the cover pattern 300 and the first semiconductor pattern 210 may be improved. For example, no electron trap may be generated between the cover pattern 300 and the first portion 211 of the first semiconductor pattern 210. As a result, the operational reliability of the transistor manufactured according to some embodiments of the present inventive concept may be improved.

[0060] The capping pattern 300 may be disposed between the insulating pattern 310 and the first semiconductor pattern 210 and between the insulating pattern 310 and the second semiconductor pattern 220. The capping pattern 300 may also be disposed between the insulating pattern 310 and the device isolation pattern 130. If the capping pattern 300 includes nitrogen, the operating characteristics of the transistor may be degraded. However, according to some embodiments, the capping pattern 300 may not include nitrogen, and thus, the transistor may have improved operating characteristics.

[0061] The gate capping pattern 630 may be formed on the gate pattern 600. The semiconductor device 2 may be manufactured by the aforementioned embodiments. The semiconductor device 2 may include a transistor.

[0062] FIG. 4A to FIG. 4E is corresponding to Figure 1 Lines II' and II-II' are cross-sectional views showing methods of manufacturing semiconductor devices according to some embodiments of the present inventive concept. Hereinafter, for ease of explanation, descriptions of the same components and / or features as in the above embodiments will be omitted or briefly mentioned. FIG. 4A to FIG. 4E The description of the embodiments will also refer to Figure 1 .

[0063] Reference Figure 4A , the active pattern 200 and the device isolation pattern 130 may be formed on the substrate 100. The active pattern 200 and the device isolation pattern 130 may be formed by referring to Figure 2A and Figure 2B The capping pattern 300 may be formed on the top surface and the sidewalls of the active pattern 200 .

[0064] However, the capping pattern 300 may not be formed on the top surface of the device isolation pattern 130. The formation of the capping pattern 300 may be performed by a selective epitaxial growth (SEG) process. The selective epitaxial growth (SEG) process may be performed at a temperature of about 300 degrees Celsius to about 950 degrees Celsius using a silicon-containing gas as a source gas. The silicon-containing gas may be Figure 2C The cap pattern 300 may have a first thickness T1, and the first thickness T1 may be about 1000 Å. to about within the range.

[0065] Prior to the formation of the capping pattern 300 , a cleaning process may be performed on the active pattern 200 .

[0066] Reference Figure 4B , an insulating layer 311 may be formed on the top surface of the device isolation pattern 130 and the cap pattern 300. The insulating layer 311 may be in physical contact with the top surface of the device isolation pattern 130. During the process of forming the insulating layer 311, at least a portion of the cap pattern 300 may be oxidized. After the process of forming the insulating layer 311, the cap pattern 300 may have a second thickness T2 that is less than the first thickness T1. A sacrificial gate layer 321 and a mask pattern 330 may be formed on the insulating layer 311. The method of forming the insulating layer 311, the sacrificial gate layer 321, and the mask pattern 330 may be the same as described above.

[0067] Reference Figure 4C , the sacrificial gate layer 321 and the insulating layer 311 may be patterned to form a sacrificial gate pattern 320 and an insulating pattern 310. The sacrificial gate pattern 320 and the insulating pattern 310 may be formed by an etching process using the mask pattern 330 as an etching mask. Thereafter, a gate spacer 350 may be formed on the capping pattern 300 at both sides of the sacrificial gate pattern 320.

[0068] Reference Figure 4D , the cap pattern 300 and the active pattern 200 may be etched using the mask pattern 330 and the gate spacer 350 as an etching mask. Thus, a recessed portion 140 may be formed in the active pattern 200. A portion of the first semiconductor pattern 210 may be removed laterally, and thus, a sidewall of the first semiconductor pattern 210 may be laterally recessed. An insulating spacer 250 may be formed on the recessed sidewall of the first semiconductor pattern 210 and under the second semiconductor pattern 220.

[0069] Reference Figure 4E, a source / drain pattern SD may be formed in the recessed portion 140. An interlayer insulating layer 400 may be formed to at least partially cover the source / drain pattern SD. The mask pattern 330 may be removed in the process of forming the interlayer insulating layer 400. An opening 500 exposing the capping pattern 300 may be formed by removing the sacrificial gate pattern 320 and the insulating pattern 310.

[0070] Refer again Figure 2J , the exposed capping pattern 300 may be removed, and thus, the opening 500 may expose the active pattern 200 and the device isolation pattern 130. Thereafter, as shown in FIG. Figure 2K As shown, the first semiconductor pattern 210 exposed by the opening 500 may be removed by an etching process to form an opening region 520. After the formation of the opening region 520, the active pattern 201 may include second semiconductor patterns 220 spaced apart from each other.

[0071] Reference Figure 2L , the gate insulating pattern 610 and the gate pattern 600 may be formed in the opening 500 and the opening region 520. Thus, the manufacturing of the semiconductor device 1 may be completed.

[0072] Figure 4F and Figure 4G is corresponding to Figure 1 Lines II' and II-II' are cross-sectional views showing methods of manufacturing semiconductor devices according to some embodiments of the present inventive concept. Hereinafter, for ease of explanation, descriptions of the same components and / or features as in the above embodiments will be omitted or briefly mentioned.

[0073] Reference Figure 4D and Figure 4F , a base active pattern 110, a device isolation pattern 130, an active pattern 200, a capping pattern 300, an insulating pattern 310, a sacrificial gate pattern 320, a gate spacer 350, a source / drain pattern SD, and an interlayer insulating layer 400 may be formed on the substrate 100, as shown in FIG. 4A to 4D However, in Figure 4D The process of laterally recessing the sidewall of the first semiconductor pattern 210 may not be performed, and Figure 4D The insulating spacer 250 may not be formed.

[0074] The sacrificial gate pattern 320 may be removed to form an opening 500 between the gate spacers 350. The opening 500 may expose the insulating pattern 310. The opening 500 may be formed by referring to Figure 3A The etching process described is formed.

[0075] Reference Figure 4G, the gate pattern 600 may be formed in the opening 500. The gate pattern 600 may be formed by referring to Figure 3B The method described is performed. The gate pattern 600 may be provided on the insulating pattern 310 and may be spaced apart from the first semiconductor pattern 210 and the second semiconductor pattern 220 and the base active pattern 110. The insulating pattern 310 may be used as a gate insulating layer. The gate capping pattern 630 may be formed on the gate pattern 600. The manufacture of the semiconductor device 3 may be completed by the aforementioned embodiment.

[0076] FIG. 5A to FIG. 5H are views illustrating a method of fabricating a semiconductor device according to some embodiments of the inventive concept. Figure 5A , Figure 5B and FIG. 5D to FIG. 5H is corresponding to Figure 1 Cross-sectional view along lines II' and II-II'. Figure 5C yes Figure 5B Hereinafter, for the convenience of explanation, the description of the same components and / or features as those in the above embodiment will be omitted or briefly mentioned. FIG. 5A to FIG. 5H The description of the embodiments will also refer to Figure 1 .

[0077] Reference Figure 5A , the active pattern 200 and the device isolation pattern 130 may be formed on the substrate 100. The capping pattern 300 may be formed on the top surface and sidewalls of the active pattern 200 and the top surface of the device isolation pattern 130. The capping pattern 300 may be formed by referring to Figure 2C The method described is formed.

[0078] and Figure 5A Differently, the capping pattern 300 may at least partially cover the top surface and the sidewall of the active pattern 200, but may expose the top surface of the device isolation pattern 130. In this case, the capping pattern 300 may be formed by referring to Figure 4A The selective epitaxial growth (SEG) process described is formed.

[0079] Reference Figure 5B and Figure 5C , an insulating layer 311 may be formed on the capping pattern 300. The capping pattern 300 may be oxidized during the process of forming the insulating layer 311. When the formation of the insulating layer 311 is completed, the capping pattern 300 may not remain between the active pattern 200 and the insulating layer 311. Therefore, the first portion 211 of the first semiconductor pattern 210 may be in physical contact with the insulating layer 311.

[0080] The capping pattern 300 may suppress or prevent oxidation of the first semiconductor pattern 210 during a process of forming the insulating layer 311. The composition ratio of the first portion 211 of the first semiconductor pattern 210, ie, the ratio of elements or components, may be substantially equal to that of the second portion 212 of the first semiconductor pattern 210.

[0081] A sacrificial gate layer 321 and a mask pattern 330 may be sequentially formed on the insulating layer 311 .

[0082] Reference Figure 5D , the sacrificial gate layer 321 and the insulating layer 311 may be patterned to form a sacrificial gate pattern 320 and an insulating pattern 310. The formation of the sacrificial gate pattern 320 may include etching the sacrificial gate layer 321 exposed by the mask pattern 330. The formation of the insulating pattern 310 may include etching the insulating layer 311 exposed by the mask pattern 330. The gate spacer 350 may be formed on both sidewalls of the sacrificial gate pattern 320 on the active pattern 200. Since the cap pattern 300 is as shown in FIG. Figure 5B The is removed, so the insulating pattern 310 may be in direct physical contact with the active pattern 200 and the device isolation pattern 130 .

[0083] Reference Figure 5E , an etching process may be performed on the active pattern 200 to form a recessed portion 140 in the active pattern 200. The etching process may include removing portions of the active pattern 200 exposed by the mask pattern 330 and the gate spacer 350. Portions of the first semiconductor pattern 210 may be removed laterally, and thus, sidewalls of the first semiconductor pattern 210 may be laterally recessed. Insulating spacers 250 may be formed on the recessed sidewalls of the first semiconductor pattern 210 and under the second semiconductor pattern 220.

[0084] Reference Fig. 5F , a source / drain pattern SD may be formed in the recessed portion 140. An interlayer insulating layer 400 may be formed to at least partially cover the source / drain pattern SD. The mask pattern 330 may be removed in the process of forming the interlayer insulating layer 400.

[0085] Reference Figure 5G , the sacrificial gate pattern 320 and the insulating pattern 310 may be removed to form an opening 500 between the gate spacers 350. The opening 500 may expose the active pattern 200 and the device isolation pattern 130. The removal of the insulating pattern 310 and the removal of the sacrificial gate pattern 320 may be performed by a single process or different processes. The first semiconductor pattern 210 may be removed by an etching process to form an opening region 520. After the formation of the opening region 520, the active pattern 201 may include second semiconductor patterns 220 spaced apart from each other.

[0086] Reference Figure 5H , a gate insulating pattern 610 and a gate pattern 600 may be formed in the opening 500 and the opening region 520. A gate capping pattern 630 may be formed on the gate pattern 600. Thus, the manufacturing of the semiconductor device 4 may be completed. According to some embodiments, the semiconductor device 4 may not include a capping pattern.

[0087] Fig.5I and Figure 5J are views illustrating a method of fabricating a semiconductor device according to some embodiments of the inventive concept. Fig.5I and Figure 5J is corresponding to Figure 1 Hereinafter, for the convenience of explanation, the description of the same components and / or features as those in the above embodiment will be omitted or briefly mentioned.

[0088] Reference Fig. 5F and Fig.5I , a base active pattern 110, a device isolation pattern 130, an active pattern 200, an insulating pattern 310, a sacrificial gate pattern 320, a gate spacer 350, a source / drain pattern SD, and an interlayer insulating layer 400 may be formed on the substrate 100, as shown in FIG. FIG. 5A to FIG. 5F As described. Figure 5B As described above, the capping pattern 300 may be oxidized during the process of forming the insulating layer 311, and thus, may not remain after the process of forming the insulating layer 311. Figure 5E The process of laterally recessing the sidewall of the first semiconductor pattern 210 may be omitted, and Figure 5E The insulating spacer 250 may not be formed.

[0089] The sacrificial gate pattern 320 may be Fig.5I As shown, the gate spacers 350 are removed, and thus, an opening 500 may be formed between the gate spacers 350. The opening 500 may expose the insulating pattern 310.

[0090] Reference Figure 1 and Figure 5J , the gate pattern 600 may be formed in the opening 500. The gate pattern 600 may be formed by referring to Figure 3B The gate pattern 600 may be provided on the insulating pattern 310 and may be spaced apart from the first semiconductor pattern 210 and the second semiconductor pattern 220 and the base active pattern 110. The insulating pattern 310 may serve as a gate insulating layer. A gate capping pattern 630 may be formed on the gate pattern 600. The manufacture of the semiconductor device 5 may be completed by the aforementioned embodiments.

[0091] According to an embodiment of the present invention, the cap pattern can prevent the semiconductor pattern from being exposed during the process of forming the insulating layer. Therefore, oxidation of the semiconductor pattern can be suppressed or prevented. According to an embodiment of the present invention, the semiconductor device can be manufactured more easily. As a result, the reliability of the semiconductor device can be improved.

[0092] Although the inventive concept has been described with reference to example embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the inventive concept. Therefore, it should be understood that the above embodiments are not restrictive, but illustrative. Therefore, the scope of the inventive concept will be determined by the broadest permissible interpretation of the appended claims and their equivalents, and should not be restricted or limited by the foregoing description.

[0093] This application claims the benefit of Korean Patent Application No. 10-2019-0064219 filed on May 31, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: an active pattern protruding from the substrate and including a plurality of stacked semiconductor patterns; a gate pattern, disposed on the active pattern and intersecting the active pattern; a gate insulating pattern between the active pattern and the gate pattern; a gate spacer at a side of the gate pattern and on the active pattern; as well as a capping pattern disposed between the active pattern and the gate spacer and in physical contact with the active pattern, The cap pattern has a crystalline structure. 2 . The semiconductor device of claim 1 , wherein the capping pattern is in physical contact with a sidewall of the semiconductor pattern. 3 . The semiconductor device of claim 1 , wherein the capping pattern extends between the active pattern and the gate pattern. 4 . The semiconductor device of claim 3 , wherein the gate insulating pattern is disposed between the capping pattern and the gate pattern.

5. The semiconductor device according to claim 1 , wherein the cap pattern does not extend between the active pattern and the gate pattern, and The gate insulating pattern is in physical contact with a sidewall of the capping pattern.

6. The semiconductor device according to claim 1, wherein the semiconductor patterns are spaced apart from each other in a direction perpendicular to a bottom surface of the substrate, and wherein the gate pattern is provided on a top surface of the active pattern and between the semiconductor patterns. 7 . The semiconductor device according to claim 6 , wherein the gate insulating pattern is between the gate pattern and each of the semiconductor patterns.

8. The semiconductor device according to claim 1, further comprising: a source / drain pattern at the side of the gate pattern and on the sidewall of the semiconductor pattern, The source / drain pattern is in physical contact with a sidewall of the capping pattern.

9. The semiconductor device according to claim 1, further comprising: a device isolation pattern on the substrate on a lower portion of the active pattern, wherein the capping pattern does not extend onto a top surface of the device isolation pattern.

10. The semiconductor device according to claim 1, wherein the cap pattern comprises a semiconductor material, and The capping pattern does not include oxygen, germanium, and nitrogen.

11. A semiconductor device comprising: an active pattern protruding from the substrate and including a plurality of stacked semiconductor patterns; a gate pattern, disposed on the active pattern and intersecting the active pattern; a gate spacer at a side of the gate pattern and on the active pattern; as well as a capping pattern between the active pattern and the gate spacer, wherein the cap pattern has a crystalline structure, and The capping pattern is in physical contact with sidewalls of the plurality of stacked semiconductor patterns.

12. The semiconductor device according to claim 11, further comprising: A gate insulating pattern is disposed between the active pattern and the gate pattern. 13 . The semiconductor device of claim 12 , wherein the capping pattern further extends between the active pattern and the gate insulating pattern.

14. The semiconductor device according to claim 11, further comprising: a device isolation pattern on the substrate on a lower portion of the active pattern, wherein the capping pattern does not extend between the lower portion of the active pattern and the device isolation pattern.

15. The semiconductor device according to claim 11, wherein the semiconductor pattern comprises first semiconductor patterns and second semiconductor patterns alternately stacked with each other, and The second semiconductor pattern includes a material different from that of the first semiconductor pattern. 16 . The semiconductor device of claim 15 , wherein the capping pattern is in physical contact with a first sidewall of the first semiconductor pattern and a second sidewall of the second semiconductor pattern.

17. A semiconductor device comprising: an active pattern protruding from the substrate and including a plurality of stacked semiconductor patterns; a device isolation pattern provided on a lower portion of the active pattern and exposing an upper portion of the active pattern; a gate pattern, disposed on the active pattern and intersecting the active pattern; a gate insulating pattern between the gate pattern and the upper portion of the active pattern; a gate spacer at a side of the gate pattern and on the active pattern; a cap pattern between the active pattern and the gate spacer; a source / drain pattern, at the side of the gate pattern, the gate spacer being disposed between the source / drain pattern and the gate pattern; as well as an interlayer insulating layer on the upper surface of the source / drain pattern and on the outer sidewalls of the gate spacer, wherein the cover pattern is in physical contact with the active pattern, The cap pattern has a crystalline structure. 18 . The semiconductor device of claim 17 , wherein the capping pattern covers a sidewall of the semiconductor pattern.

19. The semiconductor device according to claim 17, wherein the cap pattern has: a first sidewall physically contacting the gate insulating pattern; and A second sidewall is in physical contact with the source / drain pattern and is opposite to the first sidewall. 20 . The semiconductor device of claim 17 , wherein the capping pattern further extends between the active pattern and the gate insulating pattern.

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