Semiconductor device manufacturing method and semiconductor device

Abstract

The present application discloses a method for manufacturing a semiconductor device and a semiconductor device, belonging to the field of semiconductor technology. The method for manufacturing the semiconductor device comprises: providing a substrate, the substrate comprising a transistor, the transistor comprising a gate oxide layer and a gate located on the gate oxide layer; forming an interconnection layer on the substrate, the interconnection layer comprising a connection structure connected to the gate, to obtain an intermediate structure; performing alloying annealing treatment on the intermediate structure; forming a barrier layer containing hydrogen ions on the interconnection layer, and the barrier layer covers the connection structure. The present application can improve the TDDB performance, thereby improving the reliability and stability of semiconductor devices.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a method for manufacturing a semiconductor device and a semiconductor device. Background Art

[0002] In semiconductor devices, a barrier layer is usually deposited on the connection structure of the gate in the transistor, and the barrier layer contains hydrogen ions. Under the high temperature during the process of semiconductor devices, the hydrogen ions in the barrier layer diffuse to the gate through the connection structure and accumulate in the gate oxide layer, which can easily cause the gate oxide layer to be broken down, reduce the TDDB (Time Dependent Dielectric Breakdown, a time-dependent gate dielectric breakdown phenomenon of transistors) performance, and affect the reliability and stability of semiconductor devices. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a method for manufacturing a semiconductor device and a semiconductor device, which can improve the TDDB performance, thereby improving the reliability and stability of the semiconductor device.

[0004] In a first aspect, the present application provides a method for manufacturing a semiconductor device, comprising:

[0005] Providing a substrate, the substrate comprising a transistor, the transistor comprising a gate oxide layer and a gate located on the gate oxide layer;

[0006] forming an interconnection layer on the substrate, the interconnection layer including a connection structure connected to the gate to obtain an intermediate structure;

[0007] performing alloying annealing treatment on the intermediate structure;

[0008] A barrier layer containing hydrogen ions is formed on the interconnect layer, and the barrier layer covers the connection structure.

[0009] According to one embodiment of the present application, the barrier layer includes a silicon nitride layer having a hydrogen ion content less than a target value.

[0010] According to one embodiment of the present application, forming a barrier layer containing hydrogen ions on the interconnect layer includes: forming a silicon nitride layer having a hydrogen ion content less than the target value on the interconnect layer by a reaction gas, wherein the reaction gas includes silane and nitrogen.

[0011] According to an embodiment of the present application, the reaction gas further includes ammonia gas, and the flow rate of the ammonia gas is less than or equal to 3000 sccm.

[0012] According to one embodiment of the present application, the barrier layer includes a nitrogen-doped silicon carbide layer having a hydrogen ion content less than a target value.

[0013] According to an embodiment of the present application, before performing alloying annealing on the intermediate structure, the method further includes: performing chemical mechanical polishing on a side of the interconnect layer facing away from the substrate.

[0014] According to an embodiment of the present application, the annealing temperature of the alloying annealing is 350° C.-500° C., and the protective gas includes nitrogen and hydrogen. The proportion of the hydrogen is 0%-15%, and the proportion of the nitrogen is 85%-100%.

[0015] According to an embodiment of the present application, the method further includes: forming a passivation layer on the barrier layer; forming a pad penetrating the passivation layer and the barrier layer, and the pad is connected to the connection structure.

[0016] In a second aspect, the present application provides a semiconductor device, comprising:

[0017] A substrate, comprising a transistor, wherein the transistor comprises a gate oxide layer and a gate located on the gate oxide layer;

[0018] An interconnection layer, located on the substrate, and comprising a connection structure connected to the gate;

[0019] A barrier layer containing hydrogen ions is located on the interconnect layer.

[0020] According to one embodiment of the present application, the barrier layer includes a silicon nitride layer or a nitrogen-doped silicon carbide layer having a hydrogen ion content less than a target value.

[0021] The above one or more technical solutions in the embodiments of the present application have at least one of the following technical effects:

[0022] After forming the connection structure of the gate and before forming the barrier layer containing hydrogen ions, an alloying annealing treatment is performed to reduce the content of hydrogen ions in the barrier layer diffusing into the gate oxide layer through the connection structure of the gate, reduce the risk of the gate oxide layer being broken down, improve the TDDB performance, and thus improve the reliability and stability of the semiconductor device;

[0023] Furthermore, by forming a barrier layer with a hydrogen ion content less than a target value on the interconnect layer, the hydrogen ion content diffused from the barrier layer to the gate oxide layer is further reduced, the risk of the gate oxide layer being broken down is further reduced, and the TDDB performance is further improved, thereby improving the reliability and stability of the semiconductor device.

[0024] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0026] Figure 1 It is a schematic flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0027] Figure 2 It is one of the structural schematic diagrams in the method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0028] Figure 3 This is the second structural schematic diagram of the method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0029] Figure 4 This is the third structural schematic diagram of the method for manufacturing a semiconductor device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0031] The following describes a method for manufacturing a semiconductor device and a semiconductor device provided in an embodiment of the present application with reference to the accompanying drawings.

[0032] Figure 1 A schematic flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application.

[0033] like Figure 1 As shown, the method for manufacturing a semiconductor device provided in an embodiment of the present application includes steps 110 to 140.

[0034] Step 110: Provide a substrate, wherein the substrate includes a transistor, and the transistor includes a gate oxide layer and a gate located on the gate oxide layer.

[0035] like Figure 2As shown, the gate oxide layer 12 and the gate 11 can be arranged near the surface of one side of the substrate 1 (such as the upper surface of the substrate 1). In some embodiments, the substrate 1 may also include a substrate 18, a buried oxide layer 17 and an SOI (Silicon-On-Insulator) layer 15. The buried oxide layer 17 is located on the substrate 18, and the SOI layer 15 is located on the buried oxide layer 17. The gate oxide layer 12 can be located on the SOI layer 15, and the gate 11 is located on the gate oxide layer 12. The transistor also includes an active region, which is located in the SOI layer 15 and is arranged near the upper surface of the SOI layer 15. The active region includes a source region 13 and a drain region 14 that are arranged at intervals, and the gate oxide layer 12 is located on the active region between the source region 13 and the drain region 14.

[0036] Step 120: forming an interconnection layer on the substrate, wherein the interconnection layer includes a connection structure connected to the gate to obtain an intermediate structure.

[0037] like Figure 2 As shown, the interconnection layer 2 is located on the substrate 1 and covers the substrate 1, that is, the interconnection layer 2 covers the gate 11, the source region 13 and the drain region 14. The interconnection layer 2 may include a plurality of interconnection sublayers stacked in sequence. Each interconnection sublayer may include a dielectric layer and a routing layer, and the routing layer in each interconnection sublayer is located on the dielectric layer and penetrates the dielectric layer. The routing layers in adjacent interconnection sublayers are connected. Among them, the material of the dielectric layer may include silicon dioxide, etc., and the material of the routing layer may include copper, etc.

[0038] Each routing layer includes a gate routing, and the gate routings of multiple routing layers in the interconnect layer 2 are connected in sequence to form a connection structure connected to the gate 11. Each routing layer may also include a source routing, and the source routings of multiple routing layers in the interconnect layer 2 are connected in sequence to form a connection structure connected to the source region 13. Each routing layer may also include a drain routing, and the drain routings of multiple routing layers in the interconnect layer 2 are connected in sequence to form a connection structure connected to the drain region 14. Each routing layer may also include an electrode routing, and the electrode routings of multiple routing layers in the interconnect layer 2 are connected in sequence to form a connection structure connected to the substrate 18.

[0039] It should be noted that the gate wiring, source wiring, drain wiring and electrode wiring in each wiring layer are arranged at intervals. When the potential of the gate 11 is equal to the potential of the substrate 18, the gate wiring in each wiring layer is connected to the electrode wiring.

[0040] For example, the interconnection layer 2 may include a first interconnection sublayer 21, a second interconnection sublayer 22, and a third interconnection sublayer 23, which are stacked in sequence. The first interconnection sublayer 21 includes a first dielectric layer 31 and a first routing layer 41, the second interconnection sublayer 22 includes a second dielectric layer 32 and a second routing layer 42, and the third interconnection sublayer 23 includes a third dielectric layer 33 and a third routing layer 43.

[0041] First, a first dielectric layer 31 is formed on the substrate 1, and the first dielectric layer 31 covers the gate 11, the source region 13, and the drain region 14. Then, a first wiring layer 41 is formed on the first dielectric layer 31. The first wiring layer 41 may include gate wiring, source wiring, drain wiring, and electrode wiring. The gate wiring, source wiring, drain wiring, and electrode wiring in the first wiring layer 41 respectively penetrate the first dielectric layer 31, and respectively connect the gate 11, the source region 13, the drain region 14, and the substrate 18.

[0042] Then, a second dielectric layer 32 is formed on the first interconnection sublayer 21, and the second dielectric layer 32 covers the first wiring layer 41. Then, a second wiring layer 42 is formed on the second dielectric layer 32. The second wiring layer 42 may include gate wiring, source wiring, drain wiring, and electrode wiring, and the gate wiring, source wiring, drain wiring, and electrode wiring in the second wiring layer 42 respectively penetrate the second dielectric layer 32, and are respectively connected to the gate wiring, source wiring, drain wiring, and electrode wiring in the first wiring layer 41.

[0043] Then, a third dielectric layer 33 is formed on the second interconnection sublayer 22, and the third dielectric layer 33 covers the second wiring layer 42. Then, a third wiring layer 43 is formed on the third dielectric layer 33. The third wiring layer 43 may include gate wiring, source wiring, drain wiring, and electrode wiring, and the gate wiring, source wiring, drain wiring, and electrode wiring in the third wiring layer 43 respectively penetrate the third dielectric layer 33, and are respectively connected to the gate wiring, source wiring, drain wiring, and electrode wiring in the second wiring layer 42.

[0044] Among them, the gate wiring in the first wiring layer 41, the gate wiring in the second wiring layer 42, and the gate wiring in the third wiring layer 43 are connected in sequence to form a connection structure connected to the gate 11. The source wiring in the first wiring layer 41, the source wiring in the second wiring layer 42, and the source wiring in the third wiring layer 43 are connected in sequence to form a connection structure connected to the source region 13. The drain wiring in the first wiring layer 41, the drain wiring in the second wiring layer 42, and the drain wiring in the third wiring layer 43 are connected in sequence to form a connection structure connected to the drain region 14. The electrode wiring in the first wiring layer 41, the electrode wiring in the second wiring layer 42, and the electrode wiring in the third wiring layer 43 are connected in sequence to form a connection structure connected to the substrate 18.

[0045] In some embodiments, before forming an interconnection layer on the substrate in step 120 and before performing alloying annealing on the intermediate structure in step 130, the method for manufacturing a semiconductor device further includes: performing chemical mechanical polishing on a side of the interconnection layer facing away from the substrate.

[0046] The interconnection layer 2 may further include a fourth dielectric layer 34. Figure 2 After the third interconnect sublayer 23 in the top interconnect sublayer is formed, a fourth dielectric layer 34 is formed on the top interconnect sublayer, and the fourth dielectric layer 34 covers the top wiring layer (such as Figure 2 The third wiring layer 43 in the substrate 1 is subjected to chemical mechanical polishing on the side of the fourth dielectric layer 34 facing away from the substrate 1 (ie, the upper surface of the fourth dielectric layer 34) to expose the top wiring layer.

[0047] After the interconnection layer 2 is formed on the substrate 1 , an intermediate structure of the semiconductor device is obtained, that is, the intermediate structure includes the substrate 1 and the interconnection layer 2 .

[0048] Step 130: performing alloying annealing treatment on the intermediate structure.

[0049] After the intermediate structure is obtained, an alloying annealing process is used under certain temperature conditions to treat the intermediate structure to improve the composition uniformity and shape stability of the intermediate structure and provide a good processing basis for the subsequent production of semiconductor devices.

[0050] In some embodiments, the annealing temperature of the alloying annealing is 350° C.-500° C., and the protective gas includes nitrogen and hydrogen, with the proportion of hydrogen being 0%-15% and the proportion of nitrogen being 85%-100%. When the proportion of hydrogen is 0%, the protective gas introduced in the alloying annealing process may not include hydrogen, but only include nitrogen.

[0051] Step 140: forming a barrier layer containing hydrogen ions on the interconnect layer, wherein the barrier layer covers the connection structure.

[0052] like Figure 3 As shown, after the intermediate structure is subjected to alloying annealing, a barrier layer 5 is formed on the side of the interconnect layer 2 facing away from the substrate 1 by using a thin film deposition process.

[0053] The barrier layer 5 covers the top wiring layer (such as Figure 2 The barrier layer 5 can be used as a barrier layer for the gate wiring, source wiring, drain wiring and electrode wiring in the interconnect layer 2 to prevent the diffusion of metal ions (such as copper ions) in the gate wiring, source wiring, drain wiring and electrode wiring. The thin film deposition process may include physical vapor deposition, chemical vapor deposition, atomic layer deposition, laser assisted deposition, etc.

[0054] It should be noted that ammonia gas needs to be introduced during the process of forming the barrier layer 5 (for example, the barrier layer 5 generally includes silicon nitride), and hydrogen gas is also generated while the barrier layer 5 is generated, resulting in the barrier layer 5 containing hydrogen ions.

[0055] The related art performs an alloying annealing process when the semiconductor device is manufactured (i.e. after the barrier layer is formed), which easily causes the hydrogen ions in the barrier layer to drift under the action of an external electric field and diffuse to the gate oxide layer, so that a large number of silicon-hydrogen bonds are formed between the gate oxide layer and the active area. The silicon-hydrogen bonds break under the action of the external electric field and release a large amount of energy. At the same time, a large number of electron traps and interface states accumulate in the gate oxide layer. The electron traps and interface states capture electrons and holes, which enhances the local electric field and increases the leakage current, thereby causing the gate oxide layer to be broken down in advance. As a result, the TDDB life of the semiconductor device is short, the TDDB performance is poor, and the reliability and stability of the semiconductor device are low.

[0056] In the present embodiment, the alloying annealing process is advanced to after the connection structure of the gate 11 is formed, and before the barrier layer 5 containing hydrogen ions is formed. After the barrier layer 5 is formed, the alloying annealing process is no longer performed, so as to reduce the content of hydrogen ions in the barrier layer 5 diffusing into the gate oxide layer 12 through the connection structure of the gate 11, reduce the content of silicon-hydrogen bonds between the gate oxide layer 12 and the active area, reduce the energy generated by the breaking of silicon-hydrogen bonds under the action of an external electric field, reduce the number of electron traps and interface states in the gate oxide layer 12, reduce the local electric field and leakage current, thereby reducing the risk of breakdown of the gate oxide layer 12, and improve the TDDB performance of the semiconductor device, thereby improving the reliability and stability of the semiconductor device.

[0057] In some embodiments, the barrier layer 5 includes a silicon nitride layer having a hydrogen ion content greater than or equal to a target value.

[0058] By using silane, nitrogen and ammonia as reaction gases, a chemical reaction occurs (the reaction formula of the chemical reaction can be 3SiH4+2NH3+N2=Si3N4+9H2) to form a silicon nitride layer containing hydrogen ions. In order to increase the film formation rate of the silicon nitride layer, the flow rate of ammonia in this embodiment can be set higher so that the hydrogen ion content in the silicon nitride layer is higher, that is, the hydrogen ion content in the silicon nitride layer is greater than or equal to the target value. For example, the flow rate of ammonia can be 4000sccm, and the target value can be the hydrogen ion content of the silicon nitride layer formed when the flow rate of ammonia is 4000sccm.

[0059] In this embodiment, the alloying annealing process is advanced to after the connection structure of the gate 11 is formed, and before the barrier layer 5 containing hydrogen ions is formed, and after the barrier layer 5 is formed, the alloying annealing process is no longer performed. Even if the hydrogen ion content of the barrier layer 5 is high, the content of hydrogen ions in the barrier layer 5 diffusing to the gate oxide layer 12 through the connection structure of the gate 11 can be reduced, the risk of the gate oxide layer 12 being broken down can be reduced, and the TDDB performance can be improved, such as the TDDB life is increased by 60%. Moreover, in this embodiment, the flow rate of ammonia gas introduced when forming the barrier layer 5 is high, which increases the film formation rate of the barrier layer 5, thereby increasing the process speed of semiconductor device manufacturing and shortening the process time.

[0060] In some embodiments, the barrier layer 5 includes a silicon nitride layer having a hydrogen ion content less than a target value.

[0061] In the process of forming the silicon nitride layer in this embodiment, the hydrogen ion content in the formed silicon nitride layer can be reduced by adjusting the flow rate of ammonia gas, so that the hydrogen ion content in the silicon nitride layer is less than the target value. For example, the target value can be the hydrogen ion content of the silicon nitride layer formed when the flow rate of ammonia gas is 4000 sccm.

[0062] This embodiment reduces the hydrogen ion content in the barrier layer 5, further reduces the content of hydrogen ions in the barrier layer 5 that diffuse into the gate oxide layer 12 through the connection structure of the gate 11, and further reduces the content of silicon-hydrogen bonds between the gate oxide layer 12 and the active area, so as to further reduce the local electric field and leakage current, reduce the risk of breakdown of the gate oxide layer 12, and thus further improve the TDDB performance of the semiconductor device.

[0063] In some embodiments, forming a barrier layer containing hydrogen ions on the interconnect layer in step 140 includes: forming a silicon nitride layer having a hydrogen ion content less than a target value on the interconnect layer by a reaction gas, the reaction gas including silane, nitrogen and ammonia, and the flow rate of ammonia is less than or equal to 3000sccm.

[0064] In the process of forming the barrier layer 5, by reducing the flow rate of the introduced ammonia gas, such as the flow rate of the introduced ammonia gas does not exceed 3000 sccm, that is, in the present embodiment, the use of ammonia gas is reduced when forming the silicon nitride layer, so as to reduce the generation of hydrogen gas while generating the silicon nitride layer, reduce the content of hydrogen ions in the silicon nitride layer, make the hydrogen ion content of the silicon nitride layer less than the target value, further reduce the content of hydrogen ions in the barrier layer 5 diffused to the gate oxide layer 12 through the connection structure of the gate 11, thereby further reducing the risk of the gate oxide layer 12 being broken down. For example, the target value may be the hydrogen ion content of the silicon nitride layer formed when the flow rate of the introduced ammonia gas is greater than 3000 sccm.

[0065] In some embodiments, forming a barrier layer containing hydrogen ions on the interconnect layer in step 140 includes: forming a silicon nitride layer having a hydrogen ion content less than a target value on the interconnect layer by a reaction gas, wherein the reaction gas includes silane and nitrogen.

[0066] In this embodiment, silane and nitrogen are used as reaction gases, that is, the reaction gas does not include ammonia. While forming a silicon nitride layer on the side of the interconnect layer 2 facing away from the substrate 1, the generation of hydrogen is further reduced, the content of hydrogen ions in the silicon nitride layer is further reduced, and the content of hydrogen ions in the barrier layer 5 that diffuses to the gate oxide layer 12 through the connection structure of the gate 11 is further reduced, thereby further reducing the risk of the gate oxide layer 12 being broken down.

[0067] It should be noted that reducing the flow rate of ammonia or not using ammonia to reduce the hydrogen ion content of the barrier layer 5 may affect the film formation rate of the silicon nitride layer, but will not affect the barrier performance of the silicon nitride layer, that is, the barrier layer 5 with a hydrogen ion content less than the target value can still effectively block the diffusion of metal ions (such as copper ions) in the gate wiring, source wiring, drain wiring and electrode wiring in the interconnect layer 2.

[0068] In some embodiments, the barrier layer 5 includes a nitrogen-doped silicon carbide layer having a hydrogen ion content less than a target value.

[0069] In this embodiment, the hydrogen ion content in the barrier layer 5 can be reduced by changing the material composition of the barrier layer 5. Tetramethylsiloxane and ammonia are used as reactants to undergo a chemical reaction to form a nitrogen-doped silicon carbide layer on the side of the interconnect layer 2 facing away from the substrate 1. In the chemical reaction to form the nitrogen-doped silicon carbide layer, the ammonia in the reactants is ionized to form nitrogen ions, hydrogen ions and NH i (i=1,2,3) plasma. In nitrogen ions, hydrogen ions and NH i (i=1,2,3) Under the bombardment of plasma, the Si-CH3 bond of tetramethylsiloxane in the reactant is ionized to produce silicon ions and carbon ions. The nitrogen ions, hydrogen ions and NH4+ formed by the ionization of ammonia are i (i=1,2,3) Plasma combines with silicon ions and carbon ions formed by ionization of tetramethylsiloxane, and is retained in the nitrogen-doped silicon carbide layer in the form of silicon-nitrogen bonds and carbon-nitrogen bonds. Among them, hydrogen ions are extracted to reduce the hydrogen ion content in the nitrogen-doped silicon carbide layer, so that the hydrogen ion content of the nitrogen-doped silicon carbide layer is less than the target value, further reducing the content of hydrogen ions in the barrier layer 5 diffusing to the gate oxide layer 12 through the connection structure of the gate 11, thereby further reducing the risk of the gate oxide layer 12 being broken down.

[0070] In some embodiments, the method for manufacturing a semiconductor device further includes: forming a passivation layer on the barrier layer; forming a pad penetrating the passivation layer and the barrier layer, and the pad is connected to the connection structure.

[0071] like Figure 3 As shown, a thin film deposition process is used to form a passivation layer (ie, a first passivation layer 6) on the side of the barrier layer 5 away from the interconnection layer 2. The material of the first passivation layer 6 may include silicon oxide or the like.

[0072] Then, an etching process is adopted to etch the first passivation layer 6 and the barrier layer 5 using the barrier layer 5 as an etching stop layer to form a first opening penetrating the first passivation layer 6 and the barrier layer 5 to expose the top wiring layer (such as Figure 2 The gate wiring, source wiring, drain wiring and electrode wiring in the third wiring layer 43) are away from the side of the substrate 1. Then, as Figure 4 As shown, a pad 7 is formed in the first opening of the first passivation layer 6 and the barrier layer 5 by an electroplating process, that is, the pad 7 penetrates the first passivation layer 6 and the barrier layer 5. There may be multiple pads 7, and the multiple pads 7 are respectively connected to the connection structure of the gate 11, the connection structure of the source region 13, the connection structure of the drain region 14, and the connection structure of the substrate 18.

[0073] In some embodiments, the pad 7 may also be located on a side of the first passivation layer 6 away from the barrier layer 5. The material of the pad 7 may include metals such as aluminum.

[0074] In some embodiments, the method for manufacturing a semiconductor device further includes: forming a second passivation layer 8 on the first passivation layer 6, and forming a third passivation layer 9 on the second passivation layer 8; forming a second opening penetrating the second passivation layer 8 and the third passivation layer 9 to expose the pad 7 in the first opening.

[0075] like Figure 4 As shown, when the pad 7 is located on the side of the first passivation layer 6 away from the barrier layer 5 and the first opening, a thin film deposition process is used to form a second passivation layer 8 on the side of the pad 7 away from the barrier layer 5, and a third passivation layer 9 is formed on the side of the second passivation layer 8 away from the first passivation layer 6. Then, the third passivation layer 9 and the second passivation layer 8 are etched by an etching process to form a second opening to expose a plurality of pads 7 respectively connected to the connection structure of the gate 11, the connection structure of the source region 13, the connection structure of the drain region 14, and the connection structure of the substrate 18. The material of the second passivation layer 8 may include silicon oxide, etc. The material of the third passivation layer 9 may include silicon nitride, etc.

[0076] In summary, according to the method for manufacturing a semiconductor device provided in an embodiment of the present application, the alloying annealing process is advanced to after the connection structure of the gate 11 is formed, and before the barrier layer 5 containing hydrogen ions is formed, and the alloying annealing process is no longer performed after the barrier layer 5 is formed, so as to reduce the content of hydrogen ions in the barrier layer 5 diffusing to the gate oxide layer 12 through the connection structure of the gate 11, so as to reduce the risk of the gate oxide layer 12 being broken down, improve the TDDB performance of the semiconductor device, and thus improve the reliability and stability of the semiconductor device. In addition, by reducing the hydrogen ion content in the barrier layer 5, the content of hydrogen ions in the barrier layer 5 diffusing to the gate oxide layer 12 through the connection structure of the gate 11 is further reduced, so as to further reduce the risk of the gate oxide layer 12 being broken down, thereby further improving the TDDB performance of the semiconductor device, and thus improving the reliability and stability of the semiconductor device. In addition, by reducing the hydrogen ion content in the barrier layer 5, the hydrogen ion content in the barrier layer 5 diffusing to the gate oxide layer 12 through the connection structure of the gate 11 is further reduced, so as to further reduce the risk of the gate oxide layer 12 being broken down, thereby further improving the TDDB performance of the semiconductor device, and thus improving the reliability and stability of the semiconductor device.

[0077] Correspondingly, an embodiment of the present application also provides a semiconductor device that can be manufactured using the semiconductor device manufacturing method in the above embodiment.

[0078] like Figure 4 As shown, the semiconductor device provided by the embodiment of the present application includes a substrate 1, an interconnection layer 2 and a barrier layer 5 containing hydrogen ions.

[0079] The substrate 1 includes a transistor, and the transistor includes a gate oxide layer 12 and a gate 11 located on the gate oxide layer 12. Figure 4 As shown, the gate oxide layer 12 and the gate 11 can be arranged near the surface of one side of the substrate 1 (such as the upper surface of the substrate 1). In some embodiments, the substrate 1 may also include a substrate 18, a buried oxide layer 17 and an SOI layer 15. The buried oxide layer 17 is located on the substrate 18, and the SOI layer 15 is located on the buried oxide layer 17. The gate oxide layer 12 may be located on the SOI layer 15, and the gate 11 is located on the gate oxide layer 12. The transistor also includes an active region, which is located in the SOI layer 15 and is arranged near the upper surface of the SOI layer 15. The active region includes a source region 13 and a drain region 14 that are spaced apart, and the gate oxide layer 12 is located on the active region between the source region 13 and the drain region 14.

[0080] The interconnection layer 2 is located on the substrate 1, and the interconnection layer 2 includes a connection structure connected to the gate 11. Figure 4 As shown, the interconnection layer 2 covers the substrate 1 , that is, the interconnection layer 2 covers the gate 11 , the source region 13 and the drain region 14 .

[0081] In some embodiments, the interconnection layer 2 may include a plurality of interconnection sublayers stacked in sequence. Each interconnection sublayer may include a dielectric layer and a routing layer, and the routing layer in each interconnection sublayer is located on the dielectric layer and penetrates the dielectric layer. The routing layers in adjacent interconnection sublayers are connected.

[0082] Each routing layer includes a gate routing, and the gate routings of multiple routing layers in the interconnect layer 2 are connected in sequence to form a connection structure connected to the gate 11. Each routing layer may also include a source routing, and the source routings of multiple routing layers in the interconnect layer 2 are connected in sequence to form a connection structure connected to the source region 13. Each routing layer may also include a drain routing, and the drain routings of multiple routing layers in the interconnect layer 2 are connected in sequence to form a connection structure connected to the drain region 14. Each routing layer may also include an electrode routing, and the electrode routings of multiple routing layers in the interconnect layer 2 are connected in sequence to form a connection structure connected to the substrate 18.

[0083] It should be noted that the gate wiring, source wiring, drain wiring and electrode wiring in each wiring layer are arranged at intervals. When the potential of the gate 11 is equal to the potential of the substrate 18, the gate wiring in each wiring layer is connected to the electrode wiring.

[0084] For example, the interconnection layer 2 may include a first interconnection sublayer 21, a second interconnection sublayer 22, and a third interconnection sublayer 23, which are stacked in sequence. The first interconnection sublayer 21 includes a first dielectric layer 31 and a first routing layer 41, the second interconnection sublayer 22 includes a second dielectric layer 32 and a second routing layer 42, and the third interconnection sublayer 23 includes a third dielectric layer 33 and a third routing layer 43.

[0085] The first dielectric layer 31 is located on one side of the substrate 1 and covers the gate 11, the source region 13 and the drain region 14. The first wiring layer 41 is located on the side of the first dielectric layer 31 away from the substrate 1 and penetrates the first dielectric layer 31. The first wiring layer 41 may include gate wiring, source wiring, drain wiring and electrode wiring. The gate wiring, source wiring, drain wiring and electrode wiring in the first wiring layer 41 respectively penetrate the first dielectric layer 31 and respectively connect the gate 11, the source region 13, the drain region 14 and the substrate 18.

[0086] The second dielectric layer 32 is located on a side of the first wiring layer 41 away from the first dielectric layer 31, and covers the first wiring layer 41. The second wiring layer 42 is located on a side of the second dielectric layer 32 away from the first wiring layer 41 and penetrates the second dielectric layer 32. The second wiring layer 42 may include a gate wiring, a source wiring, a drain wiring, and an electrode wiring, and the gate wiring, source wiring, drain wiring, and electrode wiring in the second wiring layer 42 respectively penetrate the second dielectric layer 32, and respectively connect to the gate wiring, source wiring, drain wiring, and electrode wiring in the first wiring layer 41.

[0087] The third dielectric layer 33 is located on a side of the second wiring layer 42 away from the second dielectric layer 32, and covers the second wiring layer 42. The third wiring layer 43 is located on a side of the third dielectric layer 33 away from the second wiring layer 42 and penetrates the third dielectric layer 33. The third wiring layer 43 may include a gate wiring, a source wiring, a drain wiring, and an electrode wiring, and the gate wiring, source wiring, drain wiring, and electrode wiring in the third wiring layer 43 respectively penetrate the third dielectric layer 33, and are respectively connected to the gate wiring, source wiring, drain wiring, and electrode wiring in the second wiring layer 42.

[0088] Among them, the gate wiring in the first wiring layer 41, the gate wiring in the second wiring layer 42, and the gate wiring in the third wiring layer 43 are connected in sequence to form a connection structure connected to the gate 11. The source wiring in the first wiring layer 41, the source wiring in the second wiring layer 42, and the source wiring in the third wiring layer 43 are connected in sequence to form a connection structure connected to the source region 13. The drain wiring in the first wiring layer 41, the drain wiring in the second wiring layer 42, and the drain wiring in the third wiring layer 43 are connected in sequence to form a connection structure connected to the drain region 14. The electrode wiring in the first wiring layer 41, the electrode wiring in the second wiring layer 42, and the electrode wiring in the third wiring layer 43 are connected in sequence to form a connection structure connected to the substrate 18.

[0089] The interconnect layer 2 may further include a fourth dielectric layer 34. The fourth dielectric layer 34 is located at the top wiring layer (eg Figure 4 The dielectric layer (such as the third wiring layer 43 in Figure 4 The surface of the fourth dielectric layer 34 facing away from the substrate 1 is connected to the top wiring layer (such as Figure 4 The surface of the third wiring layer 43) in the substrate 1 is flush with the surface of the third wiring layer 43) facing away from the substrate 1.

[0090] The barrier layer 5 containing hydrogen ions is located on the interconnect layer 2. The barrier layer 5 is located on the side of the interconnect layer 2 facing away from the substrate 1.

[0091] This embodiment can reduce the content of hydrogen ions in the barrier layer 5 diffusing into the gate oxide layer 12 through the connection structure of the gate 11, so as to reduce the risk of the gate oxide layer 12 being broken down, thereby improving the TDDB performance of the semiconductor device, and further improving the reliability and stability of the semiconductor device.

[0092] In some embodiments, the semiconductor device may further include a first passivation layer 6 and a pad 7. The first passivation layer 6 is located on the side of the barrier layer 5 away from the interconnection layer 2. There may be multiple pads 7, and the multiple pads 7 penetrate the first passivation layer 6 and the barrier layer 5, and are correspondingly connected to the connection structure of the gate 11, the connection structure of the source region 13, the connection structure of the drain region 14, and the connection structure of the substrate 18.

[0093] In some embodiments, the pad 7 may also be located on a side of the first passivation layer 6 facing away from the barrier layer 5 .

[0094] In some embodiments, the semiconductor device may further include a second passivation layer 8 and a third passivation layer 9. Figure 4 As shown, the second passivation layer 8 may be located on the side of the pad 7 away from the first passivation layer 6, and the third passivation layer 9 may be located on the side of the second passivation layer 8 away from the pad 7. The second passivation layer 8 and the third passivation layer 9 have a second opening to expose the pad 7 connected to the connection structure of the gate 11, the connection structure of the source region 13, the connection structure of the drain region 14, and the connection structure of the substrate 18.

[0095] In some embodiments, the barrier layer 5 includes a silicon nitride layer or a nitrogen-doped silicon carbide layer having a hydrogen ion content less than a target value. For example, the target value may be the hydrogen ion content of the silicon nitride layer formed when the flow rate of the introduced ammonia gas is 4000 sccm.

[0096] In summary, according to the semiconductor device provided in the embodiment of the present application, by reducing the hydrogen ion content in the barrier layer 5, the content of hydrogen ions in the barrier layer 5 that diffuse into the gate oxide layer 12 through the connection structure of the gate 11 is reduced, so as to reduce the risk of breakdown of the gate oxide layer 12, thereby improving the TDDB performance of the semiconductor device, and further improving the reliability and stability of the semiconductor device.

[0097] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more.

[0098] In the description of the present application, “plurality” means two or more.

[0099] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0100] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, the substrate comprising a transistor, the transistor comprising a gate oxide layer and a gate located on the gate oxide layer; forming an interconnection layer on the substrate, the interconnection layer including a connection structure connected to the gate to obtain an intermediate structure; performing alloying annealing treatment on the intermediate structure; A barrier layer containing hydrogen ions is formed on the interconnect layer, and the barrier layer covers the connection structure.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The barrier layer includes a silicon nitride layer having a hydrogen ion content less than a target value.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The step of forming a barrier layer containing hydrogen ions on the interconnect layer comprises: A silicon nitride layer having a hydrogen ion content less than the target value is formed on the interconnect layer by a reaction gas, wherein the reaction gas includes silane and nitrogen.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: The reaction gas further includes ammonia gas, and the flow rate of the ammonia gas is less than or equal to 3000 sccm.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The barrier layer includes a nitrogen-doped silicon carbide layer having a hydrogen ion content less than a target value.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: Before performing alloying annealing treatment on the intermediate structure, the method further comprises: Chemical mechanical polishing is performed on a side of the interconnect layer facing away from the substrate.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: The annealing temperature of the alloying annealing is 350° C.-500° C., and the protective gas includes nitrogen and hydrogen. The proportion of the hydrogen is 0%-15%, and the proportion of the nitrogen is 85%-100%.

8. The method for manufacturing a semiconductor device according to any one of claims 1 to 7, characterized in that: The method further comprises: forming a passivation layer on the barrier layer; A pad is formed penetrating the passivation layer and the barrier layer, and the pad is connected to the connection structure.

9. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 8; the semiconductor device comprises: A substrate, comprising a transistor, wherein the transistor comprises a gate oxide layer and a gate located on the gate oxide layer; An interconnection layer, located on the substrate, and comprising a connection structure connected to the gate; A barrier layer containing hydrogen ions is located on the interconnect layer.

10. The semiconductor device according to claim 9, characterized in that The barrier layer includes a silicon nitride layer or a nitrogen-doped silicon carbide layer having a hydrogen ion content less than a target value.

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