Fin type p-type multi-channel GaN transistor structure and preparation method thereof
By designing a fin structure and a multi-channel structure in a GaN-based p-type field effect transistor, multiple two-dimensional hole air and hole accumulation areas are formed, and gate electrodes are provided on the fin structure, the problems of low current density and high on-resistance of existing GaN-based p-type field effect transistors are solved, and higher current density and lower on-resistance are achieved.
Patent Information
- Application Number
- CN202411647199.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-18
- Publication Date
- 2025-04-08
AI Technical Summary
The current density of existing GaN-based p-type field effect transistors is low and have high on-resistance, and the presence of 2DHG weakens the gate-to-interface control capability, resulting in poor device performance.
A fin-type p-type multi-channel GaN transistor structure is designed, and by forming multiple two-dimensional hole gas and hole accumulation regions in the GaN transistor as conductive channels, and setting a gate electrode on the fin-type structure, the control of the gate electrode on the conductive channel is enhanced.
The open-state current density of GaN transistors is improved, the on-resistance is reduced, the device footprint is reduced, and the short channel effect is effectively suppressed, achieving better sub-threshold performance.
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Figure CN119789472A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a fin-type p-type multi-channel GaN transistor structure and a preparation method thereof. Background Art
[0002] GaN and other compounds such as AlN, InN, BN, etc. can exist in sphalerite structure, wurtzite structure and salt mine structure, among which the stable structure of GaN, AlN, InN is wurtzite structure, while the stable structure of BN is salt mine structure. In the GaN wurtzite structure, Ga atoms and N atoms are arranged alternately along the direction. The situation where Ga atoms are at the top of the Ga-N bilayer is called Ga polarity, and vice versa, so that the non-centrosymmetric arrangement in the direction produces a strong spontaneous polarization effect in this direction. The spontaneous polarization effect of GaN wurtzite and the piezoelectric polarization effect caused by lattice mismatch stress at the heterojunction interface composed of GaN and other nitride materials have been deeply studied. At present, most of the research results on GaN are focused on Ga polarity, and the present invention is also based on Ga polarity GaN.
[0003] At present, the main methods for realizing GaN-based enhancement-mode devices include thin barrier structure, fluorine ion implantation, P-type cap layer GaN structure, recessed gate structure, and fin field effect transistor (FinFET) structure. In 1996, Khan et al. prepared the first GaN enhancement-mode device by modulating the threshold voltage with doping concentration. Professor Hu Zhengming invented the fin field effect transistor structure device. This structure was initially used in Si-based MOS devices to transform the device structure from a planar structure to a three-dimensional structure, increase the area controlled by the gate, and improve the device gate control capability. In 2011, Intel began to launch commercial fin field effect transistors in its 22nm process technology, and began mass production of 14nm and 7nm process technologies. Fin field effect transistor devices have become the mainstream devices of today's electronic products, and vertical three-dimensional gate devices will also be further used in the 3nm process technology.
[0004] Nitrides are usually doped with Si to form n-type materials and with Mg to form p-type materials. However, the ionization energy of Mg is relatively large and is affected by residual impurities in the material. Therefore, the ionized hole concentration obtained by Mg doping is much lower than the ionized electron concentration obtained by Si doping at the same doping concentration. In addition, since the hole mobility is lower than the electron mobility, the current density obtained by the p-FET device is lower than that of the n-FET.
[0005] A fin structure is introduced into GaN-based devices. The fin structure can be forward biased in the threshold voltage compared to the planar structure. At this time, due to the additional gate control capability provided on the sidewall, when no gate voltage is applied, the side gate will deplete the two-dimensional electron gas from both sides. At the same time, the introduction of the side gate will release part of the stress in the potential barrier, resulting in a reduction in piezoelectric polarization. When the width of the fin structure is less than a certain value, the gate can deplete the two-dimensional electron gas by zero bias, making the device threshold positively biased and normally off. At the same time, due to the existence of the side gate, the gate control capability is further improved, providing high current, low leakage and better subthreshold performance for miniaturization and high-speed applications, and weakening the short channel effect.
[0006] Research on 2DHG (two-dimensional hole gas) has been going on for some time. The mobility of GaN holes is not high. Even for 2DHG in the quantum well channel, its mobility at room temperature is only about 100%. According to previous modeling research on 2DHG at the GaN / AlGaN / GaN heterojunction interface, the presence of 2DHG will weaken the gate's control over the 2DEG at the AlGaN / GaN interface. However, in applications such as BisFET and GaN-based varactor diodes prepared using the electron-hole pair condensation effect, the presence of 2DHG can still play an important role. In addition, the presence of only 2DHG in the channel of the GaN heterojunction can also be used to prepare p-channel GaN HEMT. At present, there is still a big gap in this regard.
[0007] To this end, we propose a fin-type p-type multi-channel GaN transistor structure and a preparation method thereof to solve the above problems. Summary of the invention
[0008] In order to make up for the deficiencies of the prior art, the present invention provides the following technical solutions: a fin-type p-type multi-channel GaN transistor structure and a method for preparing the same, comprising a substrate, a buffer layer being located on the substrate;
[0009] a first barrier layer, wherein the first channel layer is located on the buffer layer;
[0010] A first channel layer, wherein the first channel layer is located on the first barrier layer, and the first channel layer includes, from bottom to top, a first channel layer undoped region and a first channel layer p-type doped region;
[0011] a second barrier layer, wherein the second barrier layer is located on the first channel layer;
[0012] a second channel layer, wherein the second channel layer is located on the second barrier layer, and the structure of the second channel layer is similar to that of the first channel layer;
[0013] A plurality of similar barrier layers and an N-1th channel layer are sequentially arranged from bottom to top, until an N-th barrier layer and an N-th channel layer, wherein the N-th barrier layer is located on the N-1th channel layer;
[0014] The Nth channel layer is located on the Nth barrier layer, and the Nth channel layer includes, from bottom to top, an Nth channel layer undoped region and an Nth channel layer p-type doped region;
[0015] The materials of the buffer layer, the first barrier layer, the first channel layer, the second barrier layer, the second channel layer to the Nth barrier layer and the Nth channel layer are group III nitrides, which are one of GaN, InN and AlN, or a compound formed by several of them. A plurality of two-dimensional hole gases and hole accumulation regions are formed near the interface between the interior of the first channel layer and the first barrier layer, near the interface between the interior of the second barrier layer and the second channel layer, and near the interface between the interior of the Nth barrier layer and the Nth channel layer, as a plurality of conductive channels of the GaN transistor;
[0016] Etching a portion of the area from the first barrier layer to the Nth channel layer, the etching depth reaching the first barrier layer or penetrating the first barrier layer into the buffer layer to form a fin structure;
[0017] A dielectric layer, the dielectric layer is coated on the table surface, the side surface and the bottom surface of the groove between the fin structure; a gate electrode, the gate electrode is coated on the table surface, the side surface and the bottom surface of the groove between the fin structure coated by the dielectric layer, and the gate electrode regulates the conductive channel formed by the two-dimensional hole gas and the hole accumulation area;
[0018] A drain electrode, the drain electrode is coated on the terrace, the side and the bottom of the groove between the fin-shaped structures, and is in contact with the conductive channel formed by the two-dimensional hole gas and the hole accumulation area;
[0019] A source electrode, the source electrode is coated on the terrace, the side and the bottom of the groove between the fin-shaped structures, and is in contact with the conductive channel formed by the two-dimensional hole gas and the hole accumulation area;
[0020] In one embodiment of the present invention, multiple conductive channels are formed near the interface between the first channel layer and the first barrier layer, near the interface between the second barrier layer and the second channel layer, and near the interface between the Nth barrier layer and the Nth channel layer, which increases the on-current of the GaN transistor and reduces the on-resistance of the GaN transistor.
[0021] The design of the fin structure, dielectric layer, and gate electrode enhances the control of the gate electrode over the conductive channel of the GaN transistor, making it easy to achieve an enhanced operating mode.
[0022] The design of the undoped region of the first channel layer, the undoped region of the second channel layer to the undoped region of the Nth channel layer in the first channel layer, the second channel layer to the Nth channel layer reduces the impurity scattering of holes in the conductive channel and improves the mobility of holes;
[0023] In the first channel layer, the second channel layer to the N-th channel layer, the design of the first channel layer p-type doping region, the second channel layer p-type doping region to the N-th channel layer p-type doping region provides holes for the conductive channel and also suppresses the generation of parasitic two-dimensional electron gas.
[0024] Preferably, a first channel layer p-type heavily doped region is provided inside the first channel layer and between the first channel layer p-type doped region and the second barrier layer, and the first channel layer p-type heavily doped region further effectively suppresses the formation of parasitic two-dimensional electron gas between the first channel layer p-type doped region and the second barrier layer, and reduces the contact resistance between the first conductive channel and the source electrode, and between the first conductive channel and the drain electrode;
[0025] A second channel layer p-type heavily doped region is provided inside the second channel layer and between the second channel layer p-type doped region and the third barrier layer. The second channel layer p-type heavily doped region further effectively suppresses the formation of a parasitic two-dimensional electron gas between the second channel layer p-type doped region and the third barrier layer, and reduces the contact resistance between the second conductive channel and the source electrode, and between the second conductive channel and the drain electrode;
[0026] In the Nth channel layer, on the Nth channel layer p-type doped region, an Nth channel layer p-type heavily doped region is provided to reduce the contact resistance between the conductive channel and the source electrode, and between the Nth conductive channel and the drain electrode.
[0027] Preferably, the substrate material is Sapphire, Si or SiC, and the thickness is 50nm-1000μm.
[0028] Preferably, the buffer layer material is GaN, AlGaN or AlN, and has a thickness of 0.1-5 μm.
[0029] Preferably, the material from the first channel layer undoped region to the Nth channel layer undoped region is InGaN or GaN, has a thickness of 5-50 nm, and is not intentionally doped.
[0030] Preferably, the material from the first channel layer p-type doping region to the Nth channel layer p-type doping region is InGaN or GaN, and the doping impurity is Mg, and the doping concentration is 1x10 18 -5x10 19 cm -3 , thickness is 10-100nm.
[0031] Preferably, the first barrier layer to the Nth barrier layer are made of AlGaN, AlN or InAlN, and have a thickness of 2-100 nm.
[0032] Preferably, the material from the first channel layer p-type heavily doped region to the Nth channel layer p-type heavily doped region is InGaN or GaN, and the doping impurity is Mg, and the doping concentration is 1x10 19-1x10 21 cm -3 , thickness is 10-100nm.
[0033] Preferably, the material of the dielectric layer is one or more of Al2O3, SiO2, SiN, HfO2, ZrO2, and Ta2O5, and the thickness is 3-50 nm.
[0034] Preferably, the gate electrode material is one or more of Ti, Au, TiN, Al, and W.
[0035] Preferably, the drain electrode and the source electrode have a first layer material of Ni, and other metals are one or more of Au, Al, and W.
[0036] Preferably, the method comprises the following steps:
[0037] S1: Select substrate;
[0038] S2: epitaxially growing a buffer layer, a first barrier layer, a first channel layer, a second barrier layer and a second channel layer on the substrate in sequence, and stacking a plurality of similar barrier layers and channel layers in a similar manner until an Nth barrier layer and an Nth channel layer are formed;
[0039] S3: etching in a partial area to form a fin-shaped structure;
[0040] S4: depositing a dielectric layer on the surface of the sample obtained in S3;
[0041] S5: depositing metal in a partial area of the dielectric layer to form a gate electrode covering the surface of the fin-shaped structure;
[0042] S6: Remove the dielectric layer on both sides of the gate electrode and deposit metal to form a drain electrode and a source electrode.
[0043] Preferably, step S3 includes:
[0044] S31: depositing a SiO2 mask on the p-GaN;
[0045] S32: etching or ion implantation to form device isolation;
[0046] S33: dry etching to obtain a trapezoidal structure;
[0047] S34: performing wet etching to obtain a vertical fin structure;
[0048] S35: removing the mask.
[0049] Beneficial Effects
[0050] Compared with the prior art, the present invention provides a fin-type p-type multi-channel GaN transistor structure and a preparation method thereof, which has the following beneficial effects:
[0051] 1. The fin-type p-type multi-channel GaN transistor proposed in the present invention stacks conductive channels with multiple two-dimensional hole gases and hole accumulation regions in the vertical direction, thereby improving the on-state current density of the GaN transistor, reducing the on-resistance of the GaN transistor, and reducing the transistor's footprint.
[0052] 2. The fin-type p-type multi-channel GaN transistor proposed in the present invention has gate electrodes on the side, top and bottom surfaces of the fin-shaped table, which effectively improves the control effect of the gate electrode on the conductive channel, effectively suppresses the short channel effect, and is also conducive to achieving enhanced operation.
[0053] 3. The process technology used in the present invention is all existing mature technology with good process repeatability, which effectively reduces the manufacturing cost of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0054] Figure 1 A schematic structural diagram of a fin-type p-type multi-channel GaN transistor provided in an embodiment of the present invention;
[0055] Figure 2 A schematic cross-sectional view of a fin-type p-type double-channel GaN transistor provided in an embodiment of the present invention;
[0056] Figure 3 A schematic diagram of a process of manufacturing a fin-type p-type multi-channel GaN transistor provided by an embodiment of the present invention;
[0057] Figure 4 Schematic diagram of GaN / AlN heterojunction interface.
[0058] In the figure: 1, substrate; 2, buffer layer; 3, first barrier layer; 4, first channel layer; 41, undoped region of first channel layer; 42, p-type doped region of first channel layer; 43, p-type heavily doped region of first channel layer; 44, first conductive channel; 5, second barrier layer; 6, second channel layer; 62, p-type doped region of second channel layer; 621, third barrier layer; 63, p-type heavily doped region of second channel layer; 64, second conductive channel Electrical channel; 7. Barrier layer-channel layer stacking structure from the third layer to the N-1th layer; 71. N-1th channel layer; 8. Nth barrier layer; 9. Nth channel layer; 91. Nth channel layer undoped region; 92. Nth channel layer p-type doped region; 93. Nth channel layer p-type heavily doped region; 94. Nth conductive channel; 10. Dielectric layer; 11. Gate electrode; 12. Drain electrode; 13. Source electrode; 14. Fin structure. DETAILED DESCRIPTION
[0059] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0060] Example 1
[0061] A fin-type p-type multi-channel GaN transistor structure of this embodiment, such as Figure 1 As shown, specifically including:
[0062] Substrate layer 1,
[0063] A buffer layer 2, located on the upper side of the substrate layer 1;
[0064] A first barrier layer 3, wherein the first barrier layer 3 is located on the buffer layer 2;
[0065] A first channel layer 4, wherein the first channel layer 4 is located on the first barrier layer 3, and the first channel layer includes, from bottom to top, a first channel layer undoped region 41 and a first channel layer p-type doped region 42;
[0066] a second barrier layer 5, wherein the second barrier layer 5 is located on the first channel layer 4;
[0067] A second channel layer 6, wherein the second channel layer 6 is located on the second barrier layer 5, and the structure of the second channel layer 6 is similar to that of the first channel layer 4;
[0068] A plurality of similar barrier layers and the N-1th channel layer 7 are sequentially arranged from bottom to top, until the N-th barrier layer 8 and the N-th channel layer 9, wherein the N-th barrier layer 8 is located on the N-1th channel layer 71;
[0069] The Nth channel layer 9 is located on the Nth barrier layer 8, and the Nth channel layer 9 includes, from bottom to top, an Nth channel layer undoped region 91 and an Nth channel layer p-type doped region 92;
[0070] The materials of the buffer layer 2, the first barrier layer 3, the first channel layer 4, the second barrier layer 5, the second channel layer 6 to the Nth barrier layer 8 and the Nth channel layer 9 are group III nitrides, which are one of GaN, InN and AlN, or a compound formed by several of them. A plurality of two-dimensional hole gas and hole accumulation regions are formed near the interface between the inside of the first channel layer 4 and the first barrier layer 3, near the interface between the inside of the second barrier layer 5 and the second channel layer 6, and near the interface between the inside of the Nth barrier layer 8 and the Nth channel layer 9, serving as a plurality of conductive channels of the GaN transistor;
[0071] Etching a portion of the first barrier layer 3 to the Nth channel layer 9 to a depth reaching the first barrier layer 3 or penetrating the first barrier layer 3 into the buffer layer 2 to form a fin structure 14;
[0072] A dielectric layer 10, the dielectric layer 10 is coated on the table surface, the side edge and the bottom surface of the groove between the fin structure 14; a gate electrode 11, the gate electrode 11 is coated on the table surface, the side edge and the bottom surface of the groove between the fin structure 14 coated by the dielectric layer 10, and the gate electrode 11 regulates the conductive channel formed by the two-dimensional hole gas and the hole accumulation area;
[0073] A drain electrode 12, wherein the drain electrode 12 is coated on the terrace, the side edge and the bottom surface of the groove between the fin-shaped structures 14, and is in contact with the conductive channel formed by the two-dimensional hole gas and the hole accumulation area;
[0074] A source electrode 13, wherein the source electrode 13 is coated on the terrace, the side edge and the bottom surface of the groove between the fin-shaped structures 14, and is in contact with the conductive channel formed by the two-dimensional hole gas and the hole accumulation area;
[0075] Multiple conductive channels are formed near the interface between the first channel layer 4 and the first barrier layer 3, near the interface between the second barrier layer 5 and the second channel layer 6, and near the interface between the Nth barrier layer 8 and the Nth channel layer 9, which increase the on-current of the GaN transistor and reduce the on-resistance of the GaN transistor.
[0076] The design of the fin structure 14, the dielectric layer 10 and the gate electrode 11 enhances the control of the gate electrode 11 over the conductive channel of the GaN transistor, making it easy to achieve an enhanced working mode;
[0077] In the first channel layer 4, the second channel layer 6 to the Nth channel layer 9, the design of the first channel layer undoped region 41, the second channel layer undoped region 61 to the Nth channel layer undoped region 91 reduces the impurity scattering of holes in the conductive channel and improves the mobility of holes;
[0078] In the first channel layer 4, the second channel layer 6 to the N-th channel layer 9, the design of the first channel layer p-type doping region 42, the second channel layer p-type doping region 62 to the N-th channel layer p-type doping region 92 provides holes for the conductive channel and also suppresses the formation of parasitic two-dimensional electron gas;
[0079] Specifically, inside the first channel layer 4, between the first channel layer p-type doping region 42 and the second barrier layer 5, a first channel layer p-type heavily doped region 43 is provided, and the first channel layer p-type heavily doped region 43 further effectively suppresses the formation of parasitic two-dimensional electron gas between the first channel layer p-type doping region 42 and the second barrier layer 5, and reduces the contact resistance between the first conductive channel 44 and the source electrode 13, and between the first conductive channel 44 and the drain electrode 12;
[0080] Similarly, a second channel layer p-type heavily doped region 63 is provided between the second channel layer p-type doped region 62 and the third barrier layer 621 inside the second channel layer 6. The second channel layer p-type heavily doped region 63 further effectively suppresses the formation of parasitic two-dimensional electron gas between the second channel layer p-type doped region 62 and the third barrier layer 621, and reduces the contact resistance between the second conductive channel 64 and the source electrode 13, and between the second conductive channel 64 and the drain electrode 12.
[0081] On the Nth channel layer p-type doping region 92 inside the Nth channel layer 9, an Nth channel layer p-type heavily doped region 93 is provided to reduce the contact resistance between the conductive channel 94 and the source electrode 13, and between the Nth conductive channel 94 and the drain electrode 12;
[0082] The device is based on a Ga-polarity GaN heterojunction. This is because Ga-polarity GaN is easier to achieve p-type doping and has a relatively flat surface, which is conducive to subsequent epitaxial growth. In addition, Ga-polarity GaN has a higher hole mobility, which is conducive to improving the performance of the device.
[0083] Preferably, in order to improve the thermal conductivity of the device and reduce the production cost as much as possible, the substrate 1 is made of Si and has a thickness of 675 μm;
[0084] Preferably, the material of the buffer layer 2 is graded AlGaN and GaN, with a thickness of 0.1-5 μm;
[0085] Preferably, the first channel layer undoped region 41 to the Nth channel layer undoped region 91 are made of GaN, have a thickness of 20 nm, and are not intentionally doped;
[0086] Preferably, the first channel layer p-type doping region 42 to the Nth channel layer p-type doping region 92 are made of GaN, doped with Mg as an impurity, and have a doping concentration of 1×10 18 -5x10 19 cm -3 , thickness is 10-100nm;
[0087] Preferably, the first barrier layer 3 to the Nth barrier layer 8 are made of AlGaN and have a thickness of 20 nm;
[0088] Preferably, the first channel layer p-type heavily doped region 43 to the Nth channel layer p-type heavily doped region 93 are made of GaN, doped with Mg as an impurity, and have a doping concentration of 1×10 19 -1x10 21 cm -3 , thickness is 20nm;
[0089] Preferably, the material of the dielectric layer 10 is Al2O3, and the thickness is 10 nm;
[0090] Preferably, the gate electrode 11 is made of Ti and Au from bottom to top;
[0091] Preferably, the materials of the drain electrode 12 and the source electrode 13 are Ni and Au from bottom to top.
[0092] Example 2
[0093] A fin-type p-type multi-channel GaN transistor structure and a method for manufacturing the same are shown in the embodiment. Figure 2-4 As shown, specifically including:
[0094] S1: Select substrate 1;
[0095] S2: using MOCVD epitaxial technology on the substrate 1, epitaxially growing a buffer layer 2, a first barrier layer 3, a first channel layer 4, a second barrier layer 5, a second channel layer 6 to an Nth barrier layer 8, and an Nth channel layer 9 in sequence;
[0096] S3: using SiO2 as a mask, performing dry etching by ICP in a partial area, etching to a depth that reaches the buffer layer 2, and forming a fin-shaped structure;
[0097] S4: using an atomic layer deposition system ALD on the surface of the sample obtained in S3 to deposit Al2O3 as a dielectric layer 10;
[0098] S5: depositing metal Ti and Au in a partial area of the dielectric layer 10 by magnetron sputtering technology to form a gate electrode 11 covering the surface of the fin-shaped structure;
[0099] S6: On both sides of the gate electrode 11 , the dielectric layer 10 is removed by using a BOE solution, and Ni and Au metals are deposited by a magnetron sputtering system to form a drain electrode 12 and a source electrode 13 .
[0100] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.
[0101] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.
[0102] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A fin-type p-type multi-channel GaN transistor structure, characterized in that: include: Substrate (1); A buffer layer (2), wherein the buffer layer (2) is located on the substrate (1); A first barrier layer (3), wherein the first barrier layer (3) is located on the buffer layer (2); A first channel layer (4), the first channel layer (4) being located on the first barrier layer (3), the first channel layer (4) comprising, from bottom to top, a first channel layer undoped region (41) and a first channel layer p-type doped region (42); A second barrier layer (5), wherein the second barrier layer (5) is located on the first channel layer (4); The second channel layer (6) is located on the second barrier layer (5); A plurality of similar barrier layers and an N-1th channel layer (7) are sequentially arranged from bottom to top, until an N-th barrier layer (8) and an N-th channel layer (9), wherein the N-th barrier layer (8) is located on the N-1th channel layer (71); The Nth channel layer (9) is located on the Nth barrier layer (8), and the Nth channel layer (9) comprises, from bottom to top, an Nth channel layer undoped region (91) and an Nth channel layer p-type doped region (92); The materials of the buffer layer (2), the first barrier layer (3), the first channel layer (4), the second barrier layer (5), the second channel layer (6) to the Nth barrier layer (8) and the Nth channel layer (9) are group III nitrides, which are one of GaN, InN and AlN, or a compound formed by several of them. A plurality of two-dimensional hole gas and hole accumulation regions are formed near the interface between the interior of the first channel layer (4) and the first barrier layer (3), near the interface between the interior of the second barrier layer (5) and the second channel layer (6), and near the interface between the interior of the Nth barrier layer (8) and the Nth channel layer (9), serving as a plurality of conductive channels of the GaN transistor. Etching a portion of the first barrier layer (3) to the Nth channel layer (9) to a depth that reaches the first barrier layer (3) or penetrates through the first barrier layer (3) into the buffer layer (2), thereby forming a fin-type structure (14); A dielectric layer (10), the dielectric layer (10) covering the table surface, the side edge and the bottom surface of the groove between the fin structure (14); a gate electrode (11), the gate electrode (11) covering the table surface, the side edge and the bottom surface of the groove between the fin structure (14) covered by the dielectric layer (10), the gate electrode (11) regulating the conductive channel formed by the two-dimensional hole gas and the hole accumulation area; A drain electrode (12), the drain electrode (12) being coated on the terrace, the side edge and the bottom surface of the groove between the fin-shaped structures (14), and being in contact with the conductive channel formed by the two-dimensional hole gas and the hole accumulation region; A source electrode (13), the source electrode (13) being coated on the terrace, the side edge and the bottom surface of the groove between the fin-shaped structures (14), and being in contact with the conductive channel formed by the two-dimensional hole gas and the hole accumulation region; Multiple conductive channels are formed near the interface between the first channel layer (4) and the first barrier layer (3), near the interface between the second barrier layer (5) and the second channel layer (6), and near the interface between the Nth barrier layer (8) and the Nth channel layer (9), thereby increasing the on-state current of the GaN transistor and reducing the on-state resistance of the GaN transistor; Design of the first channel layer undoped region (41), the second channel layer undoped region (61) to the Nth channel layer undoped region (91) in the first channel layer (4), the second channel layer (6) to the Nth channel layer (9); In the first channel layer (4), the second channel layer (6) to the Nth channel layer (9), the design of the first channel layer p-type doping region (42), the second channel layer p-type doping region (62) to the Nth channel layer p-type doping region (92) provides holes for the conductive channel and also suppresses the formation of parasitic two-dimensional electron gas.
2. A fin-type p-type multi-channel GaN transistor structure and a method for manufacturing the same according to claim 1, characterized in that: A first channel layer p-type heavily doped region (43) is provided inside the first channel layer (4) and between the first channel layer p-type doped region (42) and the second barrier layer (5); the first channel layer p-type heavily doped region (43) further effectively suppresses the formation of a parasitic two-dimensional electron gas between the first channel layer p-type doped region (42) and the second barrier layer (5), and reduces the contact resistance between the first conductive channel (44) and the source electrode (13), and between the first conductive channel (44) and the drain electrode (12); A second channel layer p-type heavily doped region (63) is provided between the second channel layer p-type doped region (62) and the third barrier layer (621) inside the second channel layer (6); the second channel layer p-type heavily doped region (63) further effectively suppresses the formation of a parasitic two-dimensional electron gas between the second channel layer p-type doped region (62) and the third barrier layer (621), and reduces the contact resistance between the second conductive channel (64) and the source electrode (13), and between the second conductive channel (64) and the drain electrode (12); An Nth channel layer p-type heavily doped region (93) is provided on the Nth channel layer p-type doped region (92) inside the Nth channel layer (9) to reduce the contact resistance between the conductive channel (94) and the source electrode (13), and between the Nth conductive channel (94) and the drain electrode (12).
3. The fin-type p-type multi-channel GaN transistor structure and the method for manufacturing the same according to claim 1, characterized in that: The substrate (1) is made of Sapphire, Si, or SiC, and has a thickness of 50nm-1000μm.
4. The fin-type p-type multi-channel GaN transistor structure and the method for manufacturing the same according to claim 1, characterized in that: The buffer layer (2) is made of GaN, AlGaN or AlN and has a thickness of 0.1-5 μm.
5. The fin-type p-type multi-channel GaN transistor structure and the method for manufacturing the same according to claim 1, characterized in that: The first channel layer undoped region (41) to the Nth channel layer undoped region (91) are made of InGaN or GaN, have a thickness of 5-50nm, and are not intentionally doped.
6. The fin-type p-type multi-channel GaN transistor structure and the method for manufacturing the same according to claim 1, characterized in that: The first channel layer p-type doping region (42) to the Nth channel layer p-type doping region (92) are made of InGaN or GaN, doped with Mg as an impurity, and have a doping concentration of 1×10 18 -5x10 19 cm -3 , thickness is 10-100nm.
7. The fin-type p-type multi-channel GaN transistor structure and the method for manufacturing the same according to claim 1, characterized in that: The first barrier layer (3) to the Nth barrier layer (8) are made of AlGaN, AlN or InAlN, and have a thickness of 2-100 nm.
8. The fin-type p-type multi-channel GaN transistor structure and the method for manufacturing the same according to claim 1, characterized in that: The first channel layer p-type heavily doped region (43) to the Nth channel layer p-type heavily doped region (93) are made of InGaN or GaN, doped with Mg as an impurity, and have a doping concentration of 1×10 19 -1x10 21 cm -3 , thickness is 10-100nm.
9. The fin-type p-type multi-channel GaN transistor structure and the method for manufacturing the same according to claim 1, characterized in that: The material of the dielectric layer (10) is one or more of Al2O3, SiO2, SiN, HfO2, ZrO2, and Ta2O5, and the thickness is 3-50 nm.
10. The fin-type p-type multi-channel GaN transistor structure and the method for manufacturing the same according to claim 2, characterized in that: The gate electrode (11) is made of one or more materials selected from the group consisting of Ti, Au, TiN, Al, and W.
11. The method for preparing a fin-type p-type multi-channel GaN transistor structure according to claim 2, characterized in that: The drain electrode (12) and the source electrode (13) have a first layer material of Ni, and other metals are one or more of Au, Al, and W.
12. The fin-type p-type multi-channel GaN transistor structure and the method for manufacturing the same according to claim 2, characterized in that: The following steps are involved: S1: Select a substrate (1); S2: epitaxially growing a buffer layer (2), a first barrier layer (3), a first channel layer (4), a second barrier layer (5) and a second channel layer (6) on the substrate (1) in sequence, and stacking a plurality of similar barrier layers and channel layers (7) in a similar manner until an Nth barrier layer (8) and an Nth channel layer (9) are formed; S3: etching in a partial area to form a fin-shaped structure; S4: depositing a dielectric layer (10) on the surface of the sample obtained in S3; S5: depositing metal in a partial area of the dielectric layer (10) to form a gate electrode (11) covering the surface of the fin-shaped structure; S6: removing the dielectric layer (10) on both sides of the gate electrode (11), and depositing metal to form a drain electrode (12) and a source electrode (13).
13. The fin-type p-type multi-channel GaN transistor structure and the method for manufacturing the same according to claim 10, characterized in that: Step S3 includes: S31: depositing a SiO2 mask on the p-GaN; S32: etching or ion implantation to form device isolation; S33: dry etching to obtain a trapezoidal structure; S34: performing wet etching to obtain a vertical fin structure (14); S35: removing the mask.