Enhanced vertical transistor and method for manufacturing the same

Abstract

The present application provides an enhanced vertical transistor and a method for manufacturing the same. The enhanced vertical transistor includes a semiconductor layer, a source structure layer, a trench gate and a current control layer. The source structure layer includes a first doped region, a trench passes through a source contact layer adjacent to the first doped region, and the current control layer is located between the semiconductor layer and the source structure layer, and includes a current aperture and a high resistance structure. Under preset conditions, a channel formed along the sidewall of the trench gate close to the first doped region is connected to the current aperture to turn on the enhanced vertical transistor, and the high resistance structure is used to block the passage of current and to reduce the electric field strength on the side of the trench gate close to the semiconductor layer. The high resistance structure in the present application can cooperate with other structures in the transistor to realize the shutoff of the current channel in the current aperture, and the high resistance structure also reduces the gate leakage current of the transistor in the off state and helps to increase the breakdown voltage. The manufacturing method is simple in process and compatible with traditional processes.

Description

Technical Field

[0001] The present application belongs to the technical field of semiconductor devices and relates to an enhanced vertical transistor and a method for manufacturing the same. Background Art

[0002] Power semiconductor devices are core components in power electronic systems. Their application scenarios include industrial control, renewable energy and new energy systems, electric vehicles, rail transit, etc. They should have the characteristics of low on-resistance and high blocking voltage when turned off. Gallium oxide, as a new generation of power semiconductor materials, has a wide bandgap, high breakdown field strength and low growth cost, making it a semiconductor material more suitable for power device manufacturing than materials such as silicon carbide and gallium nitride.

[0003] At present, enhancement-mode gallium oxide power devices include fin field effect transistors (FinFETs) and current aperture vertical electron transistors (CAVETs). Figure 1 , Figure 1 It is a schematic diagram of the structure of a FinFET, which includes a drain metal 101, a substrate 102 and a drift region 103 (for example, lightly n-type doped). The top of the drift region 103 is etched into a fin-like vertical channel structure with a width of hundreds of nanometers. The gate dielectric layer 104 and the gate electrode 105 are sequentially covered on the opposite sides of the fin-like vertical channel structure. An active region 106 and a source metal 107 covering the source region 106 are formed above the fin-like vertical channel structure. By controlling the width of the fin-like vertical channel structure and based on the depletion effect of the gate electrodes 105 on both sides of the fin-like vertical channel structure on the channel, an enhancement-mode device is realized. The width of the fin-like vertical channel in the FinFET needs to be strictly limited (i.e., at the level of hundreds of nanometers). If the width is too large, the device may not be effectively turned off. In addition, the etching process and sidewall repair of the fin-like vertical channel are critical, and its surface defects will form lattice scattering, which will affect the on-state resistance of the device. Therefore, due to the complex preparation process, gallium oxide FinFET is not suitable for mass production. Please refer to Figure 2 , Figure 2 A schematic diagram of the structure of a CAVET is shown, in which a current blocking region 108 and a contact region 109 and a channel region 110 located above the current blocking region 108 and on opposite sides of a source region 106 are formed in a drift layer 103 of the CAVET. The CAVET is prone to low device breakdown voltage due to quality problems of the current blocking region 108, and its working performance needs to be improved.

[0004] Therefore, how to provide an enhanced vertical transistor and a method for manufacturing the same, so as to realize an enhanced vertical transistor with a simple process and improved breakdown voltage, has become an important technical problem to be solved urgently by those skilled in the art.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application.

[0006] Application Contents

[0007] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide an enhanced vertical transistor and a method for manufacturing the same, so as to solve the problem in the prior art that the enhanced vertical transistor has a complex manufacturing process or the breakdown voltage needs to be improved.

[0008] To achieve the above objectives and other related objectives, in a first aspect, an enhancement-mode vertical transistor is provided, comprising:

[0009] Semiconductor layer;

[0010] A source structure layer, located on the semiconductor layer, wherein the source structure layer includes a first doping region;

[0011] A trench gate, located on the semiconductor layer and penetrating the source structure layer, wherein the trench gate is adjacent to the first doping region;

[0012] A current control layer is located between the semiconductor layer and the source structure layer, and the current control layer includes a current aperture and a high resistance structure. Under preset conditions, a channel formed along the side wall of the trench gate close to the first doped region is connected to the current aperture to turn on the enhanced vertical transistor, and the high resistance structure is used to block the passage of current and to reduce the electric field strength on the side of the trench gate close to the semiconductor layer.

[0013] Optionally, the trench gate comprises a trench and a gate, and the gate comprises a first portion filled in the trench and a second portion located above the source structure layer;

[0014] Wherein, along the direction from the semiconductor layer to the source structure layer, the projection of the first doping region is within the range of the projection of the second part.

[0015] Optionally, along the direction from the semiconductor layer to the source structure layer, the depth of the trench is less than the sum of the thickness of the source structure layer and the thickness of the current control layer.

[0016] Optionally, along the direction from the semiconductor layer to the source structure layer, a projection of a side of the current aperture away from the high resistance structure is within a range of a projection of the first doping region.

[0017] Optionally, along the direction from the semiconductor layer to the source structure layer, a projection of a side of the high resistance structure close to the trench gate is within a range of a projection of a side of the trench gate close to the high resistance structure.

[0018] Optionally, the resistivity of the high resistance structure is greater than 10 9 Ω·cm; the material of the high resistance structure includes at least one of ion-doped gallium oxide, an insulating compound and a P-type oxide, wherein the ion-doped gallium oxide is doped with at least one of nitrogen ions and magnesium ions, and the P-type oxide includes at least one of nickel oxide and copper oxide.

[0019] Optionally, the source structure layer further includes a second doping region, the second doping region is located on a side of the first doping region away from the trench gate, and the doping concentration of the second doping region is greater than the doping concentration of the first doping region.

[0020] Optionally, the current control layer further includes a current blocking layer, and along a direction perpendicular to the semiconductor layer to the source structure layer, the current aperture is located between the current blocking layer and the high resistance structure.

[0021] In a second aspect, a method for manufacturing an enhancement mode vertical transistor is provided, comprising the following steps:

[0022] providing a semiconductor layer;

[0023] forming a current control layer on the semiconductor layer, wherein the current control layer comprises a current aperture and a high resistance structure;

[0024] forming a source structure layer on the semiconductor layer, wherein the current control layer is located between the semiconductor layer and the source structure layer, and the source structure layer includes a first doping region;

[0025] forming a trench gate on the semiconductor layer, wherein the trench gate penetrates the source structure layer and is adjacent to the first doping region;

[0026] Under preset conditions, a channel formed along the sidewall of the trench gate close to the first doped region is connected to the current aperture to turn on the enhanced vertical transistor, and the high-resistance structure is used to block the passage of current and reduce the electric field strength on the side of the trench gate close to the semiconductor layer.

[0027] Optionally, the current control layer also includes a current blocking layer, and along the direction perpendicular to the semiconductor layer to the source structure layer, the current aperture is located between the current blocking layer and the high resistance structure, and the manufacturing method also includes the step of forming a current blocking layer; wherein the method of forming the high resistance structure includes at least one of an ion implantation method and a groove etching and filling method; the method of forming the current blocking layer includes at least one of an ion implantation method and a groove etching and filling method.

[0028] As described above, the vertical heterogeneous transistor of the present application includes a semiconductor layer, a source structure layer, a trench gate and a current control layer, and the current control layer includes a current aperture and a high-resistance structure. When the transistor is in a reverse bias state, the high-resistance structure cooperates with other structures in the transistor (for example, the sidewalls of the trench gate and the current blocking layer) to achieve the shutoff of the current channel in the current aperture, thereby achieving the normal shutoff of the transistor, and the high-resistance structure can also reduce the gate leakage current of the transistor in the off state. In addition, the high-resistance structure also helps to reduce the electric field strength of the trench gate close to the semiconductor layer side, avoid the occurrence of premature device breakdown caused by the electric field concentration of the trench gate close to the semiconductor layer side, and improve the breakdown voltage strength and reliability.

[0029] The manufacturing method of the enhanced vertical transistor of the present application realizes normal conduction and shutdown of the transistor and realizes the enhanced working mode by manufacturing a high-resistance structure and a current aperture between the semiconductor layer and the source structure layer. The high-resistance structure can be manufactured by at least one of an ion implantation method and a groove etching and filling method, and the high-resistance structure can also be manufactured in the same step as the current blocking region, and an enhanced vertical transistor with effectively improved breakdown voltage and reliability can be manufactured. The process is simple and compatible with traditional processes, and is suitable for large-scale applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a schematic diagram of the structure of a FinFET in the related art;

[0031] Figure 2 It is a structural schematic diagram of a CAVET in the related art;

[0032] Figure 3 It is a structural schematic diagram of a U-MOSFET in the related art;

[0033] Figure 4 is a schematic structural diagram of an enhanced vertical transistor provided in an embodiment of the present application;

[0034] Figure 5 yes Figure 4 A magnified schematic diagram of the middle A area;

[0035] Figure 6is a schematic structural diagram of another enhancement-type vertical transistor provided in an embodiment of the present application;

[0036] Figure 7 is an electron density distribution diagram of an enhanced vertical transistor in an off state provided by an embodiment of the present application;

[0037] Figure 8 It is a flowchart of the steps of a method for manufacturing an enhanced vertical transistor provided in an embodiment of the present application.

[0038] Description of reference numerals:

[0039] 101 - drain metal, 102 - substrate, 103 - drift region, 104 - gate dielectric layer, 105 - gate electrode, 106 - source region, 107 - source metal, 108 - current blocking region, 109 - contact region, 110 - channel region;

[0040] 10-semiconductor layer, 11-substrate, 12-drift layer, 20-current aperture, 30-high resistance structure, 40-current blocking layer, 50-source structure layer, 51-first doping region, 52-second doping region, 60-trench gate, 61-trench, 62-gate, 621-first part, 622-second part, 63-gate dielectric, 70-first metal layer, 80-second metal layer, S1~S3-steps. DETAILED DESCRIPTION

[0041] The following describes the implementation of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application.

[0042] See also Figures 3 to 8 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present application in a schematic manner, and the drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0043] For technical issues mentioned in the background technology, please refer to Figure 3 , Figure 3The invention relates to a U-MOSFET device with a trench gate, wherein the device has a groove gate structure with a U-shaped groove, and an N-type current blocking region 108 and a source region 106 are formed by ion implantation in the drift region 103 on opposite sides of the groove gate structure, wherein the source region 106 is located above the current blocking region 108. The current between the source metal 107 and the drain metal 101 is isolated by the current blocking region 108. Under the gate voltage applied by the gate electrode 105, the sidewall of the U-shaped groove attracts electrons that can move freely in the current blocking region 108 to form an electron accumulation layer, thereby promoting the conduction of the device, thereby realizing an enhanced device. However, under high voltage conditions, the bottom of the groove gate structure of the device structure is prone to electric field concentration, which easily leads to premature breakdown of the device, and still cannot achieve improvement in breakdown voltage.

[0044] Embodiment 1

[0045] The present application embodiment provides an enhanced vertical transistor (hereinafter referred to as "transistor"), see Figure 4 , Figure 4 1 is a schematic diagram of the structure of an enhanced vertical transistor provided in an embodiment of the present application. The transistor includes a semiconductor layer 10, a source structure layer 50, a trench gate 60 and a current control layer (not marked).

[0046] Specifically, the source structure layer 50 is located on the semiconductor layer 10, and the source structure layer 50 includes a first doping region 51. The trench gate 60 is located on the semiconductor layer 10 and penetrates the source structure layer 50, and the trench gate 60 is adjacent to the first doping region 51. The current control layer is located between the semiconductor layer 10 and the source structure layer 50, and the current control layer includes the current aperture 20 and the high resistance structure 30. Under preset conditions, the channel formed along the side wall of the trench gate 60 close to the first doping region 51 is connected to the current aperture 20 to turn on the enhanced vertical transistor, and the high resistance structure 30 is used to block the passage of current and to reduce the electric field strength on the side of the trench gate 60 close to the semiconductor layer 10. "Preset conditions" refer to the case where the gate voltage of the transistor is greater than the threshold voltage.

[0047] In an optional embodiment, the current control layer further includes a current blocking layer 40, which is perpendicular to the direction from the semiconductor layer 10 to the source structure layer 50 ( Figure 4 In the embodiment shown in FIG. 1 , the current aperture 20 is located between the current blocking layer 40 and the high resistance structure 30. The side of the trench gate 60 close to the semiconductor layer 10 is adjacent to the high resistance structure 30, that is, the high resistance structure 30 is located on the side of the trench gate 60 close to the semiconductor layer 10, so that the concentrated electric field intensity on the side of the trench gate 60 close to the semiconductor layer 10 can be alleviated and dispersed.

[0048] In an optional embodiment, the transistor includes a plurality of cell structures, for example, Figure 4 and Figure 6 All shown are cross-sectional views of a single cell structure, in which the current blocking layer 40 in each cell structure is arranged around the high resistance structure 30, and in this case, each cell has a ring-shaped current aperture 20. Alternatively, the current blocking layer 40, the current aperture 20, and the high resistance structure 30 in each cell structure are arranged in sequence in a direction perpendicular to the semiconductor layer 10 to the source structure layer 50, and in this case, each cell has a double current aperture 20. That is, the high resistance structure provided in the embodiment of the present application can be applied to transistors with different cell structures, and the structure is flexible and diversified to meet the requirements of different application scenarios.

[0049] In the embodiment of the present application, the transistor includes a semiconductor layer 10, a source structure layer 50, a trench gate 60 and a current control layer. When the gate voltage of the transistor is greater than the threshold voltage, electrons are accumulated at the side wall of the trench gate 60 close to the first doping region 51 to form a channel. The formed channel flows with the current aperture 20, so that the current flows into the semiconductor layer 10 through the current aperture 20 to achieve the conduction of the transistor. At the same time, the high resistance structure 30 is used to block the passage of current. When the transistor is in a reverse bias state, the depletion effect generated by the first doping region 51 where the side wall of the trench gate 60 close to the first doping region 51, the high resistance structure 30 and the current blocking layer 40 realizes the effective pinching off of the current channel in the current aperture 20, thereby turning off the transistor. The first doping region 51 in the source structure layer 50 near the trench gate 60 adopts a relatively low doping concentration. When the transistor is in a reverse bias state, the depletion effect of the first doping region 51 on the side wall of the trench gate 60, the current blocking layer 40 and the high resistance structure 30 can effectively pinch off the current channel of the current aperture 20, thereby effectively turning off the transistor. In addition, since the transistor is provided with the high resistance structure 30, a new depletion region is introduced on the side of the trench gate 60 close to the semiconductor layer 10, which can alleviate the problem of electric field concentration on the side of the trench gate 60 close to the semiconductor layer 10, making the electric field distribution inside the transistor more uniform, which helps to improve the breakdown voltage of the transistor. At the same time, when the transistor is in the off state, due to the depletion effect of the high resistance structure 30, the electrons in the current aperture 20 region of the transistor are completely depleted. Please refer to Figure 7 , Figure 7 Figure 2 shows the electron density distribution of the transistor in the off state. Figure 7 It can be seen that the electron density in each area of ​​the current aperture 20 is within 1e -14 There are basically no free electrons, so the arrangement of the high resistance structure 30 is also helpful to reduce the gate leakage current.

[0050] In an optional embodiment, the source structure layer 50 further includes a second doping region 52, which is located on a side of the first doping region 51 away from the trench gate 60, and the doping concentration of the second doping region 52 is greater than the doping concentration of the first doping region 51. In one embodiment, the doping concentration of the first doping region 51 is in the range of 5×10 16 / cm 3 ~5×10 17 / cm 3 (including the endpoint value), the doping concentration range of the second doping region 52 is 5×10 17 / cm 3 ~5×10 18 / cm 3 (including the endpoint value). That is, the first doping region 51 is an n-doping region, and the second doping region 52 is an n++ doping region.

[0051] In the embodiment of the present application, the doping concentration of the region of the source structure layer 50 close to the trench gate 60 (i.e., the first doping region 51) is set (for example, the doping concentration of the first doping region 51 is 1×10 17 / cm 3 ) is lower than the doping concentration of the region of the source structure layer 50 far from the trench gate 60 (i.e., the second doping region 52) (for example, the doping concentration is 1×10 18 / cm 3 ), forming a variable doping channel, the design of the variable doping channel enables the transistor to be turned on only under a larger gate voltage condition, thereby realizing an enhancement type device, while ensuring the current density of the transistor. That is, the design of the variable doping channel and the high resistance structure 30 work together to realize the enhancement type working mode of the device.

[0052] In an optional embodiment, the trench gate 60 includes a trench 61 and a gate 62, and the gate 62 includes a first portion 621 filled in the trench 61 and a second portion 622 located above the source structure layer 50. Figure 4 In the figure, the projection of the first doped region 51 is within the range of the projection of the second portion 622. “The projection of the first doped region 51 is within the range of the projection of the second portion 622” includes the following two implementations: the edge of the projection of the first doped region 51 does not overlap with the edge of the projection of the second portion 622, or the edge of the projection of the first doped region 51 partially overlaps with the edge of the projection of the second portion 622. For example, see Figure 5 , Figure 5 Shows Figure 4The enlarged schematic diagram of the A region in FIG. 1 shows that the width of the first doped region 51 ( Figure 5 (shown in a) is less than or equal to the width of the portion of the second portion 622 located above the source structure layer 50 ( Figure 5 As shown in b), that is, the gate 62 needs to completely cover the first doped region 51, which helps to ensure that the transistor can be normally turned on.

[0053] In an optional embodiment, along the direction from the semiconductor layer 10 to the source structure layer 50, the depth of the groove 61 ( Figure 5 c) is smaller than the thickness of the source structure layer 50 and the current control layer ( Figure 5 The thickness (( Figure 5 The thickness of the current control layer is the maximum value of the thickness of the current aperture 20, the high resistance structure 30 and the current blocking layer 40 included in the structure layer. For example, when the thickness of the current aperture 20 ( Figure 5 f) is greater than the thickness of the high resistance structure 30 ( Figure 5 When the thickness of the current aperture 20 is used as the thickness of the structural layer, the thickness of the current aperture 20 is used as the thickness of the structural layer.

[0054] In the embodiment of the present application, on the one hand, in order to ensure that the transistor can achieve enhancement mode and the transistor can be turned on and off normally, the channel formed along the sidewall of the trench gate 60 must be connected to the current aperture 20. Therefore, the depth of the trench 61 needs to be greater than or equal to the thickness of the source structure layer 50 (that is, the trench 61 needs to completely penetrate the heterostructure layer in the direction from the drift layer 12 to the current control layer), so as to avoid the presence of other structural layers between the trench gate 60 and the current aperture 20 to hinder the connection between the channel and the current aperture 20. On the other hand, the depth of the trench 61 also needs to be less than the sum of the thickness of the source structure layer 50 and the thickness of the structural layer where the current aperture 20 and the high resistance structure 30 are located, so that the depletion region formed by the high resistance structure 30 and the current blocking layer 40 on the side of the trench gate 60 close to the semiconductor layer 10 in the transistor off state can effectively pinch off the current aperture 20 and the channel, thereby reducing the leakage of the device in the off state. If the depth of the groove 61 is too large, the groove 61 will further extend into the semiconductor layer 10, causing the electric field distribution at the side wall of the trench gate 60 to change, which may cause the transistor to be accidentally turned on in the zero voltage state. And when the transistor is in the off state, due to the increase in the electric field strength at the side wall of the trench gate 60, a new leakage current path may be formed, thereby affecting the leakage performance of the transistor in the off state. Based on the above, it is necessary to control the appropriate depth of the groove 61 so that the high-resistance structure and the current blocking layer 40 located on the side of the trench gate 60 close to the semiconductor layer 10 can form an effective depletion region when the transistor is in the off state, thereby effectively pinching off the current aperture 20 and the channel, and reducing the leakage of the device in the off state. Therefore, the side of the trench gate 60 close to the semiconductor layer 10 can be exactly adjacent to the side of the high-resistance structure 30 away from the semiconductor layer 10 (such as Figure 5 Alternatively, see Figure 6 , Figure 6 A schematic structural diagram of another transistor provided in an embodiment of the present application is shown, wherein a side of the trench gate 60 close to the semiconductor layer 10 may also be located in the structural layer where the high resistance structure 30 and the current aperture 20 are located.

[0055] In an optional embodiment, along the direction from the semiconductor layer 10 to the source structure layer 50, the projection of one side of the high-resistance structure 30 close to the trench gate 60 is within the range of the projection of one side of the trench gate 60 close to the high-resistance structure 30. When this condition is met, the current can flow along the channel formed along the sidewall of the trench gate 60 to the current aperture 20. If this condition is not met, the portion of the high-resistance structure 30 protruding outside the trench gate 60 along the direction perpendicular to the semiconductor layer 10 to the source structure layer 50 may hinder the smooth connection between the channel and the current aperture 20 to a certain extent, thereby affecting the conduction performance of the device. Among them, "the projection of one side of the high-resistance source structure layer 50 close to the trench gate 60 is within the range of the projection of one side of the trench gate 60 close to the high-resistance structure 30" includes the following three situations: the edges of the two do not overlap at all, the edges of the two partially overlap, and the edges of the two completely overlap. For example, as Figure 5 As shown, along the direction from the semiconductor layer 10 to the source structure layer 50, the width of the side of the high resistance structure 30 close to the trench gate 60 ( Figure 5 h in the figure) is less than or equal to the width of the side of the trench gate 60 close to the high resistance structure 30 ( Figure 5 It should be noted that the groove 61 and the high resistance structure 30 shown in the cross-sectional view in the embodiment of the present application are both rectangular in shape on the cross-section. In practical applications, the groove 61 may also be a trapezoidal groove, and the high resistance structure 30 may also be a trapezoid or a polygon.

[0056] In an optional embodiment, along the direction from the semiconductor layer 10 to the source structure layer 50, the projection of the side of the current aperture 20 away from the high resistance structure 30 is within the range of the projection of the first doping region 51. Similarly, "the projection of the side of the current aperture 20 away from the high resistance structure 30 is within the range of the projection of the first doping region 51" includes the following two implementations: the projection of the side of the current aperture 20 away from the high resistance structure 30 is completely located inside the projection of the first doping region 51, or the side of the current aperture 20 away from the high resistance structure 30 partially overlaps with the edge of the projection of the first doping region 51. Through the above arrangement, it is possible to avoid the second doping region 52 being directly connected to the current aperture 20, so that the first doping region 51 covers the area of ​​the current aperture 20 that is not covered by the trench gate 60, and it is possible to avoid the transistor being in the on state under the condition of zero gate voltage, thereby ensuring the realization of the enhancement mode of operation of the transistor. For example, when the projection of one side of the high resistance structure 30 close to the trench gate 60 completely overlaps with the edge of the projection of one side of the trench gate 60 close to the high resistance structure 30, the current aperture 20 is completely covered by the first doping region 51, and in the direction perpendicular to the semiconductor layer 10 to the source structure layer 50, the width ( Figure 5 j) is less than or equal to the width of the first doping region 51 ( Figure 5 (shown in a).

[0057] In an optional embodiment, along the direction from the semiconductor layer 10 to the source structure layer 50, the thickness of the current aperture 20 ( Figure 5 The width of the current aperture 20 along the direction perpendicular to the semiconductor layer 10 to the source structure layer 50 is (shown in FIG. 5 ) in the range of 0.2 μm to 1.5 μm (including the end value), and can be 0.6 μm, 1.0 μm or 1.2 μm. Figure 5 The range of (as shown in j) is 0.5 μm to 1.5 μm (including the endpoint values), and can be 0.8 μm or 1.2 μm.

[0058] In an optional embodiment, the semiconductor layer 10 includes a substrate 11 and a drift layer 12, and the drift layer 12 is located between the substrate 11 and the current control layer. The material of the substrate 11 can be a material such as gallium oxide, and the conductivity type of the substrate 11 is the same as the conductivity type of the drift layer 12. In one embodiment, the doping concentration of the substrate 11 is greater than the doping concentration of the drift layer 12. For example, the conductivity type of the substrate 11 is N-type, and the doping concentration of N-type ions in the substrate 11 is in the range of 10 19 / cm 3 ~10 20 / cm 3(including endpoint values), for example, the N-type ions in the substrate 11 are Si ions.

[0059] In an optional embodiment, the doping concentration of the current aperture 20 is greater than the doping concentration of the drift layer 12, which helps to improve the conduction characteristics of the device. The doping concentration of the current aperture 20 is in the range of 10 15 / cm 3 ~10 17 / cm 3 (including the endpoint values).

[0060] In an optional embodiment, the resistivity of the high resistance structure 30 is greater than 10 9 Under the condition of satisfying the resistivity, the high resistance structure 30 can effectively prevent the current from passing through the high resistance structure 30 and entering the semiconductor layer 10, thereby achieving depletion effect and reducing current leakage.

[0061] In an optional embodiment, the material of the high resistance structure 30 includes at least one of ion-doped gallium oxide, an insulating compound and a P-type oxide, wherein the ion-doped gallium oxide is doped with at least one of nitrogen ions and magnesium ions, and the P-type oxide includes at least one of nickel oxide and copper oxide. The ion doping concentration of the ion-doped gallium oxide is in the range of 10 18 / cm 3 ~10 19 / cm 3 (including endpoint values). The insulating compound includes silicon oxide SiO2, silicon nitride SiN x (x>0) and at least one of aluminum oxide Al2O3. The insulating compounds listed above are relatively common materials in semiconductor devices. Other types of insulating compounds can also be used in practical applications, which are not specifically limited here. Since the high-resistance structure 30 can be formed by ion implantation or trench 61 etching and deposition, the material types of the high-resistance structure 30 formed by different methods may be different. For example, the material of the high-resistance structure 30 formed by ion implantation can be ion-doped gallium oxide (Ga2O3), that is, by ion implanting suitable ions (for example, nitrogen ions) into the gallium oxide material layer, the resistance of the ion implantation area of ​​the gallium oxide material layer meets the resistivity requirements of the high-resistance structure 30. For another example, the material of the high-resistance structure 30 formed by the trench 61 etching and deposition method can be an insulating compound material (for example, SiO2) or a P-type oxide.

[0062] In an optional embodiment, in a direction perpendicular to the semiconductor layer 10 to the source structure layer, the width of the high resistance structure 30 ( Figure 5h) is in the range of 0.5μm to 3μm (including the endpoint values), which can be 1.0μm, 1.5μm, 2.0μm or 2.5μm. Since the current aperture 20 is formed based on the area between the high resistance structure 30 and the current blocking layer 40, if the current blocking layer 40 has the same structure, if the above-mentioned width of the high resistance structure 30 is too large, it may cause the current aperture 20 to be too narrow, thereby affecting the conduction performance and reliability of the transistor. In actual application, the width of the high resistance structure 30 needs to be adjusted based on the width of the trench 61 in the trench gate 60, etc.

[0063] In an optional embodiment, along the direction from the semiconductor layer 10 to the source structure layer, the thickness of the high resistance structure 30 is ( Figure 5 g) is in the range of 0.2μm to 1.5μm (including the end value), which can be 0.5μm, 0.8μm or 1.2μm. In the case where the thickness of the high-resistance structure 30 is less than 0.2μm, the depletion region introduced by the high-resistance structure 30 has a limited effect on improving the electric field concentration phenomenon in the area of ​​the trench gate 60 close to the drift layer 12 and blocking the current. In the case where the thickness of the high-resistance structure 30 is greater than 1.5μm, the chip area and cost will be increased.

[0064] In an optional embodiment, the trench gate 60 also covers the gate dielectric 63 on the inner wall of the trench 61, and the material of the gate dielectric 63 includes at least one of silicon oxide, silicon nitride, hafnium oxide and aluminum oxide. The thickness of the gate dielectric 63 ranges from 5μm to 50μm (including end points), and can be 15μm, 25μm or 35μm. The formation method of the gate dielectric 63 includes at least one of plasma enhanced chemical vapor deposition (PECVD), plasma enhanced atomic layer deposition (PEALD) and low pressure chemical vapor deposition (LPCVD).

[0065] In an optional embodiment, the transistor further includes a first metal layer 70 and a second metal layer 80, wherein the first metal layer 70 penetrates at least a portion of the source structure layer 50, and the second metal layer 80 is located on a side of the semiconductor layer 10 away from the current blocking layer 40. In one embodiment, the first metal layer 70 completely penetrates the source structure layer 50 to connect with the current blocking layer 40. The first metal layer 70 can be used as a source metal of the transistor, and the second metal layer 80 can be used as a drain metal of the transistor.

[0066] In an optional embodiment, the first doping region 51, the second doping region 52, the current aperture 20, the drift layer 12 and the substrate 11 are all of the first conductivity type, the high resistance structure 30 is of the second conductivity type or the insulating type, and the current blocking layer 40 is of the second conductivity type or the insulating type. In the embodiment of the present application, the first conductivity type is n-type, and the second conductivity type is p-type. The n-type ions doped in each structure of the first conductivity type (for example, the first doping region 51, the current aperture 20, etc.) are Si ions.

[0067] The vertical heterogeneous transistor in the embodiment of the present application includes a semiconductor layer, a source structure layer, a trench gate and a current control layer, and the current control layer includes a current aperture and a high-resistance structure. When the transistor is in a reverse bias state, the high-resistance structure cooperates with other structures in the transistor (for example, the sidewalls of the trench gate and the current blocking layer) to achieve the shutoff of the current channel in the current aperture, thereby achieving the normal shutoff of the transistor, and the high-resistance junction can also reduce the gate leakage current of the transistor in the off state. In addition, the high-resistance structure also helps to reduce the electric field strength of the trench gate close to the semiconductor layer, avoid the occurrence of premature device breakdown caused by the electric field concentration of the trench gate close to the semiconductor layer, and improve the breakdown voltage strength and reliability.

[0068] Embodiment 2

[0069] The present application also provides a method for manufacturing an enhanced vertical transistor, which can be used to manufacture the enhanced vertical transistor described in the first embodiment or other suitable transistors. Figure 8 , which is a flowchart of the steps of the production method, and the production method includes the following steps:

[0070] S1: providing a semiconductor layer;

[0071] S2: forming a current control layer on the semiconductor layer, wherein the current control layer includes a current aperture and a high resistance structure;

[0072] S3: forming a source structure layer on the semiconductor layer, wherein the current control layer is located between the semiconductor layer and the source structure layer, and the source structure layer includes a first doping region;

[0073] S4: forming a trench gate on the semiconductor layer, wherein the trench gate penetrates the source structure layer and is adjacent to the first doping region;

[0074] Under preset conditions, a channel formed along the side wall of the trench gate close to the first doped region is connected to the current aperture to turn on the enhanced vertical transistor; the high-resistance structure is also used to block the passage of current and reduce the electric field strength on the side of the trench gate close to the semiconductor layer.

[0075] In an optional embodiment, the current control layer also includes a current blocking layer 40. Along the direction perpendicular to the semiconductor layer 10 to the source structure layer 50, the current aperture 20 is located between the current blocking layer 40 and the high resistance structure 30. The manufacturing method also includes the step of forming a current blocking layer 40. Among them, the method of forming the high resistance structure 30 includes at least one of an ion implantation method and a groove etching and filling method; the method of forming the current blocking layer 40 includes at least one of an ion implantation method and a groove etching and filling method. To avoid ambiguity, the "groove etching deposition method" described in this article is to first etch a groove in a structural layer (not shown) located above the semiconductor layer 10, and then deposit the corresponding material in the groove to obtain a current blocking layer 40 or a high resistance structure 30.

[0076] In an optional embodiment, when the method for forming the current blocking layer 40 is the same as the method for forming the high resistance structure 30, the formation of the current blocking layer 40 and the formation of the high resistance structure 30 are performed in the same step, which helps to save process steps and reduce process difficulty. Of course, in the case where the doping concentration or structural parameters of the current blocking layer 40 and the high resistance structure 30 are different, the same method can also be selected to form the current blocking layer 40 and the high resistance structure 30 in steps, so as to realize flexible and targeted production of transistor structures.

[0077] In an optional embodiment, when the method for forming the current blocking layer 40 and the method for forming the high resistance structure 30 are both ion implantation methods, in one embodiment, an ion implantation mask layer (not shown) is formed on a structural layer located above the semiconductor layer 10 and the ion implantation mask layer is patterned to form a first implantation window (not shown) and a second implantation window (not shown), the first implantation window being used to define a pattern of the current blocking layer 40, and the second implantation window being used to define a pattern of the high resistance structure 30; based on the patterned ion implantation mask layer, one or more ion implantations are performed to synchronously form the current blocking layer 40 and the high resistance structure 30.

[0078] In an optional embodiment, when the method for forming the current blocking layer 40 is an ion implantation method or a groove etching deposition method, and the method for forming the high resistance structure 30 is an ion implantation method, in one embodiment, the source structure layer 50 is formed above the drift layer 12 after the current blocking layer 40 is formed; and etching is performed to form a groove 61 that at least penetrates the source structure layer 50; a high resistance structure injection mask layer (not shown) is formed on the structure layer after the groove 61 is formed and the high resistance structure injection mask layer is patterned to form an injection window (not shown), the injection window exposes at least a portion of the bottom wall of the groove 61, and ion implantation is performed based on the injection window to form a high resistance structure 30 located on the side of the groove 61 close to the semiconductor layer 10.

[0079] The method for manufacturing an enhanced vertical transistor provided in an embodiment of the present application realizes normal conduction and shutdown of the transistor and realizes an enhanced working mode by manufacturing a current control layer between the semiconductor layer and the source structure layer, wherein the current control layer includes a high resistance structure and a current aperture. The high resistance structure can be manufactured by at least one of an ion implantation method and a groove etching and filling method, and the high resistance structure can also be manufactured in the same step as the current blocking region. The process is simple and compatible with traditional processes, and can manufacture an enhanced vertical transistor with effectively improved breakdown voltage and reliability, which is suitable for large-scale applications.

[0080] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. An enhancement type vertical transistor, characterized in that: include: Semiconductor layer; A source structure layer, located on the semiconductor layer, wherein the source structure layer includes a first doped region; A trench gate, located on the semiconductor layer and penetrating the source structure layer, wherein the trench gate is adjacent to the first doping region; A current control layer, located between the semiconductor layer and the source structure layer, the current control layer comprising a current aperture and a high resistance structure; Under preset conditions, a channel formed along the sidewall of the trench gate close to the first doped region is connected to the current aperture to turn on the enhanced vertical transistor, and the high-resistance structure is used to block the passage of current and to reduce the electric field strength on the side of the trench gate close to the semiconductor layer.

2. The enhancement mode vertical transistor according to claim 1, characterized in that: The trench gate comprises a trench and a gate, wherein the gate comprises a first portion filled in the trench and a second portion located above the source structure layer; Wherein, along the direction from the semiconductor layer to the source structure layer, the projection of the first doping region is within the range of the projection of the second part.

3. The enhancement mode vertical transistor according to claim 2, characterized in that: In a direction from the semiconductor layer to the source structure layer, the depth of the trench is less than the sum of the thickness of the source structure layer and the thickness of the current control layer.

4. The enhancement mode vertical transistor according to claim 1, characterized in that: Along the direction from the semiconductor layer to the source structure layer, a projection of a side of the current aperture away from the high resistance structure is within a range of a projection of the first doping region.

5. The enhancement mode vertical transistor according to claim 1, characterized in that: Along the direction from the semiconductor layer to the source structure layer, a projection of a side of the high resistance structure close to the trench gate is within a range of a projection of a side of the trench gate close to the high resistance structure.

6. The enhancement mode vertical transistor according to claim 1, characterized in that: The resistivity of the high resistance structure is greater than 10 9 Ω·cm; the material of the high resistance structure includes at least one of ion-doped gallium oxide, an insulating compound and a P-type oxide, wherein the ion-doped gallium oxide is doped with at least one of nitrogen ions and magnesium ions, and the P-type oxide includes at least one of nickel oxide and copper oxide.

7. The enhancement mode vertical transistor according to claim 1, characterized in that: The source structure layer further includes a second doping region, which is located on a side of the first doping region away from the trench gate, and a doping concentration of the second doping region is greater than a doping concentration of the first doping region.

8. The enhancement mode vertical transistor according to claim 1, characterized in that: The current control layer further includes a current blocking layer. Along a direction perpendicular to the semiconductor layer to the source structure layer, the current aperture is located between the current blocking layer and the high resistance structure.

9. A method for manufacturing an enhancement mode vertical transistor, characterized in that: The following steps are involved: providing a semiconductor layer; forming a current control layer on the semiconductor layer, wherein the current control layer comprises a current aperture and a high resistance structure; forming a source structure layer on the semiconductor layer, wherein the current control layer is located between the semiconductor layer and the source structure layer, and the source structure layer includes a first doping region; forming a trench gate on the semiconductor layer, wherein the trench gate penetrates the source structure layer and is adjacent to the first doping region; Under preset conditions, a channel formed along the sidewall of the trench gate close to the first doped region is connected to the current aperture to turn on the enhanced vertical transistor, and the high-resistance structure is used to block the passage of current and reduce the electric field strength on the side of the trench gate close to the semiconductor layer.

10. The method for manufacturing an enhancement-mode vertical transistor according to claim 9, characterized in that: The current control layer further comprises a current blocking layer, and along a direction perpendicular to the semiconductor layer to the source structure layer, the current aperture is located between the current blocking layer and the high resistance structure, and the manufacturing method further comprises the step of forming the current blocking layer; Among them, the method of forming the high resistance structure includes at least one of an ion implantation method and a groove etching and filling method; the method of forming the current blocking layer includes at least one of an ion implantation method and a groove etching and filling method.

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